1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 static void ath9k_set_assoc_state(struct ath_softc *sc, 23 struct ieee80211_vif *vif); 24 25 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 26 { 27 /* 28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 29 * 0 for no restriction 30 * 1 for 1/4 us 31 * 2 for 1/2 us 32 * 3 for 1 us 33 * 4 for 2 us 34 * 5 for 4 us 35 * 6 for 8 us 36 * 7 for 16 us 37 */ 38 switch (mpdudensity) { 39 case 0: 40 return 0; 41 case 1: 42 case 2: 43 case 3: 44 /* Our lower layer calculations limit our precision to 45 1 microsecond */ 46 return 1; 47 case 4: 48 return 2; 49 case 5: 50 return 4; 51 case 6: 52 return 8; 53 case 7: 54 return 16; 55 default: 56 return 0; 57 } 58 } 59 60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 61 { 62 bool pending = false; 63 64 spin_lock_bh(&txq->axq_lock); 65 66 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 67 pending = true; 68 69 spin_unlock_bh(&txq->axq_lock); 70 return pending; 71 } 72 73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 74 { 75 unsigned long flags; 76 bool ret; 77 78 spin_lock_irqsave(&sc->sc_pm_lock, flags); 79 ret = ath9k_hw_setpower(sc->sc_ah, mode); 80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 81 82 return ret; 83 } 84 85 void ath_ps_full_sleep(unsigned long data) 86 { 87 struct ath_softc *sc = (struct ath_softc *) data; 88 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 89 bool reset; 90 91 spin_lock(&common->cc_lock); 92 ath_hw_cycle_counters_update(common); 93 spin_unlock(&common->cc_lock); 94 95 ath9k_hw_setrxabort(sc->sc_ah, 1); 96 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 97 98 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 99 } 100 101 void ath9k_ps_wakeup(struct ath_softc *sc) 102 { 103 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 104 unsigned long flags; 105 enum ath9k_power_mode power_mode; 106 107 spin_lock_irqsave(&sc->sc_pm_lock, flags); 108 if (++sc->ps_usecount != 1) 109 goto unlock; 110 111 del_timer_sync(&sc->sleep_timer); 112 power_mode = sc->sc_ah->power_mode; 113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 114 115 /* 116 * While the hardware is asleep, the cycle counters contain no 117 * useful data. Better clear them now so that they don't mess up 118 * survey data results. 119 */ 120 if (power_mode != ATH9K_PM_AWAKE) { 121 spin_lock(&common->cc_lock); 122 ath_hw_cycle_counters_update(common); 123 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 124 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 125 spin_unlock(&common->cc_lock); 126 } 127 128 unlock: 129 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 130 } 131 132 void ath9k_ps_restore(struct ath_softc *sc) 133 { 134 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 135 enum ath9k_power_mode mode; 136 unsigned long flags; 137 138 spin_lock_irqsave(&sc->sc_pm_lock, flags); 139 if (--sc->ps_usecount != 0) 140 goto unlock; 141 142 if (sc->ps_idle) { 143 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 144 goto unlock; 145 } 146 147 if (sc->ps_enabled && 148 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 149 PS_WAIT_FOR_CAB | 150 PS_WAIT_FOR_PSPOLL_DATA | 151 PS_WAIT_FOR_TX_ACK | 152 PS_WAIT_FOR_ANI))) { 153 mode = ATH9K_PM_NETWORK_SLEEP; 154 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 155 ath9k_btcoex_stop_gen_timer(sc); 156 } else { 157 goto unlock; 158 } 159 160 spin_lock(&common->cc_lock); 161 ath_hw_cycle_counters_update(common); 162 spin_unlock(&common->cc_lock); 163 164 ath9k_hw_setpower(sc->sc_ah, mode); 165 166 unlock: 167 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 168 } 169 170 static void __ath_cancel_work(struct ath_softc *sc) 171 { 172 cancel_work_sync(&sc->paprd_work); 173 cancel_work_sync(&sc->hw_check_work); 174 cancel_delayed_work_sync(&sc->tx_complete_work); 175 cancel_delayed_work_sync(&sc->hw_pll_work); 176 177 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 178 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 179 cancel_work_sync(&sc->mci_work); 180 #endif 181 } 182 183 void ath_cancel_work(struct ath_softc *sc) 184 { 185 __ath_cancel_work(sc); 186 cancel_work_sync(&sc->hw_reset_work); 187 } 188 189 void ath_restart_work(struct ath_softc *sc) 190 { 191 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 192 193 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 194 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 195 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 196 197 ath_start_rx_poll(sc, 3); 198 ath_start_ani(sc); 199 } 200 201 static bool ath_prepare_reset(struct ath_softc *sc) 202 { 203 struct ath_hw *ah = sc->sc_ah; 204 bool ret = true; 205 206 ieee80211_stop_queues(sc->hw); 207 208 sc->hw_busy_count = 0; 209 ath_stop_ani(sc); 210 del_timer_sync(&sc->rx_poll_timer); 211 212 ath9k_hw_disable_interrupts(ah); 213 214 if (!ath_drain_all_txq(sc)) 215 ret = false; 216 217 if (!ath_stoprecv(sc)) 218 ret = false; 219 220 return ret; 221 } 222 223 static bool ath_complete_reset(struct ath_softc *sc, bool start) 224 { 225 struct ath_hw *ah = sc->sc_ah; 226 struct ath_common *common = ath9k_hw_common(ah); 227 unsigned long flags; 228 int i; 229 230 if (ath_startrecv(sc) != 0) { 231 ath_err(common, "Unable to restart recv logic\n"); 232 return false; 233 } 234 235 ath9k_cmn_update_txpow(ah, sc->curtxpow, 236 sc->config.txpowlimit, &sc->curtxpow); 237 238 clear_bit(SC_OP_HW_RESET, &sc->sc_flags); 239 ath9k_hw_set_interrupts(ah); 240 ath9k_hw_enable_interrupts(ah); 241 242 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { 243 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) 244 goto work; 245 246 if (ah->opmode == NL80211_IFTYPE_STATION && 247 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 248 spin_lock_irqsave(&sc->sc_pm_lock, flags); 249 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 250 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 251 } else { 252 ath9k_set_beacon(sc); 253 } 254 work: 255 ath_restart_work(sc); 256 257 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 258 if (!ATH_TXQ_SETUP(sc, i)) 259 continue; 260 261 spin_lock_bh(&sc->tx.txq[i].axq_lock); 262 ath_txq_schedule(sc, &sc->tx.txq[i]); 263 spin_unlock_bh(&sc->tx.txq[i].axq_lock); 264 } 265 } 266 267 ieee80211_wake_queues(sc->hw); 268 269 return true; 270 } 271 272 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 273 { 274 struct ath_hw *ah = sc->sc_ah; 275 struct ath_common *common = ath9k_hw_common(ah); 276 struct ath9k_hw_cal_data *caldata = NULL; 277 bool fastcc = true; 278 int r; 279 280 __ath_cancel_work(sc); 281 282 tasklet_disable(&sc->intr_tq); 283 spin_lock_bh(&sc->sc_pcu_lock); 284 285 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { 286 fastcc = false; 287 caldata = &sc->caldata; 288 } 289 290 if (!hchan) { 291 fastcc = false; 292 hchan = ah->curchan; 293 } 294 295 if (!ath_prepare_reset(sc)) 296 fastcc = false; 297 298 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 299 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 300 301 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 302 if (r) { 303 ath_err(common, 304 "Unable to reset channel, reset status %d\n", r); 305 306 ath9k_hw_enable_interrupts(ah); 307 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 308 309 goto out; 310 } 311 312 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 313 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 314 ath9k_mci_set_txpower(sc, true, false); 315 316 if (!ath_complete_reset(sc, true)) 317 r = -EIO; 318 319 out: 320 spin_unlock_bh(&sc->sc_pcu_lock); 321 tasklet_enable(&sc->intr_tq); 322 323 return r; 324 } 325 326 327 /* 328 * Set/change channels. If the channel is really being changed, it's done 329 * by reseting the chip. To accomplish this we must first cleanup any pending 330 * DMA, then restart stuff. 331 */ 332 static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chandef) 333 { 334 struct ath_hw *ah = sc->sc_ah; 335 struct ath_common *common = ath9k_hw_common(ah); 336 struct ieee80211_hw *hw = sc->hw; 337 struct ath9k_channel *hchan; 338 struct ieee80211_channel *chan = chandef->chan; 339 unsigned long flags; 340 bool offchannel; 341 int pos = chan->hw_value; 342 int old_pos = -1; 343 int r; 344 345 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 346 return -EIO; 347 348 offchannel = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL); 349 350 if (ah->curchan) 351 old_pos = ah->curchan - &ah->channels[0]; 352 353 ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n", 354 chan->center_freq, chandef->width); 355 356 /* update survey stats for the old channel before switching */ 357 spin_lock_irqsave(&common->cc_lock, flags); 358 ath_update_survey_stats(sc); 359 spin_unlock_irqrestore(&common->cc_lock, flags); 360 361 ath9k_cmn_get_channel(hw, ah, chandef); 362 363 /* 364 * If the operating channel changes, change the survey in-use flags 365 * along with it. 366 * Reset the survey data for the new channel, unless we're switching 367 * back to the operating channel from an off-channel operation. 368 */ 369 if (!offchannel && sc->cur_survey != &sc->survey[pos]) { 370 if (sc->cur_survey) 371 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; 372 373 sc->cur_survey = &sc->survey[pos]; 374 375 memset(sc->cur_survey, 0, sizeof(struct survey_info)); 376 sc->cur_survey->filled |= SURVEY_INFO_IN_USE; 377 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { 378 memset(&sc->survey[pos], 0, sizeof(struct survey_info)); 379 } 380 381 hchan = &sc->sc_ah->channels[pos]; 382 r = ath_reset_internal(sc, hchan); 383 if (r) 384 return r; 385 386 /* 387 * The most recent snapshot of channel->noisefloor for the old 388 * channel is only available after the hardware reset. Copy it to 389 * the survey stats now. 390 */ 391 if (old_pos >= 0) 392 ath_update_survey_nf(sc, old_pos); 393 394 /* 395 * Enable radar pulse detection if on a DFS channel. Spectral 396 * scanning and radar detection can not be used concurrently. 397 */ 398 if (hw->conf.radar_enabled) { 399 u32 rxfilter; 400 401 /* set HW specific DFS configuration */ 402 ath9k_hw_set_radar_params(ah); 403 rxfilter = ath9k_hw_getrxfilter(ah); 404 rxfilter |= ATH9K_RX_FILTER_PHYRADAR | 405 ATH9K_RX_FILTER_PHYERR; 406 ath9k_hw_setrxfilter(ah, rxfilter); 407 ath_dbg(common, DFS, "DFS enabled at freq %d\n", 408 chan->center_freq); 409 } else { 410 /* perform spectral scan if requested. */ 411 if (test_bit(SC_OP_SCANNING, &sc->sc_flags) && 412 sc->spectral_mode == SPECTRAL_CHANSCAN) 413 ath9k_spectral_scan_trigger(hw); 414 } 415 416 return 0; 417 } 418 419 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 420 struct ieee80211_vif *vif) 421 { 422 struct ath_node *an; 423 an = (struct ath_node *)sta->drv_priv; 424 425 an->sc = sc; 426 an->sta = sta; 427 an->vif = vif; 428 429 ath_tx_node_init(sc, an); 430 431 if (sta->ht_cap.ht_supported) { 432 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 433 sta->ht_cap.ampdu_factor); 434 an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 435 } 436 } 437 438 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 439 { 440 struct ath_node *an = (struct ath_node *)sta->drv_priv; 441 ath_tx_node_cleanup(sc, an); 442 } 443 444 void ath9k_tasklet(unsigned long data) 445 { 446 struct ath_softc *sc = (struct ath_softc *)data; 447 struct ath_hw *ah = sc->sc_ah; 448 struct ath_common *common = ath9k_hw_common(ah); 449 enum ath_reset_type type; 450 unsigned long flags; 451 u32 status = sc->intrstatus; 452 u32 rxmask; 453 454 ath9k_ps_wakeup(sc); 455 spin_lock(&sc->sc_pcu_lock); 456 457 if ((status & ATH9K_INT_FATAL) || 458 (status & ATH9K_INT_BB_WATCHDOG)) { 459 460 if (status & ATH9K_INT_FATAL) 461 type = RESET_TYPE_FATAL_INT; 462 else 463 type = RESET_TYPE_BB_WATCHDOG; 464 465 ath9k_queue_reset(sc, type); 466 467 /* 468 * Increment the ref. counter here so that 469 * interrupts are enabled in the reset routine. 470 */ 471 atomic_inc(&ah->intr_ref_cnt); 472 ath_dbg(common, ANY, "FATAL: Skipping interrupts\n"); 473 goto out; 474 } 475 476 spin_lock_irqsave(&sc->sc_pm_lock, flags); 477 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 478 /* 479 * TSF sync does not look correct; remain awake to sync with 480 * the next Beacon. 481 */ 482 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 483 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 484 } 485 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 486 487 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 488 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 489 ATH9K_INT_RXORN); 490 else 491 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 492 493 if (status & rxmask) { 494 /* Check for high priority Rx first */ 495 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 496 (status & ATH9K_INT_RXHP)) 497 ath_rx_tasklet(sc, 0, true); 498 499 ath_rx_tasklet(sc, 0, false); 500 } 501 502 if (status & ATH9K_INT_TX) { 503 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 504 ath_tx_edma_tasklet(sc); 505 else 506 ath_tx_tasklet(sc); 507 508 wake_up(&sc->tx_wait); 509 } 510 511 ath9k_btcoex_handle_interrupt(sc, status); 512 513 /* re-enable hardware interrupt */ 514 ath9k_hw_enable_interrupts(ah); 515 out: 516 spin_unlock(&sc->sc_pcu_lock); 517 ath9k_ps_restore(sc); 518 } 519 520 irqreturn_t ath_isr(int irq, void *dev) 521 { 522 #define SCHED_INTR ( \ 523 ATH9K_INT_FATAL | \ 524 ATH9K_INT_BB_WATCHDOG | \ 525 ATH9K_INT_RXORN | \ 526 ATH9K_INT_RXEOL | \ 527 ATH9K_INT_RX | \ 528 ATH9K_INT_RXLP | \ 529 ATH9K_INT_RXHP | \ 530 ATH9K_INT_TX | \ 531 ATH9K_INT_BMISS | \ 532 ATH9K_INT_CST | \ 533 ATH9K_INT_TSFOOR | \ 534 ATH9K_INT_GENTIMER | \ 535 ATH9K_INT_MCI) 536 537 struct ath_softc *sc = dev; 538 struct ath_hw *ah = sc->sc_ah; 539 struct ath_common *common = ath9k_hw_common(ah); 540 enum ath9k_int status; 541 bool sched = false; 542 543 /* 544 * The hardware is not ready/present, don't 545 * touch anything. Note this can happen early 546 * on if the IRQ is shared. 547 */ 548 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 549 return IRQ_NONE; 550 551 /* shared irq, not for us */ 552 553 if (!ath9k_hw_intrpend(ah)) 554 return IRQ_NONE; 555 556 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { 557 ath9k_hw_kill_interrupts(ah); 558 return IRQ_HANDLED; 559 } 560 561 /* 562 * Figure out the reason(s) for the interrupt. Note 563 * that the hal returns a pseudo-ISR that may include 564 * bits we haven't explicitly enabled so we mask the 565 * value to insure we only process bits we requested. 566 */ 567 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 568 status &= ah->imask; /* discard unasked-for bits */ 569 570 /* 571 * If there are no status bits set, then this interrupt was not 572 * for me (should have been caught above). 573 */ 574 if (!status) 575 return IRQ_NONE; 576 577 /* Cache the status */ 578 sc->intrstatus = status; 579 580 if (status & SCHED_INTR) 581 sched = true; 582 583 /* 584 * If a FATAL or RXORN interrupt is received, we have to reset the 585 * chip immediately. 586 */ 587 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 588 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 589 goto chip_reset; 590 591 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 592 (status & ATH9K_INT_BB_WATCHDOG)) { 593 594 spin_lock(&common->cc_lock); 595 ath_hw_cycle_counters_update(common); 596 ar9003_hw_bb_watchdog_dbg_info(ah); 597 spin_unlock(&common->cc_lock); 598 599 goto chip_reset; 600 } 601 602 #ifdef CONFIG_ATH9K_WOW 603 if (status & ATH9K_INT_BMISS) { 604 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 605 ath_dbg(common, ANY, "during WoW we got a BMISS\n"); 606 atomic_inc(&sc->wow_got_bmiss_intr); 607 atomic_dec(&sc->wow_sleep_proc_intr); 608 } 609 } 610 #endif 611 612 613 if (status & ATH9K_INT_SWBA) 614 tasklet_schedule(&sc->bcon_tasklet); 615 616 if (status & ATH9K_INT_TXURN) 617 ath9k_hw_updatetxtriglevel(ah, true); 618 619 if (status & ATH9K_INT_RXEOL) { 620 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 621 ath9k_hw_set_interrupts(ah); 622 } 623 624 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 625 if (status & ATH9K_INT_TIM_TIMER) { 626 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 627 goto chip_reset; 628 /* Clear RxAbort bit so that we can 629 * receive frames */ 630 ath9k_setpower(sc, ATH9K_PM_AWAKE); 631 spin_lock(&sc->sc_pm_lock); 632 ath9k_hw_setrxabort(sc->sc_ah, 0); 633 sc->ps_flags |= PS_WAIT_FOR_BEACON; 634 spin_unlock(&sc->sc_pm_lock); 635 } 636 637 chip_reset: 638 639 ath_debug_stat_interrupt(sc, status); 640 641 if (sched) { 642 /* turn off every interrupt */ 643 ath9k_hw_disable_interrupts(ah); 644 tasklet_schedule(&sc->intr_tq); 645 } 646 647 return IRQ_HANDLED; 648 649 #undef SCHED_INTR 650 } 651 652 int ath_reset(struct ath_softc *sc) 653 { 654 int r; 655 656 ath9k_ps_wakeup(sc); 657 r = ath_reset_internal(sc, NULL); 658 ath9k_ps_restore(sc); 659 660 return r; 661 } 662 663 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 664 { 665 #ifdef CONFIG_ATH9K_DEBUGFS 666 RESET_STAT_INC(sc, type); 667 #endif 668 set_bit(SC_OP_HW_RESET, &sc->sc_flags); 669 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 670 } 671 672 void ath_reset_work(struct work_struct *work) 673 { 674 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 675 676 ath_reset(sc); 677 } 678 679 /**********************/ 680 /* mac80211 callbacks */ 681 /**********************/ 682 683 static int ath9k_start(struct ieee80211_hw *hw) 684 { 685 struct ath_softc *sc = hw->priv; 686 struct ath_hw *ah = sc->sc_ah; 687 struct ath_common *common = ath9k_hw_common(ah); 688 struct ieee80211_channel *curchan = hw->conf.chandef.chan; 689 struct ath9k_channel *init_channel; 690 int r; 691 692 ath_dbg(common, CONFIG, 693 "Starting driver with initial channel: %d MHz\n", 694 curchan->center_freq); 695 696 ath9k_ps_wakeup(sc); 697 mutex_lock(&sc->mutex); 698 699 init_channel = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); 700 701 /* Reset SERDES registers */ 702 ath9k_hw_configpcipowersave(ah, false); 703 704 /* 705 * The basic interface to setting the hardware in a good 706 * state is ``reset''. On return the hardware is known to 707 * be powered up and with interrupts disabled. This must 708 * be followed by initialization of the appropriate bits 709 * and then setup of the interrupt mask. 710 */ 711 spin_lock_bh(&sc->sc_pcu_lock); 712 713 atomic_set(&ah->intr_ref_cnt, -1); 714 715 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 716 if (r) { 717 ath_err(common, 718 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 719 r, curchan->center_freq); 720 ah->reset_power_on = false; 721 } 722 723 /* Setup our intr mask. */ 724 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 725 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 726 ATH9K_INT_GLOBAL; 727 728 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 729 ah->imask |= ATH9K_INT_RXHP | 730 ATH9K_INT_RXLP | 731 ATH9K_INT_BB_WATCHDOG; 732 else 733 ah->imask |= ATH9K_INT_RX; 734 735 ah->imask |= ATH9K_INT_GTT; 736 737 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 738 ah->imask |= ATH9K_INT_CST; 739 740 ath_mci_enable(sc); 741 742 clear_bit(SC_OP_INVALID, &sc->sc_flags); 743 sc->sc_ah->is_monitoring = false; 744 745 if (!ath_complete_reset(sc, false)) 746 ah->reset_power_on = false; 747 748 if (ah->led_pin >= 0) { 749 ath9k_hw_cfg_output(ah, ah->led_pin, 750 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 751 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 752 } 753 754 /* 755 * Reset key cache to sane defaults (all entries cleared) instead of 756 * semi-random values after suspend/resume. 757 */ 758 ath9k_cmn_init_crypto(sc->sc_ah); 759 760 spin_unlock_bh(&sc->sc_pcu_lock); 761 762 mutex_unlock(&sc->mutex); 763 764 ath9k_ps_restore(sc); 765 766 return 0; 767 } 768 769 static void ath9k_tx(struct ieee80211_hw *hw, 770 struct ieee80211_tx_control *control, 771 struct sk_buff *skb) 772 { 773 struct ath_softc *sc = hw->priv; 774 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 775 struct ath_tx_control txctl; 776 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 777 unsigned long flags; 778 779 if (sc->ps_enabled) { 780 /* 781 * mac80211 does not set PM field for normal data frames, so we 782 * need to update that based on the current PS mode. 783 */ 784 if (ieee80211_is_data(hdr->frame_control) && 785 !ieee80211_is_nullfunc(hdr->frame_control) && 786 !ieee80211_has_pm(hdr->frame_control)) { 787 ath_dbg(common, PS, 788 "Add PM=1 for a TX frame while in PS mode\n"); 789 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 790 } 791 } 792 793 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 794 /* 795 * We are using PS-Poll and mac80211 can request TX while in 796 * power save mode. Need to wake up hardware for the TX to be 797 * completed and if needed, also for RX of buffered frames. 798 */ 799 ath9k_ps_wakeup(sc); 800 spin_lock_irqsave(&sc->sc_pm_lock, flags); 801 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 802 ath9k_hw_setrxabort(sc->sc_ah, 0); 803 if (ieee80211_is_pspoll(hdr->frame_control)) { 804 ath_dbg(common, PS, 805 "Sending PS-Poll to pick a buffered frame\n"); 806 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 807 } else { 808 ath_dbg(common, PS, "Wake up to complete TX\n"); 809 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 810 } 811 /* 812 * The actual restore operation will happen only after 813 * the ps_flags bit is cleared. We are just dropping 814 * the ps_usecount here. 815 */ 816 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 817 ath9k_ps_restore(sc); 818 } 819 820 /* 821 * Cannot tx while the hardware is in full sleep, it first needs a full 822 * chip reset to recover from that 823 */ 824 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 825 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 826 goto exit; 827 } 828 829 memset(&txctl, 0, sizeof(struct ath_tx_control)); 830 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 831 txctl.sta = control->sta; 832 833 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 834 835 if (ath_tx_start(hw, skb, &txctl) != 0) { 836 ath_dbg(common, XMIT, "TX failed\n"); 837 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 838 goto exit; 839 } 840 841 return; 842 exit: 843 ieee80211_free_txskb(hw, skb); 844 } 845 846 static void ath9k_stop(struct ieee80211_hw *hw) 847 { 848 struct ath_softc *sc = hw->priv; 849 struct ath_hw *ah = sc->sc_ah; 850 struct ath_common *common = ath9k_hw_common(ah); 851 bool prev_idle; 852 853 mutex_lock(&sc->mutex); 854 855 ath_cancel_work(sc); 856 del_timer_sync(&sc->rx_poll_timer); 857 858 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 859 ath_dbg(common, ANY, "Device not present\n"); 860 mutex_unlock(&sc->mutex); 861 return; 862 } 863 864 /* Ensure HW is awake when we try to shut it down. */ 865 ath9k_ps_wakeup(sc); 866 867 spin_lock_bh(&sc->sc_pcu_lock); 868 869 /* prevent tasklets to enable interrupts once we disable them */ 870 ah->imask &= ~ATH9K_INT_GLOBAL; 871 872 /* make sure h/w will not generate any interrupt 873 * before setting the invalid flag. */ 874 ath9k_hw_disable_interrupts(ah); 875 876 spin_unlock_bh(&sc->sc_pcu_lock); 877 878 /* we can now sync irq and kill any running tasklets, since we already 879 * disabled interrupts and not holding a spin lock */ 880 synchronize_irq(sc->irq); 881 tasklet_kill(&sc->intr_tq); 882 tasklet_kill(&sc->bcon_tasklet); 883 884 prev_idle = sc->ps_idle; 885 sc->ps_idle = true; 886 887 spin_lock_bh(&sc->sc_pcu_lock); 888 889 if (ah->led_pin >= 0) { 890 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 891 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 892 } 893 894 ath_prepare_reset(sc); 895 896 if (sc->rx.frag) { 897 dev_kfree_skb_any(sc->rx.frag); 898 sc->rx.frag = NULL; 899 } 900 901 if (!ah->curchan) 902 ah->curchan = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); 903 904 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 905 ath9k_hw_phy_disable(ah); 906 907 ath9k_hw_configpcipowersave(ah, true); 908 909 spin_unlock_bh(&sc->sc_pcu_lock); 910 911 ath9k_ps_restore(sc); 912 913 set_bit(SC_OP_INVALID, &sc->sc_flags); 914 sc->ps_idle = prev_idle; 915 916 mutex_unlock(&sc->mutex); 917 918 ath_dbg(common, CONFIG, "Driver halt\n"); 919 } 920 921 static bool ath9k_uses_beacons(int type) 922 { 923 switch (type) { 924 case NL80211_IFTYPE_AP: 925 case NL80211_IFTYPE_ADHOC: 926 case NL80211_IFTYPE_MESH_POINT: 927 return true; 928 default: 929 return false; 930 } 931 } 932 933 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 934 { 935 struct ath9k_vif_iter_data *iter_data = data; 936 int i; 937 938 if (iter_data->has_hw_macaddr) { 939 for (i = 0; i < ETH_ALEN; i++) 940 iter_data->mask[i] &= 941 ~(iter_data->hw_macaddr[i] ^ mac[i]); 942 } else { 943 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 944 iter_data->has_hw_macaddr = true; 945 } 946 947 switch (vif->type) { 948 case NL80211_IFTYPE_AP: 949 iter_data->naps++; 950 break; 951 case NL80211_IFTYPE_STATION: 952 iter_data->nstations++; 953 break; 954 case NL80211_IFTYPE_ADHOC: 955 iter_data->nadhocs++; 956 break; 957 case NL80211_IFTYPE_MESH_POINT: 958 iter_data->nmeshes++; 959 break; 960 case NL80211_IFTYPE_WDS: 961 iter_data->nwds++; 962 break; 963 default: 964 break; 965 } 966 } 967 968 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 969 { 970 struct ath_softc *sc = data; 971 struct ath_vif *avp = (void *)vif->drv_priv; 972 973 if (vif->type != NL80211_IFTYPE_STATION) 974 return; 975 976 if (avp->primary_sta_vif) 977 ath9k_set_assoc_state(sc, vif); 978 } 979 980 /* Called with sc->mutex held. */ 981 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 982 struct ieee80211_vif *vif, 983 struct ath9k_vif_iter_data *iter_data) 984 { 985 struct ath_softc *sc = hw->priv; 986 struct ath_hw *ah = sc->sc_ah; 987 struct ath_common *common = ath9k_hw_common(ah); 988 989 /* 990 * Use the hardware MAC address as reference, the hardware uses it 991 * together with the BSSID mask when matching addresses. 992 */ 993 memset(iter_data, 0, sizeof(*iter_data)); 994 memset(&iter_data->mask, 0xff, ETH_ALEN); 995 996 if (vif) 997 ath9k_vif_iter(iter_data, vif->addr, vif); 998 999 /* Get list of all active MAC addresses */ 1000 ieee80211_iterate_active_interfaces_atomic( 1001 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1002 ath9k_vif_iter, iter_data); 1003 1004 memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN); 1005 } 1006 1007 /* Called with sc->mutex held. */ 1008 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, 1009 struct ieee80211_vif *vif) 1010 { 1011 struct ath_softc *sc = hw->priv; 1012 struct ath_hw *ah = sc->sc_ah; 1013 struct ath_common *common = ath9k_hw_common(ah); 1014 struct ath9k_vif_iter_data iter_data; 1015 enum nl80211_iftype old_opmode = ah->opmode; 1016 1017 ath9k_calculate_iter_data(hw, vif, &iter_data); 1018 1019 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1020 ath_hw_setbssidmask(common); 1021 1022 if (iter_data.naps > 0) { 1023 ath9k_hw_set_tsfadjust(ah, true); 1024 ah->opmode = NL80211_IFTYPE_AP; 1025 } else { 1026 ath9k_hw_set_tsfadjust(ah, false); 1027 1028 if (iter_data.nmeshes) 1029 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1030 else if (iter_data.nwds) 1031 ah->opmode = NL80211_IFTYPE_AP; 1032 else if (iter_data.nadhocs) 1033 ah->opmode = NL80211_IFTYPE_ADHOC; 1034 else 1035 ah->opmode = NL80211_IFTYPE_STATION; 1036 } 1037 1038 ath9k_hw_setopmode(ah); 1039 1040 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1041 ah->imask |= ATH9K_INT_TSFOOR; 1042 else 1043 ah->imask &= ~ATH9K_INT_TSFOOR; 1044 1045 ath9k_hw_set_interrupts(ah); 1046 1047 /* 1048 * If we are changing the opmode to STATION, 1049 * a beacon sync needs to be done. 1050 */ 1051 if (ah->opmode == NL80211_IFTYPE_STATION && 1052 old_opmode == NL80211_IFTYPE_AP && 1053 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { 1054 ieee80211_iterate_active_interfaces_atomic( 1055 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1056 ath9k_sta_vif_iter, sc); 1057 } 1058 } 1059 1060 static int ath9k_add_interface(struct ieee80211_hw *hw, 1061 struct ieee80211_vif *vif) 1062 { 1063 struct ath_softc *sc = hw->priv; 1064 struct ath_hw *ah = sc->sc_ah; 1065 struct ath_common *common = ath9k_hw_common(ah); 1066 struct ath_vif *avp = (void *)vif->drv_priv; 1067 struct ath_node *an = &avp->mcast_node; 1068 1069 mutex_lock(&sc->mutex); 1070 1071 if (config_enabled(CONFIG_ATH9K_TX99)) { 1072 if (sc->nvifs >= 1) { 1073 mutex_unlock(&sc->mutex); 1074 return -EOPNOTSUPP; 1075 } 1076 sc->tx99_vif = vif; 1077 } 1078 1079 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1080 sc->nvifs++; 1081 1082 ath9k_ps_wakeup(sc); 1083 ath9k_calculate_summary_state(hw, vif); 1084 ath9k_ps_restore(sc); 1085 1086 if (ath9k_uses_beacons(vif->type)) 1087 ath9k_beacon_assign_slot(sc, vif); 1088 1089 an->sc = sc; 1090 an->sta = NULL; 1091 an->vif = vif; 1092 an->no_ps_filter = true; 1093 ath_tx_node_init(sc, an); 1094 1095 mutex_unlock(&sc->mutex); 1096 return 0; 1097 } 1098 1099 static int ath9k_change_interface(struct ieee80211_hw *hw, 1100 struct ieee80211_vif *vif, 1101 enum nl80211_iftype new_type, 1102 bool p2p) 1103 { 1104 struct ath_softc *sc = hw->priv; 1105 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1106 1107 mutex_lock(&sc->mutex); 1108 1109 if (config_enabled(CONFIG_ATH9K_TX99)) { 1110 mutex_unlock(&sc->mutex); 1111 return -EOPNOTSUPP; 1112 } 1113 1114 ath_dbg(common, CONFIG, "Change Interface\n"); 1115 1116 if (ath9k_uses_beacons(vif->type)) 1117 ath9k_beacon_remove_slot(sc, vif); 1118 1119 vif->type = new_type; 1120 vif->p2p = p2p; 1121 1122 ath9k_ps_wakeup(sc); 1123 ath9k_calculate_summary_state(hw, vif); 1124 ath9k_ps_restore(sc); 1125 1126 if (ath9k_uses_beacons(vif->type)) 1127 ath9k_beacon_assign_slot(sc, vif); 1128 1129 mutex_unlock(&sc->mutex); 1130 return 0; 1131 } 1132 1133 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1134 struct ieee80211_vif *vif) 1135 { 1136 struct ath_softc *sc = hw->priv; 1137 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1138 struct ath_vif *avp = (void *)vif->drv_priv; 1139 1140 ath_dbg(common, CONFIG, "Detach Interface\n"); 1141 1142 mutex_lock(&sc->mutex); 1143 1144 sc->nvifs--; 1145 sc->tx99_vif = NULL; 1146 1147 if (ath9k_uses_beacons(vif->type)) 1148 ath9k_beacon_remove_slot(sc, vif); 1149 1150 if (sc->csa_vif == vif) 1151 sc->csa_vif = NULL; 1152 1153 ath9k_ps_wakeup(sc); 1154 ath9k_calculate_summary_state(hw, NULL); 1155 ath9k_ps_restore(sc); 1156 1157 ath_tx_node_cleanup(sc, &avp->mcast_node); 1158 1159 mutex_unlock(&sc->mutex); 1160 } 1161 1162 static void ath9k_enable_ps(struct ath_softc *sc) 1163 { 1164 struct ath_hw *ah = sc->sc_ah; 1165 struct ath_common *common = ath9k_hw_common(ah); 1166 1167 if (config_enabled(CONFIG_ATH9K_TX99)) 1168 return; 1169 1170 sc->ps_enabled = true; 1171 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1172 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1173 ah->imask |= ATH9K_INT_TIM_TIMER; 1174 ath9k_hw_set_interrupts(ah); 1175 } 1176 ath9k_hw_setrxabort(ah, 1); 1177 } 1178 ath_dbg(common, PS, "PowerSave enabled\n"); 1179 } 1180 1181 static void ath9k_disable_ps(struct ath_softc *sc) 1182 { 1183 struct ath_hw *ah = sc->sc_ah; 1184 struct ath_common *common = ath9k_hw_common(ah); 1185 1186 if (config_enabled(CONFIG_ATH9K_TX99)) 1187 return; 1188 1189 sc->ps_enabled = false; 1190 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1191 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1192 ath9k_hw_setrxabort(ah, 0); 1193 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1194 PS_WAIT_FOR_CAB | 1195 PS_WAIT_FOR_PSPOLL_DATA | 1196 PS_WAIT_FOR_TX_ACK); 1197 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1198 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1199 ath9k_hw_set_interrupts(ah); 1200 } 1201 } 1202 ath_dbg(common, PS, "PowerSave disabled\n"); 1203 } 1204 1205 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1206 { 1207 struct ath_softc *sc = hw->priv; 1208 struct ath_hw *ah = sc->sc_ah; 1209 struct ath_common *common = ath9k_hw_common(ah); 1210 u32 rxfilter; 1211 1212 if (config_enabled(CONFIG_ATH9K_TX99)) 1213 return; 1214 1215 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1216 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1217 return; 1218 } 1219 1220 ath9k_ps_wakeup(sc); 1221 rxfilter = ath9k_hw_getrxfilter(ah); 1222 ath9k_hw_setrxfilter(ah, rxfilter | 1223 ATH9K_RX_FILTER_PHYRADAR | 1224 ATH9K_RX_FILTER_PHYERR); 1225 1226 /* TODO: usually this should not be neccesary, but for some reason 1227 * (or in some mode?) the trigger must be called after the 1228 * configuration, otherwise the register will have its values reset 1229 * (on my ar9220 to value 0x01002310) 1230 */ 1231 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1232 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1233 ath9k_ps_restore(sc); 1234 } 1235 1236 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1237 enum spectral_mode spectral_mode) 1238 { 1239 struct ath_softc *sc = hw->priv; 1240 struct ath_hw *ah = sc->sc_ah; 1241 struct ath_common *common = ath9k_hw_common(ah); 1242 1243 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1244 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1245 return -1; 1246 } 1247 1248 switch (spectral_mode) { 1249 case SPECTRAL_DISABLED: 1250 sc->spec_config.enabled = 0; 1251 break; 1252 case SPECTRAL_BACKGROUND: 1253 /* send endless samples. 1254 * TODO: is this really useful for "background"? 1255 */ 1256 sc->spec_config.endless = 1; 1257 sc->spec_config.enabled = 1; 1258 break; 1259 case SPECTRAL_CHANSCAN: 1260 case SPECTRAL_MANUAL: 1261 sc->spec_config.endless = 0; 1262 sc->spec_config.enabled = 1; 1263 break; 1264 default: 1265 return -1; 1266 } 1267 1268 ath9k_ps_wakeup(sc); 1269 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1270 ath9k_ps_restore(sc); 1271 1272 sc->spectral_mode = spectral_mode; 1273 1274 return 0; 1275 } 1276 1277 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1278 { 1279 struct ath_softc *sc = hw->priv; 1280 struct ath_hw *ah = sc->sc_ah; 1281 struct ath_common *common = ath9k_hw_common(ah); 1282 struct ieee80211_conf *conf = &hw->conf; 1283 bool reset_channel = false; 1284 1285 ath9k_ps_wakeup(sc); 1286 mutex_lock(&sc->mutex); 1287 1288 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1289 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1290 if (sc->ps_idle) { 1291 ath_cancel_work(sc); 1292 ath9k_stop_btcoex(sc); 1293 } else { 1294 ath9k_start_btcoex(sc); 1295 /* 1296 * The chip needs a reset to properly wake up from 1297 * full sleep 1298 */ 1299 reset_channel = ah->chip_fullsleep; 1300 } 1301 } 1302 1303 /* 1304 * We just prepare to enable PS. We have to wait until our AP has 1305 * ACK'd our null data frame to disable RX otherwise we'll ignore 1306 * those ACKs and end up retransmitting the same null data frames. 1307 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1308 */ 1309 if (changed & IEEE80211_CONF_CHANGE_PS) { 1310 unsigned long flags; 1311 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1312 if (conf->flags & IEEE80211_CONF_PS) 1313 ath9k_enable_ps(sc); 1314 else 1315 ath9k_disable_ps(sc); 1316 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1317 } 1318 1319 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1320 if (conf->flags & IEEE80211_CONF_MONITOR) { 1321 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1322 sc->sc_ah->is_monitoring = true; 1323 } else { 1324 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1325 sc->sc_ah->is_monitoring = false; 1326 } 1327 } 1328 1329 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { 1330 if (ath_set_channel(sc, &hw->conf.chandef) < 0) { 1331 ath_err(common, "Unable to set channel\n"); 1332 mutex_unlock(&sc->mutex); 1333 ath9k_ps_restore(sc); 1334 return -EINVAL; 1335 } 1336 } 1337 1338 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1339 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1340 sc->config.txpowlimit = 2 * conf->power_level; 1341 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1342 sc->config.txpowlimit, &sc->curtxpow); 1343 } 1344 1345 mutex_unlock(&sc->mutex); 1346 ath9k_ps_restore(sc); 1347 1348 return 0; 1349 } 1350 1351 #define SUPPORTED_FILTERS \ 1352 (FIF_PROMISC_IN_BSS | \ 1353 FIF_ALLMULTI | \ 1354 FIF_CONTROL | \ 1355 FIF_PSPOLL | \ 1356 FIF_OTHER_BSS | \ 1357 FIF_BCN_PRBRESP_PROMISC | \ 1358 FIF_PROBE_REQ | \ 1359 FIF_FCSFAIL) 1360 1361 /* FIXME: sc->sc_full_reset ? */ 1362 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1363 unsigned int changed_flags, 1364 unsigned int *total_flags, 1365 u64 multicast) 1366 { 1367 struct ath_softc *sc = hw->priv; 1368 u32 rfilt; 1369 1370 changed_flags &= SUPPORTED_FILTERS; 1371 *total_flags &= SUPPORTED_FILTERS; 1372 1373 sc->rx.rxfilter = *total_flags; 1374 ath9k_ps_wakeup(sc); 1375 rfilt = ath_calcrxfilter(sc); 1376 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1377 ath9k_ps_restore(sc); 1378 1379 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1380 rfilt); 1381 } 1382 1383 static int ath9k_sta_add(struct ieee80211_hw *hw, 1384 struct ieee80211_vif *vif, 1385 struct ieee80211_sta *sta) 1386 { 1387 struct ath_softc *sc = hw->priv; 1388 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1389 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1390 struct ieee80211_key_conf ps_key = { }; 1391 int key; 1392 1393 ath_node_attach(sc, sta, vif); 1394 1395 if (vif->type != NL80211_IFTYPE_AP && 1396 vif->type != NL80211_IFTYPE_AP_VLAN) 1397 return 0; 1398 1399 key = ath_key_config(common, vif, sta, &ps_key); 1400 if (key > 0) 1401 an->ps_key = key; 1402 1403 return 0; 1404 } 1405 1406 static void ath9k_del_ps_key(struct ath_softc *sc, 1407 struct ieee80211_vif *vif, 1408 struct ieee80211_sta *sta) 1409 { 1410 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1411 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1412 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1413 1414 if (!an->ps_key) 1415 return; 1416 1417 ath_key_delete(common, &ps_key); 1418 an->ps_key = 0; 1419 } 1420 1421 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1422 struct ieee80211_vif *vif, 1423 struct ieee80211_sta *sta) 1424 { 1425 struct ath_softc *sc = hw->priv; 1426 1427 ath9k_del_ps_key(sc, vif, sta); 1428 ath_node_detach(sc, sta); 1429 1430 return 0; 1431 } 1432 1433 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1434 struct ieee80211_vif *vif, 1435 enum sta_notify_cmd cmd, 1436 struct ieee80211_sta *sta) 1437 { 1438 struct ath_softc *sc = hw->priv; 1439 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1440 1441 switch (cmd) { 1442 case STA_NOTIFY_SLEEP: 1443 an->sleeping = true; 1444 ath_tx_aggr_sleep(sta, sc, an); 1445 break; 1446 case STA_NOTIFY_AWAKE: 1447 an->sleeping = false; 1448 ath_tx_aggr_wakeup(sc, an); 1449 break; 1450 } 1451 } 1452 1453 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1454 struct ieee80211_vif *vif, u16 queue, 1455 const struct ieee80211_tx_queue_params *params) 1456 { 1457 struct ath_softc *sc = hw->priv; 1458 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1459 struct ath_txq *txq; 1460 struct ath9k_tx_queue_info qi; 1461 int ret = 0; 1462 1463 if (queue >= IEEE80211_NUM_ACS) 1464 return 0; 1465 1466 txq = sc->tx.txq_map[queue]; 1467 1468 ath9k_ps_wakeup(sc); 1469 mutex_lock(&sc->mutex); 1470 1471 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1472 1473 qi.tqi_aifs = params->aifs; 1474 qi.tqi_cwmin = params->cw_min; 1475 qi.tqi_cwmax = params->cw_max; 1476 qi.tqi_burstTime = params->txop * 32; 1477 1478 ath_dbg(common, CONFIG, 1479 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1480 queue, txq->axq_qnum, params->aifs, params->cw_min, 1481 params->cw_max, params->txop); 1482 1483 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1484 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1485 if (ret) 1486 ath_err(common, "TXQ Update failed\n"); 1487 1488 mutex_unlock(&sc->mutex); 1489 ath9k_ps_restore(sc); 1490 1491 return ret; 1492 } 1493 1494 static int ath9k_set_key(struct ieee80211_hw *hw, 1495 enum set_key_cmd cmd, 1496 struct ieee80211_vif *vif, 1497 struct ieee80211_sta *sta, 1498 struct ieee80211_key_conf *key) 1499 { 1500 struct ath_softc *sc = hw->priv; 1501 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1502 int ret = 0; 1503 1504 if (ath9k_modparam_nohwcrypt) 1505 return -ENOSPC; 1506 1507 if ((vif->type == NL80211_IFTYPE_ADHOC || 1508 vif->type == NL80211_IFTYPE_MESH_POINT) && 1509 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1510 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1511 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1512 /* 1513 * For now, disable hw crypto for the RSN IBSS group keys. This 1514 * could be optimized in the future to use a modified key cache 1515 * design to support per-STA RX GTK, but until that gets 1516 * implemented, use of software crypto for group addressed 1517 * frames is a acceptable to allow RSN IBSS to be used. 1518 */ 1519 return -EOPNOTSUPP; 1520 } 1521 1522 mutex_lock(&sc->mutex); 1523 ath9k_ps_wakeup(sc); 1524 ath_dbg(common, CONFIG, "Set HW Key\n"); 1525 1526 switch (cmd) { 1527 case SET_KEY: 1528 if (sta) 1529 ath9k_del_ps_key(sc, vif, sta); 1530 1531 ret = ath_key_config(common, vif, sta, key); 1532 if (ret >= 0) { 1533 key->hw_key_idx = ret; 1534 /* push IV and Michael MIC generation to stack */ 1535 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1536 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1537 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1538 if (sc->sc_ah->sw_mgmt_crypto && 1539 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1540 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1541 ret = 0; 1542 } 1543 break; 1544 case DISABLE_KEY: 1545 ath_key_delete(common, key); 1546 break; 1547 default: 1548 ret = -EINVAL; 1549 } 1550 1551 ath9k_ps_restore(sc); 1552 mutex_unlock(&sc->mutex); 1553 1554 return ret; 1555 } 1556 1557 static void ath9k_set_assoc_state(struct ath_softc *sc, 1558 struct ieee80211_vif *vif) 1559 { 1560 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1561 struct ath_vif *avp = (void *)vif->drv_priv; 1562 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1563 unsigned long flags; 1564 1565 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1566 avp->primary_sta_vif = true; 1567 1568 /* 1569 * Set the AID, BSSID and do beacon-sync only when 1570 * the HW opmode is STATION. 1571 * 1572 * But the primary bit is set above in any case. 1573 */ 1574 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 1575 return; 1576 1577 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1578 common->curaid = bss_conf->aid; 1579 ath9k_hw_write_associd(sc->sc_ah); 1580 1581 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1582 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1583 1584 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1585 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1586 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1587 1588 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1589 ath9k_mci_update_wlan_channels(sc, false); 1590 1591 ath_dbg(common, CONFIG, 1592 "Primary Station interface: %pM, BSSID: %pM\n", 1593 vif->addr, common->curbssid); 1594 } 1595 1596 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 1597 { 1598 struct ath_softc *sc = data; 1599 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1600 1601 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) 1602 return; 1603 1604 if (bss_conf->assoc) 1605 ath9k_set_assoc_state(sc, vif); 1606 } 1607 1608 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1609 struct ieee80211_vif *vif, 1610 struct ieee80211_bss_conf *bss_conf, 1611 u32 changed) 1612 { 1613 #define CHECK_ANI \ 1614 (BSS_CHANGED_ASSOC | \ 1615 BSS_CHANGED_IBSS | \ 1616 BSS_CHANGED_BEACON_ENABLED) 1617 1618 struct ath_softc *sc = hw->priv; 1619 struct ath_hw *ah = sc->sc_ah; 1620 struct ath_common *common = ath9k_hw_common(ah); 1621 struct ath_vif *avp = (void *)vif->drv_priv; 1622 int slottime; 1623 1624 ath9k_ps_wakeup(sc); 1625 mutex_lock(&sc->mutex); 1626 1627 if (changed & BSS_CHANGED_ASSOC) { 1628 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1629 bss_conf->bssid, bss_conf->assoc); 1630 1631 if (avp->primary_sta_vif && !bss_conf->assoc) { 1632 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); 1633 avp->primary_sta_vif = false; 1634 1635 if (ah->opmode == NL80211_IFTYPE_STATION) 1636 clear_bit(SC_OP_BEACONS, &sc->sc_flags); 1637 } 1638 1639 ieee80211_iterate_active_interfaces_atomic( 1640 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 1641 ath9k_bss_assoc_iter, sc); 1642 1643 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && 1644 ah->opmode == NL80211_IFTYPE_STATION) { 1645 memset(common->curbssid, 0, ETH_ALEN); 1646 common->curaid = 0; 1647 ath9k_hw_write_associd(sc->sc_ah); 1648 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1649 ath9k_mci_update_wlan_channels(sc, true); 1650 } 1651 } 1652 1653 if (changed & BSS_CHANGED_IBSS) { 1654 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1655 common->curaid = bss_conf->aid; 1656 ath9k_hw_write_associd(sc->sc_ah); 1657 } 1658 1659 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1660 (changed & BSS_CHANGED_BEACON_INT)) { 1661 if (ah->opmode == NL80211_IFTYPE_AP && 1662 bss_conf->enable_beacon) 1663 ath9k_set_tsfadjust(sc, vif); 1664 if (ath9k_allow_beacon_config(sc, vif)) 1665 ath9k_beacon_config(sc, vif, changed); 1666 } 1667 1668 if (changed & BSS_CHANGED_ERP_SLOT) { 1669 if (bss_conf->use_short_slot) 1670 slottime = 9; 1671 else 1672 slottime = 20; 1673 if (vif->type == NL80211_IFTYPE_AP) { 1674 /* 1675 * Defer update, so that connected stations can adjust 1676 * their settings at the same time. 1677 * See beacon.c for more details 1678 */ 1679 sc->beacon.slottime = slottime; 1680 sc->beacon.updateslot = UPDATE; 1681 } else { 1682 ah->slottime = slottime; 1683 ath9k_hw_init_global_settings(ah); 1684 } 1685 } 1686 1687 if (changed & CHECK_ANI) 1688 ath_check_ani(sc); 1689 1690 mutex_unlock(&sc->mutex); 1691 ath9k_ps_restore(sc); 1692 1693 #undef CHECK_ANI 1694 } 1695 1696 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1697 { 1698 struct ath_softc *sc = hw->priv; 1699 u64 tsf; 1700 1701 mutex_lock(&sc->mutex); 1702 ath9k_ps_wakeup(sc); 1703 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1704 ath9k_ps_restore(sc); 1705 mutex_unlock(&sc->mutex); 1706 1707 return tsf; 1708 } 1709 1710 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1711 struct ieee80211_vif *vif, 1712 u64 tsf) 1713 { 1714 struct ath_softc *sc = hw->priv; 1715 1716 mutex_lock(&sc->mutex); 1717 ath9k_ps_wakeup(sc); 1718 ath9k_hw_settsf64(sc->sc_ah, tsf); 1719 ath9k_ps_restore(sc); 1720 mutex_unlock(&sc->mutex); 1721 } 1722 1723 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1724 { 1725 struct ath_softc *sc = hw->priv; 1726 1727 mutex_lock(&sc->mutex); 1728 1729 ath9k_ps_wakeup(sc); 1730 ath9k_hw_reset_tsf(sc->sc_ah); 1731 ath9k_ps_restore(sc); 1732 1733 mutex_unlock(&sc->mutex); 1734 } 1735 1736 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1737 struct ieee80211_vif *vif, 1738 enum ieee80211_ampdu_mlme_action action, 1739 struct ieee80211_sta *sta, 1740 u16 tid, u16 *ssn, u8 buf_size) 1741 { 1742 struct ath_softc *sc = hw->priv; 1743 bool flush = false; 1744 int ret = 0; 1745 1746 mutex_lock(&sc->mutex); 1747 1748 switch (action) { 1749 case IEEE80211_AMPDU_RX_START: 1750 break; 1751 case IEEE80211_AMPDU_RX_STOP: 1752 break; 1753 case IEEE80211_AMPDU_TX_START: 1754 ath9k_ps_wakeup(sc); 1755 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1756 if (!ret) 1757 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1758 ath9k_ps_restore(sc); 1759 break; 1760 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1761 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1762 flush = true; 1763 case IEEE80211_AMPDU_TX_STOP_CONT: 1764 ath9k_ps_wakeup(sc); 1765 ath_tx_aggr_stop(sc, sta, tid); 1766 if (!flush) 1767 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1768 ath9k_ps_restore(sc); 1769 break; 1770 case IEEE80211_AMPDU_TX_OPERATIONAL: 1771 ath9k_ps_wakeup(sc); 1772 ath_tx_aggr_resume(sc, sta, tid); 1773 ath9k_ps_restore(sc); 1774 break; 1775 default: 1776 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1777 } 1778 1779 mutex_unlock(&sc->mutex); 1780 1781 return ret; 1782 } 1783 1784 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1785 struct survey_info *survey) 1786 { 1787 struct ath_softc *sc = hw->priv; 1788 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1789 struct ieee80211_supported_band *sband; 1790 struct ieee80211_channel *chan; 1791 unsigned long flags; 1792 int pos; 1793 1794 if (config_enabled(CONFIG_ATH9K_TX99)) 1795 return -EOPNOTSUPP; 1796 1797 spin_lock_irqsave(&common->cc_lock, flags); 1798 if (idx == 0) 1799 ath_update_survey_stats(sc); 1800 1801 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1802 if (sband && idx >= sband->n_channels) { 1803 idx -= sband->n_channels; 1804 sband = NULL; 1805 } 1806 1807 if (!sband) 1808 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1809 1810 if (!sband || idx >= sband->n_channels) { 1811 spin_unlock_irqrestore(&common->cc_lock, flags); 1812 return -ENOENT; 1813 } 1814 1815 chan = &sband->channels[idx]; 1816 pos = chan->hw_value; 1817 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1818 survey->channel = chan; 1819 spin_unlock_irqrestore(&common->cc_lock, flags); 1820 1821 return 0; 1822 } 1823 1824 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1825 { 1826 struct ath_softc *sc = hw->priv; 1827 struct ath_hw *ah = sc->sc_ah; 1828 1829 if (config_enabled(CONFIG_ATH9K_TX99)) 1830 return; 1831 1832 mutex_lock(&sc->mutex); 1833 ah->coverage_class = coverage_class; 1834 1835 ath9k_ps_wakeup(sc); 1836 ath9k_hw_init_global_settings(ah); 1837 ath9k_ps_restore(sc); 1838 1839 mutex_unlock(&sc->mutex); 1840 } 1841 1842 static bool ath9k_has_tx_pending(struct ath_softc *sc) 1843 { 1844 int i, npend; 1845 1846 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1847 if (!ATH_TXQ_SETUP(sc, i)) 1848 continue; 1849 1850 if (!sc->tx.txq[i].axq_depth) 1851 continue; 1852 1853 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1854 if (npend) 1855 break; 1856 } 1857 1858 return !!npend; 1859 } 1860 1861 static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1862 { 1863 struct ath_softc *sc = hw->priv; 1864 struct ath_hw *ah = sc->sc_ah; 1865 struct ath_common *common = ath9k_hw_common(ah); 1866 int timeout = HZ / 5; /* 200 ms */ 1867 bool drain_txq; 1868 1869 mutex_lock(&sc->mutex); 1870 cancel_delayed_work_sync(&sc->tx_complete_work); 1871 1872 if (ah->ah_flags & AH_UNPLUGGED) { 1873 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1874 mutex_unlock(&sc->mutex); 1875 return; 1876 } 1877 1878 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { 1879 ath_dbg(common, ANY, "Device not present\n"); 1880 mutex_unlock(&sc->mutex); 1881 return; 1882 } 1883 1884 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), 1885 timeout) > 0) 1886 drop = false; 1887 1888 if (drop) { 1889 ath9k_ps_wakeup(sc); 1890 spin_lock_bh(&sc->sc_pcu_lock); 1891 drain_txq = ath_drain_all_txq(sc); 1892 spin_unlock_bh(&sc->sc_pcu_lock); 1893 1894 if (!drain_txq) 1895 ath_reset(sc); 1896 1897 ath9k_ps_restore(sc); 1898 ieee80211_wake_queues(hw); 1899 } 1900 1901 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1902 mutex_unlock(&sc->mutex); 1903 } 1904 1905 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1906 { 1907 struct ath_softc *sc = hw->priv; 1908 int i; 1909 1910 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1911 if (!ATH_TXQ_SETUP(sc, i)) 1912 continue; 1913 1914 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1915 return true; 1916 } 1917 return false; 1918 } 1919 1920 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1921 { 1922 struct ath_softc *sc = hw->priv; 1923 struct ath_hw *ah = sc->sc_ah; 1924 struct ieee80211_vif *vif; 1925 struct ath_vif *avp; 1926 struct ath_buf *bf; 1927 struct ath_tx_status ts; 1928 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1929 int status; 1930 1931 vif = sc->beacon.bslot[0]; 1932 if (!vif) 1933 return 0; 1934 1935 if (!vif->bss_conf.enable_beacon) 1936 return 0; 1937 1938 avp = (void *)vif->drv_priv; 1939 1940 if (!sc->beacon.tx_processed && !edma) { 1941 tasklet_disable(&sc->bcon_tasklet); 1942 1943 bf = avp->av_bcbuf; 1944 if (!bf || !bf->bf_mpdu) 1945 goto skip; 1946 1947 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1948 if (status == -EINPROGRESS) 1949 goto skip; 1950 1951 sc->beacon.tx_processed = true; 1952 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 1953 1954 skip: 1955 tasklet_enable(&sc->bcon_tasklet); 1956 } 1957 1958 return sc->beacon.tx_last; 1959 } 1960 1961 static int ath9k_get_stats(struct ieee80211_hw *hw, 1962 struct ieee80211_low_level_stats *stats) 1963 { 1964 struct ath_softc *sc = hw->priv; 1965 struct ath_hw *ah = sc->sc_ah; 1966 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 1967 1968 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 1969 stats->dot11RTSFailureCount = mib_stats->rts_bad; 1970 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 1971 stats->dot11RTSSuccessCount = mib_stats->rts_good; 1972 return 0; 1973 } 1974 1975 static u32 fill_chainmask(u32 cap, u32 new) 1976 { 1977 u32 filled = 0; 1978 int i; 1979 1980 for (i = 0; cap && new; i++, cap >>= 1) { 1981 if (!(cap & BIT(0))) 1982 continue; 1983 1984 if (new & BIT(0)) 1985 filled |= BIT(i); 1986 1987 new >>= 1; 1988 } 1989 1990 return filled; 1991 } 1992 1993 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 1994 { 1995 if (AR_SREV_9300_20_OR_LATER(ah)) 1996 return true; 1997 1998 switch (val & 0x7) { 1999 case 0x1: 2000 case 0x3: 2001 case 0x7: 2002 return true; 2003 case 0x2: 2004 return (ah->caps.rx_chainmask == 1); 2005 default: 2006 return false; 2007 } 2008 } 2009 2010 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2011 { 2012 struct ath_softc *sc = hw->priv; 2013 struct ath_hw *ah = sc->sc_ah; 2014 2015 if (ah->caps.rx_chainmask != 1) 2016 rx_ant |= tx_ant; 2017 2018 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2019 return -EINVAL; 2020 2021 sc->ant_rx = rx_ant; 2022 sc->ant_tx = tx_ant; 2023 2024 if (ah->caps.rx_chainmask == 1) 2025 return 0; 2026 2027 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2028 if (AR_SREV_9100(ah)) 2029 ah->rxchainmask = 0x7; 2030 else 2031 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2032 2033 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2034 ath9k_reload_chainmask_settings(sc); 2035 2036 return 0; 2037 } 2038 2039 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2040 { 2041 struct ath_softc *sc = hw->priv; 2042 2043 *tx_ant = sc->ant_tx; 2044 *rx_ant = sc->ant_rx; 2045 return 0; 2046 } 2047 2048 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2049 { 2050 struct ath_softc *sc = hw->priv; 2051 set_bit(SC_OP_SCANNING, &sc->sc_flags); 2052 } 2053 2054 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2055 { 2056 struct ath_softc *sc = hw->priv; 2057 clear_bit(SC_OP_SCANNING, &sc->sc_flags); 2058 } 2059 2060 static void ath9k_channel_switch_beacon(struct ieee80211_hw *hw, 2061 struct ieee80211_vif *vif, 2062 struct cfg80211_chan_def *chandef) 2063 { 2064 struct ath_softc *sc = hw->priv; 2065 2066 /* mac80211 does not support CSA in multi-if cases (yet) */ 2067 if (WARN_ON(sc->csa_vif)) 2068 return; 2069 2070 sc->csa_vif = vif; 2071 } 2072 2073 struct ieee80211_ops ath9k_ops = { 2074 .tx = ath9k_tx, 2075 .start = ath9k_start, 2076 .stop = ath9k_stop, 2077 .add_interface = ath9k_add_interface, 2078 .change_interface = ath9k_change_interface, 2079 .remove_interface = ath9k_remove_interface, 2080 .config = ath9k_config, 2081 .configure_filter = ath9k_configure_filter, 2082 .sta_add = ath9k_sta_add, 2083 .sta_remove = ath9k_sta_remove, 2084 .sta_notify = ath9k_sta_notify, 2085 .conf_tx = ath9k_conf_tx, 2086 .bss_info_changed = ath9k_bss_info_changed, 2087 .set_key = ath9k_set_key, 2088 .get_tsf = ath9k_get_tsf, 2089 .set_tsf = ath9k_set_tsf, 2090 .reset_tsf = ath9k_reset_tsf, 2091 .ampdu_action = ath9k_ampdu_action, 2092 .get_survey = ath9k_get_survey, 2093 .rfkill_poll = ath9k_rfkill_poll_state, 2094 .set_coverage_class = ath9k_set_coverage_class, 2095 .flush = ath9k_flush, 2096 .tx_frames_pending = ath9k_tx_frames_pending, 2097 .tx_last_beacon = ath9k_tx_last_beacon, 2098 .release_buffered_frames = ath9k_release_buffered_frames, 2099 .get_stats = ath9k_get_stats, 2100 .set_antenna = ath9k_set_antenna, 2101 .get_antenna = ath9k_get_antenna, 2102 2103 #ifdef CONFIG_ATH9K_WOW 2104 .suspend = ath9k_suspend, 2105 .resume = ath9k_resume, 2106 .set_wakeup = ath9k_set_wakeup, 2107 #endif 2108 2109 #ifdef CONFIG_ATH9K_DEBUGFS 2110 .get_et_sset_count = ath9k_get_et_sset_count, 2111 .get_et_stats = ath9k_get_et_stats, 2112 .get_et_strings = ath9k_get_et_strings, 2113 #endif 2114 2115 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 2116 .sta_add_debugfs = ath9k_sta_add_debugfs, 2117 #endif 2118 .sw_scan_start = ath9k_sw_scan_start, 2119 .sw_scan_complete = ath9k_sw_scan_complete, 2120 .channel_switch_beacon = ath9k_channel_switch_beacon, 2121 }; 2122