1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/ath9k_platform.h> 20 #include <linux/module.h> 21 22 #include "ath9k.h" 23 24 static char *dev_info = "ath9k"; 25 26 MODULE_AUTHOR("Atheros Communications"); 27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 29 MODULE_LICENSE("Dual BSD/GPL"); 30 31 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 32 module_param_named(debug, ath9k_debug, uint, 0); 33 MODULE_PARM_DESC(debug, "Debugging mask"); 34 35 int ath9k_modparam_nohwcrypt; 36 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 37 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 38 39 int led_blink; 40 module_param_named(blink, led_blink, int, 0444); 41 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 42 43 static int ath9k_btcoex_enable; 44 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 45 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 46 47 bool is_ath9k_unloaded; 48 /* We use the hw_value as an index into our private channel structure */ 49 50 #define CHAN2G(_freq, _idx) { \ 51 .band = IEEE80211_BAND_2GHZ, \ 52 .center_freq = (_freq), \ 53 .hw_value = (_idx), \ 54 .max_power = 20, \ 55 } 56 57 #define CHAN5G(_freq, _idx) { \ 58 .band = IEEE80211_BAND_5GHZ, \ 59 .center_freq = (_freq), \ 60 .hw_value = (_idx), \ 61 .max_power = 20, \ 62 } 63 64 /* Some 2 GHz radios are actually tunable on 2312-2732 65 * on 5 MHz steps, we support the channels which we know 66 * we have calibration data for all cards though to make 67 * this static */ 68 static const struct ieee80211_channel ath9k_2ghz_chantable[] = { 69 CHAN2G(2412, 0), /* Channel 1 */ 70 CHAN2G(2417, 1), /* Channel 2 */ 71 CHAN2G(2422, 2), /* Channel 3 */ 72 CHAN2G(2427, 3), /* Channel 4 */ 73 CHAN2G(2432, 4), /* Channel 5 */ 74 CHAN2G(2437, 5), /* Channel 6 */ 75 CHAN2G(2442, 6), /* Channel 7 */ 76 CHAN2G(2447, 7), /* Channel 8 */ 77 CHAN2G(2452, 8), /* Channel 9 */ 78 CHAN2G(2457, 9), /* Channel 10 */ 79 CHAN2G(2462, 10), /* Channel 11 */ 80 CHAN2G(2467, 11), /* Channel 12 */ 81 CHAN2G(2472, 12), /* Channel 13 */ 82 CHAN2G(2484, 13), /* Channel 14 */ 83 }; 84 85 /* Some 5 GHz radios are actually tunable on XXXX-YYYY 86 * on 5 MHz steps, we support the channels which we know 87 * we have calibration data for all cards though to make 88 * this static */ 89 static const struct ieee80211_channel ath9k_5ghz_chantable[] = { 90 /* _We_ call this UNII 1 */ 91 CHAN5G(5180, 14), /* Channel 36 */ 92 CHAN5G(5200, 15), /* Channel 40 */ 93 CHAN5G(5220, 16), /* Channel 44 */ 94 CHAN5G(5240, 17), /* Channel 48 */ 95 /* _We_ call this UNII 2 */ 96 CHAN5G(5260, 18), /* Channel 52 */ 97 CHAN5G(5280, 19), /* Channel 56 */ 98 CHAN5G(5300, 20), /* Channel 60 */ 99 CHAN5G(5320, 21), /* Channel 64 */ 100 /* _We_ call this "Middle band" */ 101 CHAN5G(5500, 22), /* Channel 100 */ 102 CHAN5G(5520, 23), /* Channel 104 */ 103 CHAN5G(5540, 24), /* Channel 108 */ 104 CHAN5G(5560, 25), /* Channel 112 */ 105 CHAN5G(5580, 26), /* Channel 116 */ 106 CHAN5G(5600, 27), /* Channel 120 */ 107 CHAN5G(5620, 28), /* Channel 124 */ 108 CHAN5G(5640, 29), /* Channel 128 */ 109 CHAN5G(5660, 30), /* Channel 132 */ 110 CHAN5G(5680, 31), /* Channel 136 */ 111 CHAN5G(5700, 32), /* Channel 140 */ 112 /* _We_ call this UNII 3 */ 113 CHAN5G(5745, 33), /* Channel 149 */ 114 CHAN5G(5765, 34), /* Channel 153 */ 115 CHAN5G(5785, 35), /* Channel 157 */ 116 CHAN5G(5805, 36), /* Channel 161 */ 117 CHAN5G(5825, 37), /* Channel 165 */ 118 }; 119 120 /* Atheros hardware rate code addition for short premble */ 121 #define SHPCHECK(__hw_rate, __flags) \ 122 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) 123 124 #define RATE(_bitrate, _hw_rate, _flags) { \ 125 .bitrate = (_bitrate), \ 126 .flags = (_flags), \ 127 .hw_value = (_hw_rate), \ 128 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 129 } 130 131 static struct ieee80211_rate ath9k_legacy_rates[] = { 132 RATE(10, 0x1b, 0), 133 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), 134 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), 135 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), 136 RATE(60, 0x0b, 0), 137 RATE(90, 0x0f, 0), 138 RATE(120, 0x0a, 0), 139 RATE(180, 0x0e, 0), 140 RATE(240, 0x09, 0), 141 RATE(360, 0x0d, 0), 142 RATE(480, 0x08, 0), 143 RATE(540, 0x0c, 0), 144 }; 145 146 #ifdef CONFIG_MAC80211_LEDS 147 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 148 { .throughput = 0 * 1024, .blink_time = 334 }, 149 { .throughput = 1 * 1024, .blink_time = 260 }, 150 { .throughput = 5 * 1024, .blink_time = 220 }, 151 { .throughput = 10 * 1024, .blink_time = 190 }, 152 { .throughput = 20 * 1024, .blink_time = 170 }, 153 { .throughput = 50 * 1024, .blink_time = 150 }, 154 { .throughput = 70 * 1024, .blink_time = 130 }, 155 { .throughput = 100 * 1024, .blink_time = 110 }, 156 { .throughput = 200 * 1024, .blink_time = 80 }, 157 { .throughput = 300 * 1024, .blink_time = 50 }, 158 }; 159 #endif 160 161 static void ath9k_deinit_softc(struct ath_softc *sc); 162 163 /* 164 * Read and write, they both share the same lock. We do this to serialize 165 * reads and writes on Atheros 802.11n PCI devices only. This is required 166 * as the FIFO on these devices can only accept sanely 2 requests. 167 */ 168 169 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 170 { 171 struct ath_hw *ah = (struct ath_hw *) hw_priv; 172 struct ath_common *common = ath9k_hw_common(ah); 173 struct ath_softc *sc = (struct ath_softc *) common->priv; 174 175 if (ah->config.serialize_regmode == SER_REG_MODE_ON) { 176 unsigned long flags; 177 spin_lock_irqsave(&sc->sc_serial_rw, flags); 178 iowrite32(val, sc->mem + reg_offset); 179 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 180 } else 181 iowrite32(val, sc->mem + reg_offset); 182 } 183 184 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 185 { 186 struct ath_hw *ah = (struct ath_hw *) hw_priv; 187 struct ath_common *common = ath9k_hw_common(ah); 188 struct ath_softc *sc = (struct ath_softc *) common->priv; 189 u32 val; 190 191 if (ah->config.serialize_regmode == SER_REG_MODE_ON) { 192 unsigned long flags; 193 spin_lock_irqsave(&sc->sc_serial_rw, flags); 194 val = ioread32(sc->mem + reg_offset); 195 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 196 } else 197 val = ioread32(sc->mem + reg_offset); 198 return val; 199 } 200 201 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 202 u32 set, u32 clr) 203 { 204 u32 val; 205 206 val = ioread32(sc->mem + reg_offset); 207 val &= ~clr; 208 val |= set; 209 iowrite32(val, sc->mem + reg_offset); 210 211 return val; 212 } 213 214 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 215 { 216 struct ath_hw *ah = (struct ath_hw *) hw_priv; 217 struct ath_common *common = ath9k_hw_common(ah); 218 struct ath_softc *sc = (struct ath_softc *) common->priv; 219 unsigned long uninitialized_var(flags); 220 u32 val; 221 222 if (ah->config.serialize_regmode == SER_REG_MODE_ON) { 223 spin_lock_irqsave(&sc->sc_serial_rw, flags); 224 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 225 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 226 } else 227 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 228 229 return val; 230 } 231 232 /**************************/ 233 /* Initialization */ 234 /**************************/ 235 236 static void setup_ht_cap(struct ath_softc *sc, 237 struct ieee80211_sta_ht_cap *ht_info) 238 { 239 struct ath_hw *ah = sc->sc_ah; 240 struct ath_common *common = ath9k_hw_common(ah); 241 u8 tx_streams, rx_streams; 242 int i, max_streams; 243 244 ht_info->ht_supported = true; 245 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 246 IEEE80211_HT_CAP_SM_PS | 247 IEEE80211_HT_CAP_SGI_40 | 248 IEEE80211_HT_CAP_DSSSCCK40; 249 250 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) 251 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; 252 253 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 254 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 255 256 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 257 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 258 259 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) 260 max_streams = 1; 261 else if (AR_SREV_9462(ah)) 262 max_streams = 2; 263 else if (AR_SREV_9300_20_OR_LATER(ah)) 264 max_streams = 3; 265 else 266 max_streams = 2; 267 268 if (AR_SREV_9280_20_OR_LATER(ah)) { 269 if (max_streams >= 2) 270 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; 271 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 272 } 273 274 /* set up supported mcs set */ 275 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 276 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); 277 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); 278 279 ath_dbg(common, ATH_DBG_CONFIG, 280 "TX streams %d, RX streams: %d\n", 281 tx_streams, rx_streams); 282 283 if (tx_streams != rx_streams) { 284 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 285 ht_info->mcs.tx_params |= ((tx_streams - 1) << 286 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 287 } 288 289 for (i = 0; i < rx_streams; i++) 290 ht_info->mcs.rx_mask[i] = 0xff; 291 292 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 293 } 294 295 static int ath9k_reg_notifier(struct wiphy *wiphy, 296 struct regulatory_request *request) 297 { 298 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 299 struct ath_softc *sc = hw->priv; 300 struct ath_hw *ah = sc->sc_ah; 301 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 302 int ret; 303 304 ret = ath_reg_notifier_apply(wiphy, request, reg); 305 306 /* Set tx power */ 307 if (ah->curchan) { 308 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; 309 ath9k_ps_wakeup(sc); 310 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); 311 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; 312 ath9k_ps_restore(sc); 313 } 314 315 return ret; 316 } 317 318 /* 319 * This function will allocate both the DMA descriptor structure, and the 320 * buffers it contains. These are used to contain the descriptors used 321 * by the system. 322 */ 323 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 324 struct list_head *head, const char *name, 325 int nbuf, int ndesc, bool is_tx) 326 { 327 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 328 u8 *ds; 329 struct ath_buf *bf; 330 int i, bsize, error, desc_len; 331 332 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", 333 name, nbuf, ndesc); 334 335 INIT_LIST_HEAD(head); 336 337 if (is_tx) 338 desc_len = sc->sc_ah->caps.tx_desc_len; 339 else 340 desc_len = sizeof(struct ath_desc); 341 342 /* ath_desc must be a multiple of DWORDs */ 343 if ((desc_len % 4) != 0) { 344 ath_err(common, "ath_desc not DWORD aligned\n"); 345 BUG_ON((desc_len % 4) != 0); 346 error = -ENOMEM; 347 goto fail; 348 } 349 350 dd->dd_desc_len = desc_len * nbuf * ndesc; 351 352 /* 353 * Need additional DMA memory because we can't use 354 * descriptors that cross the 4K page boundary. Assume 355 * one skipped descriptor per 4K page. 356 */ 357 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 358 u32 ndesc_skipped = 359 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 360 u32 dma_len; 361 362 while (ndesc_skipped) { 363 dma_len = ndesc_skipped * desc_len; 364 dd->dd_desc_len += dma_len; 365 366 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 367 } 368 } 369 370 /* allocate descriptors */ 371 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, 372 &dd->dd_desc_paddr, GFP_KERNEL); 373 if (dd->dd_desc == NULL) { 374 error = -ENOMEM; 375 goto fail; 376 } 377 ds = (u8 *) dd->dd_desc; 378 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 379 name, ds, (u32) dd->dd_desc_len, 380 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 381 382 /* allocate buffers */ 383 bsize = sizeof(struct ath_buf) * nbuf; 384 bf = kzalloc(bsize, GFP_KERNEL); 385 if (bf == NULL) { 386 error = -ENOMEM; 387 goto fail2; 388 } 389 dd->dd_bufptr = bf; 390 391 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 392 bf->bf_desc = ds; 393 bf->bf_daddr = DS2PHYS(dd, ds); 394 395 if (!(sc->sc_ah->caps.hw_caps & 396 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 397 /* 398 * Skip descriptor addresses which can cause 4KB 399 * boundary crossing (addr + length) with a 32 dword 400 * descriptor fetch. 401 */ 402 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 403 BUG_ON((caddr_t) bf->bf_desc >= 404 ((caddr_t) dd->dd_desc + 405 dd->dd_desc_len)); 406 407 ds += (desc_len * ndesc); 408 bf->bf_desc = ds; 409 bf->bf_daddr = DS2PHYS(dd, ds); 410 } 411 } 412 list_add_tail(&bf->list, head); 413 } 414 return 0; 415 fail2: 416 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, 417 dd->dd_desc_paddr); 418 fail: 419 memset(dd, 0, sizeof(*dd)); 420 return error; 421 } 422 423 static int ath9k_init_btcoex(struct ath_softc *sc) 424 { 425 struct ath_txq *txq; 426 struct ath_hw *ah = sc->sc_ah; 427 int r; 428 429 switch (sc->sc_ah->btcoex_hw.scheme) { 430 case ATH_BTCOEX_CFG_NONE: 431 break; 432 case ATH_BTCOEX_CFG_2WIRE: 433 ath9k_hw_btcoex_init_2wire(sc->sc_ah); 434 break; 435 case ATH_BTCOEX_CFG_3WIRE: 436 ath9k_hw_btcoex_init_3wire(sc->sc_ah); 437 r = ath_init_btcoex_timer(sc); 438 if (r) 439 return -1; 440 txq = sc->tx.txq_map[WME_AC_BE]; 441 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); 442 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 443 break; 444 case ATH_BTCOEX_CFG_MCI: 445 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 446 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE; 447 INIT_LIST_HEAD(&sc->btcoex.mci.info); 448 449 r = ath_mci_setup(sc); 450 if (r) 451 return r; 452 453 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) { 454 ah->btcoex_hw.mci.ready = false; 455 ah->btcoex_hw.mci.bt_state = 0; 456 ah->btcoex_hw.mci.bt_ver_major = 3; 457 ah->btcoex_hw.mci.bt_ver_minor = 0; 458 ah->btcoex_hw.mci.bt_version_known = false; 459 ah->btcoex_hw.mci.update_2g5g = true; 460 ah->btcoex_hw.mci.is_2g = true; 461 ah->btcoex_hw.mci.wlan_channels_update = false; 462 ah->btcoex_hw.mci.wlan_channels[0] = 0x00000000; 463 ah->btcoex_hw.mci.wlan_channels[1] = 0xffffffff; 464 ah->btcoex_hw.mci.wlan_channels[2] = 0xffffffff; 465 ah->btcoex_hw.mci.wlan_channels[3] = 0x7fffffff; 466 ah->btcoex_hw.mci.query_bt = true; 467 ah->btcoex_hw.mci.unhalt_bt_gpm = true; 468 ah->btcoex_hw.mci.halted_bt_gpm = false; 469 ah->btcoex_hw.mci.need_flush_btinfo = false; 470 ah->btcoex_hw.mci.wlan_cal_seq = 0; 471 ah->btcoex_hw.mci.wlan_cal_done = 0; 472 ah->btcoex_hw.mci.config = 0x2201; 473 } 474 break; 475 default: 476 WARN_ON(1); 477 break; 478 } 479 480 return 0; 481 } 482 483 static int ath9k_init_queues(struct ath_softc *sc) 484 { 485 int i = 0; 486 487 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 488 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 489 490 sc->config.cabqReadytime = ATH_CABQ_READY_TIME; 491 ath_cabq_update(sc); 492 493 for (i = 0; i < WME_NUM_AC; i++) { 494 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 495 sc->tx.txq_map[i]->mac80211_qnum = i; 496 } 497 return 0; 498 } 499 500 static int ath9k_init_channels_rates(struct ath_softc *sc) 501 { 502 void *channels; 503 504 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + 505 ARRAY_SIZE(ath9k_5ghz_chantable) != 506 ATH9K_NUM_CHANNELS); 507 508 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { 509 channels = kmemdup(ath9k_2ghz_chantable, 510 sizeof(ath9k_2ghz_chantable), GFP_KERNEL); 511 if (!channels) 512 return -ENOMEM; 513 514 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; 515 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 516 sc->sbands[IEEE80211_BAND_2GHZ].n_channels = 517 ARRAY_SIZE(ath9k_2ghz_chantable); 518 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 519 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 520 ARRAY_SIZE(ath9k_legacy_rates); 521 } 522 523 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { 524 channels = kmemdup(ath9k_5ghz_chantable, 525 sizeof(ath9k_5ghz_chantable), GFP_KERNEL); 526 if (!channels) { 527 if (sc->sbands[IEEE80211_BAND_2GHZ].channels) 528 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); 529 return -ENOMEM; 530 } 531 532 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; 533 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 534 sc->sbands[IEEE80211_BAND_5GHZ].n_channels = 535 ARRAY_SIZE(ath9k_5ghz_chantable); 536 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 537 ath9k_legacy_rates + 4; 538 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 539 ARRAY_SIZE(ath9k_legacy_rates) - 4; 540 } 541 return 0; 542 } 543 544 static void ath9k_init_misc(struct ath_softc *sc) 545 { 546 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 547 int i = 0; 548 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 549 550 sc->config.txpowlimit = ATH_TXPOWER_MAX; 551 552 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 553 sc->sc_flags |= SC_OP_TXAGGR; 554 sc->sc_flags |= SC_OP_RXAGGR; 555 } 556 557 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); 558 559 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 560 561 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 562 563 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 564 sc->beacon.bslot[i] = NULL; 565 566 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 567 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 568 } 569 570 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 571 const struct ath_bus_ops *bus_ops) 572 { 573 struct ath9k_platform_data *pdata = sc->dev->platform_data; 574 struct ath_hw *ah = NULL; 575 struct ath_common *common; 576 int ret = 0, i; 577 int csz = 0; 578 579 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 580 if (!ah) 581 return -ENOMEM; 582 583 ah->hw = sc->hw; 584 ah->hw_version.devid = devid; 585 ah->reg_ops.read = ath9k_ioread32; 586 ah->reg_ops.write = ath9k_iowrite32; 587 ah->reg_ops.rmw = ath9k_reg_rmw; 588 atomic_set(&ah->intr_ref_cnt, -1); 589 sc->sc_ah = ah; 590 591 if (!pdata) { 592 ah->ah_flags |= AH_USE_EEPROM; 593 sc->sc_ah->led_pin = -1; 594 } else { 595 sc->sc_ah->gpio_mask = pdata->gpio_mask; 596 sc->sc_ah->gpio_val = pdata->gpio_val; 597 sc->sc_ah->led_pin = pdata->led_pin; 598 ah->is_clk_25mhz = pdata->is_clk_25mhz; 599 ah->get_mac_revision = pdata->get_mac_revision; 600 ah->external_reset = pdata->external_reset; 601 } 602 603 common = ath9k_hw_common(ah); 604 common->ops = &ah->reg_ops; 605 common->bus_ops = bus_ops; 606 common->ah = ah; 607 common->hw = sc->hw; 608 common->priv = sc; 609 common->debug_mask = ath9k_debug; 610 common->btcoex_enabled = ath9k_btcoex_enable == 1; 611 common->disable_ani = false; 612 spin_lock_init(&common->cc_lock); 613 614 spin_lock_init(&sc->sc_serial_rw); 615 spin_lock_init(&sc->sc_pm_lock); 616 mutex_init(&sc->mutex); 617 #ifdef CONFIG_ATH9K_DEBUGFS 618 spin_lock_init(&sc->nodes_lock); 619 spin_lock_init(&sc->debug.samp_lock); 620 INIT_LIST_HEAD(&sc->nodes); 621 #endif 622 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 623 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, 624 (unsigned long)sc); 625 626 /* 627 * Cache line size is used to size and align various 628 * structures used to communicate with the hardware. 629 */ 630 ath_read_cachesize(common, &csz); 631 common->cachelsz = csz << 2; /* convert to bytes */ 632 633 /* Initializes the hardware for all supported chipsets */ 634 ret = ath9k_hw_init(ah); 635 if (ret) 636 goto err_hw; 637 638 if (pdata && pdata->macaddr) 639 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 640 641 ret = ath9k_init_queues(sc); 642 if (ret) 643 goto err_queues; 644 645 ret = ath9k_init_btcoex(sc); 646 if (ret) 647 goto err_btcoex; 648 649 ret = ath9k_init_channels_rates(sc); 650 if (ret) 651 goto err_btcoex; 652 653 ath9k_cmn_init_crypto(sc->sc_ah); 654 ath9k_init_misc(sc); 655 656 return 0; 657 658 err_btcoex: 659 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 660 if (ATH_TXQ_SETUP(sc, i)) 661 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 662 err_queues: 663 ath9k_hw_deinit(ah); 664 err_hw: 665 666 kfree(ah); 667 sc->sc_ah = NULL; 668 669 return ret; 670 } 671 672 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 673 { 674 struct ieee80211_supported_band *sband; 675 struct ieee80211_channel *chan; 676 struct ath_hw *ah = sc->sc_ah; 677 int i; 678 679 sband = &sc->sbands[band]; 680 for (i = 0; i < sband->n_channels; i++) { 681 chan = &sband->channels[i]; 682 ah->curchan = &ah->channels[chan->hw_value]; 683 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); 684 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 685 } 686 } 687 688 static void ath9k_init_txpower_limits(struct ath_softc *sc) 689 { 690 struct ath_hw *ah = sc->sc_ah; 691 struct ath9k_channel *curchan = ah->curchan; 692 693 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 694 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 695 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 696 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 697 698 ah->curchan = curchan; 699 } 700 701 void ath9k_reload_chainmask_settings(struct ath_softc *sc) 702 { 703 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) 704 return; 705 706 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 707 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 708 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 709 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 710 } 711 712 713 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 714 { 715 struct ath_hw *ah = sc->sc_ah; 716 struct ath_common *common = ath9k_hw_common(ah); 717 718 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 719 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 720 IEEE80211_HW_SIGNAL_DBM | 721 IEEE80211_HW_SUPPORTS_PS | 722 IEEE80211_HW_PS_NULLFUNC_STACK | 723 IEEE80211_HW_SPECTRUM_MGMT | 724 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 725 726 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 727 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 728 729 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 730 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 731 732 hw->wiphy->interface_modes = 733 BIT(NL80211_IFTYPE_P2P_GO) | 734 BIT(NL80211_IFTYPE_P2P_CLIENT) | 735 BIT(NL80211_IFTYPE_AP) | 736 BIT(NL80211_IFTYPE_WDS) | 737 BIT(NL80211_IFTYPE_STATION) | 738 BIT(NL80211_IFTYPE_ADHOC) | 739 BIT(NL80211_IFTYPE_MESH_POINT); 740 741 if (AR_SREV_5416(sc->sc_ah)) 742 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 743 744 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 745 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 746 747 hw->queues = 4; 748 hw->max_rates = 4; 749 hw->channel_change_time = 5000; 750 hw->max_listen_interval = 10; 751 hw->max_rate_tries = 10; 752 hw->sta_data_size = sizeof(struct ath_node); 753 hw->vif_data_size = sizeof(struct ath_vif); 754 755 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 756 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 757 758 /* single chain devices with rx diversity */ 759 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 760 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 761 762 sc->ant_rx = hw->wiphy->available_antennas_rx; 763 sc->ant_tx = hw->wiphy->available_antennas_tx; 764 765 #ifdef CONFIG_ATH9K_RATE_CONTROL 766 hw->rate_control_algorithm = "ath9k_rate_control"; 767 #endif 768 769 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 770 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 771 &sc->sbands[IEEE80211_BAND_2GHZ]; 772 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 773 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 774 &sc->sbands[IEEE80211_BAND_5GHZ]; 775 776 ath9k_reload_chainmask_settings(sc); 777 778 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 779 } 780 781 int ath9k_init_device(u16 devid, struct ath_softc *sc, 782 const struct ath_bus_ops *bus_ops) 783 { 784 struct ieee80211_hw *hw = sc->hw; 785 struct ath_common *common; 786 struct ath_hw *ah; 787 int error = 0; 788 struct ath_regulatory *reg; 789 790 /* Bring up device */ 791 error = ath9k_init_softc(devid, sc, bus_ops); 792 if (error != 0) 793 goto error_init; 794 795 ah = sc->sc_ah; 796 common = ath9k_hw_common(ah); 797 ath9k_set_hw_capab(sc, hw); 798 799 /* Initialize regulatory */ 800 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 801 ath9k_reg_notifier); 802 if (error) 803 goto error_regd; 804 805 reg = &common->regulatory; 806 807 /* Setup TX DMA */ 808 error = ath_tx_init(sc, ATH_TXBUF); 809 if (error != 0) 810 goto error_tx; 811 812 /* Setup RX DMA */ 813 error = ath_rx_init(sc, ATH_RXBUF); 814 if (error != 0) 815 goto error_rx; 816 817 ath9k_init_txpower_limits(sc); 818 819 #ifdef CONFIG_MAC80211_LEDS 820 /* must be initialized before ieee80211_register_hw */ 821 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 822 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 823 ARRAY_SIZE(ath9k_tpt_blink)); 824 #endif 825 826 /* Register with mac80211 */ 827 error = ieee80211_register_hw(hw); 828 if (error) 829 goto error_register; 830 831 error = ath9k_init_debug(ah); 832 if (error) { 833 ath_err(common, "Unable to create debugfs files\n"); 834 goto error_world; 835 } 836 837 /* Handle world regulatory */ 838 if (!ath_is_world_regd(reg)) { 839 error = regulatory_hint(hw->wiphy, reg->alpha2); 840 if (error) 841 goto error_world; 842 } 843 844 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 845 INIT_WORK(&sc->hw_check_work, ath_hw_check); 846 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 847 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 848 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 849 850 ath_init_leds(sc); 851 ath_start_rfkill_poll(sc); 852 853 return 0; 854 855 error_world: 856 ieee80211_unregister_hw(hw); 857 error_register: 858 ath_rx_cleanup(sc); 859 error_rx: 860 ath_tx_cleanup(sc); 861 error_tx: 862 /* Nothing */ 863 error_regd: 864 ath9k_deinit_softc(sc); 865 error_init: 866 return error; 867 } 868 869 /*****************************/ 870 /* De-Initialization */ 871 /*****************************/ 872 873 static void ath9k_deinit_softc(struct ath_softc *sc) 874 { 875 int i = 0; 876 877 if (sc->sbands[IEEE80211_BAND_2GHZ].channels) 878 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); 879 880 if (sc->sbands[IEEE80211_BAND_5GHZ].channels) 881 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); 882 883 if ((sc->btcoex.no_stomp_timer) && 884 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) 885 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); 886 887 if (sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_MCI) 888 ath_mci_cleanup(sc); 889 890 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 891 if (ATH_TXQ_SETUP(sc, i)) 892 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 893 894 ath9k_hw_deinit(sc->sc_ah); 895 896 kfree(sc->sc_ah); 897 sc->sc_ah = NULL; 898 } 899 900 void ath9k_deinit_device(struct ath_softc *sc) 901 { 902 struct ieee80211_hw *hw = sc->hw; 903 904 ath9k_ps_wakeup(sc); 905 906 wiphy_rfkill_stop_polling(sc->hw->wiphy); 907 ath_deinit_leds(sc); 908 909 ath9k_ps_restore(sc); 910 911 ieee80211_unregister_hw(hw); 912 ath_rx_cleanup(sc); 913 ath_tx_cleanup(sc); 914 ath9k_deinit_softc(sc); 915 } 916 917 void ath_descdma_cleanup(struct ath_softc *sc, 918 struct ath_descdma *dd, 919 struct list_head *head) 920 { 921 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, 922 dd->dd_desc_paddr); 923 924 INIT_LIST_HEAD(head); 925 kfree(dd->dd_bufptr); 926 memset(dd, 0, sizeof(*dd)); 927 } 928 929 /************************/ 930 /* Module Hooks */ 931 /************************/ 932 933 static int __init ath9k_init(void) 934 { 935 int error; 936 937 /* Register rate control algorithm */ 938 error = ath_rate_control_register(); 939 if (error != 0) { 940 printk(KERN_ERR 941 "ath9k: Unable to register rate control " 942 "algorithm: %d\n", 943 error); 944 goto err_out; 945 } 946 947 error = ath_pci_init(); 948 if (error < 0) { 949 printk(KERN_ERR 950 "ath9k: No PCI devices found, driver not installed.\n"); 951 error = -ENODEV; 952 goto err_rate_unregister; 953 } 954 955 error = ath_ahb_init(); 956 if (error < 0) { 957 error = -ENODEV; 958 goto err_pci_exit; 959 } 960 961 return 0; 962 963 err_pci_exit: 964 ath_pci_exit(); 965 966 err_rate_unregister: 967 ath_rate_control_unregister(); 968 err_out: 969 return error; 970 } 971 module_init(ath9k_init); 972 973 static void __exit ath9k_exit(void) 974 { 975 is_ath9k_unloaded = true; 976 ath_ahb_exit(); 977 ath_pci_exit(); 978 ath_rate_control_unregister(); 979 printk(KERN_INFO "%s: Driver unloaded\n", dev_info); 980 } 981 module_exit(ath9k_exit); 982