1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_net.h> 24 #include <linux/nvmem-consumer.h> 25 #include <linux/relay.h> 26 #include <linux/dmi.h> 27 #include <net/ieee80211_radiotap.h> 28 29 #include "ath9k.h" 30 31 struct ath9k_eeprom_ctx { 32 struct completion complete; 33 struct ath_hw *ah; 34 }; 35 36 static char *dev_info = "ath9k"; 37 38 MODULE_AUTHOR("Atheros Communications"); 39 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 40 MODULE_LICENSE("Dual BSD/GPL"); 41 42 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 43 module_param_named(debug, ath9k_debug, uint, 0); 44 MODULE_PARM_DESC(debug, "Debugging mask"); 45 46 int ath9k_modparam_nohwcrypt; 47 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 48 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 49 50 int ath9k_led_blink; 51 module_param_named(blink, ath9k_led_blink, int, 0444); 52 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 53 54 static int ath9k_led_active_high = -1; 55 module_param_named(led_active_high, ath9k_led_active_high, int, 0444); 56 MODULE_PARM_DESC(led_active_high, "Invert LED polarity"); 57 58 static int ath9k_btcoex_enable; 59 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 60 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 61 62 static int ath9k_bt_ant_diversity; 63 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 64 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 65 66 static int ath9k_ps_enable; 67 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 68 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 69 70 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 71 72 int ath9k_use_chanctx; 73 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); 74 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); 75 76 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 77 78 int ath9k_use_msi; 79 module_param_named(use_msi, ath9k_use_msi, int, 0444); 80 MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible"); 81 82 bool is_ath9k_unloaded; 83 84 #ifdef CONFIG_MAC80211_LEDS 85 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 86 { .throughput = 0 * 1024, .blink_time = 334 }, 87 { .throughput = 1 * 1024, .blink_time = 260 }, 88 { .throughput = 5 * 1024, .blink_time = 220 }, 89 { .throughput = 10 * 1024, .blink_time = 190 }, 90 { .throughput = 20 * 1024, .blink_time = 170 }, 91 { .throughput = 50 * 1024, .blink_time = 150 }, 92 { .throughput = 70 * 1024, .blink_time = 130 }, 93 { .throughput = 100 * 1024, .blink_time = 110 }, 94 { .throughput = 200 * 1024, .blink_time = 80 }, 95 { .throughput = 300 * 1024, .blink_time = 50 }, 96 }; 97 #endif 98 99 static int __init set_use_msi(const struct dmi_system_id *dmi) 100 { 101 ath9k_use_msi = 1; 102 return 1; 103 } 104 105 static const struct dmi_system_id ath9k_quirks[] __initconst = { 106 { 107 .callback = set_use_msi, 108 .ident = "Dell Inspiron 24-3460", 109 .matches = { 110 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 111 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"), 112 }, 113 }, 114 { 115 .callback = set_use_msi, 116 .ident = "Dell Vostro 3262", 117 .matches = { 118 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 119 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"), 120 }, 121 }, 122 { 123 .callback = set_use_msi, 124 .ident = "Dell Inspiron 3472", 125 .matches = { 126 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 127 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"), 128 }, 129 }, 130 { 131 .callback = set_use_msi, 132 .ident = "Dell Vostro 15-3572", 133 .matches = { 134 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 135 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"), 136 }, 137 }, 138 { 139 .callback = set_use_msi, 140 .ident = "Dell Inspiron 14-3473", 141 .matches = { 142 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 143 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"), 144 }, 145 }, 146 {} 147 }; 148 149 static void ath9k_deinit_softc(struct ath_softc *sc); 150 151 static void ath9k_op_ps_wakeup(struct ath_common *common) 152 { 153 ath9k_ps_wakeup(common->priv); 154 } 155 156 static void ath9k_op_ps_restore(struct ath_common *common) 157 { 158 ath9k_ps_restore(common->priv); 159 } 160 161 static const struct ath_ps_ops ath9k_ps_ops = { 162 .wakeup = ath9k_op_ps_wakeup, 163 .restore = ath9k_op_ps_restore, 164 }; 165 166 /* 167 * Read and write, they both share the same lock. We do this to serialize 168 * reads and writes on Atheros 802.11n PCI devices only. This is required 169 * as the FIFO on these devices can only accept sanely 2 requests. 170 */ 171 172 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 173 { 174 struct ath_hw *ah = hw_priv; 175 struct ath_common *common = ath9k_hw_common(ah); 176 struct ath_softc *sc = common->priv; 177 178 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 179 unsigned long flags; 180 spin_lock_irqsave(&sc->sc_serial_rw, flags); 181 iowrite32(val, sc->mem + reg_offset); 182 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 183 } else 184 iowrite32(val, sc->mem + reg_offset); 185 } 186 187 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 188 { 189 struct ath_hw *ah = hw_priv; 190 struct ath_common *common = ath9k_hw_common(ah); 191 struct ath_softc *sc = common->priv; 192 u32 val; 193 194 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 195 unsigned long flags; 196 spin_lock_irqsave(&sc->sc_serial_rw, flags); 197 val = ioread32(sc->mem + reg_offset); 198 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 199 } else 200 val = ioread32(sc->mem + reg_offset); 201 return val; 202 } 203 204 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr, 205 u32 *val, u16 count) 206 { 207 int i; 208 209 for (i = 0; i < count; i++) 210 val[i] = ath9k_ioread32(hw_priv, addr[i]); 211 } 212 213 214 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 215 u32 set, u32 clr) 216 { 217 u32 val; 218 219 val = ioread32(sc->mem + reg_offset); 220 val &= ~clr; 221 val |= set; 222 iowrite32(val, sc->mem + reg_offset); 223 224 return val; 225 } 226 227 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 228 { 229 struct ath_hw *ah = hw_priv; 230 struct ath_common *common = ath9k_hw_common(ah); 231 struct ath_softc *sc = common->priv; 232 unsigned long flags; 233 u32 val; 234 235 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 236 spin_lock_irqsave(&sc->sc_serial_rw, flags); 237 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 238 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 239 } else 240 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 241 242 return val; 243 } 244 245 /**************************/ 246 /* Initialization */ 247 /**************************/ 248 249 static void ath9k_reg_notifier(struct wiphy *wiphy, 250 struct regulatory_request *request) 251 { 252 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 253 struct ath_softc *sc = hw->priv; 254 struct ath_hw *ah = sc->sc_ah; 255 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 256 257 ath_reg_notifier_apply(wiphy, request, reg); 258 259 /* synchronize DFS detector if regulatory domain changed */ 260 if (sc->dfs_detector != NULL) 261 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 262 request->dfs_region); 263 264 /* Set tx power */ 265 if (!ah->curchan) 266 return; 267 268 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; 269 ath9k_ps_wakeup(sc); 270 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 271 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 272 sc->cur_chan->txpower, 273 &sc->cur_chan->cur_txpower); 274 ath9k_ps_restore(sc); 275 } 276 277 /* 278 * This function will allocate both the DMA descriptor structure, and the 279 * buffers it contains. These are used to contain the descriptors used 280 * by the system. 281 */ 282 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 283 struct list_head *head, const char *name, 284 int nbuf, int ndesc, bool is_tx) 285 { 286 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 287 u8 *ds; 288 int i, desc_len; 289 290 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 291 name, nbuf, ndesc); 292 293 INIT_LIST_HEAD(head); 294 295 if (is_tx) 296 desc_len = sc->sc_ah->caps.tx_desc_len; 297 else 298 desc_len = sizeof(struct ath_desc); 299 300 /* ath_desc must be a multiple of DWORDs */ 301 if ((desc_len % 4) != 0) { 302 ath_err(common, "ath_desc not DWORD aligned\n"); 303 BUG_ON((desc_len % 4) != 0); 304 return -ENOMEM; 305 } 306 307 dd->dd_desc_len = desc_len * nbuf * ndesc; 308 309 /* 310 * Need additional DMA memory because we can't use 311 * descriptors that cross the 4K page boundary. Assume 312 * one skipped descriptor per 4K page. 313 */ 314 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 315 u32 ndesc_skipped = 316 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 317 u32 dma_len; 318 319 while (ndesc_skipped) { 320 dma_len = ndesc_skipped * desc_len; 321 dd->dd_desc_len += dma_len; 322 323 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 324 } 325 } 326 327 /* allocate descriptors */ 328 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 329 &dd->dd_desc_paddr, GFP_KERNEL); 330 if (!dd->dd_desc) 331 return -ENOMEM; 332 333 ds = dd->dd_desc; 334 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 335 name, ds, (u32) dd->dd_desc_len, 336 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 337 338 /* allocate buffers */ 339 if (is_tx) { 340 struct ath_buf *bf; 341 342 bf = devm_kcalloc(sc->dev, sizeof(*bf), nbuf, GFP_KERNEL); 343 if (!bf) 344 return -ENOMEM; 345 346 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 347 bf->bf_desc = ds; 348 bf->bf_daddr = DS2PHYS(dd, ds); 349 350 if (!(sc->sc_ah->caps.hw_caps & 351 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 352 /* 353 * Skip descriptor addresses which can cause 4KB 354 * boundary crossing (addr + length) with a 32 dword 355 * descriptor fetch. 356 */ 357 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 358 BUG_ON((caddr_t) bf->bf_desc >= 359 ((caddr_t) dd->dd_desc + 360 dd->dd_desc_len)); 361 362 ds += (desc_len * ndesc); 363 bf->bf_desc = ds; 364 bf->bf_daddr = DS2PHYS(dd, ds); 365 } 366 } 367 list_add_tail(&bf->list, head); 368 } 369 } else { 370 struct ath_rxbuf *bf; 371 372 bf = devm_kcalloc(sc->dev, sizeof(struct ath_rxbuf), nbuf, GFP_KERNEL); 373 if (!bf) 374 return -ENOMEM; 375 376 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 377 bf->bf_desc = ds; 378 bf->bf_daddr = DS2PHYS(dd, ds); 379 380 if (!(sc->sc_ah->caps.hw_caps & 381 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 382 /* 383 * Skip descriptor addresses which can cause 4KB 384 * boundary crossing (addr + length) with a 32 dword 385 * descriptor fetch. 386 */ 387 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 388 BUG_ON((caddr_t) bf->bf_desc >= 389 ((caddr_t) dd->dd_desc + 390 dd->dd_desc_len)); 391 392 ds += (desc_len * ndesc); 393 bf->bf_desc = ds; 394 bf->bf_daddr = DS2PHYS(dd, ds); 395 } 396 } 397 list_add_tail(&bf->list, head); 398 } 399 } 400 return 0; 401 } 402 403 static int ath9k_init_queues(struct ath_softc *sc) 404 { 405 int i = 0; 406 407 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 408 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 409 ath_cabq_update(sc); 410 411 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 412 413 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 414 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 415 sc->tx.txq_map[i]->mac80211_qnum = i; 416 } 417 return 0; 418 } 419 420 static void ath9k_init_misc(struct ath_softc *sc) 421 { 422 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 423 int i = 0; 424 425 timer_setup(&common->ani.timer, ath_ani_calibrate, 0); 426 427 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 428 eth_broadcast_addr(common->bssidmask); 429 sc->beacon.slottime = 9; 430 431 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 432 sc->beacon.bslot[i] = NULL; 433 434 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 435 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 436 437 sc->spec_priv.ah = sc->sc_ah; 438 sc->spec_priv.spec_config.enabled = 0; 439 sc->spec_priv.spec_config.short_repeat = true; 440 sc->spec_priv.spec_config.count = 8; 441 sc->spec_priv.spec_config.endless = false; 442 sc->spec_priv.spec_config.period = 0xFF; 443 sc->spec_priv.spec_config.fft_period = 0xF; 444 } 445 446 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 447 { 448 struct ath_hw *ah = sc->sc_ah; 449 struct ath9k_hw_capabilities *pCap = &ah->caps; 450 struct ath_common *common = ath9k_hw_common(ah); 451 452 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM)) 453 return; 454 455 if (common->bus_ops->ath_bus_type != ATH_PCI) 456 return; 457 458 if (sc->driver_data & (ATH9K_PCI_CUS198 | 459 ATH9K_PCI_CUS230)) { 460 ah->config.xlna_gpio = 9; 461 ah->config.xatten_margin_cfg = true; 462 ah->config.alt_mingainidx = true; 463 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 464 sc->ant_comb.low_rssi_thresh = 20; 465 sc->ant_comb.fast_div_bias = 3; 466 467 ath_info(common, "Set parameters for %s\n", 468 (sc->driver_data & ATH9K_PCI_CUS198) ? 469 "CUS198" : "CUS230"); 470 } 471 472 if (sc->driver_data & ATH9K_PCI_CUS217) 473 ath_info(common, "CUS217 card detected\n"); 474 475 if (sc->driver_data & ATH9K_PCI_CUS252) 476 ath_info(common, "CUS252 card detected\n"); 477 478 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 479 ath_info(common, "WB335 1-ANT card detected\n"); 480 481 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 482 ath_info(common, "WB335 2-ANT card detected\n"); 483 484 if (sc->driver_data & ATH9K_PCI_KILLER) 485 ath_info(common, "Killer Wireless card detected\n"); 486 487 /* 488 * Some WB335 cards do not support antenna diversity. Since 489 * we use a hardcoded value for AR9565 instead of using the 490 * EEPROM/OTP data, remove the combining feature from 491 * the HW capabilities bitmap. 492 */ 493 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 494 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 495 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 496 } 497 498 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 499 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 500 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 501 } 502 503 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 504 ah->config.pcie_waen = 0x0040473b; 505 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 506 } 507 508 /* 509 * The default value of pll_pwrsave is 1. 510 * For certain AR9485 cards, it is set to 0. 511 * For AR9462, AR9565 it's set to 7. 512 */ 513 ah->config.pll_pwrsave = 1; 514 515 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 516 ah->config.pll_pwrsave = 0; 517 ath_info(common, "Disable PLL PowerSave\n"); 518 } 519 520 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI) 521 ah->config.led_active_high = true; 522 } 523 524 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 525 void *ctx) 526 { 527 struct ath9k_eeprom_ctx *ec = ctx; 528 529 if (eeprom_blob) 530 ec->ah->eeprom_blob = eeprom_blob; 531 532 complete(&ec->complete); 533 } 534 535 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 536 { 537 struct ath9k_eeprom_ctx ec; 538 struct ath_hw *ah = sc->sc_ah; 539 int err; 540 541 /* try to load the EEPROM content asynchronously */ 542 init_completion(&ec.complete); 543 ec.ah = sc->sc_ah; 544 545 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 546 &ec, ath9k_eeprom_request_cb); 547 if (err < 0) { 548 ath_err(ath9k_hw_common(ah), 549 "EEPROM request failed\n"); 550 return err; 551 } 552 553 wait_for_completion(&ec.complete); 554 555 if (!ah->eeprom_blob) { 556 ath_err(ath9k_hw_common(ah), 557 "Unable to load EEPROM file %s\n", name); 558 return -EINVAL; 559 } 560 561 return 0; 562 } 563 564 static void ath9k_eeprom_release(struct ath_softc *sc) 565 { 566 release_firmware(sc->sc_ah->eeprom_blob); 567 } 568 569 static int ath9k_nvmem_request_eeprom(struct ath_softc *sc) 570 { 571 struct ath_hw *ah = sc->sc_ah; 572 struct nvmem_cell *cell; 573 void *buf; 574 size_t len; 575 int err; 576 577 cell = nvmem_cell_get(sc->dev, "calibration"); 578 if (IS_ERR(cell)) { 579 err = PTR_ERR(cell); 580 581 /* nvmem cell might not be defined, or the nvmem 582 * subsystem isn't included. In this case, follow 583 * the established "just return 0;" convention 584 * to say: 585 * "All good. Nothing to see here. Please go on." 586 */ 587 if (err == -ENOENT || err == -EOPNOTSUPP) 588 return 0; 589 590 return err; 591 } 592 593 buf = nvmem_cell_read(cell, &len); 594 nvmem_cell_put(cell); 595 if (IS_ERR(buf)) 596 return PTR_ERR(buf); 597 598 /* run basic sanity checks on the returned nvram cell length. 599 * That length has to be a multiple of a "u16" (i.e.: & 1). 600 * Furthermore, it has to be more than "let's say" 512 bytes 601 * but less than the maximum of AR9300_EEPROM_SIZE (16kb). 602 */ 603 if ((len & 1) == 1 || len < 512 || len >= AR9300_EEPROM_SIZE) { 604 kfree(buf); 605 return -EINVAL; 606 } 607 608 /* devres manages the calibration values release on shutdown */ 609 ah->nvmem_blob = devm_kmemdup(sc->dev, buf, len, GFP_KERNEL); 610 kfree(buf); 611 if (!ah->nvmem_blob) 612 return -ENOMEM; 613 614 ah->nvmem_blob_len = len; 615 ah->ah_flags &= ~AH_USE_EEPROM; 616 ah->ah_flags |= AH_NO_EEP_SWAP; 617 618 return 0; 619 } 620 621 static int ath9k_of_init(struct ath_softc *sc) 622 { 623 struct device_node *np = sc->dev->of_node; 624 struct ath_hw *ah = sc->sc_ah; 625 struct ath_common *common = ath9k_hw_common(ah); 626 enum ath_bus_type bus_type = common->bus_ops->ath_bus_type; 627 char eeprom_name[100]; 628 int ret; 629 630 if (!of_device_is_available(np)) 631 return 0; 632 633 ath_dbg(common, CONFIG, "parsing configuration from OF node\n"); 634 635 if (of_property_read_bool(np, "qca,no-eeprom")) { 636 /* ath9k-eeprom-<bus>-<id>.bin */ 637 scnprintf(eeprom_name, sizeof(eeprom_name), 638 "ath9k-eeprom-%s-%s.bin", 639 ath_bus_type_to_string(bus_type), dev_name(ah->dev)); 640 641 ret = ath9k_eeprom_request(sc, eeprom_name); 642 if (ret) 643 return ret; 644 645 ah->ah_flags &= ~AH_USE_EEPROM; 646 ah->ah_flags |= AH_NO_EEP_SWAP; 647 } 648 649 ret = of_get_mac_address(np, common->macaddr); 650 if (ret == -EPROBE_DEFER) 651 return ret; 652 653 return 0; 654 } 655 656 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 657 const struct ath_bus_ops *bus_ops) 658 { 659 struct ath_hw *ah = NULL; 660 struct ath9k_hw_capabilities *pCap; 661 struct ath_common *common; 662 int ret = 0, i; 663 int csz = 0; 664 665 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 666 if (!ah) 667 return -ENOMEM; 668 669 ah->dev = sc->dev; 670 ah->hw = sc->hw; 671 ah->hw_version.devid = devid; 672 ah->ah_flags |= AH_USE_EEPROM; 673 ah->led_pin = -1; 674 ah->reg_ops.read = ath9k_ioread32; 675 ah->reg_ops.multi_read = ath9k_multi_ioread32; 676 ah->reg_ops.write = ath9k_iowrite32; 677 ah->reg_ops.rmw = ath9k_reg_rmw; 678 pCap = &ah->caps; 679 680 common = ath9k_hw_common(ah); 681 682 /* Will be cleared in ath9k_start() */ 683 set_bit(ATH_OP_INVALID, &common->op_flags); 684 685 sc->sc_ah = ah; 686 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 687 sc->tx99_power = MAX_RATE_POWER + 1; 688 init_waitqueue_head(&sc->tx_wait); 689 sc->cur_chan = &sc->chanctx[0]; 690 if (!ath9k_is_chanctx_enabled()) 691 sc->cur_chan->hw_queue_base = 0; 692 693 common->ops = &ah->reg_ops; 694 common->bus_ops = bus_ops; 695 common->ps_ops = &ath9k_ps_ops; 696 common->ah = ah; 697 common->hw = sc->hw; 698 common->priv = sc; 699 common->debug_mask = ath9k_debug; 700 common->btcoex_enabled = ath9k_btcoex_enable == 1; 701 common->disable_ani = false; 702 703 /* 704 * Platform quirks. 705 */ 706 ath9k_init_pcoem_platform(sc); 707 708 ret = ath9k_of_init(sc); 709 if (ret) 710 return ret; 711 712 ret = ath9k_nvmem_request_eeprom(sc); 713 if (ret) 714 return ret; 715 716 if (ath9k_led_active_high != -1) 717 ah->config.led_active_high = ath9k_led_active_high == 1; 718 719 /* 720 * Enable WLAN/BT RX Antenna diversity only when: 721 * 722 * - BTCOEX is disabled. 723 * - the user manually requests the feature. 724 * - the HW cap is set using the platform data. 725 */ 726 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 727 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 728 common->bt_ant_diversity = 1; 729 730 spin_lock_init(&common->cc_lock); 731 spin_lock_init(&sc->intr_lock); 732 spin_lock_init(&sc->sc_serial_rw); 733 spin_lock_init(&sc->sc_pm_lock); 734 spin_lock_init(&sc->chan_lock); 735 mutex_init(&sc->mutex); 736 tasklet_setup(&sc->intr_tq, ath9k_tasklet); 737 tasklet_setup(&sc->bcon_tasklet, ath9k_beacon_tasklet); 738 739 timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0); 740 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 741 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 742 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 743 INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work); 744 745 ath9k_init_channel_context(sc); 746 747 /* 748 * Cache line size is used to size and align various 749 * structures used to communicate with the hardware. 750 */ 751 ath_read_cachesize(common, &csz); 752 common->cachelsz = csz << 2; /* convert to bytes */ 753 754 /* Initializes the hardware for all supported chipsets */ 755 ret = ath9k_hw_init(ah); 756 if (ret) 757 goto err_hw; 758 759 ret = ath9k_init_queues(sc); 760 if (ret) 761 goto err_queues; 762 763 ret = ath9k_init_btcoex(sc); 764 if (ret) 765 goto err_btcoex; 766 767 ret = ath9k_cmn_init_channels_rates(common); 768 if (ret) 769 goto err_btcoex; 770 771 ret = ath9k_init_p2p(sc); 772 if (ret) 773 goto err_btcoex; 774 775 ath9k_cmn_init_crypto(sc->sc_ah); 776 ath9k_init_misc(sc); 777 ath_chanctx_init(sc); 778 ath9k_offchannel_init(sc); 779 780 if (common->bus_ops->aspm_init) 781 common->bus_ops->aspm_init(common); 782 783 return 0; 784 785 err_btcoex: 786 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 787 if (ATH_TXQ_SETUP(sc, i)) 788 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 789 err_queues: 790 ath9k_hw_deinit(ah); 791 err_hw: 792 ath9k_eeprom_release(sc); 793 dev_kfree_skb_any(sc->tx99_skb); 794 return ret; 795 } 796 797 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 798 { 799 struct ieee80211_supported_band *sband; 800 struct ieee80211_channel *chan; 801 struct ath_hw *ah = sc->sc_ah; 802 struct ath_common *common = ath9k_hw_common(ah); 803 struct cfg80211_chan_def chandef; 804 int i; 805 806 sband = &common->sbands[band]; 807 for (i = 0; i < sband->n_channels; i++) { 808 chan = &sband->channels[i]; 809 ah->curchan = &ah->channels[chan->hw_value]; 810 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 811 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 812 ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true); 813 } 814 } 815 816 static void ath9k_init_txpower_limits(struct ath_softc *sc) 817 { 818 struct ath_hw *ah = sc->sc_ah; 819 struct ath9k_channel *curchan = ah->curchan; 820 821 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 822 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ); 823 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 824 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ); 825 826 ah->curchan = curchan; 827 } 828 829 static const struct ieee80211_iface_limit if_limits[] = { 830 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 831 { .max = 8, .types = 832 #ifdef CONFIG_MAC80211_MESH 833 BIT(NL80211_IFTYPE_MESH_POINT) | 834 #endif 835 BIT(NL80211_IFTYPE_AP) }, 836 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 837 BIT(NL80211_IFTYPE_P2P_GO) }, 838 }; 839 840 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 841 842 static const struct ieee80211_iface_limit if_limits_multi[] = { 843 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | 844 BIT(NL80211_IFTYPE_AP) | 845 BIT(NL80211_IFTYPE_P2P_CLIENT) | 846 BIT(NL80211_IFTYPE_P2P_GO) }, 847 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, 848 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) }, 849 }; 850 851 static const struct ieee80211_iface_combination if_comb_multi[] = { 852 { 853 .limits = if_limits_multi, 854 .n_limits = ARRAY_SIZE(if_limits_multi), 855 .max_interfaces = 3, 856 .num_different_channels = 2, 857 .beacon_int_infra_match = true, 858 }, 859 }; 860 861 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 862 863 static const struct ieee80211_iface_combination if_comb[] = { 864 { 865 .limits = if_limits, 866 .n_limits = ARRAY_SIZE(if_limits), 867 .max_interfaces = 2048, 868 .num_different_channels = 1, 869 .beacon_int_infra_match = true, 870 #ifdef CONFIG_ATH9K_DFS_CERTIFIED 871 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 872 BIT(NL80211_CHAN_WIDTH_20) | 873 BIT(NL80211_CHAN_WIDTH_40), 874 #endif 875 }, 876 }; 877 878 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 879 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 880 { 881 struct ath_hw *ah = sc->sc_ah; 882 struct ath_common *common = ath9k_hw_common(ah); 883 884 if (!ath9k_is_chanctx_enabled()) 885 return; 886 887 ieee80211_hw_set(hw, QUEUE_CONTROL); 888 hw->queues = ATH9K_NUM_TX_QUEUES; 889 hw->offchannel_tx_hw_queue = hw->queues - 1; 890 hw->wiphy->iface_combinations = if_comb_multi; 891 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi); 892 hw->wiphy->max_scan_ssids = 255; 893 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 894 hw->wiphy->max_remain_on_channel_duration = 10000; 895 hw->chanctx_data_size = sizeof(void *); 896 hw->extra_beacon_tailroom = 897 sizeof(struct ieee80211_p2p_noa_attr) + 9; 898 899 ath_dbg(common, CHAN_CTX, "Use channel contexts\n"); 900 } 901 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 902 903 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 904 { 905 struct ath_hw *ah = sc->sc_ah; 906 struct ath_common *common = ath9k_hw_common(ah); 907 908 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES); 909 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); 910 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 911 ieee80211_hw_set(hw, SPECTRUM_MGMT); 912 ieee80211_hw_set(hw, PS_NULLFUNC_STACK); 913 ieee80211_hw_set(hw, SIGNAL_DBM); 914 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 915 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); 916 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 917 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS); 918 919 if (ath9k_ps_enable) 920 ieee80211_hw_set(hw, SUPPORTS_PS); 921 922 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 923 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 924 925 if (AR_SREV_9280_20_OR_LATER(ah)) 926 hw->radiotap_mcs_details |= 927 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 928 } 929 930 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 931 ieee80211_hw_set(hw, MFP_CAPABLE); 932 933 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR | 934 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | 935 NL80211_FEATURE_P2P_GO_CTWIN; 936 937 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) { 938 hw->wiphy->interface_modes = 939 BIT(NL80211_IFTYPE_P2P_GO) | 940 BIT(NL80211_IFTYPE_P2P_CLIENT) | 941 BIT(NL80211_IFTYPE_AP) | 942 BIT(NL80211_IFTYPE_STATION) | 943 BIT(NL80211_IFTYPE_ADHOC) | 944 BIT(NL80211_IFTYPE_MESH_POINT) | 945 BIT(NL80211_IFTYPE_OCB); 946 947 if (ath9k_is_chanctx_enabled()) 948 hw->wiphy->interface_modes |= 949 BIT(NL80211_IFTYPE_P2P_DEVICE); 950 951 hw->wiphy->iface_combinations = if_comb; 952 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 953 } 954 955 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 956 957 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 958 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 959 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 960 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 961 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; 962 963 hw->queues = 4; 964 hw->max_rates = 4; 965 hw->max_listen_interval = 10; 966 hw->max_rate_tries = 10; 967 hw->sta_data_size = sizeof(struct ath_node); 968 hw->vif_data_size = sizeof(struct ath_vif); 969 hw->txq_data_size = sizeof(struct ath_atx_tid); 970 hw->extra_tx_headroom = 4; 971 972 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 973 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 974 975 /* single chain devices with rx diversity */ 976 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 977 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 978 979 sc->ant_rx = hw->wiphy->available_antennas_rx; 980 sc->ant_tx = hw->wiphy->available_antennas_tx; 981 982 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 983 hw->wiphy->bands[NL80211_BAND_2GHZ] = 984 &common->sbands[NL80211_BAND_2GHZ]; 985 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 986 hw->wiphy->bands[NL80211_BAND_5GHZ] = 987 &common->sbands[NL80211_BAND_5GHZ]; 988 989 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 990 ath9k_set_mcc_capab(sc, hw); 991 #endif 992 ath9k_init_wow(hw); 993 ath9k_cmn_reload_chainmask(ah); 994 995 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 996 997 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 998 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS); 999 wiphy_ext_feature_set(hw->wiphy, 1000 NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS); 1001 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 1002 } 1003 1004 int ath9k_init_device(u16 devid, struct ath_softc *sc, 1005 const struct ath_bus_ops *bus_ops) 1006 { 1007 struct ieee80211_hw *hw = sc->hw; 1008 struct ath_common *common; 1009 struct ath_hw *ah; 1010 int error = 0; 1011 struct ath_regulatory *reg; 1012 1013 /* Bring up device */ 1014 error = ath9k_init_softc(devid, sc, bus_ops); 1015 if (error) 1016 return error; 1017 1018 ah = sc->sc_ah; 1019 common = ath9k_hw_common(ah); 1020 ath9k_set_hw_capab(sc, hw); 1021 1022 /* Initialize regulatory */ 1023 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 1024 ath9k_reg_notifier); 1025 if (error) 1026 goto deinit; 1027 1028 reg = &common->regulatory; 1029 1030 /* Setup TX DMA */ 1031 error = ath_tx_init(sc, ATH_TXBUF); 1032 if (error != 0) 1033 goto deinit; 1034 1035 /* Setup RX DMA */ 1036 error = ath_rx_init(sc, ATH_RXBUF); 1037 if (error != 0) 1038 goto deinit; 1039 1040 ath9k_init_txpower_limits(sc); 1041 1042 #ifdef CONFIG_MAC80211_LEDS 1043 /* must be initialized before ieee80211_register_hw */ 1044 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 1045 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 1046 ARRAY_SIZE(ath9k_tpt_blink)); 1047 #endif 1048 1049 wiphy_read_of_freq_limits(hw->wiphy); 1050 1051 /* Register with mac80211 */ 1052 error = ieee80211_register_hw(hw); 1053 if (error) 1054 goto rx_cleanup; 1055 1056 error = ath9k_init_debug(ah); 1057 if (error) { 1058 ath_err(common, "Unable to create debugfs files\n"); 1059 goto unregister; 1060 } 1061 1062 /* Handle world regulatory */ 1063 if (!ath_is_world_regd(reg)) { 1064 error = regulatory_hint(hw->wiphy, reg->alpha2); 1065 if (error) 1066 goto debug_cleanup; 1067 } 1068 1069 ath_init_leds(sc); 1070 ath_start_rfkill_poll(sc); 1071 1072 return 0; 1073 1074 debug_cleanup: 1075 ath9k_deinit_debug(sc); 1076 unregister: 1077 ieee80211_unregister_hw(hw); 1078 rx_cleanup: 1079 ath_rx_cleanup(sc); 1080 deinit: 1081 ath9k_deinit_softc(sc); 1082 return error; 1083 } 1084 1085 /*****************************/ 1086 /* De-Initialization */ 1087 /*****************************/ 1088 1089 static void ath9k_deinit_softc(struct ath_softc *sc) 1090 { 1091 int i = 0; 1092 1093 ath9k_deinit_p2p(sc); 1094 ath9k_deinit_btcoex(sc); 1095 1096 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1097 if (ATH_TXQ_SETUP(sc, i)) 1098 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1099 1100 timer_delete_sync(&sc->sleep_timer); 1101 ath9k_hw_deinit(sc->sc_ah); 1102 if (sc->dfs_detector != NULL) 1103 sc->dfs_detector->exit(sc->dfs_detector); 1104 1105 ath9k_eeprom_release(sc); 1106 } 1107 1108 void ath9k_deinit_device(struct ath_softc *sc) 1109 { 1110 struct ieee80211_hw *hw = sc->hw; 1111 1112 ath9k_ps_wakeup(sc); 1113 1114 wiphy_rfkill_stop_polling(sc->hw->wiphy); 1115 ath_deinit_leds(sc); 1116 1117 ath9k_ps_restore(sc); 1118 1119 ath9k_deinit_debug(sc); 1120 ath9k_deinit_wow(hw); 1121 ieee80211_unregister_hw(hw); 1122 ath_rx_cleanup(sc); 1123 ath9k_deinit_softc(sc); 1124 } 1125 1126 /************************/ 1127 /* Module Hooks */ 1128 /************************/ 1129 1130 static int __init ath9k_init(void) 1131 { 1132 int error; 1133 1134 error = ath_pci_init(); 1135 if (error < 0) { 1136 pr_err("No PCI devices found, driver not installed\n"); 1137 error = -ENODEV; 1138 goto err_out; 1139 } 1140 1141 error = ath_ahb_init(); 1142 if (error < 0) { 1143 error = -ENODEV; 1144 goto err_pci_exit; 1145 } 1146 1147 dmi_check_system(ath9k_quirks); 1148 1149 return 0; 1150 1151 err_pci_exit: 1152 ath_pci_exit(); 1153 err_out: 1154 return error; 1155 } 1156 module_init(ath9k_init); 1157 1158 static void __exit ath9k_exit(void) 1159 { 1160 is_ath9k_unloaded = true; 1161 ath_ahb_exit(); 1162 ath_pci_exit(); 1163 pr_info("%s: Driver unloaded\n", dev_info); 1164 } 1165 module_exit(ath9k_exit); 1166