1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/dma-mapping.h> 20 #include <linux/slab.h> 21 #include <linux/ath9k_platform.h> 22 #include <linux/module.h> 23 #include <linux/relay.h> 24 #include <net/ieee80211_radiotap.h> 25 26 #include "ath9k.h" 27 28 struct ath9k_eeprom_ctx { 29 struct completion complete; 30 struct ath_hw *ah; 31 }; 32 33 static char *dev_info = "ath9k"; 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 41 module_param_named(debug, ath9k_debug, uint, 0); 42 MODULE_PARM_DESC(debug, "Debugging mask"); 43 44 int ath9k_modparam_nohwcrypt; 45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); 46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 47 48 int led_blink; 49 module_param_named(blink, led_blink, int, 0444); 50 MODULE_PARM_DESC(blink, "Enable LED blink on activity"); 51 52 static int ath9k_btcoex_enable; 53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); 54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); 55 56 static int ath9k_bt_ant_diversity; 57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); 58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); 59 60 static int ath9k_ps_enable; 61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444); 62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); 63 64 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 65 66 int ath9k_use_chanctx; 67 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); 68 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); 69 70 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 71 72 bool is_ath9k_unloaded; 73 74 #ifdef CONFIG_MAC80211_LEDS 75 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { 76 { .throughput = 0 * 1024, .blink_time = 334 }, 77 { .throughput = 1 * 1024, .blink_time = 260 }, 78 { .throughput = 5 * 1024, .blink_time = 220 }, 79 { .throughput = 10 * 1024, .blink_time = 190 }, 80 { .throughput = 20 * 1024, .blink_time = 170 }, 81 { .throughput = 50 * 1024, .blink_time = 150 }, 82 { .throughput = 70 * 1024, .blink_time = 130 }, 83 { .throughput = 100 * 1024, .blink_time = 110 }, 84 { .throughput = 200 * 1024, .blink_time = 80 }, 85 { .throughput = 300 * 1024, .blink_time = 50 }, 86 }; 87 #endif 88 89 static void ath9k_deinit_softc(struct ath_softc *sc); 90 91 static void ath9k_op_ps_wakeup(struct ath_common *common) 92 { 93 ath9k_ps_wakeup((struct ath_softc *) common->priv); 94 } 95 96 static void ath9k_op_ps_restore(struct ath_common *common) 97 { 98 ath9k_ps_restore((struct ath_softc *) common->priv); 99 } 100 101 static struct ath_ps_ops ath9k_ps_ops = { 102 .wakeup = ath9k_op_ps_wakeup, 103 .restore = ath9k_op_ps_restore, 104 }; 105 106 /* 107 * Read and write, they both share the same lock. We do this to serialize 108 * reads and writes on Atheros 802.11n PCI devices only. This is required 109 * as the FIFO on these devices can only accept sanely 2 requests. 110 */ 111 112 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 113 { 114 struct ath_hw *ah = (struct ath_hw *) hw_priv; 115 struct ath_common *common = ath9k_hw_common(ah); 116 struct ath_softc *sc = (struct ath_softc *) common->priv; 117 118 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 119 unsigned long flags; 120 spin_lock_irqsave(&sc->sc_serial_rw, flags); 121 iowrite32(val, sc->mem + reg_offset); 122 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 123 } else 124 iowrite32(val, sc->mem + reg_offset); 125 } 126 127 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 128 { 129 struct ath_hw *ah = (struct ath_hw *) hw_priv; 130 struct ath_common *common = ath9k_hw_common(ah); 131 struct ath_softc *sc = (struct ath_softc *) common->priv; 132 u32 val; 133 134 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 135 unsigned long flags; 136 spin_lock_irqsave(&sc->sc_serial_rw, flags); 137 val = ioread32(sc->mem + reg_offset); 138 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 139 } else 140 val = ioread32(sc->mem + reg_offset); 141 return val; 142 } 143 144 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, 145 u32 set, u32 clr) 146 { 147 u32 val; 148 149 val = ioread32(sc->mem + reg_offset); 150 val &= ~clr; 151 val |= set; 152 iowrite32(val, sc->mem + reg_offset); 153 154 return val; 155 } 156 157 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 158 { 159 struct ath_hw *ah = (struct ath_hw *) hw_priv; 160 struct ath_common *common = ath9k_hw_common(ah); 161 struct ath_softc *sc = (struct ath_softc *) common->priv; 162 unsigned long uninitialized_var(flags); 163 u32 val; 164 165 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { 166 spin_lock_irqsave(&sc->sc_serial_rw, flags); 167 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 168 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 169 } else 170 val = __ath9k_reg_rmw(sc, reg_offset, set, clr); 171 172 return val; 173 } 174 175 /**************************/ 176 /* Initialization */ 177 /**************************/ 178 179 static void ath9k_reg_notifier(struct wiphy *wiphy, 180 struct regulatory_request *request) 181 { 182 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 183 struct ath_softc *sc = hw->priv; 184 struct ath_hw *ah = sc->sc_ah; 185 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 186 187 ath_reg_notifier_apply(wiphy, request, reg); 188 189 /* Set tx power */ 190 if (!ah->curchan) 191 return; 192 193 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; 194 ath9k_ps_wakeup(sc); 195 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); 196 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, 197 sc->cur_chan->txpower, 198 &sc->cur_chan->cur_txpower); 199 /* synchronize DFS detector if regulatory domain changed */ 200 if (sc->dfs_detector != NULL) 201 sc->dfs_detector->set_dfs_domain(sc->dfs_detector, 202 request->dfs_region); 203 ath9k_ps_restore(sc); 204 } 205 206 /* 207 * This function will allocate both the DMA descriptor structure, and the 208 * buffers it contains. These are used to contain the descriptors used 209 * by the system. 210 */ 211 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 212 struct list_head *head, const char *name, 213 int nbuf, int ndesc, bool is_tx) 214 { 215 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 216 u8 *ds; 217 int i, bsize, desc_len; 218 219 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", 220 name, nbuf, ndesc); 221 222 INIT_LIST_HEAD(head); 223 224 if (is_tx) 225 desc_len = sc->sc_ah->caps.tx_desc_len; 226 else 227 desc_len = sizeof(struct ath_desc); 228 229 /* ath_desc must be a multiple of DWORDs */ 230 if ((desc_len % 4) != 0) { 231 ath_err(common, "ath_desc not DWORD aligned\n"); 232 BUG_ON((desc_len % 4) != 0); 233 return -ENOMEM; 234 } 235 236 dd->dd_desc_len = desc_len * nbuf * ndesc; 237 238 /* 239 * Need additional DMA memory because we can't use 240 * descriptors that cross the 4K page boundary. Assume 241 * one skipped descriptor per 4K page. 242 */ 243 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 244 u32 ndesc_skipped = 245 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 246 u32 dma_len; 247 248 while (ndesc_skipped) { 249 dma_len = ndesc_skipped * desc_len; 250 dd->dd_desc_len += dma_len; 251 252 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 253 } 254 } 255 256 /* allocate descriptors */ 257 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 258 &dd->dd_desc_paddr, GFP_KERNEL); 259 if (!dd->dd_desc) 260 return -ENOMEM; 261 262 ds = (u8 *) dd->dd_desc; 263 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 264 name, ds, (u32) dd->dd_desc_len, 265 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 266 267 /* allocate buffers */ 268 if (is_tx) { 269 struct ath_buf *bf; 270 271 bsize = sizeof(struct ath_buf) * nbuf; 272 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 273 if (!bf) 274 return -ENOMEM; 275 276 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 277 bf->bf_desc = ds; 278 bf->bf_daddr = DS2PHYS(dd, ds); 279 280 if (!(sc->sc_ah->caps.hw_caps & 281 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 282 /* 283 * Skip descriptor addresses which can cause 4KB 284 * boundary crossing (addr + length) with a 32 dword 285 * descriptor fetch. 286 */ 287 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 288 BUG_ON((caddr_t) bf->bf_desc >= 289 ((caddr_t) dd->dd_desc + 290 dd->dd_desc_len)); 291 292 ds += (desc_len * ndesc); 293 bf->bf_desc = ds; 294 bf->bf_daddr = DS2PHYS(dd, ds); 295 } 296 } 297 list_add_tail(&bf->list, head); 298 } 299 } else { 300 struct ath_rxbuf *bf; 301 302 bsize = sizeof(struct ath_rxbuf) * nbuf; 303 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); 304 if (!bf) 305 return -ENOMEM; 306 307 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { 308 bf->bf_desc = ds; 309 bf->bf_daddr = DS2PHYS(dd, ds); 310 311 if (!(sc->sc_ah->caps.hw_caps & 312 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 313 /* 314 * Skip descriptor addresses which can cause 4KB 315 * boundary crossing (addr + length) with a 32 dword 316 * descriptor fetch. 317 */ 318 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 319 BUG_ON((caddr_t) bf->bf_desc >= 320 ((caddr_t) dd->dd_desc + 321 dd->dd_desc_len)); 322 323 ds += (desc_len * ndesc); 324 bf->bf_desc = ds; 325 bf->bf_daddr = DS2PHYS(dd, ds); 326 } 327 } 328 list_add_tail(&bf->list, head); 329 } 330 } 331 return 0; 332 } 333 334 static int ath9k_init_queues(struct ath_softc *sc) 335 { 336 int i = 0; 337 338 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); 339 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 340 ath_cabq_update(sc); 341 342 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); 343 344 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 345 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); 346 sc->tx.txq_map[i]->mac80211_qnum = i; 347 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; 348 } 349 return 0; 350 } 351 352 static void ath9k_init_misc(struct ath_softc *sc) 353 { 354 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 355 int i = 0; 356 357 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 358 359 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 360 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 361 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 362 363 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) 364 sc->beacon.bslot[i] = NULL; 365 366 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 367 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; 368 369 sc->spec_priv.ah = sc->sc_ah; 370 sc->spec_priv.spec_config.enabled = 0; 371 sc->spec_priv.spec_config.short_repeat = true; 372 sc->spec_priv.spec_config.count = 8; 373 sc->spec_priv.spec_config.endless = false; 374 sc->spec_priv.spec_config.period = 0xFF; 375 sc->spec_priv.spec_config.fft_period = 0xF; 376 } 377 378 static void ath9k_init_pcoem_platform(struct ath_softc *sc) 379 { 380 struct ath_hw *ah = sc->sc_ah; 381 struct ath9k_hw_capabilities *pCap = &ah->caps; 382 struct ath_common *common = ath9k_hw_common(ah); 383 384 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM)) 385 return; 386 387 if (common->bus_ops->ath_bus_type != ATH_PCI) 388 return; 389 390 if (sc->driver_data & (ATH9K_PCI_CUS198 | 391 ATH9K_PCI_CUS230)) { 392 ah->config.xlna_gpio = 9; 393 ah->config.xatten_margin_cfg = true; 394 ah->config.alt_mingainidx = true; 395 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; 396 sc->ant_comb.low_rssi_thresh = 20; 397 sc->ant_comb.fast_div_bias = 3; 398 399 ath_info(common, "Set parameters for %s\n", 400 (sc->driver_data & ATH9K_PCI_CUS198) ? 401 "CUS198" : "CUS230"); 402 } 403 404 if (sc->driver_data & ATH9K_PCI_CUS217) 405 ath_info(common, "CUS217 card detected\n"); 406 407 if (sc->driver_data & ATH9K_PCI_CUS252) 408 ath_info(common, "CUS252 card detected\n"); 409 410 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) 411 ath_info(common, "WB335 1-ANT card detected\n"); 412 413 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) 414 ath_info(common, "WB335 2-ANT card detected\n"); 415 416 if (sc->driver_data & ATH9K_PCI_KILLER) 417 ath_info(common, "Killer Wireless card detected\n"); 418 419 /* 420 * Some WB335 cards do not support antenna diversity. Since 421 * we use a hardcoded value for AR9565 instead of using the 422 * EEPROM/OTP data, remove the combining feature from 423 * the HW capabilities bitmap. 424 */ 425 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { 426 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) 427 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; 428 } 429 430 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { 431 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; 432 ath_info(common, "Set BT/WLAN RX diversity capability\n"); 433 } 434 435 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { 436 ah->config.pcie_waen = 0x0040473b; 437 ath_info(common, "Enable WAR for ASPM D3/L1\n"); 438 } 439 440 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { 441 ah->config.no_pll_pwrsave = true; 442 ath_info(common, "Disable PLL PowerSave\n"); 443 } 444 445 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI) 446 ah->config.led_active_high = true; 447 } 448 449 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, 450 void *ctx) 451 { 452 struct ath9k_eeprom_ctx *ec = ctx; 453 454 if (eeprom_blob) 455 ec->ah->eeprom_blob = eeprom_blob; 456 457 complete(&ec->complete); 458 } 459 460 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) 461 { 462 struct ath9k_eeprom_ctx ec; 463 struct ath_hw *ah = ah = sc->sc_ah; 464 int err; 465 466 /* try to load the EEPROM content asynchronously */ 467 init_completion(&ec.complete); 468 ec.ah = sc->sc_ah; 469 470 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, 471 &ec, ath9k_eeprom_request_cb); 472 if (err < 0) { 473 ath_err(ath9k_hw_common(ah), 474 "EEPROM request failed\n"); 475 return err; 476 } 477 478 wait_for_completion(&ec.complete); 479 480 if (!ah->eeprom_blob) { 481 ath_err(ath9k_hw_common(ah), 482 "Unable to load EEPROM file %s\n", name); 483 return -EINVAL; 484 } 485 486 return 0; 487 } 488 489 static void ath9k_eeprom_release(struct ath_softc *sc) 490 { 491 release_firmware(sc->sc_ah->eeprom_blob); 492 } 493 494 static int ath9k_init_soc_platform(struct ath_softc *sc) 495 { 496 struct ath9k_platform_data *pdata = sc->dev->platform_data; 497 struct ath_hw *ah = sc->sc_ah; 498 int ret = 0; 499 500 if (!pdata) 501 return 0; 502 503 if (pdata->eeprom_name) { 504 ret = ath9k_eeprom_request(sc, pdata->eeprom_name); 505 if (ret) 506 return ret; 507 } 508 509 if (pdata->tx_gain_buffalo) 510 ah->config.tx_gain_buffalo = true; 511 512 return ret; 513 } 514 515 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, 516 const struct ath_bus_ops *bus_ops) 517 { 518 struct ath9k_platform_data *pdata = sc->dev->platform_data; 519 struct ath_hw *ah = NULL; 520 struct ath9k_hw_capabilities *pCap; 521 struct ath_common *common; 522 int ret = 0, i; 523 int csz = 0; 524 525 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); 526 if (!ah) 527 return -ENOMEM; 528 529 ah->dev = sc->dev; 530 ah->hw = sc->hw; 531 ah->hw_version.devid = devid; 532 ah->reg_ops.read = ath9k_ioread32; 533 ah->reg_ops.write = ath9k_iowrite32; 534 ah->reg_ops.rmw = ath9k_reg_rmw; 535 pCap = &ah->caps; 536 537 common = ath9k_hw_common(ah); 538 539 /* Will be cleared in ath9k_start() */ 540 set_bit(ATH_OP_INVALID, &common->op_flags); 541 542 sc->sc_ah = ah; 543 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); 544 sc->tx99_power = MAX_RATE_POWER + 1; 545 init_waitqueue_head(&sc->tx_wait); 546 sc->cur_chan = &sc->chanctx[0]; 547 if (!ath9k_is_chanctx_enabled()) 548 sc->cur_chan->hw_queue_base = 0; 549 550 if (!pdata || pdata->use_eeprom) { 551 ah->ah_flags |= AH_USE_EEPROM; 552 sc->sc_ah->led_pin = -1; 553 } else { 554 sc->sc_ah->gpio_mask = pdata->gpio_mask; 555 sc->sc_ah->gpio_val = pdata->gpio_val; 556 sc->sc_ah->led_pin = pdata->led_pin; 557 ah->is_clk_25mhz = pdata->is_clk_25mhz; 558 ah->get_mac_revision = pdata->get_mac_revision; 559 ah->external_reset = pdata->external_reset; 560 ah->disable_2ghz = pdata->disable_2ghz; 561 ah->disable_5ghz = pdata->disable_5ghz; 562 if (!pdata->endian_check) 563 ah->ah_flags |= AH_NO_EEP_SWAP; 564 } 565 566 common->ops = &ah->reg_ops; 567 common->bus_ops = bus_ops; 568 common->ps_ops = &ath9k_ps_ops; 569 common->ah = ah; 570 common->hw = sc->hw; 571 common->priv = sc; 572 common->debug_mask = ath9k_debug; 573 common->btcoex_enabled = ath9k_btcoex_enable == 1; 574 common->disable_ani = false; 575 576 /* 577 * Platform quirks. 578 */ 579 ath9k_init_pcoem_platform(sc); 580 581 ret = ath9k_init_soc_platform(sc); 582 if (ret) 583 return ret; 584 585 /* 586 * Enable WLAN/BT RX Antenna diversity only when: 587 * 588 * - BTCOEX is disabled. 589 * - the user manually requests the feature. 590 * - the HW cap is set using the platform data. 591 */ 592 if (!common->btcoex_enabled && ath9k_bt_ant_diversity && 593 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) 594 common->bt_ant_diversity = 1; 595 596 spin_lock_init(&common->cc_lock); 597 spin_lock_init(&sc->sc_serial_rw); 598 spin_lock_init(&sc->sc_pm_lock); 599 spin_lock_init(&sc->chan_lock); 600 mutex_init(&sc->mutex); 601 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); 602 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, 603 (unsigned long)sc); 604 605 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); 606 INIT_WORK(&sc->hw_reset_work, ath_reset_work); 607 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); 608 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); 609 610 ath9k_init_channel_context(sc); 611 612 /* 613 * Cache line size is used to size and align various 614 * structures used to communicate with the hardware. 615 */ 616 ath_read_cachesize(common, &csz); 617 common->cachelsz = csz << 2; /* convert to bytes */ 618 619 /* Initializes the hardware for all supported chipsets */ 620 ret = ath9k_hw_init(ah); 621 if (ret) 622 goto err_hw; 623 624 if (pdata && pdata->macaddr) 625 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); 626 627 ret = ath9k_init_queues(sc); 628 if (ret) 629 goto err_queues; 630 631 ret = ath9k_init_btcoex(sc); 632 if (ret) 633 goto err_btcoex; 634 635 ret = ath9k_cmn_init_channels_rates(common); 636 if (ret) 637 goto err_btcoex; 638 639 ret = ath9k_init_p2p(sc); 640 if (ret) 641 goto err_btcoex; 642 643 ath9k_cmn_init_crypto(sc->sc_ah); 644 ath9k_init_misc(sc); 645 ath_fill_led_pin(sc); 646 ath_chanctx_init(sc); 647 ath9k_offchannel_init(sc); 648 649 if (common->bus_ops->aspm_init) 650 common->bus_ops->aspm_init(common); 651 652 return 0; 653 654 err_btcoex: 655 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 656 if (ATH_TXQ_SETUP(sc, i)) 657 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 658 err_queues: 659 ath9k_hw_deinit(ah); 660 err_hw: 661 ath9k_eeprom_release(sc); 662 dev_kfree_skb_any(sc->tx99_skb); 663 return ret; 664 } 665 666 static void ath9k_init_band_txpower(struct ath_softc *sc, int band) 667 { 668 struct ieee80211_supported_band *sband; 669 struct ieee80211_channel *chan; 670 struct ath_hw *ah = sc->sc_ah; 671 struct ath_common *common = ath9k_hw_common(ah); 672 struct cfg80211_chan_def chandef; 673 int i; 674 675 sband = &common->sbands[band]; 676 for (i = 0; i < sband->n_channels; i++) { 677 chan = &sband->channels[i]; 678 ah->curchan = &ah->channels[chan->hw_value]; 679 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); 680 ath9k_cmn_get_channel(sc->hw, ah, &chandef); 681 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); 682 } 683 } 684 685 static void ath9k_init_txpower_limits(struct ath_softc *sc) 686 { 687 struct ath_hw *ah = sc->sc_ah; 688 struct ath9k_channel *curchan = ah->curchan; 689 690 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 691 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); 692 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 693 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); 694 695 ah->curchan = curchan; 696 } 697 698 static const struct ieee80211_iface_limit if_limits[] = { 699 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 700 { .max = 8, .types = 701 #ifdef CONFIG_MAC80211_MESH 702 BIT(NL80211_IFTYPE_MESH_POINT) | 703 #endif 704 BIT(NL80211_IFTYPE_AP) }, 705 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 706 BIT(NL80211_IFTYPE_P2P_GO) }, 707 }; 708 709 static const struct ieee80211_iface_limit wds_limits[] = { 710 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, 711 }; 712 713 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 714 715 static const struct ieee80211_iface_limit if_limits_multi[] = { 716 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | 717 BIT(NL80211_IFTYPE_AP) | 718 BIT(NL80211_IFTYPE_P2P_CLIENT) | 719 BIT(NL80211_IFTYPE_P2P_GO) }, 720 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, 721 }; 722 723 static const struct ieee80211_iface_combination if_comb_multi[] = { 724 { 725 .limits = if_limits_multi, 726 .n_limits = ARRAY_SIZE(if_limits_multi), 727 .max_interfaces = 2, 728 .num_different_channels = 2, 729 .beacon_int_infra_match = true, 730 }, 731 }; 732 733 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 734 735 static const struct ieee80211_iface_limit if_dfs_limits[] = { 736 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | 737 #ifdef CONFIG_MAC80211_MESH 738 BIT(NL80211_IFTYPE_MESH_POINT) | 739 #endif 740 BIT(NL80211_IFTYPE_ADHOC) }, 741 }; 742 743 static const struct ieee80211_iface_combination if_comb[] = { 744 { 745 .limits = if_limits, 746 .n_limits = ARRAY_SIZE(if_limits), 747 .max_interfaces = 2048, 748 .num_different_channels = 1, 749 .beacon_int_infra_match = true, 750 }, 751 { 752 .limits = wds_limits, 753 .n_limits = ARRAY_SIZE(wds_limits), 754 .max_interfaces = 2048, 755 .num_different_channels = 1, 756 .beacon_int_infra_match = true, 757 }, 758 #ifdef CONFIG_ATH9K_DFS_CERTIFIED 759 { 760 .limits = if_dfs_limits, 761 .n_limits = ARRAY_SIZE(if_dfs_limits), 762 .max_interfaces = 1, 763 .num_different_channels = 1, 764 .beacon_int_infra_match = true, 765 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 766 BIT(NL80211_CHAN_WIDTH_20), 767 } 768 #endif 769 }; 770 771 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 772 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 773 { 774 struct ath_hw *ah = sc->sc_ah; 775 struct ath_common *common = ath9k_hw_common(ah); 776 777 if (!ath9k_is_chanctx_enabled()) 778 return; 779 780 hw->flags |= IEEE80211_HW_QUEUE_CONTROL; 781 hw->queues = ATH9K_NUM_TX_QUEUES; 782 hw->offchannel_tx_hw_queue = hw->queues - 1; 783 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS); 784 hw->wiphy->iface_combinations = if_comb_multi; 785 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi); 786 hw->wiphy->max_scan_ssids = 255; 787 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 788 hw->wiphy->max_remain_on_channel_duration = 10000; 789 hw->chanctx_data_size = sizeof(void *); 790 hw->extra_beacon_tailroom = 791 sizeof(struct ieee80211_p2p_noa_attr) + 9; 792 793 ath_dbg(common, CHAN_CTX, "Use channel contexts\n"); 794 } 795 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ 796 797 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) 798 { 799 struct ath_hw *ah = sc->sc_ah; 800 struct ath_common *common = ath9k_hw_common(ah); 801 802 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 803 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 804 IEEE80211_HW_SIGNAL_DBM | 805 IEEE80211_HW_PS_NULLFUNC_STACK | 806 IEEE80211_HW_SPECTRUM_MGMT | 807 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 808 IEEE80211_HW_SUPPORTS_RC_TABLE | 809 IEEE80211_HW_SUPPORTS_HT_CCK_RATES; 810 811 if (ath9k_ps_enable) 812 hw->flags |= IEEE80211_HW_SUPPORTS_PS; 813 814 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 815 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; 816 817 if (AR_SREV_9280_20_OR_LATER(ah)) 818 hw->radiotap_mcs_details |= 819 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 820 } 821 822 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) 823 hw->flags |= IEEE80211_HW_MFP_CAPABLE; 824 825 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR | 826 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | 827 NL80211_FEATURE_P2P_GO_CTWIN; 828 829 if (!config_enabled(CONFIG_ATH9K_TX99)) { 830 hw->wiphy->interface_modes = 831 BIT(NL80211_IFTYPE_P2P_GO) | 832 BIT(NL80211_IFTYPE_P2P_CLIENT) | 833 BIT(NL80211_IFTYPE_AP) | 834 BIT(NL80211_IFTYPE_STATION) | 835 BIT(NL80211_IFTYPE_ADHOC) | 836 BIT(NL80211_IFTYPE_MESH_POINT) | 837 BIT(NL80211_IFTYPE_WDS); 838 839 hw->wiphy->iface_combinations = if_comb; 840 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); 841 } 842 843 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 844 845 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 846 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; 847 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; 848 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 849 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 850 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; 851 852 hw->queues = 4; 853 hw->max_rates = 4; 854 hw->max_listen_interval = 10; 855 hw->max_rate_tries = 10; 856 hw->sta_data_size = sizeof(struct ath_node); 857 hw->vif_data_size = sizeof(struct ath_vif); 858 859 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; 860 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; 861 862 /* single chain devices with rx diversity */ 863 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 864 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); 865 866 sc->ant_rx = hw->wiphy->available_antennas_rx; 867 sc->ant_tx = hw->wiphy->available_antennas_tx; 868 869 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) 870 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 871 &common->sbands[IEEE80211_BAND_2GHZ]; 872 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) 873 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 874 &common->sbands[IEEE80211_BAND_5GHZ]; 875 876 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 877 ath9k_set_mcc_capab(sc, hw); 878 #endif 879 ath9k_init_wow(hw); 880 ath9k_cmn_reload_chainmask(ah); 881 882 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 883 } 884 885 int ath9k_init_device(u16 devid, struct ath_softc *sc, 886 const struct ath_bus_ops *bus_ops) 887 { 888 struct ieee80211_hw *hw = sc->hw; 889 struct ath_common *common; 890 struct ath_hw *ah; 891 int error = 0; 892 struct ath_regulatory *reg; 893 894 /* Bring up device */ 895 error = ath9k_init_softc(devid, sc, bus_ops); 896 if (error) 897 return error; 898 899 ah = sc->sc_ah; 900 common = ath9k_hw_common(ah); 901 ath9k_set_hw_capab(sc, hw); 902 903 /* Initialize regulatory */ 904 error = ath_regd_init(&common->regulatory, sc->hw->wiphy, 905 ath9k_reg_notifier); 906 if (error) 907 goto deinit; 908 909 reg = &common->regulatory; 910 911 /* Setup TX DMA */ 912 error = ath_tx_init(sc, ATH_TXBUF); 913 if (error != 0) 914 goto deinit; 915 916 /* Setup RX DMA */ 917 error = ath_rx_init(sc, ATH_RXBUF); 918 if (error != 0) 919 goto deinit; 920 921 ath9k_init_txpower_limits(sc); 922 923 #ifdef CONFIG_MAC80211_LEDS 924 /* must be initialized before ieee80211_register_hw */ 925 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, 926 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, 927 ARRAY_SIZE(ath9k_tpt_blink)); 928 #endif 929 930 /* Register with mac80211 */ 931 error = ieee80211_register_hw(hw); 932 if (error) 933 goto rx_cleanup; 934 935 error = ath9k_init_debug(ah); 936 if (error) { 937 ath_err(common, "Unable to create debugfs files\n"); 938 goto unregister; 939 } 940 941 /* Handle world regulatory */ 942 if (!ath_is_world_regd(reg)) { 943 error = regulatory_hint(hw->wiphy, reg->alpha2); 944 if (error) 945 goto debug_cleanup; 946 } 947 948 ath_init_leds(sc); 949 ath_start_rfkill_poll(sc); 950 951 return 0; 952 953 debug_cleanup: 954 ath9k_deinit_debug(sc); 955 unregister: 956 ieee80211_unregister_hw(hw); 957 rx_cleanup: 958 ath_rx_cleanup(sc); 959 deinit: 960 ath9k_deinit_softc(sc); 961 return error; 962 } 963 964 /*****************************/ 965 /* De-Initialization */ 966 /*****************************/ 967 968 static void ath9k_deinit_softc(struct ath_softc *sc) 969 { 970 int i = 0; 971 972 ath9k_deinit_p2p(sc); 973 ath9k_deinit_btcoex(sc); 974 975 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 976 if (ATH_TXQ_SETUP(sc, i)) 977 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 978 979 del_timer_sync(&sc->sleep_timer); 980 ath9k_hw_deinit(sc->sc_ah); 981 if (sc->dfs_detector != NULL) 982 sc->dfs_detector->exit(sc->dfs_detector); 983 984 ath9k_eeprom_release(sc); 985 } 986 987 void ath9k_deinit_device(struct ath_softc *sc) 988 { 989 struct ieee80211_hw *hw = sc->hw; 990 991 ath9k_ps_wakeup(sc); 992 993 wiphy_rfkill_stop_polling(sc->hw->wiphy); 994 ath_deinit_leds(sc); 995 996 ath9k_ps_restore(sc); 997 998 ath9k_deinit_debug(sc); 999 ieee80211_unregister_hw(hw); 1000 ath_rx_cleanup(sc); 1001 ath9k_deinit_softc(sc); 1002 } 1003 1004 /************************/ 1005 /* Module Hooks */ 1006 /************************/ 1007 1008 static int __init ath9k_init(void) 1009 { 1010 int error; 1011 1012 error = ath_pci_init(); 1013 if (error < 0) { 1014 pr_err("No PCI devices found, driver not installed\n"); 1015 error = -ENODEV; 1016 goto err_out; 1017 } 1018 1019 error = ath_ahb_init(); 1020 if (error < 0) { 1021 error = -ENODEV; 1022 goto err_pci_exit; 1023 } 1024 1025 return 0; 1026 1027 err_pci_exit: 1028 ath_pci_exit(); 1029 err_out: 1030 return error; 1031 } 1032 module_init(ath9k_init); 1033 1034 static void __exit ath9k_exit(void) 1035 { 1036 is_ath9k_unloaded = true; 1037 ath_ahb_exit(); 1038 ath_pci_exit(); 1039 pr_info("%s: Driver unloaded\n", dev_info); 1040 } 1041 module_exit(ath9k_exit); 1042