1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 24 #include "mac.h" 25 #include "ani.h" 26 #include "eeprom.h" 27 #include "calib.h" 28 #include "reg.h" 29 #include "phy.h" 30 #include "btcoex.h" 31 32 #include "../regd.h" 33 34 #define ATHEROS_VENDOR_ID 0x168c 35 36 #define AR5416_DEVID_PCI 0x0023 37 #define AR5416_DEVID_PCIE 0x0024 38 #define AR9160_DEVID_PCI 0x0027 39 #define AR9280_DEVID_PCI 0x0029 40 #define AR9280_DEVID_PCIE 0x002a 41 #define AR9285_DEVID_PCIE 0x002b 42 #define AR2427_DEVID_PCIE 0x002c 43 #define AR9287_DEVID_PCI 0x002d 44 #define AR9287_DEVID_PCIE 0x002e 45 #define AR9300_DEVID_PCIE 0x0030 46 #define AR9300_DEVID_AR9340 0x0031 47 #define AR9300_DEVID_AR9485_PCIE 0x0032 48 #define AR9300_DEVID_AR9580 0x0033 49 #define AR9300_DEVID_AR9462 0x0034 50 #define AR9300_DEVID_AR9330 0x0035 51 #define AR9300_DEVID_QCA955X 0x0038 52 #define AR9485_DEVID_AR1111 0x0037 53 #define AR9300_DEVID_AR9565 0x0036 54 55 #define AR5416_AR9100_DEVID 0x000b 56 57 #define AR_SUBVENDOR_ID_NOG 0x0e11 58 #define AR_SUBVENDOR_ID_NEW_A 0x7065 59 #define AR5416_MAGIC 0x19641014 60 61 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 62 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 63 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 64 65 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 66 67 #define ATH_DEFAULT_NOISE_FLOOR -95 68 69 #define ATH9K_RSSI_BAD -128 70 71 #define ATH9K_NUM_CHANNELS 38 72 73 /* Register read/write primitives */ 74 #define REG_WRITE(_ah, _reg, _val) \ 75 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 76 77 #define REG_READ(_ah, _reg) \ 78 (_ah)->reg_ops.read((_ah), (_reg)) 79 80 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 81 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 82 83 #define REG_RMW(_ah, _reg, _set, _clr) \ 84 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 85 86 #define ENABLE_REGWRITE_BUFFER(_ah) \ 87 do { \ 88 if ((_ah)->reg_ops.enable_write_buffer) \ 89 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 90 } while (0) 91 92 #define REGWRITE_BUFFER_FLUSH(_ah) \ 93 do { \ 94 if ((_ah)->reg_ops.write_flush) \ 95 (_ah)->reg_ops.write_flush((_ah)); \ 96 } while (0) 97 98 #define PR_EEP(_s, _val) \ 99 do { \ 100 len += snprintf(buf + len, size - len, "%20s : %10d\n", \ 101 _s, (_val)); \ 102 } while (0) 103 104 #define SM(_v, _f) (((_v) << _f##_S) & _f) 105 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 106 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 107 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 108 #define REG_READ_FIELD(_a, _r, _f) \ 109 (((REG_READ(_a, _r) & _f) >> _f##_S)) 110 #define REG_SET_BIT(_a, _r, _f) \ 111 REG_RMW(_a, _r, (_f), 0) 112 #define REG_CLR_BIT(_a, _r, _f) \ 113 REG_RMW(_a, _r, 0, (_f)) 114 115 #define DO_DELAY(x) do { \ 116 if (((++(x) % 64) == 0) && \ 117 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 118 != ATH_USB)) \ 119 udelay(1); \ 120 } while (0) 121 122 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 123 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 124 125 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 126 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 128 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 129 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 130 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 132 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 136 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 137 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 138 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 139 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 140 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 141 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 142 143 #define AR_GPIOD_MASK 0x00001FFF 144 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 145 146 #define BASE_ACTIVATE_DELAY 100 147 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 148 #define COEF_SCALE_S 24 149 #define HT40_CHANNEL_CENTER_SHIFT 10 150 151 #define ATH9K_ANTENNA0_CHAINMASK 0x1 152 #define ATH9K_ANTENNA1_CHAINMASK 0x2 153 154 #define ATH9K_NUM_DMA_DEBUG_REGS 8 155 #define ATH9K_NUM_QUEUES 10 156 157 #define MAX_RATE_POWER 63 158 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 159 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 160 #define AH_TIME_QUANTUM 10 161 #define AR_KEYTABLE_SIZE 128 162 #define POWER_UP_TIME 10000 163 #define SPUR_RSSI_THRESH 40 164 #define UPPER_5G_SUB_BAND_START 5700 165 #define MID_5G_SUB_BAND_START 5400 166 167 #define CAB_TIMEOUT_VAL 10 168 #define BEACON_TIMEOUT_VAL 10 169 #define MIN_BEACON_TIMEOUT_VAL 1 170 #define SLEEP_SLOP 3 171 172 #define INIT_CONFIG_STATUS 0x00000000 173 #define INIT_RSSI_THR 0x00000700 174 #define INIT_BCON_CNTRL_REG 0x00000000 175 176 #define TU_TO_USEC(_tu) ((_tu) << 10) 177 178 #define ATH9K_HW_RX_HP_QDEPTH 16 179 #define ATH9K_HW_RX_LP_QDEPTH 128 180 181 #define PAPRD_GAIN_TABLE_ENTRIES 32 182 #define PAPRD_TABLE_SZ 24 183 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 184 185 /* 186 * Wake on Wireless 187 */ 188 189 /* Keep Alive Frame */ 190 #define KAL_FRAME_LEN 28 191 #define KAL_FRAME_TYPE 0x2 /* data frame */ 192 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ 193 #define KAL_DURATION_ID 0x3d 194 #define KAL_NUM_DATA_WORDS 6 195 #define KAL_NUM_DESC_WORDS 12 196 #define KAL_ANTENNA_MODE 1 197 #define KAL_TO_DS 1 198 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ 199 #define KAL_TIMEOUT 900 200 201 #define MAX_PATTERN_SIZE 256 202 #define MAX_PATTERN_MASK_SIZE 32 203 #define MAX_NUM_PATTERN 8 204 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and 205 deauthenticate packets */ 206 207 /* 208 * WoW trigger mapping to hardware code 209 */ 210 211 #define AH_WOW_USER_PATTERN_EN BIT(0) 212 #define AH_WOW_MAGIC_PATTERN_EN BIT(1) 213 #define AH_WOW_LINK_CHANGE BIT(2) 214 #define AH_WOW_BEACON_MISS BIT(3) 215 216 enum ath_hw_txq_subtype { 217 ATH_TXQ_AC_BE = 0, 218 ATH_TXQ_AC_BK = 1, 219 ATH_TXQ_AC_VI = 2, 220 ATH_TXQ_AC_VO = 3, 221 }; 222 223 enum ath_ini_subsys { 224 ATH_INI_PRE = 0, 225 ATH_INI_CORE, 226 ATH_INI_POST, 227 ATH_INI_NUM_SPLIT, 228 }; 229 230 enum ath9k_hw_caps { 231 ATH9K_HW_CAP_HT = BIT(0), 232 ATH9K_HW_CAP_RFSILENT = BIT(1), 233 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 234 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 235 ATH9K_HW_CAP_EDMA = BIT(4), 236 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 237 ATH9K_HW_CAP_LDPC = BIT(6), 238 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 239 ATH9K_HW_CAP_SGI_20 = BIT(8), 240 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 241 ATH9K_HW_CAP_2GHZ = BIT(11), 242 ATH9K_HW_CAP_5GHZ = BIT(12), 243 ATH9K_HW_CAP_APM = BIT(13), 244 ATH9K_HW_CAP_RTT = BIT(14), 245 ATH9K_HW_CAP_MCI = BIT(15), 246 ATH9K_HW_CAP_DFS = BIT(16), 247 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17), 248 ATH9K_HW_WOW_PATTERN_MATCH_EXACT = BIT(18), 249 ATH9K_HW_WOW_PATTERN_MATCH_DWORD = BIT(19), 250 }; 251 252 /* 253 * WoW device capabilities 254 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. 255 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching 256 * an exact user defined pattern or de-authentication/disassoc pattern. 257 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four 258 * bytes of the pattern for user defined pattern, de-authentication and 259 * disassociation patterns for all types of possible frames recieved 260 * of those types. 261 */ 262 263 struct ath9k_hw_capabilities { 264 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 265 u16 rts_aggr_limit; 266 u8 tx_chainmask; 267 u8 rx_chainmask; 268 u8 max_txchains; 269 u8 max_rxchains; 270 u8 num_gpio_pins; 271 u8 rx_hp_qdepth; 272 u8 rx_lp_qdepth; 273 u8 rx_status_len; 274 u8 tx_desc_len; 275 u8 txs_len; 276 u16 pcie_lcr_offset; 277 bool pcie_lcr_extsync_en; 278 }; 279 280 struct ath9k_ops_config { 281 int dma_beacon_response_time; 282 int sw_beacon_response_time; 283 int additional_swba_backoff; 284 int ack_6mb; 285 u32 cwm_ignore_extcca; 286 bool pcieSerDesWrite; 287 u8 pcie_clock_req; 288 u32 pcie_waen; 289 u8 analog_shiftreg; 290 u32 ofdm_trig_low; 291 u32 ofdm_trig_high; 292 u32 cck_trig_high; 293 u32 cck_trig_low; 294 u32 enable_ani; 295 u32 enable_paprd; 296 int serialize_regmode; 297 bool rx_intr_mitigation; 298 bool tx_intr_mitigation; 299 #define SPUR_DISABLE 0 300 #define SPUR_ENABLE_IOCTL 1 301 #define SPUR_ENABLE_EEPROM 2 302 #define AR_SPUR_5413_1 1640 303 #define AR_SPUR_5413_2 1200 304 #define AR_NO_SPUR 0x8000 305 #define AR_BASE_FREQ_2GHZ 2300 306 #define AR_BASE_FREQ_5GHZ 4900 307 #define AR_SPUR_FEEQ_BOUND_HT40 19 308 #define AR_SPUR_FEEQ_BOUND_HT20 10 309 int spurmode; 310 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 311 u8 max_txtrig_level; 312 u16 ani_poll_interval; /* ANI poll interval in ms */ 313 }; 314 315 enum ath9k_int { 316 ATH9K_INT_RX = 0x00000001, 317 ATH9K_INT_RXDESC = 0x00000002, 318 ATH9K_INT_RXHP = 0x00000001, 319 ATH9K_INT_RXLP = 0x00000002, 320 ATH9K_INT_RXNOFRM = 0x00000008, 321 ATH9K_INT_RXEOL = 0x00000010, 322 ATH9K_INT_RXORN = 0x00000020, 323 ATH9K_INT_TX = 0x00000040, 324 ATH9K_INT_TXDESC = 0x00000080, 325 ATH9K_INT_TIM_TIMER = 0x00000100, 326 ATH9K_INT_MCI = 0x00000200, 327 ATH9K_INT_BB_WATCHDOG = 0x00000400, 328 ATH9K_INT_TXURN = 0x00000800, 329 ATH9K_INT_MIB = 0x00001000, 330 ATH9K_INT_RXPHY = 0x00004000, 331 ATH9K_INT_RXKCM = 0x00008000, 332 ATH9K_INT_SWBA = 0x00010000, 333 ATH9K_INT_BMISS = 0x00040000, 334 ATH9K_INT_BNR = 0x00100000, 335 ATH9K_INT_TIM = 0x00200000, 336 ATH9K_INT_DTIM = 0x00400000, 337 ATH9K_INT_DTIMSYNC = 0x00800000, 338 ATH9K_INT_GPIO = 0x01000000, 339 ATH9K_INT_CABEND = 0x02000000, 340 ATH9K_INT_TSFOOR = 0x04000000, 341 ATH9K_INT_GENTIMER = 0x08000000, 342 ATH9K_INT_CST = 0x10000000, 343 ATH9K_INT_GTT = 0x20000000, 344 ATH9K_INT_FATAL = 0x40000000, 345 ATH9K_INT_GLOBAL = 0x80000000, 346 ATH9K_INT_BMISC = ATH9K_INT_TIM | 347 ATH9K_INT_DTIM | 348 ATH9K_INT_DTIMSYNC | 349 ATH9K_INT_TSFOOR | 350 ATH9K_INT_CABEND, 351 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 352 ATH9K_INT_RXDESC | 353 ATH9K_INT_RXEOL | 354 ATH9K_INT_RXORN | 355 ATH9K_INT_TXURN | 356 ATH9K_INT_TXDESC | 357 ATH9K_INT_MIB | 358 ATH9K_INT_RXPHY | 359 ATH9K_INT_RXKCM | 360 ATH9K_INT_SWBA | 361 ATH9K_INT_BMISS | 362 ATH9K_INT_GPIO, 363 ATH9K_INT_NOCARD = 0xffffffff 364 }; 365 366 #define CHANNEL_CW_INT 0x00002 367 #define CHANNEL_CCK 0x00020 368 #define CHANNEL_OFDM 0x00040 369 #define CHANNEL_2GHZ 0x00080 370 #define CHANNEL_5GHZ 0x00100 371 #define CHANNEL_PASSIVE 0x00200 372 #define CHANNEL_DYN 0x00400 373 #define CHANNEL_HALF 0x04000 374 #define CHANNEL_QUARTER 0x08000 375 #define CHANNEL_HT20 0x10000 376 #define CHANNEL_HT40PLUS 0x20000 377 #define CHANNEL_HT40MINUS 0x40000 378 379 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 380 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 381 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 382 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 383 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 384 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 385 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 386 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 387 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 388 #define CHANNEL_ALL \ 389 (CHANNEL_OFDM| \ 390 CHANNEL_CCK| \ 391 CHANNEL_2GHZ | \ 392 CHANNEL_5GHZ | \ 393 CHANNEL_HT20 | \ 394 CHANNEL_HT40PLUS | \ 395 CHANNEL_HT40MINUS) 396 397 #define MAX_RTT_TABLE_ENTRY 6 398 #define MAX_IQCAL_MEASUREMENT 8 399 #define MAX_CL_TAB_ENTRY 16 400 401 struct ath9k_hw_cal_data { 402 u16 channel; 403 u32 channelFlags; 404 int32_t CalValid; 405 int8_t iCoff; 406 int8_t qCoff; 407 bool rtt_done; 408 bool paprd_packet_sent; 409 bool paprd_done; 410 bool nfcal_pending; 411 bool nfcal_interference; 412 bool done_txiqcal_once; 413 bool done_txclcal_once; 414 u16 small_signal_gain[AR9300_MAX_CHAINS]; 415 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 416 u32 num_measures[AR9300_MAX_CHAINS]; 417 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 418 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 419 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 420 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 421 }; 422 423 struct ath9k_channel { 424 struct ieee80211_channel *chan; 425 struct ar5416AniState ani; 426 u16 channel; 427 u32 channelFlags; 428 u32 chanmode; 429 s16 noisefloor; 430 }; 431 432 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 433 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 434 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 435 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 436 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 437 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 438 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 439 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 440 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 441 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 442 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 443 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 444 445 /* These macros check chanmode and not channelFlags */ 446 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 447 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 448 ((_c)->chanmode == CHANNEL_G_HT20)) 449 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 450 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 451 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 452 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 453 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 454 455 enum ath9k_power_mode { 456 ATH9K_PM_AWAKE = 0, 457 ATH9K_PM_FULL_SLEEP, 458 ATH9K_PM_NETWORK_SLEEP, 459 ATH9K_PM_UNDEFINED 460 }; 461 462 enum ser_reg_mode { 463 SER_REG_MODE_OFF = 0, 464 SER_REG_MODE_ON = 1, 465 SER_REG_MODE_AUTO = 2, 466 }; 467 468 enum ath9k_rx_qtype { 469 ATH9K_RX_QUEUE_HP, 470 ATH9K_RX_QUEUE_LP, 471 ATH9K_RX_QUEUE_MAX, 472 }; 473 474 struct ath9k_beacon_state { 475 u32 bs_nexttbtt; 476 u32 bs_nextdtim; 477 u32 bs_intval; 478 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 479 u32 bs_dtimperiod; 480 u16 bs_cfpperiod; 481 u16 bs_cfpmaxduration; 482 u32 bs_cfpnext; 483 u16 bs_timoffset; 484 u16 bs_bmissthreshold; 485 u32 bs_sleepduration; 486 u32 bs_tsfoor_threshold; 487 }; 488 489 struct chan_centers { 490 u16 synth_center; 491 u16 ctl_center; 492 u16 ext_center; 493 }; 494 495 enum { 496 ATH9K_RESET_POWER_ON, 497 ATH9K_RESET_WARM, 498 ATH9K_RESET_COLD, 499 }; 500 501 struct ath9k_hw_version { 502 u32 magic; 503 u16 devid; 504 u16 subvendorid; 505 u32 macVersion; 506 u16 macRev; 507 u16 phyRev; 508 u16 analog5GhzRev; 509 u16 analog2GhzRev; 510 enum ath_usb_dev usbdev; 511 }; 512 513 /* Generic TSF timer definitions */ 514 515 #define ATH_MAX_GEN_TIMER 16 516 517 #define AR_GENTMR_BIT(_index) (1 << (_index)) 518 519 /* 520 * Using de Bruijin sequence to look up 1's index in a 32 bit number 521 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 522 */ 523 #define debruijn32 0x077CB531U 524 525 struct ath_gen_timer_configuration { 526 u32 next_addr; 527 u32 period_addr; 528 u32 mode_addr; 529 u32 mode_mask; 530 }; 531 532 struct ath_gen_timer { 533 void (*trigger)(void *arg); 534 void (*overflow)(void *arg); 535 void *arg; 536 u8 index; 537 }; 538 539 struct ath_gen_timer_table { 540 u32 gen_timer_index[32]; 541 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 542 union { 543 unsigned long timer_bits; 544 u16 val; 545 } timer_mask; 546 }; 547 548 struct ath_hw_antcomb_conf { 549 u8 main_lna_conf; 550 u8 alt_lna_conf; 551 u8 fast_div_bias; 552 u8 main_gaintb; 553 u8 alt_gaintb; 554 int lna1_lna2_delta; 555 u8 div_group; 556 }; 557 558 /** 559 * struct ath_hw_radar_conf - radar detection initialization parameters 560 * 561 * @pulse_inband: threshold for checking the ratio of in-band power 562 * to total power for short radar pulses (half dB steps) 563 * @pulse_inband_step: threshold for checking an in-band power to total 564 * power ratio increase for short radar pulses (half dB steps) 565 * @pulse_height: threshold for detecting the beginning of a short 566 * radar pulse (dB step) 567 * @pulse_rssi: threshold for detecting if a short radar pulse is 568 * gone (dB step) 569 * @pulse_maxlen: maximum pulse length (0.8 us steps) 570 * 571 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 572 * @radar_inband: threshold for checking the ratio of in-band power 573 * to total power for long radar pulses (half dB steps) 574 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 575 * 576 * @ext_channel: enable extension channel radar detection 577 */ 578 struct ath_hw_radar_conf { 579 unsigned int pulse_inband; 580 unsigned int pulse_inband_step; 581 unsigned int pulse_height; 582 unsigned int pulse_rssi; 583 unsigned int pulse_maxlen; 584 585 unsigned int radar_rssi; 586 unsigned int radar_inband; 587 int fir_power; 588 589 bool ext_channel; 590 }; 591 592 /** 593 * struct ath_hw_private_ops - callbacks used internally by hardware code 594 * 595 * This structure contains private callbacks designed to only be used internally 596 * by the hardware core. 597 * 598 * @init_cal_settings: setup types of calibrations supported 599 * @init_cal: starts actual calibration 600 * 601 * @init_mode_regs: Initializes mode registers 602 * @init_mode_gain_regs: Initialize TX/RX gain registers 603 * 604 * @rf_set_freq: change frequency 605 * @spur_mitigate_freq: spur mitigation 606 * @rf_alloc_ext_banks: 607 * @rf_free_ext_banks: 608 * @set_rf_regs: 609 * @compute_pll_control: compute the PLL control value to use for 610 * AR_RTC_PLL_CONTROL for a given channel 611 * @setup_calibration: set up calibration 612 * @iscal_supported: used to query if a type of calibration is supported 613 * 614 * @ani_cache_ini_regs: cache the values for ANI from the initial 615 * register settings through the register initialization. 616 */ 617 struct ath_hw_private_ops { 618 /* Calibration ops */ 619 void (*init_cal_settings)(struct ath_hw *ah); 620 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 621 622 void (*init_mode_regs)(struct ath_hw *ah); 623 void (*init_mode_gain_regs)(struct ath_hw *ah); 624 void (*setup_calibration)(struct ath_hw *ah, 625 struct ath9k_cal_list *currCal); 626 627 /* PHY ops */ 628 int (*rf_set_freq)(struct ath_hw *ah, 629 struct ath9k_channel *chan); 630 void (*spur_mitigate_freq)(struct ath_hw *ah, 631 struct ath9k_channel *chan); 632 int (*rf_alloc_ext_banks)(struct ath_hw *ah); 633 void (*rf_free_ext_banks)(struct ath_hw *ah); 634 bool (*set_rf_regs)(struct ath_hw *ah, 635 struct ath9k_channel *chan, 636 u16 modesIndex); 637 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 638 void (*init_bb)(struct ath_hw *ah, 639 struct ath9k_channel *chan); 640 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 641 void (*olc_init)(struct ath_hw *ah); 642 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 643 void (*mark_phy_inactive)(struct ath_hw *ah); 644 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 645 bool (*rfbus_req)(struct ath_hw *ah); 646 void (*rfbus_done)(struct ath_hw *ah); 647 void (*restore_chainmask)(struct ath_hw *ah); 648 u32 (*compute_pll_control)(struct ath_hw *ah, 649 struct ath9k_channel *chan); 650 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 651 int param); 652 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 653 void (*set_radar_params)(struct ath_hw *ah, 654 struct ath_hw_radar_conf *conf); 655 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 656 u8 *ini_reloaded); 657 658 /* ANI */ 659 void (*ani_cache_ini_regs)(struct ath_hw *ah); 660 }; 661 662 /** 663 * struct ath_hw_ops - callbacks used by hardware code and driver code 664 * 665 * This structure contains callbacks designed to to be used internally by 666 * hardware code and also by the lower level driver. 667 * 668 * @config_pci_powersave: 669 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 670 */ 671 struct ath_hw_ops { 672 void (*config_pci_powersave)(struct ath_hw *ah, 673 bool power_off); 674 void (*rx_enable)(struct ath_hw *ah); 675 void (*set_desc_link)(void *ds, u32 link); 676 bool (*calibrate)(struct ath_hw *ah, 677 struct ath9k_channel *chan, 678 u8 rxchainmask, 679 bool longcal); 680 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 681 void (*set_txdesc)(struct ath_hw *ah, void *ds, 682 struct ath_tx_info *i); 683 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 684 struct ath_tx_status *ts); 685 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 686 struct ath_hw_antcomb_conf *antconf); 687 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 688 struct ath_hw_antcomb_conf *antconf); 689 void (*antctrl_shared_chain_lnadiv)(struct ath_hw *hw, bool enable); 690 }; 691 692 struct ath_nf_limits { 693 s16 max; 694 s16 min; 695 s16 nominal; 696 }; 697 698 enum ath_cal_list { 699 TX_IQ_CAL = BIT(0), 700 TX_IQ_ON_AGC_CAL = BIT(1), 701 TX_CL_CAL = BIT(2), 702 }; 703 704 /* ah_flags */ 705 #define AH_USE_EEPROM 0x1 706 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 707 #define AH_FASTCC 0x4 708 709 struct ath_hw { 710 struct ath_ops reg_ops; 711 712 struct ieee80211_hw *hw; 713 struct ath_common common; 714 struct ath9k_hw_version hw_version; 715 struct ath9k_ops_config config; 716 struct ath9k_hw_capabilities caps; 717 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 718 struct ath9k_channel *curchan; 719 720 union { 721 struct ar5416_eeprom_def def; 722 struct ar5416_eeprom_4k map4k; 723 struct ar9287_eeprom map9287; 724 struct ar9300_eeprom ar9300_eep; 725 } eeprom; 726 const struct eeprom_ops *eep_ops; 727 728 bool sw_mgmt_crypto; 729 bool is_pciexpress; 730 bool aspm_enabled; 731 bool is_monitoring; 732 bool need_an_top2_fixup; 733 bool shared_chain_lnadiv; 734 u16 tx_trig_level; 735 736 u32 nf_regs[6]; 737 struct ath_nf_limits nf_2g; 738 struct ath_nf_limits nf_5g; 739 u16 rfsilent; 740 u32 rfkill_gpio; 741 u32 rfkill_polarity; 742 u32 ah_flags; 743 744 bool reset_power_on; 745 bool htc_reset_init; 746 747 enum nl80211_iftype opmode; 748 enum ath9k_power_mode power_mode; 749 750 s8 noise; 751 struct ath9k_hw_cal_data *caldata; 752 struct ath9k_pacal_info pacal_info; 753 struct ar5416Stats stats; 754 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 755 756 enum ath9k_int imask; 757 u32 imrs2_reg; 758 u32 txok_interrupt_mask; 759 u32 txerr_interrupt_mask; 760 u32 txdesc_interrupt_mask; 761 u32 txeol_interrupt_mask; 762 u32 txurn_interrupt_mask; 763 atomic_t intr_ref_cnt; 764 bool chip_fullsleep; 765 u32 atim_window; 766 u32 modes_index; 767 768 /* Calibration */ 769 u32 supp_cals; 770 struct ath9k_cal_list iq_caldata; 771 struct ath9k_cal_list adcgain_caldata; 772 struct ath9k_cal_list adcdc_caldata; 773 struct ath9k_cal_list tempCompCalData; 774 struct ath9k_cal_list *cal_list; 775 struct ath9k_cal_list *cal_list_last; 776 struct ath9k_cal_list *cal_list_curr; 777 #define totalPowerMeasI meas0.unsign 778 #define totalPowerMeasQ meas1.unsign 779 #define totalIqCorrMeas meas2.sign 780 #define totalAdcIOddPhase meas0.unsign 781 #define totalAdcIEvenPhase meas1.unsign 782 #define totalAdcQOddPhase meas2.unsign 783 #define totalAdcQEvenPhase meas3.unsign 784 #define totalAdcDcOffsetIOddPhase meas0.sign 785 #define totalAdcDcOffsetIEvenPhase meas1.sign 786 #define totalAdcDcOffsetQOddPhase meas2.sign 787 #define totalAdcDcOffsetQEvenPhase meas3.sign 788 union { 789 u32 unsign[AR5416_MAX_CHAINS]; 790 int32_t sign[AR5416_MAX_CHAINS]; 791 } meas0; 792 union { 793 u32 unsign[AR5416_MAX_CHAINS]; 794 int32_t sign[AR5416_MAX_CHAINS]; 795 } meas1; 796 union { 797 u32 unsign[AR5416_MAX_CHAINS]; 798 int32_t sign[AR5416_MAX_CHAINS]; 799 } meas2; 800 union { 801 u32 unsign[AR5416_MAX_CHAINS]; 802 int32_t sign[AR5416_MAX_CHAINS]; 803 } meas3; 804 u16 cal_samples; 805 u8 enabled_cals; 806 807 u32 sta_id1_defaults; 808 u32 misc_mode; 809 810 /* Private to hardware code */ 811 struct ath_hw_private_ops private_ops; 812 /* Accessed by the lower level driver */ 813 struct ath_hw_ops ops; 814 815 /* Used to program the radio on non single-chip devices */ 816 u32 *analogBank0Data; 817 u32 *analogBank1Data; 818 u32 *analogBank2Data; 819 u32 *analogBank3Data; 820 u32 *analogBank6Data; 821 u32 *analogBank6TPCData; 822 u32 *analogBank7Data; 823 u32 *bank6Temp; 824 825 int coverage_class; 826 u32 slottime; 827 u32 globaltxtimeout; 828 829 /* ANI */ 830 u32 proc_phyerr; 831 u32 aniperiod; 832 int totalSizeDesired[5]; 833 int coarse_high[5]; 834 int coarse_low[5]; 835 int firpwr[5]; 836 enum ath9k_ani_cmd ani_function; 837 838 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 839 struct ath_btcoex_hw btcoex_hw; 840 #endif 841 842 u32 intr_txqs; 843 u8 txchainmask; 844 u8 rxchainmask; 845 846 struct ath_hw_radar_conf radar_conf; 847 848 u32 originalGain[22]; 849 int initPDADC; 850 int PDADCdelta; 851 int led_pin; 852 u32 gpio_mask; 853 u32 gpio_val; 854 855 struct ar5416IniArray iniModes; 856 struct ar5416IniArray iniCommon; 857 struct ar5416IniArray iniBank0; 858 struct ar5416IniArray iniBB_RfGain; 859 struct ar5416IniArray iniBank1; 860 struct ar5416IniArray iniBank2; 861 struct ar5416IniArray iniBank3; 862 struct ar5416IniArray iniBank6; 863 struct ar5416IniArray iniBank6TPC; 864 struct ar5416IniArray iniBank7; 865 struct ar5416IniArray iniAddac; 866 struct ar5416IniArray iniPcieSerdes; 867 #ifdef CONFIG_PM_SLEEP 868 struct ar5416IniArray iniPcieSerdesWow; 869 #endif 870 struct ar5416IniArray iniPcieSerdesLowPower; 871 struct ar5416IniArray iniModesFastClock; 872 struct ar5416IniArray iniAdditional; 873 struct ar5416IniArray iniModesRxGain; 874 struct ar5416IniArray ini_modes_rx_gain_bounds; 875 struct ar5416IniArray iniModesTxGain; 876 struct ar5416IniArray iniCckfirNormal; 877 struct ar5416IniArray iniCckfirJapan2484; 878 struct ar5416IniArray ini_japan2484; 879 struct ar5416IniArray iniModes_9271_ANI_reg; 880 struct ar5416IniArray ini_radio_post_sys2ant; 881 882 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 883 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 884 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 885 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 886 887 u32 intr_gen_timer_trigger; 888 u32 intr_gen_timer_thresh; 889 struct ath_gen_timer_table hw_gen_timers; 890 891 struct ar9003_txs *ts_ring; 892 u32 ts_paddr_start; 893 u32 ts_paddr_end; 894 u16 ts_tail; 895 u16 ts_size; 896 897 u32 bb_watchdog_last_status; 898 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 899 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 900 901 unsigned int paprd_target_power; 902 unsigned int paprd_training_power; 903 unsigned int paprd_ratemask; 904 unsigned int paprd_ratemask_ht40; 905 bool paprd_table_write_done; 906 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 907 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 908 /* 909 * Store the permanent value of Reg 0x4004in WARegVal 910 * so we dont have to R/M/W. We should not be reading 911 * this register when in sleep states. 912 */ 913 u32 WARegVal; 914 915 /* Enterprise mode cap */ 916 u32 ent_mode; 917 918 #ifdef CONFIG_PM_SLEEP 919 u32 wow_event_mask; 920 #endif 921 bool is_clk_25mhz; 922 int (*get_mac_revision)(void); 923 int (*external_reset)(void); 924 }; 925 926 struct ath_bus_ops { 927 enum ath_bus_type ath_bus_type; 928 void (*read_cachesize)(struct ath_common *common, int *csz); 929 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 930 void (*bt_coex_prep)(struct ath_common *common); 931 void (*extn_synch_en)(struct ath_common *common); 932 void (*aspm_init)(struct ath_common *common); 933 }; 934 935 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 936 { 937 return &ah->common; 938 } 939 940 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 941 { 942 return &(ath9k_hw_common(ah)->regulatory); 943 } 944 945 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 946 { 947 return &ah->private_ops; 948 } 949 950 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 951 { 952 return &ah->ops; 953 } 954 955 static inline u8 get_streams(int mask) 956 { 957 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 958 } 959 960 /* Initialization, Detach, Reset */ 961 void ath9k_hw_deinit(struct ath_hw *ah); 962 int ath9k_hw_init(struct ath_hw *ah); 963 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 964 struct ath9k_hw_cal_data *caldata, bool fastcc); 965 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 966 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 967 968 /* GPIO / RFKILL / Antennae */ 969 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 970 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 971 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 972 u32 ah_signal_type); 973 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 974 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 975 976 /* General Operation */ 977 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 978 int hw_delay); 979 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 980 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 981 int column, unsigned int *writecnt); 982 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 983 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 984 u8 phy, int kbps, 985 u32 frameLen, u16 rateix, bool shortPreamble); 986 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 987 struct ath9k_channel *chan, 988 struct chan_centers *centers); 989 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 990 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 991 bool ath9k_hw_phy_disable(struct ath_hw *ah); 992 bool ath9k_hw_disable(struct ath_hw *ah); 993 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 994 void ath9k_hw_setopmode(struct ath_hw *ah); 995 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 996 void ath9k_hw_write_associd(struct ath_hw *ah); 997 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 998 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 999 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1000 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1001 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); 1002 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1003 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1004 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 1005 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1006 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1007 const struct ath9k_beacon_state *bs); 1008 bool ath9k_hw_check_alive(struct ath_hw *ah); 1009 1010 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1011 1012 #ifdef CONFIG_ATH9K_DEBUGFS 1013 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause); 1014 #else 1015 static inline void ath9k_debug_sync_cause(struct ath_common *common, 1016 u32 sync_cause) {} 1017 #endif 1018 1019 /* Generic hw timer primitives */ 1020 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1021 void (*trigger)(void *), 1022 void (*overflow)(void *), 1023 void *arg, 1024 u8 timer_index); 1025 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1026 struct ath_gen_timer *timer, 1027 u32 timer_next, 1028 u32 timer_period); 1029 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1030 1031 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1032 void ath_gen_timer_isr(struct ath_hw *hw); 1033 1034 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1035 1036 /* PHY */ 1037 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1038 u32 *coef_mantissa, u32 *coef_exponent); 1039 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 1040 bool test); 1041 1042 /* 1043 * Code Specific to AR5008, AR9001 or AR9002, 1044 * we stuff these here to avoid callbacks for AR9003. 1045 */ 1046 int ar9002_hw_rf_claim(struct ath_hw *ah); 1047 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1048 1049 /* 1050 * Code specific to AR9003, we stuff these here to avoid callbacks 1051 * for older families 1052 */ 1053 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1054 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1055 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1056 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1057 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1058 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1059 struct ath9k_hw_cal_data *caldata, 1060 int chain); 1061 int ar9003_paprd_create_curve(struct ath_hw *ah, 1062 struct ath9k_hw_cal_data *caldata, int chain); 1063 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1064 int ar9003_paprd_init_table(struct ath_hw *ah); 1065 bool ar9003_paprd_is_done(struct ath_hw *ah); 1066 1067 /* Hardware family op attach helpers */ 1068 void ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1069 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1070 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1071 1072 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1073 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1074 1075 void ar9002_hw_attach_ops(struct ath_hw *ah); 1076 void ar9003_hw_attach_ops(struct ath_hw *ah); 1077 1078 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1079 1080 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1081 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1082 1083 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1084 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1085 { 1086 return ah->btcoex_hw.enabled; 1087 } 1088 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1089 { 1090 return ah->common.btcoex_enabled && 1091 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1092 1093 } 1094 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1095 static inline enum ath_btcoex_scheme 1096 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1097 { 1098 return ah->btcoex_hw.scheme; 1099 } 1100 #else 1101 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1102 { 1103 return false; 1104 } 1105 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1106 { 1107 return false; 1108 } 1109 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1110 { 1111 } 1112 static inline enum ath_btcoex_scheme 1113 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1114 { 1115 return ATH_BTCOEX_CFG_NONE; 1116 } 1117 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1118 1119 1120 #ifdef CONFIG_PM_SLEEP 1121 const char *ath9k_hw_wow_event_to_string(u32 wow_event); 1122 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, 1123 u8 *user_mask, int pattern_count, 1124 int pattern_len); 1125 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); 1126 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); 1127 #else 1128 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event) 1129 { 1130 return NULL; 1131 } 1132 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, 1133 u8 *user_pattern, 1134 u8 *user_mask, 1135 int pattern_count, 1136 int pattern_len) 1137 { 1138 } 1139 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) 1140 { 1141 return 0; 1142 } 1143 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) 1144 { 1145 } 1146 #endif 1147 1148 1149 1150 #define ATH9K_CLOCK_RATE_CCK 22 1151 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1152 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1153 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1154 1155 #endif 1156