1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 24 #include "mac.h" 25 #include "ani.h" 26 #include "eeprom.h" 27 #include "calib.h" 28 #include "reg.h" 29 #include "phy.h" 30 #include "btcoex.h" 31 32 #include "../regd.h" 33 34 #define ATHEROS_VENDOR_ID 0x168c 35 36 #define AR5416_DEVID_PCI 0x0023 37 #define AR5416_DEVID_PCIE 0x0024 38 #define AR9160_DEVID_PCI 0x0027 39 #define AR9280_DEVID_PCI 0x0029 40 #define AR9280_DEVID_PCIE 0x002a 41 #define AR9285_DEVID_PCIE 0x002b 42 #define AR2427_DEVID_PCIE 0x002c 43 #define AR9287_DEVID_PCI 0x002d 44 #define AR9287_DEVID_PCIE 0x002e 45 #define AR9300_DEVID_PCIE 0x0030 46 #define AR9300_DEVID_AR9340 0x0031 47 #define AR9300_DEVID_AR9485_PCIE 0x0032 48 #define AR9300_DEVID_AR9580 0x0033 49 #define AR9300_DEVID_AR9462 0x0034 50 #define AR9300_DEVID_AR9330 0x0035 51 52 #define AR5416_AR9100_DEVID 0x000b 53 54 #define AR_SUBVENDOR_ID_NOG 0x0e11 55 #define AR_SUBVENDOR_ID_NEW_A 0x7065 56 #define AR5416_MAGIC 0x19641014 57 58 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 59 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 60 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 61 62 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 63 64 #define ATH_DEFAULT_NOISE_FLOOR -95 65 66 #define ATH9K_RSSI_BAD -128 67 68 #define ATH9K_NUM_CHANNELS 38 69 70 /* Register read/write primitives */ 71 #define REG_WRITE(_ah, _reg, _val) \ 72 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 73 74 #define REG_READ(_ah, _reg) \ 75 (_ah)->reg_ops.read((_ah), (_reg)) 76 77 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 79 80 #define REG_RMW(_ah, _reg, _set, _clr) \ 81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 82 83 #define ENABLE_REGWRITE_BUFFER(_ah) \ 84 do { \ 85 if ((_ah)->reg_ops.enable_write_buffer) \ 86 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 87 } while (0) 88 89 #define REGWRITE_BUFFER_FLUSH(_ah) \ 90 do { \ 91 if ((_ah)->reg_ops.write_flush) \ 92 (_ah)->reg_ops.write_flush((_ah)); \ 93 } while (0) 94 95 #define PR_EEP(_s, _val) \ 96 do { \ 97 len += snprintf(buf + len, size - len, "%20s : %10d\n", \ 98 _s, (_val)); \ 99 } while (0) 100 101 #define SM(_v, _f) (((_v) << _f##_S) & _f) 102 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 103 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 105 #define REG_READ_FIELD(_a, _r, _f) \ 106 (((REG_READ(_a, _r) & _f) >> _f##_S)) 107 #define REG_SET_BIT(_a, _r, _f) \ 108 REG_RMW(_a, _r, (_f), 0) 109 #define REG_CLR_BIT(_a, _r, _f) \ 110 REG_RMW(_a, _r, 0, (_f)) 111 112 #define DO_DELAY(x) do { \ 113 if (((++(x) % 64) == 0) && \ 114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 115 != ATH_USB)) \ 116 udelay(1); \ 117 } while (0) 118 119 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 120 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 121 122 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 123 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 124 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 125 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 126 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 127 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 128 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 129 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 130 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 131 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 132 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 133 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 134 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 135 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 136 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 137 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 138 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 139 140 #define AR_GPIOD_MASK 0x00001FFF 141 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 142 143 #define BASE_ACTIVATE_DELAY 100 144 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 145 #define COEF_SCALE_S 24 146 #define HT40_CHANNEL_CENTER_SHIFT 10 147 148 #define ATH9K_ANTENNA0_CHAINMASK 0x1 149 #define ATH9K_ANTENNA1_CHAINMASK 0x2 150 151 #define ATH9K_NUM_DMA_DEBUG_REGS 8 152 #define ATH9K_NUM_QUEUES 10 153 154 #define MAX_RATE_POWER 63 155 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 156 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 157 #define AH_TIME_QUANTUM 10 158 #define AR_KEYTABLE_SIZE 128 159 #define POWER_UP_TIME 10000 160 #define SPUR_RSSI_THRESH 40 161 #define UPPER_5G_SUB_BAND_START 5700 162 #define MID_5G_SUB_BAND_START 5400 163 164 #define CAB_TIMEOUT_VAL 10 165 #define BEACON_TIMEOUT_VAL 10 166 #define MIN_BEACON_TIMEOUT_VAL 1 167 #define SLEEP_SLOP 3 168 169 #define INIT_CONFIG_STATUS 0x00000000 170 #define INIT_RSSI_THR 0x00000700 171 #define INIT_BCON_CNTRL_REG 0x00000000 172 173 #define TU_TO_USEC(_tu) ((_tu) << 10) 174 175 #define ATH9K_HW_RX_HP_QDEPTH 16 176 #define ATH9K_HW_RX_LP_QDEPTH 128 177 178 #define PAPRD_GAIN_TABLE_ENTRIES 32 179 #define PAPRD_TABLE_SZ 24 180 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 181 182 enum ath_hw_txq_subtype { 183 ATH_TXQ_AC_BE = 0, 184 ATH_TXQ_AC_BK = 1, 185 ATH_TXQ_AC_VI = 2, 186 ATH_TXQ_AC_VO = 3, 187 }; 188 189 enum ath_ini_subsys { 190 ATH_INI_PRE = 0, 191 ATH_INI_CORE, 192 ATH_INI_POST, 193 ATH_INI_NUM_SPLIT, 194 }; 195 196 enum ath9k_hw_caps { 197 ATH9K_HW_CAP_HT = BIT(0), 198 ATH9K_HW_CAP_RFSILENT = BIT(1), 199 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 200 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 201 ATH9K_HW_CAP_EDMA = BIT(4), 202 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 203 ATH9K_HW_CAP_LDPC = BIT(6), 204 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 205 ATH9K_HW_CAP_SGI_20 = BIT(8), 206 ATH9K_HW_CAP_PAPRD = BIT(9), 207 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 208 ATH9K_HW_CAP_2GHZ = BIT(11), 209 ATH9K_HW_CAP_5GHZ = BIT(12), 210 ATH9K_HW_CAP_APM = BIT(13), 211 ATH9K_HW_CAP_RTT = BIT(14), 212 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 213 ATH9K_HW_CAP_MCI = BIT(15), 214 #else 215 ATH9K_HW_CAP_MCI = 0, 216 #endif 217 ATH9K_HW_CAP_DFS = BIT(16), 218 }; 219 220 struct ath9k_hw_capabilities { 221 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 222 u16 rts_aggr_limit; 223 u8 tx_chainmask; 224 u8 rx_chainmask; 225 u8 max_txchains; 226 u8 max_rxchains; 227 u8 num_gpio_pins; 228 u8 rx_hp_qdepth; 229 u8 rx_lp_qdepth; 230 u8 rx_status_len; 231 u8 tx_desc_len; 232 u8 txs_len; 233 u16 pcie_lcr_offset; 234 bool pcie_lcr_extsync_en; 235 }; 236 237 struct ath9k_ops_config { 238 int dma_beacon_response_time; 239 int sw_beacon_response_time; 240 int additional_swba_backoff; 241 int ack_6mb; 242 u32 cwm_ignore_extcca; 243 bool pcieSerDesWrite; 244 u8 pcie_clock_req; 245 u32 pcie_waen; 246 u8 analog_shiftreg; 247 u8 paprd_disable; 248 u32 ofdm_trig_low; 249 u32 ofdm_trig_high; 250 u32 cck_trig_high; 251 u32 cck_trig_low; 252 u32 enable_ani; 253 int serialize_regmode; 254 bool rx_intr_mitigation; 255 bool tx_intr_mitigation; 256 #define SPUR_DISABLE 0 257 #define SPUR_ENABLE_IOCTL 1 258 #define SPUR_ENABLE_EEPROM 2 259 #define AR_SPUR_5413_1 1640 260 #define AR_SPUR_5413_2 1200 261 #define AR_NO_SPUR 0x8000 262 #define AR_BASE_FREQ_2GHZ 2300 263 #define AR_BASE_FREQ_5GHZ 4900 264 #define AR_SPUR_FEEQ_BOUND_HT40 19 265 #define AR_SPUR_FEEQ_BOUND_HT20 10 266 int spurmode; 267 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 268 u8 max_txtrig_level; 269 u16 ani_poll_interval; /* ANI poll interval in ms */ 270 }; 271 272 enum ath9k_int { 273 ATH9K_INT_RX = 0x00000001, 274 ATH9K_INT_RXDESC = 0x00000002, 275 ATH9K_INT_RXHP = 0x00000001, 276 ATH9K_INT_RXLP = 0x00000002, 277 ATH9K_INT_RXNOFRM = 0x00000008, 278 ATH9K_INT_RXEOL = 0x00000010, 279 ATH9K_INT_RXORN = 0x00000020, 280 ATH9K_INT_TX = 0x00000040, 281 ATH9K_INT_TXDESC = 0x00000080, 282 ATH9K_INT_TIM_TIMER = 0x00000100, 283 ATH9K_INT_MCI = 0x00000200, 284 ATH9K_INT_BB_WATCHDOG = 0x00000400, 285 ATH9K_INT_TXURN = 0x00000800, 286 ATH9K_INT_MIB = 0x00001000, 287 ATH9K_INT_RXPHY = 0x00004000, 288 ATH9K_INT_RXKCM = 0x00008000, 289 ATH9K_INT_SWBA = 0x00010000, 290 ATH9K_INT_BMISS = 0x00040000, 291 ATH9K_INT_BNR = 0x00100000, 292 ATH9K_INT_TIM = 0x00200000, 293 ATH9K_INT_DTIM = 0x00400000, 294 ATH9K_INT_DTIMSYNC = 0x00800000, 295 ATH9K_INT_GPIO = 0x01000000, 296 ATH9K_INT_CABEND = 0x02000000, 297 ATH9K_INT_TSFOOR = 0x04000000, 298 ATH9K_INT_GENTIMER = 0x08000000, 299 ATH9K_INT_CST = 0x10000000, 300 ATH9K_INT_GTT = 0x20000000, 301 ATH9K_INT_FATAL = 0x40000000, 302 ATH9K_INT_GLOBAL = 0x80000000, 303 ATH9K_INT_BMISC = ATH9K_INT_TIM | 304 ATH9K_INT_DTIM | 305 ATH9K_INT_DTIMSYNC | 306 ATH9K_INT_TSFOOR | 307 ATH9K_INT_CABEND, 308 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 309 ATH9K_INT_RXDESC | 310 ATH9K_INT_RXEOL | 311 ATH9K_INT_RXORN | 312 ATH9K_INT_TXURN | 313 ATH9K_INT_TXDESC | 314 ATH9K_INT_MIB | 315 ATH9K_INT_RXPHY | 316 ATH9K_INT_RXKCM | 317 ATH9K_INT_SWBA | 318 ATH9K_INT_BMISS | 319 ATH9K_INT_GPIO, 320 ATH9K_INT_NOCARD = 0xffffffff 321 }; 322 323 #define CHANNEL_CW_INT 0x00002 324 #define CHANNEL_CCK 0x00020 325 #define CHANNEL_OFDM 0x00040 326 #define CHANNEL_2GHZ 0x00080 327 #define CHANNEL_5GHZ 0x00100 328 #define CHANNEL_PASSIVE 0x00200 329 #define CHANNEL_DYN 0x00400 330 #define CHANNEL_HALF 0x04000 331 #define CHANNEL_QUARTER 0x08000 332 #define CHANNEL_HT20 0x10000 333 #define CHANNEL_HT40PLUS 0x20000 334 #define CHANNEL_HT40MINUS 0x40000 335 336 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 337 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 338 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 339 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 340 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 341 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 342 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 343 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 344 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 345 #define CHANNEL_ALL \ 346 (CHANNEL_OFDM| \ 347 CHANNEL_CCK| \ 348 CHANNEL_2GHZ | \ 349 CHANNEL_5GHZ | \ 350 CHANNEL_HT20 | \ 351 CHANNEL_HT40PLUS | \ 352 CHANNEL_HT40MINUS) 353 354 #define MAX_RTT_TABLE_ENTRY 6 355 #define RTT_HIST_MAX 3 356 struct ath9k_rtt_hist { 357 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY]; 358 u8 num_readings; 359 }; 360 361 #define MAX_IQCAL_MEASUREMENT 8 362 #define MAX_CL_TAB_ENTRY 16 363 364 struct ath9k_hw_cal_data { 365 u16 channel; 366 u32 channelFlags; 367 int32_t CalValid; 368 int8_t iCoff; 369 int8_t qCoff; 370 bool paprd_done; 371 bool nfcal_pending; 372 bool nfcal_interference; 373 bool done_txiqcal_once; 374 bool done_txclcal_once; 375 u16 small_signal_gain[AR9300_MAX_CHAINS]; 376 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 377 u32 num_measures[AR9300_MAX_CHAINS]; 378 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 379 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 380 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 381 struct ath9k_rtt_hist rtt_hist; 382 }; 383 384 struct ath9k_channel { 385 struct ieee80211_channel *chan; 386 struct ar5416AniState ani; 387 u16 channel; 388 u32 channelFlags; 389 u32 chanmode; 390 s16 noisefloor; 391 }; 392 393 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 394 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 395 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 396 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 397 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 398 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 399 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 400 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 401 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 402 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 403 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 404 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 405 406 /* These macros check chanmode and not channelFlags */ 407 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 408 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 409 ((_c)->chanmode == CHANNEL_G_HT20)) 410 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 411 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 412 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 413 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 414 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 415 416 enum ath9k_power_mode { 417 ATH9K_PM_AWAKE = 0, 418 ATH9K_PM_FULL_SLEEP, 419 ATH9K_PM_NETWORK_SLEEP, 420 ATH9K_PM_UNDEFINED 421 }; 422 423 enum ser_reg_mode { 424 SER_REG_MODE_OFF = 0, 425 SER_REG_MODE_ON = 1, 426 SER_REG_MODE_AUTO = 2, 427 }; 428 429 enum ath9k_rx_qtype { 430 ATH9K_RX_QUEUE_HP, 431 ATH9K_RX_QUEUE_LP, 432 ATH9K_RX_QUEUE_MAX, 433 }; 434 435 enum mci_message_header { /* length of payload */ 436 MCI_LNA_CTRL = 0x10, /* len = 0 */ 437 MCI_CONT_NACK = 0x20, /* len = 0 */ 438 MCI_CONT_INFO = 0x30, /* len = 4 */ 439 MCI_CONT_RST = 0x40, /* len = 0 */ 440 MCI_SCHD_INFO = 0x50, /* len = 16 */ 441 MCI_CPU_INT = 0x60, /* len = 4 */ 442 MCI_SYS_WAKING = 0x70, /* len = 0 */ 443 MCI_GPM = 0x80, /* len = 16 */ 444 MCI_LNA_INFO = 0x90, /* len = 1 */ 445 MCI_LNA_STATE = 0x94, 446 MCI_LNA_TAKE = 0x98, 447 MCI_LNA_TRANS = 0x9c, 448 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ 449 MCI_REQ_WAKE = 0xc0, /* len = 0 */ 450 MCI_DEBUG_16 = 0xfe, /* len = 2 */ 451 MCI_REMOTE_RESET = 0xff /* len = 16 */ 452 }; 453 454 enum ath_mci_gpm_coex_profile_type { 455 MCI_GPM_COEX_PROFILE_UNKNOWN, 456 MCI_GPM_COEX_PROFILE_RFCOMM, 457 MCI_GPM_COEX_PROFILE_A2DP, 458 MCI_GPM_COEX_PROFILE_HID, 459 MCI_GPM_COEX_PROFILE_BNEP, 460 MCI_GPM_COEX_PROFILE_VOICE, 461 MCI_GPM_COEX_PROFILE_MAX 462 }; 463 464 /* MCI GPM/Coex opcode/type definitions */ 465 enum { 466 MCI_GPM_COEX_W_GPM_PAYLOAD = 1, 467 MCI_GPM_COEX_B_GPM_TYPE = 4, 468 MCI_GPM_COEX_B_GPM_OPCODE = 5, 469 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ 470 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, 471 472 /* MCI_GPM_COEX_VERSION_QUERY */ 473 /* MCI_GPM_COEX_VERSION_RESPONSE */ 474 MCI_GPM_COEX_B_MAJOR_VERSION = 6, 475 MCI_GPM_COEX_B_MINOR_VERSION = 7, 476 /* MCI_GPM_COEX_STATUS_QUERY */ 477 MCI_GPM_COEX_B_BT_BITMAP = 6, 478 MCI_GPM_COEX_B_WLAN_BITMAP = 7, 479 /* MCI_GPM_COEX_HALT_BT_GPM */ 480 MCI_GPM_COEX_B_HALT_STATE = 6, 481 /* MCI_GPM_COEX_WLAN_CHANNELS */ 482 MCI_GPM_COEX_B_CHANNEL_MAP = 6, 483 /* MCI_GPM_COEX_BT_PROFILE_INFO */ 484 MCI_GPM_COEX_B_PROFILE_TYPE = 6, 485 MCI_GPM_COEX_B_PROFILE_LINKID = 7, 486 MCI_GPM_COEX_B_PROFILE_STATE = 8, 487 MCI_GPM_COEX_B_PROFILE_ROLE = 9, 488 MCI_GPM_COEX_B_PROFILE_RATE = 10, 489 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, 490 MCI_GPM_COEX_H_PROFILE_T = 12, 491 MCI_GPM_COEX_B_PROFILE_W = 14, 492 MCI_GPM_COEX_B_PROFILE_A = 15, 493 /* MCI_GPM_COEX_BT_STATUS_UPDATE */ 494 MCI_GPM_COEX_B_STATUS_TYPE = 6, 495 MCI_GPM_COEX_B_STATUS_LINKID = 7, 496 MCI_GPM_COEX_B_STATUS_STATE = 8, 497 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ 498 MCI_GPM_COEX_W_BT_FLAGS = 6, 499 MCI_GPM_COEX_B_BT_FLAGS_OP = 10 500 }; 501 502 enum mci_gpm_subtype { 503 MCI_GPM_BT_CAL_REQ = 0, 504 MCI_GPM_BT_CAL_GRANT = 1, 505 MCI_GPM_BT_CAL_DONE = 2, 506 MCI_GPM_WLAN_CAL_REQ = 3, 507 MCI_GPM_WLAN_CAL_GRANT = 4, 508 MCI_GPM_WLAN_CAL_DONE = 5, 509 MCI_GPM_COEX_AGENT = 0x0c, 510 MCI_GPM_RSVD_PATTERN = 0xfe, 511 MCI_GPM_RSVD_PATTERN32 = 0xfefefefe, 512 MCI_GPM_BT_DEBUG = 0xff 513 }; 514 515 enum mci_bt_state { 516 MCI_BT_SLEEP, 517 MCI_BT_AWAKE, 518 MCI_BT_CAL_START, 519 MCI_BT_CAL 520 }; 521 522 /* Type of state query */ 523 enum mci_state_type { 524 MCI_STATE_ENABLE, 525 MCI_STATE_INIT_GPM_OFFSET, 526 MCI_STATE_NEXT_GPM_OFFSET, 527 MCI_STATE_LAST_GPM_OFFSET, 528 MCI_STATE_BT, 529 MCI_STATE_SET_BT_SLEEP, 530 MCI_STATE_SET_BT_AWAKE, 531 MCI_STATE_SET_BT_CAL_START, 532 MCI_STATE_SET_BT_CAL, 533 MCI_STATE_LAST_SCHD_MSG_OFFSET, 534 MCI_STATE_REMOTE_SLEEP, 535 MCI_STATE_CONT_RSSI_POWER, 536 MCI_STATE_CONT_PRIORITY, 537 MCI_STATE_CONT_TXRX, 538 MCI_STATE_RESET_REQ_WAKE, 539 MCI_STATE_SEND_WLAN_COEX_VERSION, 540 MCI_STATE_SET_BT_COEX_VERSION, 541 MCI_STATE_SEND_WLAN_CHANNELS, 542 MCI_STATE_SEND_VERSION_QUERY, 543 MCI_STATE_SEND_STATUS_QUERY, 544 MCI_STATE_NEED_FLUSH_BT_INFO, 545 MCI_STATE_SET_CONCUR_TX_PRI, 546 MCI_STATE_RECOVER_RX, 547 MCI_STATE_NEED_FTP_STOMP, 548 MCI_STATE_NEED_TUNING, 549 MCI_STATE_DEBUG, 550 MCI_STATE_MAX 551 }; 552 553 enum mci_gpm_coex_opcode { 554 MCI_GPM_COEX_VERSION_QUERY, 555 MCI_GPM_COEX_VERSION_RESPONSE, 556 MCI_GPM_COEX_STATUS_QUERY, 557 MCI_GPM_COEX_HALT_BT_GPM, 558 MCI_GPM_COEX_WLAN_CHANNELS, 559 MCI_GPM_COEX_BT_PROFILE_INFO, 560 MCI_GPM_COEX_BT_STATUS_UPDATE, 561 MCI_GPM_COEX_BT_UPDATE_FLAGS 562 }; 563 564 #define MCI_GPM_NOMORE 0 565 #define MCI_GPM_MORE 1 566 #define MCI_GPM_INVALID 0xffffffff 567 568 #define MCI_GPM_RECYCLE(_p_gpm) do { \ 569 *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \ 570 MCI_GPM_RSVD_PATTERN32; \ 571 } while (0) 572 573 #define MCI_GPM_TYPE(_p_gpm) \ 574 (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) 575 576 #define MCI_GPM_OPCODE(_p_gpm) \ 577 (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) 578 579 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do { \ 580 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\ 581 } while (0) 582 583 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do { \ 584 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ 585 *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\ 586 } while (0) 587 588 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) 589 590 struct ath9k_beacon_state { 591 u32 bs_nexttbtt; 592 u32 bs_nextdtim; 593 u32 bs_intval; 594 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 595 u32 bs_dtimperiod; 596 u16 bs_cfpperiod; 597 u16 bs_cfpmaxduration; 598 u32 bs_cfpnext; 599 u16 bs_timoffset; 600 u16 bs_bmissthreshold; 601 u32 bs_sleepduration; 602 u32 bs_tsfoor_threshold; 603 }; 604 605 struct chan_centers { 606 u16 synth_center; 607 u16 ctl_center; 608 u16 ext_center; 609 }; 610 611 enum { 612 ATH9K_RESET_POWER_ON, 613 ATH9K_RESET_WARM, 614 ATH9K_RESET_COLD, 615 }; 616 617 struct ath9k_hw_version { 618 u32 magic; 619 u16 devid; 620 u16 subvendorid; 621 u32 macVersion; 622 u16 macRev; 623 u16 phyRev; 624 u16 analog5GhzRev; 625 u16 analog2GhzRev; 626 enum ath_usb_dev usbdev; 627 }; 628 629 /* Generic TSF timer definitions */ 630 631 #define ATH_MAX_GEN_TIMER 16 632 633 #define AR_GENTMR_BIT(_index) (1 << (_index)) 634 635 /* 636 * Using de Bruijin sequence to look up 1's index in a 32 bit number 637 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 638 */ 639 #define debruijn32 0x077CB531U 640 641 struct ath_gen_timer_configuration { 642 u32 next_addr; 643 u32 period_addr; 644 u32 mode_addr; 645 u32 mode_mask; 646 }; 647 648 struct ath_gen_timer { 649 void (*trigger)(void *arg); 650 void (*overflow)(void *arg); 651 void *arg; 652 u8 index; 653 }; 654 655 struct ath_gen_timer_table { 656 u32 gen_timer_index[32]; 657 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 658 union { 659 unsigned long timer_bits; 660 u16 val; 661 } timer_mask; 662 }; 663 664 struct ath_hw_antcomb_conf { 665 u8 main_lna_conf; 666 u8 alt_lna_conf; 667 u8 fast_div_bias; 668 u8 main_gaintb; 669 u8 alt_gaintb; 670 int lna1_lna2_delta; 671 u8 div_group; 672 }; 673 674 /** 675 * struct ath_hw_radar_conf - radar detection initialization parameters 676 * 677 * @pulse_inband: threshold for checking the ratio of in-band power 678 * to total power for short radar pulses (half dB steps) 679 * @pulse_inband_step: threshold for checking an in-band power to total 680 * power ratio increase for short radar pulses (half dB steps) 681 * @pulse_height: threshold for detecting the beginning of a short 682 * radar pulse (dB step) 683 * @pulse_rssi: threshold for detecting if a short radar pulse is 684 * gone (dB step) 685 * @pulse_maxlen: maximum pulse length (0.8 us steps) 686 * 687 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 688 * @radar_inband: threshold for checking the ratio of in-band power 689 * to total power for long radar pulses (half dB steps) 690 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 691 * 692 * @ext_channel: enable extension channel radar detection 693 */ 694 struct ath_hw_radar_conf { 695 unsigned int pulse_inband; 696 unsigned int pulse_inband_step; 697 unsigned int pulse_height; 698 unsigned int pulse_rssi; 699 unsigned int pulse_maxlen; 700 701 unsigned int radar_rssi; 702 unsigned int radar_inband; 703 int fir_power; 704 705 bool ext_channel; 706 }; 707 708 /** 709 * struct ath_hw_private_ops - callbacks used internally by hardware code 710 * 711 * This structure contains private callbacks designed to only be used internally 712 * by the hardware core. 713 * 714 * @init_cal_settings: setup types of calibrations supported 715 * @init_cal: starts actual calibration 716 * 717 * @init_mode_regs: Initializes mode registers 718 * @init_mode_gain_regs: Initialize TX/RX gain registers 719 * 720 * @rf_set_freq: change frequency 721 * @spur_mitigate_freq: spur mitigation 722 * @rf_alloc_ext_banks: 723 * @rf_free_ext_banks: 724 * @set_rf_regs: 725 * @compute_pll_control: compute the PLL control value to use for 726 * AR_RTC_PLL_CONTROL for a given channel 727 * @setup_calibration: set up calibration 728 * @iscal_supported: used to query if a type of calibration is supported 729 * 730 * @ani_cache_ini_regs: cache the values for ANI from the initial 731 * register settings through the register initialization. 732 */ 733 struct ath_hw_private_ops { 734 /* Calibration ops */ 735 void (*init_cal_settings)(struct ath_hw *ah); 736 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 737 738 void (*init_mode_regs)(struct ath_hw *ah); 739 void (*init_mode_gain_regs)(struct ath_hw *ah); 740 void (*setup_calibration)(struct ath_hw *ah, 741 struct ath9k_cal_list *currCal); 742 743 /* PHY ops */ 744 int (*rf_set_freq)(struct ath_hw *ah, 745 struct ath9k_channel *chan); 746 void (*spur_mitigate_freq)(struct ath_hw *ah, 747 struct ath9k_channel *chan); 748 int (*rf_alloc_ext_banks)(struct ath_hw *ah); 749 void (*rf_free_ext_banks)(struct ath_hw *ah); 750 bool (*set_rf_regs)(struct ath_hw *ah, 751 struct ath9k_channel *chan, 752 u16 modesIndex); 753 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 754 void (*init_bb)(struct ath_hw *ah, 755 struct ath9k_channel *chan); 756 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 757 void (*olc_init)(struct ath_hw *ah); 758 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 759 void (*mark_phy_inactive)(struct ath_hw *ah); 760 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 761 bool (*rfbus_req)(struct ath_hw *ah); 762 void (*rfbus_done)(struct ath_hw *ah); 763 void (*restore_chainmask)(struct ath_hw *ah); 764 u32 (*compute_pll_control)(struct ath_hw *ah, 765 struct ath9k_channel *chan); 766 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 767 int param); 768 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 769 void (*set_radar_params)(struct ath_hw *ah, 770 struct ath_hw_radar_conf *conf); 771 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 772 u8 *ini_reloaded); 773 774 /* ANI */ 775 void (*ani_cache_ini_regs)(struct ath_hw *ah); 776 }; 777 778 /** 779 * struct ath_hw_ops - callbacks used by hardware code and driver code 780 * 781 * This structure contains callbacks designed to to be used internally by 782 * hardware code and also by the lower level driver. 783 * 784 * @config_pci_powersave: 785 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 786 */ 787 struct ath_hw_ops { 788 void (*config_pci_powersave)(struct ath_hw *ah, 789 bool power_off); 790 void (*rx_enable)(struct ath_hw *ah); 791 void (*set_desc_link)(void *ds, u32 link); 792 bool (*calibrate)(struct ath_hw *ah, 793 struct ath9k_channel *chan, 794 u8 rxchainmask, 795 bool longcal); 796 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 797 void (*set_txdesc)(struct ath_hw *ah, void *ds, 798 struct ath_tx_info *i); 799 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 800 struct ath_tx_status *ts); 801 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 802 struct ath_hw_antcomb_conf *antconf); 803 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 804 struct ath_hw_antcomb_conf *antconf); 805 806 }; 807 808 struct ath_nf_limits { 809 s16 max; 810 s16 min; 811 s16 nominal; 812 }; 813 814 enum ath_cal_list { 815 TX_IQ_CAL = BIT(0), 816 TX_IQ_ON_AGC_CAL = BIT(1), 817 TX_CL_CAL = BIT(2), 818 }; 819 820 /* ah_flags */ 821 #define AH_USE_EEPROM 0x1 822 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 823 #define AH_FASTCC 0x4 824 825 struct ath_hw { 826 struct ath_ops reg_ops; 827 828 struct ieee80211_hw *hw; 829 struct ath_common common; 830 struct ath9k_hw_version hw_version; 831 struct ath9k_ops_config config; 832 struct ath9k_hw_capabilities caps; 833 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 834 struct ath9k_channel *curchan; 835 836 union { 837 struct ar5416_eeprom_def def; 838 struct ar5416_eeprom_4k map4k; 839 struct ar9287_eeprom map9287; 840 struct ar9300_eeprom ar9300_eep; 841 } eeprom; 842 const struct eeprom_ops *eep_ops; 843 844 bool sw_mgmt_crypto; 845 bool is_pciexpress; 846 bool aspm_enabled; 847 bool is_monitoring; 848 bool need_an_top2_fixup; 849 u16 tx_trig_level; 850 851 u32 nf_regs[6]; 852 struct ath_nf_limits nf_2g; 853 struct ath_nf_limits nf_5g; 854 u16 rfsilent; 855 u32 rfkill_gpio; 856 u32 rfkill_polarity; 857 u32 ah_flags; 858 859 bool htc_reset_init; 860 861 enum nl80211_iftype opmode; 862 enum ath9k_power_mode power_mode; 863 864 s8 noise; 865 struct ath9k_hw_cal_data *caldata; 866 struct ath9k_pacal_info pacal_info; 867 struct ar5416Stats stats; 868 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 869 870 int16_t curchan_rad_index; 871 enum ath9k_int imask; 872 u32 imrs2_reg; 873 u32 txok_interrupt_mask; 874 u32 txerr_interrupt_mask; 875 u32 txdesc_interrupt_mask; 876 u32 txeol_interrupt_mask; 877 u32 txurn_interrupt_mask; 878 atomic_t intr_ref_cnt; 879 bool chip_fullsleep; 880 u32 atim_window; 881 u32 modes_index; 882 883 /* Calibration */ 884 u32 supp_cals; 885 struct ath9k_cal_list iq_caldata; 886 struct ath9k_cal_list adcgain_caldata; 887 struct ath9k_cal_list adcdc_caldata; 888 struct ath9k_cal_list tempCompCalData; 889 struct ath9k_cal_list *cal_list; 890 struct ath9k_cal_list *cal_list_last; 891 struct ath9k_cal_list *cal_list_curr; 892 #define totalPowerMeasI meas0.unsign 893 #define totalPowerMeasQ meas1.unsign 894 #define totalIqCorrMeas meas2.sign 895 #define totalAdcIOddPhase meas0.unsign 896 #define totalAdcIEvenPhase meas1.unsign 897 #define totalAdcQOddPhase meas2.unsign 898 #define totalAdcQEvenPhase meas3.unsign 899 #define totalAdcDcOffsetIOddPhase meas0.sign 900 #define totalAdcDcOffsetIEvenPhase meas1.sign 901 #define totalAdcDcOffsetQOddPhase meas2.sign 902 #define totalAdcDcOffsetQEvenPhase meas3.sign 903 union { 904 u32 unsign[AR5416_MAX_CHAINS]; 905 int32_t sign[AR5416_MAX_CHAINS]; 906 } meas0; 907 union { 908 u32 unsign[AR5416_MAX_CHAINS]; 909 int32_t sign[AR5416_MAX_CHAINS]; 910 } meas1; 911 union { 912 u32 unsign[AR5416_MAX_CHAINS]; 913 int32_t sign[AR5416_MAX_CHAINS]; 914 } meas2; 915 union { 916 u32 unsign[AR5416_MAX_CHAINS]; 917 int32_t sign[AR5416_MAX_CHAINS]; 918 } meas3; 919 u16 cal_samples; 920 u8 enabled_cals; 921 922 u32 sta_id1_defaults; 923 u32 misc_mode; 924 enum { 925 AUTO_32KHZ, 926 USE_32KHZ, 927 DONT_USE_32KHZ, 928 } enable_32kHz_clock; 929 930 /* Private to hardware code */ 931 struct ath_hw_private_ops private_ops; 932 /* Accessed by the lower level driver */ 933 struct ath_hw_ops ops; 934 935 /* Used to program the radio on non single-chip devices */ 936 u32 *analogBank0Data; 937 u32 *analogBank1Data; 938 u32 *analogBank2Data; 939 u32 *analogBank3Data; 940 u32 *analogBank6Data; 941 u32 *analogBank6TPCData; 942 u32 *analogBank7Data; 943 u32 *addac5416_21; 944 u32 *bank6Temp; 945 946 u8 txpower_limit; 947 int coverage_class; 948 u32 slottime; 949 u32 globaltxtimeout; 950 951 /* ANI */ 952 u32 proc_phyerr; 953 u32 aniperiod; 954 int totalSizeDesired[5]; 955 int coarse_high[5]; 956 int coarse_low[5]; 957 int firpwr[5]; 958 enum ath9k_ani_cmd ani_function; 959 960 /* Bluetooth coexistance */ 961 struct ath_btcoex_hw btcoex_hw; 962 963 u32 intr_txqs; 964 u8 txchainmask; 965 u8 rxchainmask; 966 967 struct ath_hw_radar_conf radar_conf; 968 969 u32 originalGain[22]; 970 int initPDADC; 971 int PDADCdelta; 972 int led_pin; 973 u32 gpio_mask; 974 u32 gpio_val; 975 976 struct ar5416IniArray iniModes; 977 struct ar5416IniArray iniCommon; 978 struct ar5416IniArray iniBank0; 979 struct ar5416IniArray iniBB_RfGain; 980 struct ar5416IniArray iniBank1; 981 struct ar5416IniArray iniBank2; 982 struct ar5416IniArray iniBank3; 983 struct ar5416IniArray iniBank6; 984 struct ar5416IniArray iniBank6TPC; 985 struct ar5416IniArray iniBank7; 986 struct ar5416IniArray iniAddac; 987 struct ar5416IniArray iniPcieSerdes; 988 struct ar5416IniArray iniPcieSerdesLowPower; 989 struct ar5416IniArray iniModesAdditional; 990 struct ar5416IniArray iniModesAdditional_40M; 991 struct ar5416IniArray iniModesRxGain; 992 struct ar5416IniArray iniModesTxGain; 993 struct ar5416IniArray iniModes_9271_1_0_only; 994 struct ar5416IniArray iniCckfirNormal; 995 struct ar5416IniArray iniCckfirJapan2484; 996 struct ar5416IniArray ini_japan2484; 997 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; 998 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; 999 struct ar5416IniArray iniModes_9271_ANI_reg; 1000 struct ar5416IniArray iniModes_high_power_tx_gain_9271; 1001 struct ar5416IniArray iniModes_normal_power_tx_gain_9271; 1002 struct ar5416IniArray ini_radio_post_sys2ant; 1003 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR; 1004 1005 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 1006 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 1007 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 1008 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 1009 1010 u32 intr_gen_timer_trigger; 1011 u32 intr_gen_timer_thresh; 1012 struct ath_gen_timer_table hw_gen_timers; 1013 1014 struct ar9003_txs *ts_ring; 1015 void *ts_start; 1016 u32 ts_paddr_start; 1017 u32 ts_paddr_end; 1018 u16 ts_tail; 1019 u16 ts_size; 1020 1021 u32 bb_watchdog_last_status; 1022 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 1023 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 1024 1025 unsigned int paprd_target_power; 1026 unsigned int paprd_training_power; 1027 unsigned int paprd_ratemask; 1028 unsigned int paprd_ratemask_ht40; 1029 bool paprd_table_write_done; 1030 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 1031 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 1032 /* 1033 * Store the permanent value of Reg 0x4004in WARegVal 1034 * so we dont have to R/M/W. We should not be reading 1035 * this register when in sleep states. 1036 */ 1037 u32 WARegVal; 1038 1039 /* Enterprise mode cap */ 1040 u32 ent_mode; 1041 1042 bool is_clk_25mhz; 1043 int (*get_mac_revision)(void); 1044 int (*external_reset)(void); 1045 }; 1046 1047 struct ath_bus_ops { 1048 enum ath_bus_type ath_bus_type; 1049 void (*read_cachesize)(struct ath_common *common, int *csz); 1050 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 1051 void (*bt_coex_prep)(struct ath_common *common); 1052 void (*extn_synch_en)(struct ath_common *common); 1053 void (*aspm_init)(struct ath_common *common); 1054 }; 1055 1056 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 1057 { 1058 return &ah->common; 1059 } 1060 1061 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 1062 { 1063 return &(ath9k_hw_common(ah)->regulatory); 1064 } 1065 1066 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 1067 { 1068 return &ah->private_ops; 1069 } 1070 1071 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 1072 { 1073 return &ah->ops; 1074 } 1075 1076 static inline u8 get_streams(int mask) 1077 { 1078 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 1079 } 1080 1081 /* Initialization, Detach, Reset */ 1082 const char *ath9k_hw_probe(u16 vendorid, u16 devid); 1083 void ath9k_hw_deinit(struct ath_hw *ah); 1084 int ath9k_hw_init(struct ath_hw *ah); 1085 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1086 struct ath9k_hw_cal_data *caldata, bool bChannelChange); 1087 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 1088 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 1089 1090 /* GPIO / RFKILL / Antennae */ 1091 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 1092 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 1093 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 1094 u32 ah_signal_type); 1095 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 1096 u32 ath9k_hw_getdefantenna(struct ath_hw *ah); 1097 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 1098 1099 /* General Operation */ 1100 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 1101 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 1102 int column, unsigned int *writecnt); 1103 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 1104 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 1105 u8 phy, int kbps, 1106 u32 frameLen, u16 rateix, bool shortPreamble); 1107 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 1108 struct ath9k_channel *chan, 1109 struct chan_centers *centers); 1110 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 1111 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 1112 bool ath9k_hw_phy_disable(struct ath_hw *ah); 1113 bool ath9k_hw_disable(struct ath_hw *ah); 1114 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 1115 void ath9k_hw_setopmode(struct ath_hw *ah); 1116 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 1117 void ath9k_hw_write_associd(struct ath_hw *ah); 1118 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 1119 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 1120 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1121 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1122 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 1123 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1124 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1125 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 1126 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1127 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1128 const struct ath9k_beacon_state *bs); 1129 bool ath9k_hw_check_alive(struct ath_hw *ah); 1130 1131 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1132 1133 /* Generic hw timer primitives */ 1134 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1135 void (*trigger)(void *), 1136 void (*overflow)(void *), 1137 void *arg, 1138 u8 timer_index); 1139 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1140 struct ath_gen_timer *timer, 1141 u32 timer_next, 1142 u32 timer_period); 1143 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1144 1145 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1146 void ath_gen_timer_isr(struct ath_hw *hw); 1147 1148 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1149 1150 /* HTC */ 1151 void ath9k_hw_htc_resetinit(struct ath_hw *ah); 1152 1153 /* PHY */ 1154 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1155 u32 *coef_mantissa, u32 *coef_exponent); 1156 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan); 1157 1158 /* 1159 * Code Specific to AR5008, AR9001 or AR9002, 1160 * we stuff these here to avoid callbacks for AR9003. 1161 */ 1162 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); 1163 int ar9002_hw_rf_claim(struct ath_hw *ah); 1164 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1165 1166 /* 1167 * Code specific to AR9003, we stuff these here to avoid callbacks 1168 * for older families 1169 */ 1170 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1171 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1172 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1173 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1174 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1175 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1176 struct ath9k_hw_cal_data *caldata, 1177 int chain); 1178 int ar9003_paprd_create_curve(struct ath_hw *ah, 1179 struct ath9k_hw_cal_data *caldata, int chain); 1180 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1181 int ar9003_paprd_init_table(struct ath_hw *ah); 1182 bool ar9003_paprd_is_done(struct ath_hw *ah); 1183 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); 1184 1185 /* Hardware family op attach helpers */ 1186 void ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1187 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1188 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1189 1190 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1191 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1192 1193 void ar9002_hw_attach_ops(struct ath_hw *ah); 1194 void ar9003_hw_attach_ops(struct ath_hw *ah); 1195 1196 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1197 /* 1198 * ANI work can be shared between all families but a next 1199 * generation implementation of ANI will be used only for AR9003 only 1200 * for now as the other families still need to be tested with the same 1201 * next generation ANI. Feel free to start testing it though for the 1202 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. 1203 */ 1204 extern int modparam_force_new_ani; 1205 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1206 void ath9k_hw_proc_mib_event(struct ath_hw *ah); 1207 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1208 1209 bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag, 1210 u32 *payload, u8 len, bool wait_done, 1211 bool check_bt); 1212 void ar9003_mci_mute_bt(struct ath_hw *ah); 1213 u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data); 1214 void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf, 1215 u16 len, u32 sched_addr); 1216 void ar9003_mci_cleanup(struct ath_hw *ah); 1217 void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt, 1218 bool wait_done); 1219 u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type, 1220 u8 gpm_opcode, int time_out); 1221 void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g); 1222 void ar9003_mci_disable_interrupt(struct ath_hw *ah); 1223 void ar9003_mci_enable_interrupt(struct ath_hw *ah); 1224 void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done); 1225 void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, 1226 bool is_full_sleep); 1227 bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints); 1228 void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done); 1229 void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done); 1230 void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done); 1231 void ar9003_mci_sync_bt_state(struct ath_hw *ah); 1232 void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr, 1233 u32 *rx_msg_intr); 1234 1235 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1236 static inline enum ath_btcoex_scheme 1237 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1238 { 1239 return ah->btcoex_hw.scheme; 1240 } 1241 #else 1242 #define ath9k_hw_get_btcoex_scheme(...) ATH_BTCOEX_CFG_NONE 1243 #endif 1244 1245 #define ATH9K_CLOCK_RATE_CCK 22 1246 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1247 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1248 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1249 1250 #endif 1251