1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 #include <linux/firmware.h> 24 25 #include "mac.h" 26 #include "ani.h" 27 #include "eeprom.h" 28 #include "calib.h" 29 #include "reg.h" 30 #include "phy.h" 31 #include "btcoex.h" 32 33 #include "../regd.h" 34 35 #define ATHEROS_VENDOR_ID 0x168c 36 37 #define AR5416_DEVID_PCI 0x0023 38 #define AR5416_DEVID_PCIE 0x0024 39 #define AR9160_DEVID_PCI 0x0027 40 #define AR9280_DEVID_PCI 0x0029 41 #define AR9280_DEVID_PCIE 0x002a 42 #define AR9285_DEVID_PCIE 0x002b 43 #define AR2427_DEVID_PCIE 0x002c 44 #define AR9287_DEVID_PCI 0x002d 45 #define AR9287_DEVID_PCIE 0x002e 46 #define AR9300_DEVID_PCIE 0x0030 47 #define AR9300_DEVID_AR9340 0x0031 48 #define AR9300_DEVID_AR9485_PCIE 0x0032 49 #define AR9300_DEVID_AR9580 0x0033 50 #define AR9300_DEVID_AR9462 0x0034 51 #define AR9300_DEVID_AR9330 0x0035 52 #define AR9300_DEVID_QCA955X 0x0038 53 #define AR9485_DEVID_AR1111 0x0037 54 #define AR9300_DEVID_AR9565 0x0036 55 56 #define AR5416_AR9100_DEVID 0x000b 57 58 #define AR_SUBVENDOR_ID_NOG 0x0e11 59 #define AR_SUBVENDOR_ID_NEW_A 0x7065 60 #define AR5416_MAGIC 0x19641014 61 62 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 63 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 64 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 65 66 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 67 68 #define ATH_DEFAULT_NOISE_FLOOR -95 69 70 #define ATH9K_RSSI_BAD -128 71 72 #define ATH9K_NUM_CHANNELS 38 73 74 /* Register read/write primitives */ 75 #define REG_WRITE(_ah, _reg, _val) \ 76 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 77 78 #define REG_READ(_ah, _reg) \ 79 (_ah)->reg_ops.read((_ah), (_reg)) 80 81 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 82 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 83 84 #define REG_RMW(_ah, _reg, _set, _clr) \ 85 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 86 87 #define ENABLE_REGWRITE_BUFFER(_ah) \ 88 do { \ 89 if ((_ah)->reg_ops.enable_write_buffer) \ 90 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 91 } while (0) 92 93 #define REGWRITE_BUFFER_FLUSH(_ah) \ 94 do { \ 95 if ((_ah)->reg_ops.write_flush) \ 96 (_ah)->reg_ops.write_flush((_ah)); \ 97 } while (0) 98 99 #define PR_EEP(_s, _val) \ 100 do { \ 101 len += snprintf(buf + len, size - len, "%20s : %10d\n", \ 102 _s, (_val)); \ 103 } while (0) 104 105 #define SM(_v, _f) (((_v) << _f##_S) & _f) 106 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 107 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 108 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 109 #define REG_READ_FIELD(_a, _r, _f) \ 110 (((REG_READ(_a, _r) & _f) >> _f##_S)) 111 #define REG_SET_BIT(_a, _r, _f) \ 112 REG_RMW(_a, _r, (_f), 0) 113 #define REG_CLR_BIT(_a, _r, _f) \ 114 REG_RMW(_a, _r, 0, (_f)) 115 116 #define DO_DELAY(x) do { \ 117 if (((++(x) % 64) == 0) && \ 118 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 119 != ATH_USB)) \ 120 udelay(1); \ 121 } while (0) 122 123 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 124 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 125 126 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 128 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 129 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 130 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 132 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 137 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 138 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 139 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 140 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 141 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 142 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 143 144 #define AR_GPIOD_MASK 0x00001FFF 145 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 146 147 #define BASE_ACTIVATE_DELAY 100 148 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 149 #define COEF_SCALE_S 24 150 #define HT40_CHANNEL_CENTER_SHIFT 10 151 152 #define ATH9K_ANTENNA0_CHAINMASK 0x1 153 #define ATH9K_ANTENNA1_CHAINMASK 0x2 154 155 #define ATH9K_NUM_DMA_DEBUG_REGS 8 156 #define ATH9K_NUM_QUEUES 10 157 158 #define MAX_RATE_POWER 63 159 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 160 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 161 #define AH_TIME_QUANTUM 10 162 #define AR_KEYTABLE_SIZE 128 163 #define POWER_UP_TIME 10000 164 #define SPUR_RSSI_THRESH 40 165 #define UPPER_5G_SUB_BAND_START 5700 166 #define MID_5G_SUB_BAND_START 5400 167 168 #define CAB_TIMEOUT_VAL 10 169 #define BEACON_TIMEOUT_VAL 10 170 #define MIN_BEACON_TIMEOUT_VAL 1 171 #define SLEEP_SLOP 3 172 173 #define INIT_CONFIG_STATUS 0x00000000 174 #define INIT_RSSI_THR 0x00000700 175 #define INIT_BCON_CNTRL_REG 0x00000000 176 177 #define TU_TO_USEC(_tu) ((_tu) << 10) 178 179 #define ATH9K_HW_RX_HP_QDEPTH 16 180 #define ATH9K_HW_RX_LP_QDEPTH 128 181 182 #define PAPRD_GAIN_TABLE_ENTRIES 32 183 #define PAPRD_TABLE_SZ 24 184 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 185 186 /* 187 * Wake on Wireless 188 */ 189 190 /* Keep Alive Frame */ 191 #define KAL_FRAME_LEN 28 192 #define KAL_FRAME_TYPE 0x2 /* data frame */ 193 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ 194 #define KAL_DURATION_ID 0x3d 195 #define KAL_NUM_DATA_WORDS 6 196 #define KAL_NUM_DESC_WORDS 12 197 #define KAL_ANTENNA_MODE 1 198 #define KAL_TO_DS 1 199 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ 200 #define KAL_TIMEOUT 900 201 202 #define MAX_PATTERN_SIZE 256 203 #define MAX_PATTERN_MASK_SIZE 32 204 #define MAX_NUM_PATTERN 8 205 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and 206 deauthenticate packets */ 207 208 /* 209 * WoW trigger mapping to hardware code 210 */ 211 212 #define AH_WOW_USER_PATTERN_EN BIT(0) 213 #define AH_WOW_MAGIC_PATTERN_EN BIT(1) 214 #define AH_WOW_LINK_CHANGE BIT(2) 215 #define AH_WOW_BEACON_MISS BIT(3) 216 217 enum ath_hw_txq_subtype { 218 ATH_TXQ_AC_BE = 0, 219 ATH_TXQ_AC_BK = 1, 220 ATH_TXQ_AC_VI = 2, 221 ATH_TXQ_AC_VO = 3, 222 }; 223 224 enum ath_ini_subsys { 225 ATH_INI_PRE = 0, 226 ATH_INI_CORE, 227 ATH_INI_POST, 228 ATH_INI_NUM_SPLIT, 229 }; 230 231 enum ath9k_hw_caps { 232 ATH9K_HW_CAP_HT = BIT(0), 233 ATH9K_HW_CAP_RFSILENT = BIT(1), 234 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 235 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 236 ATH9K_HW_CAP_EDMA = BIT(4), 237 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 238 ATH9K_HW_CAP_LDPC = BIT(6), 239 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 240 ATH9K_HW_CAP_SGI_20 = BIT(8), 241 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 242 ATH9K_HW_CAP_2GHZ = BIT(11), 243 ATH9K_HW_CAP_5GHZ = BIT(12), 244 ATH9K_HW_CAP_APM = BIT(13), 245 ATH9K_HW_CAP_RTT = BIT(14), 246 ATH9K_HW_CAP_MCI = BIT(15), 247 ATH9K_HW_CAP_DFS = BIT(16), 248 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17), 249 ATH9K_HW_WOW_PATTERN_MATCH_EXACT = BIT(18), 250 ATH9K_HW_WOW_PATTERN_MATCH_DWORD = BIT(19), 251 ATH9K_HW_CAP_PAPRD = BIT(20), 252 }; 253 254 /* 255 * WoW device capabilities 256 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. 257 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching 258 * an exact user defined pattern or de-authentication/disassoc pattern. 259 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four 260 * bytes of the pattern for user defined pattern, de-authentication and 261 * disassociation patterns for all types of possible frames recieved 262 * of those types. 263 */ 264 265 struct ath9k_hw_capabilities { 266 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 267 u16 rts_aggr_limit; 268 u8 tx_chainmask; 269 u8 rx_chainmask; 270 u8 max_txchains; 271 u8 max_rxchains; 272 u8 num_gpio_pins; 273 u8 rx_hp_qdepth; 274 u8 rx_lp_qdepth; 275 u8 rx_status_len; 276 u8 tx_desc_len; 277 u8 txs_len; 278 }; 279 280 struct ath9k_ops_config { 281 int dma_beacon_response_time; 282 int sw_beacon_response_time; 283 int additional_swba_backoff; 284 int ack_6mb; 285 u32 cwm_ignore_extcca; 286 bool pcieSerDesWrite; 287 u8 pcie_clock_req; 288 u32 pcie_waen; 289 u8 analog_shiftreg; 290 u32 ofdm_trig_low; 291 u32 ofdm_trig_high; 292 u32 cck_trig_high; 293 u32 cck_trig_low; 294 u32 enable_ani; 295 u32 enable_paprd; 296 int serialize_regmode; 297 bool rx_intr_mitigation; 298 bool tx_intr_mitigation; 299 #define SPUR_DISABLE 0 300 #define SPUR_ENABLE_IOCTL 1 301 #define SPUR_ENABLE_EEPROM 2 302 #define AR_SPUR_5413_1 1640 303 #define AR_SPUR_5413_2 1200 304 #define AR_NO_SPUR 0x8000 305 #define AR_BASE_FREQ_2GHZ 2300 306 #define AR_BASE_FREQ_5GHZ 4900 307 #define AR_SPUR_FEEQ_BOUND_HT40 19 308 #define AR_SPUR_FEEQ_BOUND_HT20 10 309 int spurmode; 310 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 311 u8 max_txtrig_level; 312 u16 ani_poll_interval; /* ANI poll interval in ms */ 313 }; 314 315 enum ath9k_int { 316 ATH9K_INT_RX = 0x00000001, 317 ATH9K_INT_RXDESC = 0x00000002, 318 ATH9K_INT_RXHP = 0x00000001, 319 ATH9K_INT_RXLP = 0x00000002, 320 ATH9K_INT_RXNOFRM = 0x00000008, 321 ATH9K_INT_RXEOL = 0x00000010, 322 ATH9K_INT_RXORN = 0x00000020, 323 ATH9K_INT_TX = 0x00000040, 324 ATH9K_INT_TXDESC = 0x00000080, 325 ATH9K_INT_TIM_TIMER = 0x00000100, 326 ATH9K_INT_MCI = 0x00000200, 327 ATH9K_INT_BB_WATCHDOG = 0x00000400, 328 ATH9K_INT_TXURN = 0x00000800, 329 ATH9K_INT_MIB = 0x00001000, 330 ATH9K_INT_RXPHY = 0x00004000, 331 ATH9K_INT_RXKCM = 0x00008000, 332 ATH9K_INT_SWBA = 0x00010000, 333 ATH9K_INT_BMISS = 0x00040000, 334 ATH9K_INT_BNR = 0x00100000, 335 ATH9K_INT_TIM = 0x00200000, 336 ATH9K_INT_DTIM = 0x00400000, 337 ATH9K_INT_DTIMSYNC = 0x00800000, 338 ATH9K_INT_GPIO = 0x01000000, 339 ATH9K_INT_CABEND = 0x02000000, 340 ATH9K_INT_TSFOOR = 0x04000000, 341 ATH9K_INT_GENTIMER = 0x08000000, 342 ATH9K_INT_CST = 0x10000000, 343 ATH9K_INT_GTT = 0x20000000, 344 ATH9K_INT_FATAL = 0x40000000, 345 ATH9K_INT_GLOBAL = 0x80000000, 346 ATH9K_INT_BMISC = ATH9K_INT_TIM | 347 ATH9K_INT_DTIM | 348 ATH9K_INT_DTIMSYNC | 349 ATH9K_INT_TSFOOR | 350 ATH9K_INT_CABEND, 351 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 352 ATH9K_INT_RXDESC | 353 ATH9K_INT_RXEOL | 354 ATH9K_INT_RXORN | 355 ATH9K_INT_TXURN | 356 ATH9K_INT_TXDESC | 357 ATH9K_INT_MIB | 358 ATH9K_INT_RXPHY | 359 ATH9K_INT_RXKCM | 360 ATH9K_INT_SWBA | 361 ATH9K_INT_BMISS | 362 ATH9K_INT_GPIO, 363 ATH9K_INT_NOCARD = 0xffffffff 364 }; 365 366 #define CHANNEL_CW_INT 0x00002 367 #define CHANNEL_CCK 0x00020 368 #define CHANNEL_OFDM 0x00040 369 #define CHANNEL_2GHZ 0x00080 370 #define CHANNEL_5GHZ 0x00100 371 #define CHANNEL_PASSIVE 0x00200 372 #define CHANNEL_DYN 0x00400 373 #define CHANNEL_HALF 0x04000 374 #define CHANNEL_QUARTER 0x08000 375 #define CHANNEL_HT20 0x10000 376 #define CHANNEL_HT40PLUS 0x20000 377 #define CHANNEL_HT40MINUS 0x40000 378 379 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 380 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 381 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 382 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 383 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 384 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 385 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 386 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 387 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 388 #define CHANNEL_ALL \ 389 (CHANNEL_OFDM| \ 390 CHANNEL_CCK| \ 391 CHANNEL_2GHZ | \ 392 CHANNEL_5GHZ | \ 393 CHANNEL_HT20 | \ 394 CHANNEL_HT40PLUS | \ 395 CHANNEL_HT40MINUS) 396 397 #define MAX_RTT_TABLE_ENTRY 6 398 #define MAX_IQCAL_MEASUREMENT 8 399 #define MAX_CL_TAB_ENTRY 16 400 401 struct ath9k_hw_cal_data { 402 u16 channel; 403 u32 channelFlags; 404 u32 chanmode; 405 int32_t CalValid; 406 int8_t iCoff; 407 int8_t qCoff; 408 bool rtt_done; 409 bool paprd_packet_sent; 410 bool paprd_done; 411 bool nfcal_pending; 412 bool nfcal_interference; 413 bool done_txiqcal_once; 414 bool done_txclcal_once; 415 u16 small_signal_gain[AR9300_MAX_CHAINS]; 416 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 417 u32 num_measures[AR9300_MAX_CHAINS]; 418 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 419 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 420 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 421 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 422 }; 423 424 struct ath9k_channel { 425 struct ieee80211_channel *chan; 426 struct ar5416AniState ani; 427 u16 channel; 428 u32 channelFlags; 429 u32 chanmode; 430 s16 noisefloor; 431 }; 432 433 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 434 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 435 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 436 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 437 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 438 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 439 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 440 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 441 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 442 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 443 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 444 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 445 446 /* These macros check chanmode and not channelFlags */ 447 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 448 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 449 ((_c)->chanmode == CHANNEL_G_HT20)) 450 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 451 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 452 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 453 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 454 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 455 456 enum ath9k_power_mode { 457 ATH9K_PM_AWAKE = 0, 458 ATH9K_PM_FULL_SLEEP, 459 ATH9K_PM_NETWORK_SLEEP, 460 ATH9K_PM_UNDEFINED 461 }; 462 463 enum ser_reg_mode { 464 SER_REG_MODE_OFF = 0, 465 SER_REG_MODE_ON = 1, 466 SER_REG_MODE_AUTO = 2, 467 }; 468 469 enum ath9k_rx_qtype { 470 ATH9K_RX_QUEUE_HP, 471 ATH9K_RX_QUEUE_LP, 472 ATH9K_RX_QUEUE_MAX, 473 }; 474 475 struct ath9k_beacon_state { 476 u32 bs_nexttbtt; 477 u32 bs_nextdtim; 478 u32 bs_intval; 479 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 480 u32 bs_dtimperiod; 481 u16 bs_cfpperiod; 482 u16 bs_cfpmaxduration; 483 u32 bs_cfpnext; 484 u16 bs_timoffset; 485 u16 bs_bmissthreshold; 486 u32 bs_sleepduration; 487 u32 bs_tsfoor_threshold; 488 }; 489 490 struct chan_centers { 491 u16 synth_center; 492 u16 ctl_center; 493 u16 ext_center; 494 }; 495 496 enum { 497 ATH9K_RESET_POWER_ON, 498 ATH9K_RESET_WARM, 499 ATH9K_RESET_COLD, 500 }; 501 502 struct ath9k_hw_version { 503 u32 magic; 504 u16 devid; 505 u16 subvendorid; 506 u32 macVersion; 507 u16 macRev; 508 u16 phyRev; 509 u16 analog5GhzRev; 510 u16 analog2GhzRev; 511 enum ath_usb_dev usbdev; 512 }; 513 514 /* Generic TSF timer definitions */ 515 516 #define ATH_MAX_GEN_TIMER 16 517 518 #define AR_GENTMR_BIT(_index) (1 << (_index)) 519 520 /* 521 * Using de Bruijin sequence to look up 1's index in a 32 bit number 522 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 523 */ 524 #define debruijn32 0x077CB531U 525 526 struct ath_gen_timer_configuration { 527 u32 next_addr; 528 u32 period_addr; 529 u32 mode_addr; 530 u32 mode_mask; 531 }; 532 533 struct ath_gen_timer { 534 void (*trigger)(void *arg); 535 void (*overflow)(void *arg); 536 void *arg; 537 u8 index; 538 }; 539 540 struct ath_gen_timer_table { 541 u32 gen_timer_index[32]; 542 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 543 union { 544 unsigned long timer_bits; 545 u16 val; 546 } timer_mask; 547 }; 548 549 struct ath_hw_antcomb_conf { 550 u8 main_lna_conf; 551 u8 alt_lna_conf; 552 u8 fast_div_bias; 553 u8 main_gaintb; 554 u8 alt_gaintb; 555 int lna1_lna2_delta; 556 u8 div_group; 557 }; 558 559 /** 560 * struct ath_hw_radar_conf - radar detection initialization parameters 561 * 562 * @pulse_inband: threshold for checking the ratio of in-band power 563 * to total power for short radar pulses (half dB steps) 564 * @pulse_inband_step: threshold for checking an in-band power to total 565 * power ratio increase for short radar pulses (half dB steps) 566 * @pulse_height: threshold for detecting the beginning of a short 567 * radar pulse (dB step) 568 * @pulse_rssi: threshold for detecting if a short radar pulse is 569 * gone (dB step) 570 * @pulse_maxlen: maximum pulse length (0.8 us steps) 571 * 572 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 573 * @radar_inband: threshold for checking the ratio of in-band power 574 * to total power for long radar pulses (half dB steps) 575 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 576 * 577 * @ext_channel: enable extension channel radar detection 578 */ 579 struct ath_hw_radar_conf { 580 unsigned int pulse_inband; 581 unsigned int pulse_inband_step; 582 unsigned int pulse_height; 583 unsigned int pulse_rssi; 584 unsigned int pulse_maxlen; 585 586 unsigned int radar_rssi; 587 unsigned int radar_inband; 588 int fir_power; 589 590 bool ext_channel; 591 }; 592 593 /** 594 * struct ath_hw_private_ops - callbacks used internally by hardware code 595 * 596 * This structure contains private callbacks designed to only be used internally 597 * by the hardware core. 598 * 599 * @init_cal_settings: setup types of calibrations supported 600 * @init_cal: starts actual calibration 601 * 602 * @init_mode_regs: Initializes mode registers 603 * @init_mode_gain_regs: Initialize TX/RX gain registers 604 * 605 * @rf_set_freq: change frequency 606 * @spur_mitigate_freq: spur mitigation 607 * @rf_alloc_ext_banks: 608 * @rf_free_ext_banks: 609 * @set_rf_regs: 610 * @compute_pll_control: compute the PLL control value to use for 611 * AR_RTC_PLL_CONTROL for a given channel 612 * @setup_calibration: set up calibration 613 * @iscal_supported: used to query if a type of calibration is supported 614 * 615 * @ani_cache_ini_regs: cache the values for ANI from the initial 616 * register settings through the register initialization. 617 */ 618 struct ath_hw_private_ops { 619 /* Calibration ops */ 620 void (*init_cal_settings)(struct ath_hw *ah); 621 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 622 623 void (*init_mode_regs)(struct ath_hw *ah); 624 void (*init_mode_gain_regs)(struct ath_hw *ah); 625 void (*setup_calibration)(struct ath_hw *ah, 626 struct ath9k_cal_list *currCal); 627 628 /* PHY ops */ 629 int (*rf_set_freq)(struct ath_hw *ah, 630 struct ath9k_channel *chan); 631 void (*spur_mitigate_freq)(struct ath_hw *ah, 632 struct ath9k_channel *chan); 633 int (*rf_alloc_ext_banks)(struct ath_hw *ah); 634 void (*rf_free_ext_banks)(struct ath_hw *ah); 635 bool (*set_rf_regs)(struct ath_hw *ah, 636 struct ath9k_channel *chan, 637 u16 modesIndex); 638 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 639 void (*init_bb)(struct ath_hw *ah, 640 struct ath9k_channel *chan); 641 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 642 void (*olc_init)(struct ath_hw *ah); 643 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 644 void (*mark_phy_inactive)(struct ath_hw *ah); 645 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 646 bool (*rfbus_req)(struct ath_hw *ah); 647 void (*rfbus_done)(struct ath_hw *ah); 648 void (*restore_chainmask)(struct ath_hw *ah); 649 u32 (*compute_pll_control)(struct ath_hw *ah, 650 struct ath9k_channel *chan); 651 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 652 int param); 653 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 654 void (*set_radar_params)(struct ath_hw *ah, 655 struct ath_hw_radar_conf *conf); 656 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 657 u8 *ini_reloaded); 658 659 /* ANI */ 660 void (*ani_cache_ini_regs)(struct ath_hw *ah); 661 }; 662 663 /** 664 * struct ath_hw_ops - callbacks used by hardware code and driver code 665 * 666 * This structure contains callbacks designed to to be used internally by 667 * hardware code and also by the lower level driver. 668 * 669 * @config_pci_powersave: 670 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 671 */ 672 struct ath_hw_ops { 673 void (*config_pci_powersave)(struct ath_hw *ah, 674 bool power_off); 675 void (*rx_enable)(struct ath_hw *ah); 676 void (*set_desc_link)(void *ds, u32 link); 677 bool (*calibrate)(struct ath_hw *ah, 678 struct ath9k_channel *chan, 679 u8 rxchainmask, 680 bool longcal); 681 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 682 void (*set_txdesc)(struct ath_hw *ah, void *ds, 683 struct ath_tx_info *i); 684 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 685 struct ath_tx_status *ts); 686 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 687 struct ath_hw_antcomb_conf *antconf); 688 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 689 struct ath_hw_antcomb_conf *antconf); 690 void (*antctrl_shared_chain_lnadiv)(struct ath_hw *hw, bool enable); 691 }; 692 693 struct ath_nf_limits { 694 s16 max; 695 s16 min; 696 s16 nominal; 697 }; 698 699 enum ath_cal_list { 700 TX_IQ_CAL = BIT(0), 701 TX_IQ_ON_AGC_CAL = BIT(1), 702 TX_CL_CAL = BIT(2), 703 }; 704 705 /* ah_flags */ 706 #define AH_USE_EEPROM 0x1 707 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 708 #define AH_FASTCC 0x4 709 710 struct ath_hw { 711 struct ath_ops reg_ops; 712 713 struct ieee80211_hw *hw; 714 struct ath_common common; 715 struct ath9k_hw_version hw_version; 716 struct ath9k_ops_config config; 717 struct ath9k_hw_capabilities caps; 718 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 719 struct ath9k_channel *curchan; 720 721 union { 722 struct ar5416_eeprom_def def; 723 struct ar5416_eeprom_4k map4k; 724 struct ar9287_eeprom map9287; 725 struct ar9300_eeprom ar9300_eep; 726 } eeprom; 727 const struct eeprom_ops *eep_ops; 728 729 bool sw_mgmt_crypto; 730 bool is_pciexpress; 731 bool aspm_enabled; 732 bool is_monitoring; 733 bool need_an_top2_fixup; 734 bool shared_chain_lnadiv; 735 u16 tx_trig_level; 736 737 u32 nf_regs[6]; 738 struct ath_nf_limits nf_2g; 739 struct ath_nf_limits nf_5g; 740 u16 rfsilent; 741 u32 rfkill_gpio; 742 u32 rfkill_polarity; 743 u32 ah_flags; 744 745 bool reset_power_on; 746 bool htc_reset_init; 747 748 enum nl80211_iftype opmode; 749 enum ath9k_power_mode power_mode; 750 751 s8 noise; 752 struct ath9k_hw_cal_data *caldata; 753 struct ath9k_pacal_info pacal_info; 754 struct ar5416Stats stats; 755 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 756 757 enum ath9k_int imask; 758 u32 imrs2_reg; 759 u32 txok_interrupt_mask; 760 u32 txerr_interrupt_mask; 761 u32 txdesc_interrupt_mask; 762 u32 txeol_interrupt_mask; 763 u32 txurn_interrupt_mask; 764 atomic_t intr_ref_cnt; 765 bool chip_fullsleep; 766 u32 atim_window; 767 u32 modes_index; 768 769 /* Calibration */ 770 u32 supp_cals; 771 struct ath9k_cal_list iq_caldata; 772 struct ath9k_cal_list adcgain_caldata; 773 struct ath9k_cal_list adcdc_caldata; 774 struct ath9k_cal_list tempCompCalData; 775 struct ath9k_cal_list *cal_list; 776 struct ath9k_cal_list *cal_list_last; 777 struct ath9k_cal_list *cal_list_curr; 778 #define totalPowerMeasI meas0.unsign 779 #define totalPowerMeasQ meas1.unsign 780 #define totalIqCorrMeas meas2.sign 781 #define totalAdcIOddPhase meas0.unsign 782 #define totalAdcIEvenPhase meas1.unsign 783 #define totalAdcQOddPhase meas2.unsign 784 #define totalAdcQEvenPhase meas3.unsign 785 #define totalAdcDcOffsetIOddPhase meas0.sign 786 #define totalAdcDcOffsetIEvenPhase meas1.sign 787 #define totalAdcDcOffsetQOddPhase meas2.sign 788 #define totalAdcDcOffsetQEvenPhase meas3.sign 789 union { 790 u32 unsign[AR5416_MAX_CHAINS]; 791 int32_t sign[AR5416_MAX_CHAINS]; 792 } meas0; 793 union { 794 u32 unsign[AR5416_MAX_CHAINS]; 795 int32_t sign[AR5416_MAX_CHAINS]; 796 } meas1; 797 union { 798 u32 unsign[AR5416_MAX_CHAINS]; 799 int32_t sign[AR5416_MAX_CHAINS]; 800 } meas2; 801 union { 802 u32 unsign[AR5416_MAX_CHAINS]; 803 int32_t sign[AR5416_MAX_CHAINS]; 804 } meas3; 805 u16 cal_samples; 806 u8 enabled_cals; 807 808 u32 sta_id1_defaults; 809 u32 misc_mode; 810 811 /* Private to hardware code */ 812 struct ath_hw_private_ops private_ops; 813 /* Accessed by the lower level driver */ 814 struct ath_hw_ops ops; 815 816 /* Used to program the radio on non single-chip devices */ 817 u32 *analogBank0Data; 818 u32 *analogBank1Data; 819 u32 *analogBank2Data; 820 u32 *analogBank3Data; 821 u32 *analogBank6Data; 822 u32 *analogBank6TPCData; 823 u32 *analogBank7Data; 824 u32 *bank6Temp; 825 826 int coverage_class; 827 u32 slottime; 828 u32 globaltxtimeout; 829 830 /* ANI */ 831 u32 proc_phyerr; 832 u32 aniperiod; 833 int totalSizeDesired[5]; 834 int coarse_high[5]; 835 int coarse_low[5]; 836 int firpwr[5]; 837 enum ath9k_ani_cmd ani_function; 838 u32 ani_skip_count; 839 840 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 841 struct ath_btcoex_hw btcoex_hw; 842 #endif 843 844 u32 intr_txqs; 845 u8 txchainmask; 846 u8 rxchainmask; 847 848 struct ath_hw_radar_conf radar_conf; 849 850 u32 originalGain[22]; 851 int initPDADC; 852 int PDADCdelta; 853 int led_pin; 854 u32 gpio_mask; 855 u32 gpio_val; 856 857 struct ar5416IniArray iniModes; 858 struct ar5416IniArray iniCommon; 859 struct ar5416IniArray iniBank0; 860 struct ar5416IniArray iniBB_RfGain; 861 struct ar5416IniArray iniBank1; 862 struct ar5416IniArray iniBank2; 863 struct ar5416IniArray iniBank3; 864 struct ar5416IniArray iniBank6; 865 struct ar5416IniArray iniBank6TPC; 866 struct ar5416IniArray iniBank7; 867 struct ar5416IniArray iniAddac; 868 struct ar5416IniArray iniPcieSerdes; 869 #ifdef CONFIG_PM_SLEEP 870 struct ar5416IniArray iniPcieSerdesWow; 871 #endif 872 struct ar5416IniArray iniPcieSerdesLowPower; 873 struct ar5416IniArray iniModesFastClock; 874 struct ar5416IniArray iniAdditional; 875 struct ar5416IniArray iniModesRxGain; 876 struct ar5416IniArray ini_modes_rx_gain_bounds; 877 struct ar5416IniArray iniModesTxGain; 878 struct ar5416IniArray iniCckfirNormal; 879 struct ar5416IniArray iniCckfirJapan2484; 880 struct ar5416IniArray iniModes_9271_ANI_reg; 881 struct ar5416IniArray ini_radio_post_sys2ant; 882 883 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 884 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 885 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 886 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 887 888 u32 intr_gen_timer_trigger; 889 u32 intr_gen_timer_thresh; 890 struct ath_gen_timer_table hw_gen_timers; 891 892 struct ar9003_txs *ts_ring; 893 u32 ts_paddr_start; 894 u32 ts_paddr_end; 895 u16 ts_tail; 896 u16 ts_size; 897 898 u32 bb_watchdog_last_status; 899 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 900 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 901 902 unsigned int paprd_target_power; 903 unsigned int paprd_training_power; 904 unsigned int paprd_ratemask; 905 unsigned int paprd_ratemask_ht40; 906 bool paprd_table_write_done; 907 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 908 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 909 /* 910 * Store the permanent value of Reg 0x4004in WARegVal 911 * so we dont have to R/M/W. We should not be reading 912 * this register when in sleep states. 913 */ 914 u32 WARegVal; 915 916 /* Enterprise mode cap */ 917 u32 ent_mode; 918 919 #ifdef CONFIG_PM_SLEEP 920 u32 wow_event_mask; 921 #endif 922 bool is_clk_25mhz; 923 int (*get_mac_revision)(void); 924 int (*external_reset)(void); 925 926 const struct firmware *eeprom_blob; 927 }; 928 929 struct ath_bus_ops { 930 enum ath_bus_type ath_bus_type; 931 void (*read_cachesize)(struct ath_common *common, int *csz); 932 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 933 void (*bt_coex_prep)(struct ath_common *common); 934 void (*aspm_init)(struct ath_common *common); 935 }; 936 937 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 938 { 939 return &ah->common; 940 } 941 942 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 943 { 944 return &(ath9k_hw_common(ah)->regulatory); 945 } 946 947 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 948 { 949 return &ah->private_ops; 950 } 951 952 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 953 { 954 return &ah->ops; 955 } 956 957 static inline u8 get_streams(int mask) 958 { 959 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 960 } 961 962 /* Initialization, Detach, Reset */ 963 void ath9k_hw_deinit(struct ath_hw *ah); 964 int ath9k_hw_init(struct ath_hw *ah); 965 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 966 struct ath9k_hw_cal_data *caldata, bool fastcc); 967 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 968 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 969 970 /* GPIO / RFKILL / Antennae */ 971 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 972 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 973 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 974 u32 ah_signal_type); 975 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 976 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 977 978 /* General Operation */ 979 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 980 int hw_delay); 981 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 982 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 983 int column, unsigned int *writecnt); 984 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 985 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 986 u8 phy, int kbps, 987 u32 frameLen, u16 rateix, bool shortPreamble); 988 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 989 struct ath9k_channel *chan, 990 struct chan_centers *centers); 991 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 992 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 993 bool ath9k_hw_phy_disable(struct ath_hw *ah); 994 bool ath9k_hw_disable(struct ath_hw *ah); 995 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 996 void ath9k_hw_setopmode(struct ath_hw *ah); 997 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 998 void ath9k_hw_write_associd(struct ath_hw *ah); 999 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 1000 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 1001 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1002 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1003 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); 1004 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1005 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1006 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 1007 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1008 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1009 const struct ath9k_beacon_state *bs); 1010 bool ath9k_hw_check_alive(struct ath_hw *ah); 1011 1012 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1013 1014 #ifdef CONFIG_ATH9K_DEBUGFS 1015 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause); 1016 #else 1017 static inline void ath9k_debug_sync_cause(struct ath_common *common, 1018 u32 sync_cause) {} 1019 #endif 1020 1021 /* Generic hw timer primitives */ 1022 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1023 void (*trigger)(void *), 1024 void (*overflow)(void *), 1025 void *arg, 1026 u8 timer_index); 1027 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1028 struct ath_gen_timer *timer, 1029 u32 timer_next, 1030 u32 timer_period); 1031 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1032 1033 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1034 void ath_gen_timer_isr(struct ath_hw *hw); 1035 1036 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1037 1038 /* PHY */ 1039 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1040 u32 *coef_mantissa, u32 *coef_exponent); 1041 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 1042 bool test); 1043 1044 /* 1045 * Code Specific to AR5008, AR9001 or AR9002, 1046 * we stuff these here to avoid callbacks for AR9003. 1047 */ 1048 int ar9002_hw_rf_claim(struct ath_hw *ah); 1049 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1050 1051 /* 1052 * Code specific to AR9003, we stuff these here to avoid callbacks 1053 * for older families 1054 */ 1055 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1056 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1057 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1058 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1059 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1060 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1061 struct ath9k_hw_cal_data *caldata, 1062 int chain); 1063 int ar9003_paprd_create_curve(struct ath_hw *ah, 1064 struct ath9k_hw_cal_data *caldata, int chain); 1065 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1066 int ar9003_paprd_init_table(struct ath_hw *ah); 1067 bool ar9003_paprd_is_done(struct ath_hw *ah); 1068 bool ar9003_is_paprd_enabled(struct ath_hw *ah); 1069 1070 /* Hardware family op attach helpers */ 1071 void ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1072 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1073 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1074 1075 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1076 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1077 1078 void ar9002_hw_attach_ops(struct ath_hw *ah); 1079 void ar9003_hw_attach_ops(struct ath_hw *ah); 1080 1081 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1082 1083 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1084 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1085 1086 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1087 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1088 { 1089 return ah->btcoex_hw.enabled; 1090 } 1091 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1092 { 1093 return ah->common.btcoex_enabled && 1094 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1095 1096 } 1097 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1098 static inline enum ath_btcoex_scheme 1099 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1100 { 1101 return ah->btcoex_hw.scheme; 1102 } 1103 #else 1104 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1105 { 1106 return false; 1107 } 1108 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1109 { 1110 return false; 1111 } 1112 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1113 { 1114 } 1115 static inline enum ath_btcoex_scheme 1116 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1117 { 1118 return ATH_BTCOEX_CFG_NONE; 1119 } 1120 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1121 1122 1123 #ifdef CONFIG_PM_SLEEP 1124 const char *ath9k_hw_wow_event_to_string(u32 wow_event); 1125 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, 1126 u8 *user_mask, int pattern_count, 1127 int pattern_len); 1128 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); 1129 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); 1130 #else 1131 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event) 1132 { 1133 return NULL; 1134 } 1135 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, 1136 u8 *user_pattern, 1137 u8 *user_mask, 1138 int pattern_count, 1139 int pattern_len) 1140 { 1141 } 1142 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) 1143 { 1144 return 0; 1145 } 1146 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) 1147 { 1148 } 1149 #endif 1150 1151 1152 1153 #define ATH9K_CLOCK_RATE_CCK 22 1154 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1155 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1156 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1157 1158 #endif 1159