1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 27 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 28 29 MODULE_AUTHOR("Atheros Communications"); 30 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 31 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 32 MODULE_LICENSE("Dual BSD/GPL"); 33 34 static int __init ath9k_init(void) 35 { 36 return 0; 37 } 38 module_init(ath9k_init); 39 40 static void __exit ath9k_exit(void) 41 { 42 return; 43 } 44 module_exit(ath9k_exit); 45 46 /* Private hardware callbacks */ 47 48 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 49 { 50 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 51 } 52 53 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 54 { 55 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 56 } 57 58 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 59 struct ath9k_channel *chan) 60 { 61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 62 } 63 64 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 65 { 66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 67 return; 68 69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 70 } 71 72 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 73 { 74 /* You will not have this callback if using the old ANI */ 75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 76 return; 77 78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 79 } 80 81 /********************/ 82 /* Helper Functions */ 83 /********************/ 84 85 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 86 { 87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 88 struct ath_common *common = ath9k_hw_common(ah); 89 unsigned int clockrate; 90 91 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 93 clockrate = 117; 94 else if (!ah->curchan) /* should really check for CCK instead */ 95 clockrate = ATH9K_CLOCK_RATE_CCK; 96 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 100 else 101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 102 103 if (conf_is_ht40(conf)) 104 clockrate *= 2; 105 106 if (ah->curchan) { 107 if (IS_CHAN_HALF_RATE(ah->curchan)) 108 clockrate /= 2; 109 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 110 clockrate /= 4; 111 } 112 113 common->clockrate = clockrate; 114 } 115 116 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 117 { 118 struct ath_common *common = ath9k_hw_common(ah); 119 120 return usecs * common->clockrate; 121 } 122 123 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 124 { 125 int i; 126 127 BUG_ON(timeout < AH_TIME_QUANTUM); 128 129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 130 if ((REG_READ(ah, reg) & mask) == val) 131 return true; 132 133 udelay(AH_TIME_QUANTUM); 134 } 135 136 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, 137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 138 timeout, reg, REG_READ(ah, reg), mask, val); 139 140 return false; 141 } 142 EXPORT_SYMBOL(ath9k_hw_wait); 143 144 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 145 int column, unsigned int *writecnt) 146 { 147 int r; 148 149 ENABLE_REGWRITE_BUFFER(ah); 150 for (r = 0; r < array->ia_rows; r++) { 151 REG_WRITE(ah, INI_RA(array, r, 0), 152 INI_RA(array, r, column)); 153 DO_DELAY(*writecnt); 154 } 155 REGWRITE_BUFFER_FLUSH(ah); 156 } 157 158 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 159 { 160 u32 retval; 161 int i; 162 163 for (i = 0, retval = 0; i < n; i++) { 164 retval = (retval << 1) | (val & 1); 165 val >>= 1; 166 } 167 return retval; 168 } 169 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 171 u8 phy, int kbps, 172 u32 frameLen, u16 rateix, 173 bool shortPreamble) 174 { 175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 176 177 if (kbps == 0) 178 return 0; 179 180 switch (phy) { 181 case WLAN_RC_PHY_CCK: 182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 183 if (shortPreamble) 184 phyTime >>= 1; 185 numBits = frameLen << 3; 186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 187 break; 188 case WLAN_RC_PHY_OFDM: 189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 191 numBits = OFDM_PLCP_BITS + (frameLen << 3); 192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 193 txTime = OFDM_SIFS_TIME_QUARTER 194 + OFDM_PREAMBLE_TIME_QUARTER 195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 196 } else if (ah->curchan && 197 IS_CHAN_HALF_RATE(ah->curchan)) { 198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 199 numBits = OFDM_PLCP_BITS + (frameLen << 3); 200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 201 txTime = OFDM_SIFS_TIME_HALF + 202 OFDM_PREAMBLE_TIME_HALF 203 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 204 } else { 205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 206 numBits = OFDM_PLCP_BITS + (frameLen << 3); 207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 209 + (numSymbols * OFDM_SYMBOL_TIME); 210 } 211 break; 212 default: 213 ath_err(ath9k_hw_common(ah), 214 "Unknown phy %u (rate ix %u)\n", phy, rateix); 215 txTime = 0; 216 break; 217 } 218 219 return txTime; 220 } 221 EXPORT_SYMBOL(ath9k_hw_computetxtime); 222 223 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 224 struct ath9k_channel *chan, 225 struct chan_centers *centers) 226 { 227 int8_t extoff; 228 229 if (!IS_CHAN_HT40(chan)) { 230 centers->ctl_center = centers->ext_center = 231 centers->synth_center = chan->channel; 232 return; 233 } 234 235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 236 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 237 centers->synth_center = 238 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 239 extoff = 1; 240 } else { 241 centers->synth_center = 242 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 243 extoff = -1; 244 } 245 246 centers->ctl_center = 247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 248 /* 25 MHz spacing is supported by hw but not on upper layers */ 249 centers->ext_center = 250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 251 } 252 253 /******************/ 254 /* Chip Revisions */ 255 /******************/ 256 257 static void ath9k_hw_read_revisions(struct ath_hw *ah) 258 { 259 u32 val; 260 261 switch (ah->hw_version.devid) { 262 case AR5416_AR9100_DEVID: 263 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 264 break; 265 case AR9300_DEVID_AR9330: 266 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 267 if (ah->get_mac_revision) { 268 ah->hw_version.macRev = ah->get_mac_revision(); 269 } else { 270 val = REG_READ(ah, AR_SREV); 271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 272 } 273 return; 274 case AR9300_DEVID_AR9340: 275 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 276 val = REG_READ(ah, AR_SREV); 277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 278 return; 279 } 280 281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 282 283 if (val == 0xFF) { 284 val = REG_READ(ah, AR_SREV); 285 ah->hw_version.macVersion = 286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 288 289 if (AR_SREV_9462(ah)) 290 ah->is_pciexpress = true; 291 else 292 ah->is_pciexpress = (val & 293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 294 } else { 295 if (!AR_SREV_9100(ah)) 296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 297 298 ah->hw_version.macRev = val & AR_SREV_REVISION; 299 300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 301 ah->is_pciexpress = true; 302 } 303 } 304 305 /************************************/ 306 /* HW Attach, Detach, Init Routines */ 307 /************************************/ 308 309 static void ath9k_hw_disablepcie(struct ath_hw *ah) 310 { 311 if (!AR_SREV_5416(ah)) 312 return; 313 314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 323 324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 325 } 326 327 static void ath9k_hw_aspm_init(struct ath_hw *ah) 328 { 329 struct ath_common *common = ath9k_hw_common(ah); 330 331 if (common->bus_ops->aspm_init) 332 common->bus_ops->aspm_init(common); 333 } 334 335 /* This should work for all families including legacy */ 336 static bool ath9k_hw_chip_test(struct ath_hw *ah) 337 { 338 struct ath_common *common = ath9k_hw_common(ah); 339 u32 regAddr[2] = { AR_STA_ID0 }; 340 u32 regHold[2]; 341 static const u32 patternData[4] = { 342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 343 }; 344 int i, j, loop_max; 345 346 if (!AR_SREV_9300_20_OR_LATER(ah)) { 347 loop_max = 2; 348 regAddr[1] = AR_PHY_BASE + (8 << 2); 349 } else 350 loop_max = 1; 351 352 for (i = 0; i < loop_max; i++) { 353 u32 addr = regAddr[i]; 354 u32 wrData, rdData; 355 356 regHold[i] = REG_READ(ah, addr); 357 for (j = 0; j < 0x100; j++) { 358 wrData = (j << 16) | j; 359 REG_WRITE(ah, addr, wrData); 360 rdData = REG_READ(ah, addr); 361 if (rdData != wrData) { 362 ath_err(common, 363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 364 addr, wrData, rdData); 365 return false; 366 } 367 } 368 for (j = 0; j < 4; j++) { 369 wrData = patternData[j]; 370 REG_WRITE(ah, addr, wrData); 371 rdData = REG_READ(ah, addr); 372 if (wrData != rdData) { 373 ath_err(common, 374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 375 addr, wrData, rdData); 376 return false; 377 } 378 } 379 REG_WRITE(ah, regAddr[i], regHold[i]); 380 } 381 udelay(100); 382 383 return true; 384 } 385 386 static void ath9k_hw_init_config(struct ath_hw *ah) 387 { 388 int i; 389 390 ah->config.dma_beacon_response_time = 2; 391 ah->config.sw_beacon_response_time = 10; 392 ah->config.additional_swba_backoff = 0; 393 ah->config.ack_6mb = 0x0; 394 ah->config.cwm_ignore_extcca = 0; 395 ah->config.pcie_clock_req = 0; 396 ah->config.pcie_waen = 0; 397 ah->config.analog_shiftreg = 1; 398 ah->config.enable_ani = true; 399 400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 401 ah->config.spurchans[i][0] = AR_NO_SPUR; 402 ah->config.spurchans[i][1] = AR_NO_SPUR; 403 } 404 405 /* PAPRD needs some more work to be enabled */ 406 ah->config.paprd_disable = 1; 407 408 ah->config.rx_intr_mitigation = true; 409 ah->config.pcieSerDesWrite = true; 410 411 /* 412 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 414 * This means we use it for all AR5416 devices, and the few 415 * minor PCI AR9280 devices out there. 416 * 417 * Serialization is required because these devices do not handle 418 * well the case of two concurrent reads/writes due to the latency 419 * involved. During one read/write another read/write can be issued 420 * on another CPU while the previous read/write may still be working 421 * on our hardware, if we hit this case the hardware poops in a loop. 422 * We prevent this by serializing reads and writes. 423 * 424 * This issue is not present on PCI-Express devices or pre-AR5416 425 * devices (legacy, 802.11abg). 426 */ 427 if (num_possible_cpus() > 1) 428 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 429 } 430 431 static void ath9k_hw_init_defaults(struct ath_hw *ah) 432 { 433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 434 435 regulatory->country_code = CTRY_DEFAULT; 436 regulatory->power_limit = MAX_RATE_POWER; 437 438 ah->hw_version.magic = AR5416_MAGIC; 439 ah->hw_version.subvendorid = 0; 440 441 ah->atim_window = 0; 442 ah->sta_id1_defaults = 443 AR_STA_ID1_CRPT_MIC_ENABLE | 444 AR_STA_ID1_MCAST_KSRCH; 445 if (AR_SREV_9100(ah)) 446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 447 ah->enable_32kHz_clock = DONT_USE_32KHZ; 448 ah->slottime = ATH9K_SLOT_TIME_9; 449 ah->globaltxtimeout = (u32) -1; 450 ah->power_mode = ATH9K_PM_UNDEFINED; 451 } 452 453 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 454 { 455 struct ath_common *common = ath9k_hw_common(ah); 456 u32 sum; 457 int i; 458 u16 eeval; 459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 460 461 sum = 0; 462 for (i = 0; i < 3; i++) { 463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 464 sum += eeval; 465 common->macaddr[2 * i] = eeval >> 8; 466 common->macaddr[2 * i + 1] = eeval & 0xff; 467 } 468 if (sum == 0 || sum == 0xffff * 3) 469 return -EADDRNOTAVAIL; 470 471 return 0; 472 } 473 474 static int ath9k_hw_post_init(struct ath_hw *ah) 475 { 476 struct ath_common *common = ath9k_hw_common(ah); 477 int ecode; 478 479 if (common->bus_ops->ath_bus_type != ATH_USB) { 480 if (!ath9k_hw_chip_test(ah)) 481 return -ENODEV; 482 } 483 484 if (!AR_SREV_9300_20_OR_LATER(ah)) { 485 ecode = ar9002_hw_rf_claim(ah); 486 if (ecode != 0) 487 return ecode; 488 } 489 490 ecode = ath9k_hw_eeprom_init(ah); 491 if (ecode != 0) 492 return ecode; 493 494 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, 495 "Eeprom VER: %d, REV: %d\n", 496 ah->eep_ops->get_eeprom_ver(ah), 497 ah->eep_ops->get_eeprom_rev(ah)); 498 499 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 500 if (ecode) { 501 ath_err(ath9k_hw_common(ah), 502 "Failed allocating banks for external radio\n"); 503 ath9k_hw_rf_free_ext_banks(ah); 504 return ecode; 505 } 506 507 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) { 508 ath9k_hw_ani_setup(ah); 509 ath9k_hw_ani_init(ah); 510 } 511 512 return 0; 513 } 514 515 static void ath9k_hw_attach_ops(struct ath_hw *ah) 516 { 517 if (AR_SREV_9300_20_OR_LATER(ah)) 518 ar9003_hw_attach_ops(ah); 519 else 520 ar9002_hw_attach_ops(ah); 521 } 522 523 /* Called for all hardware families */ 524 static int __ath9k_hw_init(struct ath_hw *ah) 525 { 526 struct ath_common *common = ath9k_hw_common(ah); 527 int r = 0; 528 529 ath9k_hw_read_revisions(ah); 530 531 /* 532 * Read back AR_WA into a permanent copy and set bits 14 and 17. 533 * We need to do this to avoid RMW of this register. We cannot 534 * read the reg when chip is asleep. 535 */ 536 ah->WARegVal = REG_READ(ah, AR_WA); 537 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 538 AR_WA_ASPM_TIMER_BASED_DISABLE); 539 540 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 541 ath_err(common, "Couldn't reset chip\n"); 542 return -EIO; 543 } 544 545 if (AR_SREV_9462(ah)) 546 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 547 548 ath9k_hw_init_defaults(ah); 549 ath9k_hw_init_config(ah); 550 551 ath9k_hw_attach_ops(ah); 552 553 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 554 ath_err(common, "Couldn't wakeup chip\n"); 555 return -EIO; 556 } 557 558 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 559 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 560 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 561 !ah->is_pciexpress)) { 562 ah->config.serialize_regmode = 563 SER_REG_MODE_ON; 564 } else { 565 ah->config.serialize_regmode = 566 SER_REG_MODE_OFF; 567 } 568 } 569 570 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 571 ah->config.serialize_regmode); 572 573 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 574 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 575 else 576 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 577 578 switch (ah->hw_version.macVersion) { 579 case AR_SREV_VERSION_5416_PCI: 580 case AR_SREV_VERSION_5416_PCIE: 581 case AR_SREV_VERSION_9160: 582 case AR_SREV_VERSION_9100: 583 case AR_SREV_VERSION_9280: 584 case AR_SREV_VERSION_9285: 585 case AR_SREV_VERSION_9287: 586 case AR_SREV_VERSION_9271: 587 case AR_SREV_VERSION_9300: 588 case AR_SREV_VERSION_9330: 589 case AR_SREV_VERSION_9485: 590 case AR_SREV_VERSION_9340: 591 case AR_SREV_VERSION_9462: 592 break; 593 default: 594 ath_err(common, 595 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 596 ah->hw_version.macVersion, ah->hw_version.macRev); 597 return -EOPNOTSUPP; 598 } 599 600 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 601 AR_SREV_9330(ah)) 602 ah->is_pciexpress = false; 603 604 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 605 ath9k_hw_init_cal_settings(ah); 606 607 ah->ani_function = ATH9K_ANI_ALL; 608 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 609 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 610 if (!AR_SREV_9300_20_OR_LATER(ah)) 611 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 612 613 ath9k_hw_init_mode_regs(ah); 614 615 if (!ah->is_pciexpress) 616 ath9k_hw_disablepcie(ah); 617 618 if (!AR_SREV_9300_20_OR_LATER(ah)) 619 ar9002_hw_cck_chan14_spread(ah); 620 621 r = ath9k_hw_post_init(ah); 622 if (r) 623 return r; 624 625 ath9k_hw_init_mode_gain_regs(ah); 626 r = ath9k_hw_fill_cap_info(ah); 627 if (r) 628 return r; 629 630 if (ah->is_pciexpress) 631 ath9k_hw_aspm_init(ah); 632 633 r = ath9k_hw_init_macaddr(ah); 634 if (r) { 635 ath_err(common, "Failed to initialize MAC address\n"); 636 return r; 637 } 638 639 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 640 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 641 else 642 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 643 644 if (AR_SREV_9330(ah)) 645 ah->bb_watchdog_timeout_ms = 85; 646 else 647 ah->bb_watchdog_timeout_ms = 25; 648 649 common->state = ATH_HW_INITIALIZED; 650 651 return 0; 652 } 653 654 int ath9k_hw_init(struct ath_hw *ah) 655 { 656 int ret; 657 struct ath_common *common = ath9k_hw_common(ah); 658 659 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 660 switch (ah->hw_version.devid) { 661 case AR5416_DEVID_PCI: 662 case AR5416_DEVID_PCIE: 663 case AR5416_AR9100_DEVID: 664 case AR9160_DEVID_PCI: 665 case AR9280_DEVID_PCI: 666 case AR9280_DEVID_PCIE: 667 case AR9285_DEVID_PCIE: 668 case AR9287_DEVID_PCI: 669 case AR9287_DEVID_PCIE: 670 case AR2427_DEVID_PCIE: 671 case AR9300_DEVID_PCIE: 672 case AR9300_DEVID_AR9485_PCIE: 673 case AR9300_DEVID_AR9330: 674 case AR9300_DEVID_AR9340: 675 case AR9300_DEVID_AR9580: 676 case AR9300_DEVID_AR9462: 677 break; 678 default: 679 if (common->bus_ops->ath_bus_type == ATH_USB) 680 break; 681 ath_err(common, "Hardware device ID 0x%04x not supported\n", 682 ah->hw_version.devid); 683 return -EOPNOTSUPP; 684 } 685 686 ret = __ath9k_hw_init(ah); 687 if (ret) { 688 ath_err(common, 689 "Unable to initialize hardware; initialization status: %d\n", 690 ret); 691 return ret; 692 } 693 694 return 0; 695 } 696 EXPORT_SYMBOL(ath9k_hw_init); 697 698 static void ath9k_hw_init_qos(struct ath_hw *ah) 699 { 700 ENABLE_REGWRITE_BUFFER(ah); 701 702 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 703 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 704 705 REG_WRITE(ah, AR_QOS_NO_ACK, 706 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 707 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 708 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 709 710 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 711 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 712 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 713 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 714 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 715 716 REGWRITE_BUFFER_FLUSH(ah); 717 } 718 719 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 720 { 721 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 722 udelay(100); 723 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 724 725 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 726 udelay(100); 727 728 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 729 } 730 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 731 732 static void ath9k_hw_init_pll(struct ath_hw *ah, 733 struct ath9k_channel *chan) 734 { 735 u32 pll; 736 737 if (AR_SREV_9485(ah)) { 738 739 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 741 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 742 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 743 AR_CH0_DPLL2_KD, 0x40); 744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 745 AR_CH0_DPLL2_KI, 0x4); 746 747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 748 AR_CH0_BB_DPLL1_REFDIV, 0x5); 749 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 750 AR_CH0_BB_DPLL1_NINI, 0x58); 751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 752 AR_CH0_BB_DPLL1_NFRAC, 0x0); 753 754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 755 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 757 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 759 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 760 761 /* program BB PLL phase_shift to 0x6 */ 762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 763 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 764 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 766 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 767 udelay(1000); 768 } else if (AR_SREV_9330(ah)) { 769 u32 ddr_dpll2, pll_control2, kd; 770 771 if (ah->is_clk_25mhz) { 772 ddr_dpll2 = 0x18e82f01; 773 pll_control2 = 0xe04a3d; 774 kd = 0x1d; 775 } else { 776 ddr_dpll2 = 0x19e82f01; 777 pll_control2 = 0x886666; 778 kd = 0x3d; 779 } 780 781 /* program DDR PLL ki and kd value */ 782 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 783 784 /* program DDR PLL phase_shift */ 785 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 786 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 787 788 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 789 udelay(1000); 790 791 /* program refdiv, nint, frac to RTC register */ 792 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 793 794 /* program BB PLL kd and ki value */ 795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 796 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 797 798 /* program BB PLL phase_shift */ 799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 800 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 801 } else if (AR_SREV_9340(ah)) { 802 u32 regval, pll2_divint, pll2_divfrac, refdiv; 803 804 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 805 udelay(1000); 806 807 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 808 udelay(100); 809 810 if (ah->is_clk_25mhz) { 811 pll2_divint = 0x54; 812 pll2_divfrac = 0x1eb85; 813 refdiv = 3; 814 } else { 815 pll2_divint = 88; 816 pll2_divfrac = 0; 817 refdiv = 5; 818 } 819 820 regval = REG_READ(ah, AR_PHY_PLL_MODE); 821 regval |= (0x1 << 16); 822 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 823 udelay(100); 824 825 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 826 (pll2_divint << 18) | pll2_divfrac); 827 udelay(100); 828 829 regval = REG_READ(ah, AR_PHY_PLL_MODE); 830 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 831 (0x4 << 26) | (0x18 << 19); 832 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 833 REG_WRITE(ah, AR_PHY_PLL_MODE, 834 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 835 udelay(1000); 836 } 837 838 pll = ath9k_hw_compute_pll_control(ah, chan); 839 840 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 841 842 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 843 udelay(1000); 844 845 /* Switch the core clock for ar9271 to 117Mhz */ 846 if (AR_SREV_9271(ah)) { 847 udelay(500); 848 REG_WRITE(ah, 0x50040, 0x304); 849 } 850 851 udelay(RTC_PLL_SETTLE_DELAY); 852 853 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 854 855 if (AR_SREV_9340(ah)) { 856 if (ah->is_clk_25mhz) { 857 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 858 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 859 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 860 } else { 861 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 862 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 863 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 864 } 865 udelay(100); 866 } 867 } 868 869 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 870 enum nl80211_iftype opmode) 871 { 872 u32 sync_default = AR_INTR_SYNC_DEFAULT; 873 u32 imr_reg = AR_IMR_TXERR | 874 AR_IMR_TXURN | 875 AR_IMR_RXERR | 876 AR_IMR_RXORN | 877 AR_IMR_BCNMISC; 878 879 if (AR_SREV_9340(ah)) 880 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 881 882 if (AR_SREV_9300_20_OR_LATER(ah)) { 883 imr_reg |= AR_IMR_RXOK_HP; 884 if (ah->config.rx_intr_mitigation) 885 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 886 else 887 imr_reg |= AR_IMR_RXOK_LP; 888 889 } else { 890 if (ah->config.rx_intr_mitigation) 891 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 892 else 893 imr_reg |= AR_IMR_RXOK; 894 } 895 896 if (ah->config.tx_intr_mitigation) 897 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 898 else 899 imr_reg |= AR_IMR_TXOK; 900 901 if (opmode == NL80211_IFTYPE_AP) 902 imr_reg |= AR_IMR_MIB; 903 904 ENABLE_REGWRITE_BUFFER(ah); 905 906 REG_WRITE(ah, AR_IMR, imr_reg); 907 ah->imrs2_reg |= AR_IMR_S2_GTT; 908 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 909 910 if (!AR_SREV_9100(ah)) { 911 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 912 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 913 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 914 } 915 916 REGWRITE_BUFFER_FLUSH(ah); 917 918 if (AR_SREV_9300_20_OR_LATER(ah)) { 919 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 920 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 921 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 922 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 923 } 924 } 925 926 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 927 { 928 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 929 val = min(val, (u32) 0xFFFF); 930 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 931 } 932 933 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 934 { 935 u32 val = ath9k_hw_mac_to_clks(ah, us); 936 val = min(val, (u32) 0xFFFF); 937 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 938 } 939 940 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 941 { 942 u32 val = ath9k_hw_mac_to_clks(ah, us); 943 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 944 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 945 } 946 947 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 948 { 949 u32 val = ath9k_hw_mac_to_clks(ah, us); 950 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 951 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 952 } 953 954 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 955 { 956 if (tu > 0xFFFF) { 957 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 958 "bad global tx timeout %u\n", tu); 959 ah->globaltxtimeout = (u32) -1; 960 return false; 961 } else { 962 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 963 ah->globaltxtimeout = tu; 964 return true; 965 } 966 } 967 968 void ath9k_hw_init_global_settings(struct ath_hw *ah) 969 { 970 struct ath_common *common = ath9k_hw_common(ah); 971 struct ieee80211_conf *conf = &common->hw->conf; 972 const struct ath9k_channel *chan = ah->curchan; 973 int acktimeout, ctstimeout; 974 int slottime; 975 int sifstime; 976 int rx_lat = 0, tx_lat = 0, eifs = 0; 977 u32 reg; 978 979 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 980 ah->misc_mode); 981 982 if (!chan) 983 return; 984 985 if (ah->misc_mode != 0) 986 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 987 988 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 989 rx_lat = 41; 990 else 991 rx_lat = 37; 992 tx_lat = 54; 993 994 if (IS_CHAN_HALF_RATE(chan)) { 995 eifs = 175; 996 rx_lat *= 2; 997 tx_lat *= 2; 998 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 999 tx_lat += 11; 1000 1001 slottime = 13; 1002 sifstime = 32; 1003 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1004 eifs = 340; 1005 rx_lat = (rx_lat * 4) - 1; 1006 tx_lat *= 4; 1007 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1008 tx_lat += 22; 1009 1010 slottime = 21; 1011 sifstime = 64; 1012 } else { 1013 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1014 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1015 reg = AR_USEC_ASYNC_FIFO; 1016 } else { 1017 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1018 common->clockrate; 1019 reg = REG_READ(ah, AR_USEC); 1020 } 1021 rx_lat = MS(reg, AR_USEC_RX_LAT); 1022 tx_lat = MS(reg, AR_USEC_TX_LAT); 1023 1024 slottime = ah->slottime; 1025 if (IS_CHAN_5GHZ(chan)) 1026 sifstime = 16; 1027 else 1028 sifstime = 10; 1029 } 1030 1031 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1032 acktimeout = slottime + sifstime + 3 * ah->coverage_class; 1033 ctstimeout = acktimeout; 1034 1035 /* 1036 * Workaround for early ACK timeouts, add an offset to match the 1037 * initval's 64us ack timeout value. 1038 * This was initially only meant to work around an issue with delayed 1039 * BA frames in some implementations, but it has been found to fix ACK 1040 * timeout issues in other cases as well. 1041 */ 1042 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 1043 acktimeout += 64 - sifstime - ah->slottime; 1044 1045 ath9k_hw_set_sifs_time(ah, sifstime); 1046 ath9k_hw_setslottime(ah, slottime); 1047 ath9k_hw_set_ack_timeout(ah, acktimeout); 1048 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1049 if (ah->globaltxtimeout != (u32) -1) 1050 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1051 1052 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1053 REG_RMW(ah, AR_USEC, 1054 (common->clockrate - 1) | 1055 SM(rx_lat, AR_USEC_RX_LAT) | 1056 SM(tx_lat, AR_USEC_TX_LAT), 1057 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1058 1059 } 1060 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1061 1062 void ath9k_hw_deinit(struct ath_hw *ah) 1063 { 1064 struct ath_common *common = ath9k_hw_common(ah); 1065 1066 if (common->state < ATH_HW_INITIALIZED) 1067 goto free_hw; 1068 1069 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1070 1071 free_hw: 1072 ath9k_hw_rf_free_ext_banks(ah); 1073 } 1074 EXPORT_SYMBOL(ath9k_hw_deinit); 1075 1076 /*******/ 1077 /* INI */ 1078 /*******/ 1079 1080 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1081 { 1082 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1083 1084 if (IS_CHAN_B(chan)) 1085 ctl |= CTL_11B; 1086 else if (IS_CHAN_G(chan)) 1087 ctl |= CTL_11G; 1088 else 1089 ctl |= CTL_11A; 1090 1091 return ctl; 1092 } 1093 1094 /****************************************/ 1095 /* Reset and Channel Switching Routines */ 1096 /****************************************/ 1097 1098 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1099 { 1100 struct ath_common *common = ath9k_hw_common(ah); 1101 1102 ENABLE_REGWRITE_BUFFER(ah); 1103 1104 /* 1105 * set AHB_MODE not to do cacheline prefetches 1106 */ 1107 if (!AR_SREV_9300_20_OR_LATER(ah)) 1108 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1109 1110 /* 1111 * let mac dma reads be in 128 byte chunks 1112 */ 1113 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1114 1115 REGWRITE_BUFFER_FLUSH(ah); 1116 1117 /* 1118 * Restore TX Trigger Level to its pre-reset value. 1119 * The initial value depends on whether aggregation is enabled, and is 1120 * adjusted whenever underruns are detected. 1121 */ 1122 if (!AR_SREV_9300_20_OR_LATER(ah)) 1123 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1124 1125 ENABLE_REGWRITE_BUFFER(ah); 1126 1127 /* 1128 * let mac dma writes be in 128 byte chunks 1129 */ 1130 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1131 1132 /* 1133 * Setup receive FIFO threshold to hold off TX activities 1134 */ 1135 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1136 1137 if (AR_SREV_9300_20_OR_LATER(ah)) { 1138 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1139 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1140 1141 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1142 ah->caps.rx_status_len); 1143 } 1144 1145 /* 1146 * reduce the number of usable entries in PCU TXBUF to avoid 1147 * wrap around issues. 1148 */ 1149 if (AR_SREV_9285(ah)) { 1150 /* For AR9285 the number of Fifos are reduced to half. 1151 * So set the usable tx buf size also to half to 1152 * avoid data/delimiter underruns 1153 */ 1154 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1155 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1156 } else if (!AR_SREV_9271(ah)) { 1157 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1158 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1159 } 1160 1161 REGWRITE_BUFFER_FLUSH(ah); 1162 1163 if (AR_SREV_9300_20_OR_LATER(ah)) 1164 ath9k_hw_reset_txstatus_ring(ah); 1165 } 1166 1167 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1168 { 1169 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1170 u32 set = AR_STA_ID1_KSRCH_MODE; 1171 1172 switch (opmode) { 1173 case NL80211_IFTYPE_ADHOC: 1174 case NL80211_IFTYPE_MESH_POINT: 1175 set |= AR_STA_ID1_ADHOC; 1176 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1177 break; 1178 case NL80211_IFTYPE_AP: 1179 set |= AR_STA_ID1_STA_AP; 1180 /* fall through */ 1181 case NL80211_IFTYPE_STATION: 1182 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1183 break; 1184 default: 1185 if (!ah->is_monitoring) 1186 set = 0; 1187 break; 1188 } 1189 REG_RMW(ah, AR_STA_ID1, set, mask); 1190 } 1191 1192 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1193 u32 *coef_mantissa, u32 *coef_exponent) 1194 { 1195 u32 coef_exp, coef_man; 1196 1197 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1198 if ((coef_scaled >> coef_exp) & 0x1) 1199 break; 1200 1201 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1202 1203 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1204 1205 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1206 *coef_exponent = coef_exp - 16; 1207 } 1208 1209 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1210 { 1211 u32 rst_flags; 1212 u32 tmpReg; 1213 1214 if (AR_SREV_9100(ah)) { 1215 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1216 AR_RTC_DERIVED_CLK_PERIOD, 1); 1217 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1218 } 1219 1220 ENABLE_REGWRITE_BUFFER(ah); 1221 1222 if (AR_SREV_9300_20_OR_LATER(ah)) { 1223 REG_WRITE(ah, AR_WA, ah->WARegVal); 1224 udelay(10); 1225 } 1226 1227 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1228 AR_RTC_FORCE_WAKE_ON_INT); 1229 1230 if (AR_SREV_9100(ah)) { 1231 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1232 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1233 } else { 1234 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1235 if (tmpReg & 1236 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1237 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1238 u32 val; 1239 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1240 1241 val = AR_RC_HOSTIF; 1242 if (!AR_SREV_9300_20_OR_LATER(ah)) 1243 val |= AR_RC_AHB; 1244 REG_WRITE(ah, AR_RC, val); 1245 1246 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1247 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1248 1249 rst_flags = AR_RTC_RC_MAC_WARM; 1250 if (type == ATH9K_RESET_COLD) 1251 rst_flags |= AR_RTC_RC_MAC_COLD; 1252 } 1253 1254 if (AR_SREV_9330(ah)) { 1255 int npend = 0; 1256 int i; 1257 1258 /* AR9330 WAR: 1259 * call external reset function to reset WMAC if: 1260 * - doing a cold reset 1261 * - we have pending frames in the TX queues 1262 */ 1263 1264 for (i = 0; i < AR_NUM_QCU; i++) { 1265 npend = ath9k_hw_numtxpending(ah, i); 1266 if (npend) 1267 break; 1268 } 1269 1270 if (ah->external_reset && 1271 (npend || type == ATH9K_RESET_COLD)) { 1272 int reset_err = 0; 1273 1274 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1275 "reset MAC via external reset\n"); 1276 1277 reset_err = ah->external_reset(); 1278 if (reset_err) { 1279 ath_err(ath9k_hw_common(ah), 1280 "External reset failed, err=%d\n", 1281 reset_err); 1282 return false; 1283 } 1284 1285 REG_WRITE(ah, AR_RTC_RESET, 1); 1286 } 1287 } 1288 1289 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1290 1291 REGWRITE_BUFFER_FLUSH(ah); 1292 1293 udelay(50); 1294 1295 REG_WRITE(ah, AR_RTC_RC, 0); 1296 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1297 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1298 "RTC stuck in MAC reset\n"); 1299 return false; 1300 } 1301 1302 if (!AR_SREV_9100(ah)) 1303 REG_WRITE(ah, AR_RC, 0); 1304 1305 if (AR_SREV_9100(ah)) 1306 udelay(50); 1307 1308 return true; 1309 } 1310 1311 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1312 { 1313 ENABLE_REGWRITE_BUFFER(ah); 1314 1315 if (AR_SREV_9300_20_OR_LATER(ah)) { 1316 REG_WRITE(ah, AR_WA, ah->WARegVal); 1317 udelay(10); 1318 } 1319 1320 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1321 AR_RTC_FORCE_WAKE_ON_INT); 1322 1323 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1324 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1325 1326 REG_WRITE(ah, AR_RTC_RESET, 0); 1327 1328 REGWRITE_BUFFER_FLUSH(ah); 1329 1330 if (!AR_SREV_9300_20_OR_LATER(ah)) 1331 udelay(2); 1332 1333 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1334 REG_WRITE(ah, AR_RC, 0); 1335 1336 REG_WRITE(ah, AR_RTC_RESET, 1); 1337 1338 if (!ath9k_hw_wait(ah, 1339 AR_RTC_STATUS, 1340 AR_RTC_STATUS_M, 1341 AR_RTC_STATUS_ON, 1342 AH_WAIT_TIMEOUT)) { 1343 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 1344 "RTC not waking up\n"); 1345 return false; 1346 } 1347 1348 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1349 } 1350 1351 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1352 { 1353 1354 if (AR_SREV_9300_20_OR_LATER(ah)) { 1355 REG_WRITE(ah, AR_WA, ah->WARegVal); 1356 udelay(10); 1357 } 1358 1359 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1360 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1361 1362 switch (type) { 1363 case ATH9K_RESET_POWER_ON: 1364 return ath9k_hw_set_reset_power_on(ah); 1365 case ATH9K_RESET_WARM: 1366 case ATH9K_RESET_COLD: 1367 return ath9k_hw_set_reset(ah, type); 1368 default: 1369 return false; 1370 } 1371 } 1372 1373 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1374 struct ath9k_channel *chan) 1375 { 1376 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1377 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1378 return false; 1379 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1380 return false; 1381 1382 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1383 return false; 1384 1385 ah->chip_fullsleep = false; 1386 ath9k_hw_init_pll(ah, chan); 1387 ath9k_hw_set_rfmode(ah, chan); 1388 1389 return true; 1390 } 1391 1392 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1393 struct ath9k_channel *chan) 1394 { 1395 struct ath_common *common = ath9k_hw_common(ah); 1396 u32 qnum; 1397 int r; 1398 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1399 bool band_switch, mode_diff; 1400 u8 ini_reloaded; 1401 1402 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1403 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1404 CHANNEL_5GHZ)); 1405 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1406 1407 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1408 if (ath9k_hw_numtxpending(ah, qnum)) { 1409 ath_dbg(common, ATH_DBG_QUEUE, 1410 "Transmit frames pending on queue %d\n", qnum); 1411 return false; 1412 } 1413 } 1414 1415 if (!ath9k_hw_rfbus_req(ah)) { 1416 ath_err(common, "Could not kill baseband RX\n"); 1417 return false; 1418 } 1419 1420 if (edma && (band_switch || mode_diff)) { 1421 ath9k_hw_mark_phy_inactive(ah); 1422 udelay(5); 1423 1424 ath9k_hw_init_pll(ah, NULL); 1425 1426 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1427 ath_err(common, "Failed to do fast channel change\n"); 1428 return false; 1429 } 1430 } 1431 1432 ath9k_hw_set_channel_regs(ah, chan); 1433 1434 r = ath9k_hw_rf_set_freq(ah, chan); 1435 if (r) { 1436 ath_err(common, "Failed to set channel\n"); 1437 return false; 1438 } 1439 ath9k_hw_set_clockrate(ah); 1440 ath9k_hw_apply_txpower(ah, chan); 1441 ath9k_hw_rfbus_done(ah); 1442 1443 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1444 ath9k_hw_set_delta_slope(ah, chan); 1445 1446 ath9k_hw_spur_mitigate_freq(ah, chan); 1447 1448 if (edma && (band_switch || mode_diff)) { 1449 ah->ah_flags |= AH_FASTCC; 1450 if (band_switch || ini_reloaded) 1451 ah->eep_ops->set_board_values(ah, chan); 1452 1453 ath9k_hw_init_bb(ah, chan); 1454 1455 if (band_switch || ini_reloaded) 1456 ath9k_hw_init_cal(ah, chan); 1457 ah->ah_flags &= ~AH_FASTCC; 1458 } 1459 1460 return true; 1461 } 1462 1463 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1464 { 1465 u32 gpio_mask = ah->gpio_mask; 1466 int i; 1467 1468 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1469 if (!(gpio_mask & 1)) 1470 continue; 1471 1472 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1473 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1474 } 1475 } 1476 1477 bool ath9k_hw_check_alive(struct ath_hw *ah) 1478 { 1479 int count = 50; 1480 u32 reg; 1481 1482 if (AR_SREV_9285_12_OR_LATER(ah)) 1483 return true; 1484 1485 do { 1486 reg = REG_READ(ah, AR_OBS_BUS_1); 1487 1488 if ((reg & 0x7E7FFFEF) == 0x00702400) 1489 continue; 1490 1491 switch (reg & 0x7E000B00) { 1492 case 0x1E000000: 1493 case 0x52000B00: 1494 case 0x18000B00: 1495 continue; 1496 default: 1497 return true; 1498 } 1499 } while (count-- > 0); 1500 1501 return false; 1502 } 1503 EXPORT_SYMBOL(ath9k_hw_check_alive); 1504 1505 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1506 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1507 { 1508 struct ath_common *common = ath9k_hw_common(ah); 1509 u32 saveLedState; 1510 struct ath9k_channel *curchan = ah->curchan; 1511 u32 saveDefAntenna; 1512 u32 macStaId1; 1513 u64 tsf = 0; 1514 int i, r; 1515 bool allow_fbs = false; 1516 1517 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1518 return -EIO; 1519 1520 if (curchan && !ah->chip_fullsleep) 1521 ath9k_hw_getnf(ah, curchan); 1522 1523 ah->caldata = caldata; 1524 if (caldata && 1525 (chan->channel != caldata->channel || 1526 (chan->channelFlags & ~CHANNEL_CW_INT) != 1527 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1528 /* Operating channel changed, reset channel calibration data */ 1529 memset(caldata, 0, sizeof(*caldata)); 1530 ath9k_init_nfcal_hist_buffer(ah, chan); 1531 } 1532 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1533 1534 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1535 bChannelChange = false; 1536 1537 if (caldata && 1538 caldata->done_txiqcal_once && 1539 caldata->done_txclcal_once && 1540 caldata->rtt_hist.num_readings) 1541 allow_fbs = true; 1542 1543 if (bChannelChange && 1544 (ah->chip_fullsleep != true) && 1545 (ah->curchan != NULL) && 1546 (chan->channel != ah->curchan->channel) && 1547 (allow_fbs || 1548 ((chan->channelFlags & CHANNEL_ALL) == 1549 (ah->curchan->channelFlags & CHANNEL_ALL)))) { 1550 if (ath9k_hw_channel_change(ah, chan)) { 1551 ath9k_hw_loadnf(ah, ah->curchan); 1552 ath9k_hw_start_nfcal(ah, true); 1553 if (AR_SREV_9271(ah)) 1554 ar9002_hw_load_ani_reg(ah, chan); 1555 return 0; 1556 } 1557 } 1558 1559 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1560 if (saveDefAntenna == 0) 1561 saveDefAntenna = 1; 1562 1563 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1564 1565 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1566 if (AR_SREV_9100(ah) || 1567 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1568 tsf = ath9k_hw_gettsf64(ah); 1569 1570 saveLedState = REG_READ(ah, AR_CFG_LED) & 1571 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1572 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1573 1574 ath9k_hw_mark_phy_inactive(ah); 1575 1576 ah->paprd_table_write_done = false; 1577 1578 /* Only required on the first reset */ 1579 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1580 REG_WRITE(ah, 1581 AR9271_RESET_POWER_DOWN_CONTROL, 1582 AR9271_RADIO_RF_RST); 1583 udelay(50); 1584 } 1585 1586 if (!ath9k_hw_chip_reset(ah, chan)) { 1587 ath_err(common, "Chip reset failed\n"); 1588 return -EINVAL; 1589 } 1590 1591 /* Only required on the first reset */ 1592 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1593 ah->htc_reset_init = false; 1594 REG_WRITE(ah, 1595 AR9271_RESET_POWER_DOWN_CONTROL, 1596 AR9271_GATE_MAC_CTL); 1597 udelay(50); 1598 } 1599 1600 /* Restore TSF */ 1601 if (tsf) 1602 ath9k_hw_settsf64(ah, tsf); 1603 1604 if (AR_SREV_9280_20_OR_LATER(ah)) 1605 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1606 1607 if (!AR_SREV_9300_20_OR_LATER(ah)) 1608 ar9002_hw_enable_async_fifo(ah); 1609 1610 r = ath9k_hw_process_ini(ah, chan); 1611 if (r) 1612 return r; 1613 1614 /* 1615 * Some AR91xx SoC devices frequently fail to accept TSF writes 1616 * right after the chip reset. When that happens, write a new 1617 * value after the initvals have been applied, with an offset 1618 * based on measured time difference 1619 */ 1620 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1621 tsf += 1500; 1622 ath9k_hw_settsf64(ah, tsf); 1623 } 1624 1625 /* Setup MFP options for CCMP */ 1626 if (AR_SREV_9280_20_OR_LATER(ah)) { 1627 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1628 * frames when constructing CCMP AAD. */ 1629 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1630 0xc7ff); 1631 ah->sw_mgmt_crypto = false; 1632 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1633 /* Disable hardware crypto for management frames */ 1634 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1635 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1636 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1637 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1638 ah->sw_mgmt_crypto = true; 1639 } else 1640 ah->sw_mgmt_crypto = true; 1641 1642 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1643 ath9k_hw_set_delta_slope(ah, chan); 1644 1645 ath9k_hw_spur_mitigate_freq(ah, chan); 1646 ah->eep_ops->set_board_values(ah, chan); 1647 1648 ENABLE_REGWRITE_BUFFER(ah); 1649 1650 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1651 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1652 | macStaId1 1653 | AR_STA_ID1_RTS_USE_DEF 1654 | (ah->config. 1655 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1656 | ah->sta_id1_defaults); 1657 ath_hw_setbssidmask(common); 1658 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1659 ath9k_hw_write_associd(ah); 1660 REG_WRITE(ah, AR_ISR, ~0); 1661 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1662 1663 REGWRITE_BUFFER_FLUSH(ah); 1664 1665 ath9k_hw_set_operating_mode(ah, ah->opmode); 1666 1667 r = ath9k_hw_rf_set_freq(ah, chan); 1668 if (r) 1669 return r; 1670 1671 ath9k_hw_set_clockrate(ah); 1672 1673 ENABLE_REGWRITE_BUFFER(ah); 1674 1675 for (i = 0; i < AR_NUM_DCU; i++) 1676 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1677 1678 REGWRITE_BUFFER_FLUSH(ah); 1679 1680 ah->intr_txqs = 0; 1681 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1682 ath9k_hw_resettxqueue(ah, i); 1683 1684 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1685 ath9k_hw_ani_cache_ini_regs(ah); 1686 ath9k_hw_init_qos(ah); 1687 1688 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1689 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1690 1691 ath9k_hw_init_global_settings(ah); 1692 1693 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1694 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1695 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1696 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1697 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1698 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1699 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1700 } 1701 1702 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1703 1704 ath9k_hw_set_dma(ah); 1705 1706 REG_WRITE(ah, AR_OBS, 8); 1707 1708 if (ah->config.rx_intr_mitigation) { 1709 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1710 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1711 } 1712 1713 if (ah->config.tx_intr_mitigation) { 1714 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1715 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1716 } 1717 1718 ath9k_hw_init_bb(ah, chan); 1719 1720 if (caldata) { 1721 caldata->done_txiqcal_once = false; 1722 caldata->done_txclcal_once = false; 1723 caldata->rtt_hist.num_readings = 0; 1724 } 1725 if (!ath9k_hw_init_cal(ah, chan)) 1726 return -EIO; 1727 1728 ath9k_hw_loadnf(ah, chan); 1729 ath9k_hw_start_nfcal(ah, true); 1730 1731 ENABLE_REGWRITE_BUFFER(ah); 1732 1733 ath9k_hw_restore_chainmask(ah); 1734 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1735 1736 REGWRITE_BUFFER_FLUSH(ah); 1737 1738 /* 1739 * For big endian systems turn on swapping for descriptors 1740 */ 1741 if (AR_SREV_9100(ah)) { 1742 u32 mask; 1743 mask = REG_READ(ah, AR_CFG); 1744 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1745 ath_dbg(common, ATH_DBG_RESET, 1746 "CFG Byte Swap Set 0x%x\n", mask); 1747 } else { 1748 mask = 1749 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1750 REG_WRITE(ah, AR_CFG, mask); 1751 ath_dbg(common, ATH_DBG_RESET, 1752 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1753 } 1754 } else { 1755 if (common->bus_ops->ath_bus_type == ATH_USB) { 1756 /* Configure AR9271 target WLAN */ 1757 if (AR_SREV_9271(ah)) 1758 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1759 else 1760 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1761 } 1762 #ifdef __BIG_ENDIAN 1763 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1764 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1765 else 1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1767 #endif 1768 } 1769 1770 if (ah->btcoex_hw.enabled) 1771 ath9k_hw_btcoex_enable(ah); 1772 1773 if (AR_SREV_9300_20_OR_LATER(ah)) { 1774 ar9003_hw_bb_watchdog_config(ah); 1775 1776 ar9003_hw_disable_phy_restart(ah); 1777 } 1778 1779 ath9k_hw_apply_gpio_override(ah); 1780 1781 return 0; 1782 } 1783 EXPORT_SYMBOL(ath9k_hw_reset); 1784 1785 /******************************/ 1786 /* Power Management (Chipset) */ 1787 /******************************/ 1788 1789 /* 1790 * Notify Power Mgt is disabled in self-generated frames. 1791 * If requested, force chip to sleep. 1792 */ 1793 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1794 { 1795 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1796 if (setChip) { 1797 if (AR_SREV_9462(ah)) { 1798 REG_WRITE(ah, AR_TIMER_MODE, 1799 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 1800 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, 1801 AR_NDP2_TIMER_MODE) & 0xFFFFFF00); 1802 REG_WRITE(ah, AR_SLP32_INC, 1803 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); 1804 /* xxx Required for WLAN only case ? */ 1805 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1806 udelay(100); 1807 } 1808 1809 /* 1810 * Clear the RTC force wake bit to allow the 1811 * mac to go to sleep. 1812 */ 1813 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1814 1815 if (AR_SREV_9462(ah)) 1816 udelay(100); 1817 1818 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1819 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1820 1821 /* Shutdown chip. Active low */ 1822 if (!AR_SREV_5416(ah) && 1823 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) { 1824 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 1825 udelay(2); 1826 } 1827 } 1828 1829 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1830 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1831 } 1832 1833 /* 1834 * Notify Power Management is enabled in self-generating 1835 * frames. If request, set power mode of chip to 1836 * auto/normal. Duration in units of 128us (1/8 TU). 1837 */ 1838 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1839 { 1840 u32 val; 1841 1842 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1843 if (setChip) { 1844 struct ath9k_hw_capabilities *pCap = &ah->caps; 1845 1846 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1847 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1848 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1849 AR_RTC_FORCE_WAKE_ON_INT); 1850 } else { 1851 1852 /* When chip goes into network sleep, it could be waken 1853 * up by MCI_INT interrupt caused by BT's HW messages 1854 * (LNA_xxx, CONT_xxx) which chould be in a very fast 1855 * rate (~100us). This will cause chip to leave and 1856 * re-enter network sleep mode frequently, which in 1857 * consequence will have WLAN MCI HW to generate lots of 1858 * SYS_WAKING and SYS_SLEEPING messages which will make 1859 * BT CPU to busy to process. 1860 */ 1861 if (AR_SREV_9462(ah)) { 1862 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 1863 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 1864 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 1865 } 1866 /* 1867 * Clear the RTC force wake bit to allow the 1868 * mac to go to sleep. 1869 */ 1870 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1871 AR_RTC_FORCE_WAKE_EN); 1872 1873 if (AR_SREV_9462(ah)) 1874 udelay(30); 1875 } 1876 } 1877 1878 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1879 if (AR_SREV_9300_20_OR_LATER(ah)) 1880 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1881 } 1882 1883 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1884 { 1885 u32 val; 1886 int i; 1887 1888 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1889 if (AR_SREV_9300_20_OR_LATER(ah)) { 1890 REG_WRITE(ah, AR_WA, ah->WARegVal); 1891 udelay(10); 1892 } 1893 1894 if (setChip) { 1895 if ((REG_READ(ah, AR_RTC_STATUS) & 1896 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1897 if (ath9k_hw_set_reset_reg(ah, 1898 ATH9K_RESET_POWER_ON) != true) { 1899 return false; 1900 } 1901 if (!AR_SREV_9300_20_OR_LATER(ah)) 1902 ath9k_hw_init_pll(ah, NULL); 1903 } 1904 if (AR_SREV_9100(ah)) 1905 REG_SET_BIT(ah, AR_RTC_RESET, 1906 AR_RTC_RESET_EN); 1907 1908 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1909 AR_RTC_FORCE_WAKE_EN); 1910 udelay(50); 1911 1912 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1913 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1914 if (val == AR_RTC_STATUS_ON) 1915 break; 1916 udelay(50); 1917 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1918 AR_RTC_FORCE_WAKE_EN); 1919 } 1920 if (i == 0) { 1921 ath_err(ath9k_hw_common(ah), 1922 "Failed to wakeup in %uus\n", 1923 POWER_UP_TIME / 20); 1924 return false; 1925 } 1926 } 1927 1928 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1929 1930 return true; 1931 } 1932 1933 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1934 { 1935 struct ath_common *common = ath9k_hw_common(ah); 1936 int status = true, setChip = true; 1937 static const char *modes[] = { 1938 "AWAKE", 1939 "FULL-SLEEP", 1940 "NETWORK SLEEP", 1941 "UNDEFINED" 1942 }; 1943 1944 if (ah->power_mode == mode) 1945 return status; 1946 1947 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", 1948 modes[ah->power_mode], modes[mode]); 1949 1950 switch (mode) { 1951 case ATH9K_PM_AWAKE: 1952 status = ath9k_hw_set_power_awake(ah, setChip); 1953 break; 1954 case ATH9K_PM_FULL_SLEEP: 1955 ath9k_set_power_sleep(ah, setChip); 1956 ah->chip_fullsleep = true; 1957 break; 1958 case ATH9K_PM_NETWORK_SLEEP: 1959 ath9k_set_power_network_sleep(ah, setChip); 1960 break; 1961 default: 1962 ath_err(common, "Unknown power mode %u\n", mode); 1963 return false; 1964 } 1965 ah->power_mode = mode; 1966 1967 /* 1968 * XXX: If this warning never comes up after a while then 1969 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 1970 * ath9k_hw_setpower() return type void. 1971 */ 1972 1973 if (!(ah->ah_flags & AH_UNPLUGGED)) 1974 ATH_DBG_WARN_ON_ONCE(!status); 1975 1976 return status; 1977 } 1978 EXPORT_SYMBOL(ath9k_hw_setpower); 1979 1980 /*******************/ 1981 /* Beacon Handling */ 1982 /*******************/ 1983 1984 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1985 { 1986 int flags = 0; 1987 1988 ENABLE_REGWRITE_BUFFER(ah); 1989 1990 switch (ah->opmode) { 1991 case NL80211_IFTYPE_ADHOC: 1992 case NL80211_IFTYPE_MESH_POINT: 1993 REG_SET_BIT(ah, AR_TXCFG, 1994 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1995 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 1996 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 1997 flags |= AR_NDP_TIMER_EN; 1998 case NL80211_IFTYPE_AP: 1999 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2000 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2001 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2002 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2003 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2004 flags |= 2005 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2006 break; 2007 default: 2008 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, 2009 "%s: unsupported opmode: %d\n", 2010 __func__, ah->opmode); 2011 return; 2012 break; 2013 } 2014 2015 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2016 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2017 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2018 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2019 2020 REGWRITE_BUFFER_FLUSH(ah); 2021 2022 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2023 } 2024 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2025 2026 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2027 const struct ath9k_beacon_state *bs) 2028 { 2029 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2030 struct ath9k_hw_capabilities *pCap = &ah->caps; 2031 struct ath_common *common = ath9k_hw_common(ah); 2032 2033 ENABLE_REGWRITE_BUFFER(ah); 2034 2035 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2036 2037 REG_WRITE(ah, AR_BEACON_PERIOD, 2038 TU_TO_USEC(bs->bs_intval)); 2039 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2040 TU_TO_USEC(bs->bs_intval)); 2041 2042 REGWRITE_BUFFER_FLUSH(ah); 2043 2044 REG_RMW_FIELD(ah, AR_RSSI_THR, 2045 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2046 2047 beaconintval = bs->bs_intval; 2048 2049 if (bs->bs_sleepduration > beaconintval) 2050 beaconintval = bs->bs_sleepduration; 2051 2052 dtimperiod = bs->bs_dtimperiod; 2053 if (bs->bs_sleepduration > dtimperiod) 2054 dtimperiod = bs->bs_sleepduration; 2055 2056 if (beaconintval == dtimperiod) 2057 nextTbtt = bs->bs_nextdtim; 2058 else 2059 nextTbtt = bs->bs_nexttbtt; 2060 2061 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2062 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 2063 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 2064 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 2065 2066 ENABLE_REGWRITE_BUFFER(ah); 2067 2068 REG_WRITE(ah, AR_NEXT_DTIM, 2069 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2070 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2071 2072 REG_WRITE(ah, AR_SLEEP1, 2073 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2074 | AR_SLEEP1_ASSUME_DTIM); 2075 2076 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2077 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2078 else 2079 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2080 2081 REG_WRITE(ah, AR_SLEEP2, 2082 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2083 2084 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2085 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2086 2087 REGWRITE_BUFFER_FLUSH(ah); 2088 2089 REG_SET_BIT(ah, AR_TIMER_MODE, 2090 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2091 AR_DTIM_TIMER_EN); 2092 2093 /* TSF Out of Range Threshold */ 2094 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2095 } 2096 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2097 2098 /*******************/ 2099 /* HW Capabilities */ 2100 /*******************/ 2101 2102 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2103 { 2104 eeprom_chainmask &= chip_chainmask; 2105 if (eeprom_chainmask) 2106 return eeprom_chainmask; 2107 else 2108 return chip_chainmask; 2109 } 2110 2111 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2112 { 2113 struct ath9k_hw_capabilities *pCap = &ah->caps; 2114 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2115 struct ath_common *common = ath9k_hw_common(ah); 2116 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2117 unsigned int chip_chainmask; 2118 2119 u16 eeval; 2120 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2121 2122 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2123 regulatory->current_rd = eeval; 2124 2125 if (ah->opmode != NL80211_IFTYPE_AP && 2126 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2127 if (regulatory->current_rd == 0x64 || 2128 regulatory->current_rd == 0x65) 2129 regulatory->current_rd += 5; 2130 else if (regulatory->current_rd == 0x41) 2131 regulatory->current_rd = 0x43; 2132 ath_dbg(common, ATH_DBG_REGULATORY, 2133 "regdomain mapped to 0x%x\n", regulatory->current_rd); 2134 } 2135 2136 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2137 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2138 ath_err(common, 2139 "no band has been marked as supported in EEPROM\n"); 2140 return -EINVAL; 2141 } 2142 2143 if (eeval & AR5416_OPFLAGS_11A) 2144 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2145 2146 if (eeval & AR5416_OPFLAGS_11G) 2147 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2148 2149 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2150 chip_chainmask = 1; 2151 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2152 chip_chainmask = 7; 2153 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2154 chip_chainmask = 3; 2155 else 2156 chip_chainmask = 7; 2157 2158 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2159 /* 2160 * For AR9271 we will temporarilly uses the rx chainmax as read from 2161 * the EEPROM. 2162 */ 2163 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2164 !(eeval & AR5416_OPFLAGS_11A) && 2165 !(AR_SREV_9271(ah))) 2166 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2167 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2168 else if (AR_SREV_9100(ah)) 2169 pCap->rx_chainmask = 0x7; 2170 else 2171 /* Use rx_chainmask from EEPROM. */ 2172 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2173 2174 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2175 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2176 ah->txchainmask = pCap->tx_chainmask; 2177 ah->rxchainmask = pCap->rx_chainmask; 2178 2179 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2180 2181 /* enable key search for every frame in an aggregate */ 2182 if (AR_SREV_9300_20_OR_LATER(ah)) 2183 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2184 2185 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2186 2187 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2188 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2189 else 2190 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2191 2192 if (AR_SREV_9271(ah)) 2193 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2194 else if (AR_DEVID_7010(ah)) 2195 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2196 else if (AR_SREV_9300_20_OR_LATER(ah)) 2197 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2198 else if (AR_SREV_9287_11_OR_LATER(ah)) 2199 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2200 else if (AR_SREV_9285_12_OR_LATER(ah)) 2201 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2202 else if (AR_SREV_9280_20_OR_LATER(ah)) 2203 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2204 else 2205 pCap->num_gpio_pins = AR_NUM_GPIO; 2206 2207 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 2208 pCap->hw_caps |= ATH9K_HW_CAP_CST; 2209 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2210 } else { 2211 pCap->rts_aggr_limit = (8 * 1024); 2212 } 2213 2214 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2215 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2216 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2217 ah->rfkill_gpio = 2218 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2219 ah->rfkill_polarity = 2220 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2221 2222 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2223 } 2224 #endif 2225 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2226 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2227 else 2228 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2229 2230 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2231 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2232 else 2233 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2234 2235 if (common->btcoex_enabled) { 2236 if (AR_SREV_9300_20_OR_LATER(ah)) { 2237 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2238 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300; 2239 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300; 2240 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300; 2241 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 2242 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280; 2243 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280; 2244 2245 if (AR_SREV_9285(ah)) { 2246 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2247 btcoex_hw->btpriority_gpio = 2248 ATH_BTPRIORITY_GPIO_9285; 2249 } else { 2250 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2251 } 2252 } 2253 } else { 2254 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2255 } 2256 2257 if (AR_SREV_9300_20_OR_LATER(ah)) { 2258 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2259 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2260 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2261 2262 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2263 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2264 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2265 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2266 pCap->txs_len = sizeof(struct ar9003_txs); 2267 if (!ah->config.paprd_disable && 2268 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2269 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2270 } else { 2271 pCap->tx_desc_len = sizeof(struct ath_desc); 2272 if (AR_SREV_9280_20(ah)) 2273 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2274 } 2275 2276 if (AR_SREV_9300_20_OR_LATER(ah)) 2277 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2278 2279 if (AR_SREV_9300_20_OR_LATER(ah)) 2280 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2281 2282 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2283 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2284 2285 if (AR_SREV_9285(ah)) 2286 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2287 ant_div_ctl1 = 2288 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2289 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2290 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2291 } 2292 if (AR_SREV_9300_20_OR_LATER(ah)) { 2293 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2294 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2295 } 2296 2297 2298 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2299 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2300 /* 2301 * enable the diversity-combining algorithm only when 2302 * both enable_lna_div and enable_fast_div are set 2303 * Table for Diversity 2304 * ant_div_alt_lnaconf bit 0-1 2305 * ant_div_main_lnaconf bit 2-3 2306 * ant_div_alt_gaintb bit 4 2307 * ant_div_main_gaintb bit 5 2308 * enable_ant_div_lnadiv bit 6 2309 * enable_ant_fast_div bit 7 2310 */ 2311 if ((ant_div_ctl1 >> 0x6) == 0x3) 2312 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2313 } 2314 2315 if (AR_SREV_9485_10(ah)) { 2316 pCap->pcie_lcr_extsync_en = true; 2317 pCap->pcie_lcr_offset = 0x80; 2318 } 2319 2320 tx_chainmask = pCap->tx_chainmask; 2321 rx_chainmask = pCap->rx_chainmask; 2322 while (tx_chainmask || rx_chainmask) { 2323 if (tx_chainmask & BIT(0)) 2324 pCap->max_txchains++; 2325 if (rx_chainmask & BIT(0)) 2326 pCap->max_rxchains++; 2327 2328 tx_chainmask >>= 1; 2329 rx_chainmask >>= 1; 2330 } 2331 2332 if (AR_SREV_9300_20_OR_LATER(ah)) { 2333 ah->enabled_cals |= TX_IQ_CAL; 2334 if (!AR_SREV_9330(ah)) 2335 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2336 } 2337 if (AR_SREV_9462(ah)) 2338 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2339 2340 return 0; 2341 } 2342 2343 /****************************/ 2344 /* GPIO / RFKILL / Antennae */ 2345 /****************************/ 2346 2347 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2348 u32 gpio, u32 type) 2349 { 2350 int addr; 2351 u32 gpio_shift, tmp; 2352 2353 if (gpio > 11) 2354 addr = AR_GPIO_OUTPUT_MUX3; 2355 else if (gpio > 5) 2356 addr = AR_GPIO_OUTPUT_MUX2; 2357 else 2358 addr = AR_GPIO_OUTPUT_MUX1; 2359 2360 gpio_shift = (gpio % 6) * 5; 2361 2362 if (AR_SREV_9280_20_OR_LATER(ah) 2363 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2364 REG_RMW(ah, addr, (type << gpio_shift), 2365 (0x1f << gpio_shift)); 2366 } else { 2367 tmp = REG_READ(ah, addr); 2368 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2369 tmp &= ~(0x1f << gpio_shift); 2370 tmp |= (type << gpio_shift); 2371 REG_WRITE(ah, addr, tmp); 2372 } 2373 } 2374 2375 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2376 { 2377 u32 gpio_shift; 2378 2379 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2380 2381 if (AR_DEVID_7010(ah)) { 2382 gpio_shift = gpio; 2383 REG_RMW(ah, AR7010_GPIO_OE, 2384 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2385 (AR7010_GPIO_OE_MASK << gpio_shift)); 2386 return; 2387 } 2388 2389 gpio_shift = gpio << 1; 2390 REG_RMW(ah, 2391 AR_GPIO_OE_OUT, 2392 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2393 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2394 } 2395 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2396 2397 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2398 { 2399 #define MS_REG_READ(x, y) \ 2400 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2401 2402 if (gpio >= ah->caps.num_gpio_pins) 2403 return 0xffffffff; 2404 2405 if (AR_DEVID_7010(ah)) { 2406 u32 val; 2407 val = REG_READ(ah, AR7010_GPIO_IN); 2408 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2409 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2410 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2411 AR_GPIO_BIT(gpio)) != 0; 2412 else if (AR_SREV_9271(ah)) 2413 return MS_REG_READ(AR9271, gpio) != 0; 2414 else if (AR_SREV_9287_11_OR_LATER(ah)) 2415 return MS_REG_READ(AR9287, gpio) != 0; 2416 else if (AR_SREV_9285_12_OR_LATER(ah)) 2417 return MS_REG_READ(AR9285, gpio) != 0; 2418 else if (AR_SREV_9280_20_OR_LATER(ah)) 2419 return MS_REG_READ(AR928X, gpio) != 0; 2420 else 2421 return MS_REG_READ(AR, gpio) != 0; 2422 } 2423 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2424 2425 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2426 u32 ah_signal_type) 2427 { 2428 u32 gpio_shift; 2429 2430 if (AR_DEVID_7010(ah)) { 2431 gpio_shift = gpio; 2432 REG_RMW(ah, AR7010_GPIO_OE, 2433 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2434 (AR7010_GPIO_OE_MASK << gpio_shift)); 2435 return; 2436 } 2437 2438 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2439 gpio_shift = 2 * gpio; 2440 REG_RMW(ah, 2441 AR_GPIO_OE_OUT, 2442 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2443 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2444 } 2445 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2446 2447 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2448 { 2449 if (AR_DEVID_7010(ah)) { 2450 val = val ? 0 : 1; 2451 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2452 AR_GPIO_BIT(gpio)); 2453 return; 2454 } 2455 2456 if (AR_SREV_9271(ah)) 2457 val = ~val; 2458 2459 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2460 AR_GPIO_BIT(gpio)); 2461 } 2462 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2463 2464 u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2465 { 2466 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2467 } 2468 EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2469 2470 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2471 { 2472 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2473 } 2474 EXPORT_SYMBOL(ath9k_hw_setantenna); 2475 2476 /*********************/ 2477 /* General Operation */ 2478 /*********************/ 2479 2480 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2481 { 2482 u32 bits = REG_READ(ah, AR_RX_FILTER); 2483 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2484 2485 if (phybits & AR_PHY_ERR_RADAR) 2486 bits |= ATH9K_RX_FILTER_PHYRADAR; 2487 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2488 bits |= ATH9K_RX_FILTER_PHYERR; 2489 2490 return bits; 2491 } 2492 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2493 2494 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2495 { 2496 u32 phybits; 2497 2498 ENABLE_REGWRITE_BUFFER(ah); 2499 2500 if (AR_SREV_9462(ah)) 2501 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2502 2503 REG_WRITE(ah, AR_RX_FILTER, bits); 2504 2505 phybits = 0; 2506 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2507 phybits |= AR_PHY_ERR_RADAR; 2508 if (bits & ATH9K_RX_FILTER_PHYERR) 2509 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2510 REG_WRITE(ah, AR_PHY_ERR, phybits); 2511 2512 if (phybits) 2513 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2514 else 2515 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2516 2517 REGWRITE_BUFFER_FLUSH(ah); 2518 } 2519 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2520 2521 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2522 { 2523 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2524 return false; 2525 2526 ath9k_hw_init_pll(ah, NULL); 2527 return true; 2528 } 2529 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2530 2531 bool ath9k_hw_disable(struct ath_hw *ah) 2532 { 2533 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2534 return false; 2535 2536 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2537 return false; 2538 2539 ath9k_hw_init_pll(ah, NULL); 2540 return true; 2541 } 2542 EXPORT_SYMBOL(ath9k_hw_disable); 2543 2544 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2545 { 2546 enum eeprom_param gain_param; 2547 2548 if (IS_CHAN_2GHZ(chan)) 2549 gain_param = EEP_ANTENNA_GAIN_2G; 2550 else 2551 gain_param = EEP_ANTENNA_GAIN_5G; 2552 2553 return ah->eep_ops->get_eeprom(ah, gain_param); 2554 } 2555 2556 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan) 2557 { 2558 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2559 struct ieee80211_channel *channel; 2560 int chan_pwr, new_pwr, max_gain; 2561 int ant_gain, ant_reduction = 0; 2562 2563 if (!chan) 2564 return; 2565 2566 channel = chan->chan; 2567 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2568 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2569 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2570 2571 ant_gain = get_antenna_gain(ah, chan); 2572 if (ant_gain > max_gain) 2573 ant_reduction = ant_gain - max_gain; 2574 2575 ah->eep_ops->set_txpower(ah, chan, 2576 ath9k_regd_get_ctl(reg, chan), 2577 ant_reduction, new_pwr, false); 2578 } 2579 2580 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2581 { 2582 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2583 struct ath9k_channel *chan = ah->curchan; 2584 struct ieee80211_channel *channel = chan->chan; 2585 2586 reg->power_limit = min_t(int, limit, MAX_RATE_POWER); 2587 if (test) 2588 channel->max_power = MAX_RATE_POWER / 2; 2589 2590 ath9k_hw_apply_txpower(ah, chan); 2591 2592 if (test) 2593 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2594 } 2595 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2596 2597 void ath9k_hw_setopmode(struct ath_hw *ah) 2598 { 2599 ath9k_hw_set_operating_mode(ah, ah->opmode); 2600 } 2601 EXPORT_SYMBOL(ath9k_hw_setopmode); 2602 2603 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2604 { 2605 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2606 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2607 } 2608 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2609 2610 void ath9k_hw_write_associd(struct ath_hw *ah) 2611 { 2612 struct ath_common *common = ath9k_hw_common(ah); 2613 2614 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2615 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2616 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2617 } 2618 EXPORT_SYMBOL(ath9k_hw_write_associd); 2619 2620 #define ATH9K_MAX_TSF_READ 10 2621 2622 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2623 { 2624 u32 tsf_lower, tsf_upper1, tsf_upper2; 2625 int i; 2626 2627 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2628 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2629 tsf_lower = REG_READ(ah, AR_TSF_L32); 2630 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2631 if (tsf_upper2 == tsf_upper1) 2632 break; 2633 tsf_upper1 = tsf_upper2; 2634 } 2635 2636 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2637 2638 return (((u64)tsf_upper1 << 32) | tsf_lower); 2639 } 2640 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2641 2642 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2643 { 2644 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2645 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2646 } 2647 EXPORT_SYMBOL(ath9k_hw_settsf64); 2648 2649 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2650 { 2651 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2652 AH_TSF_WRITE_TIMEOUT)) 2653 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, 2654 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2655 2656 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2657 } 2658 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2659 2660 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2661 { 2662 if (setting) 2663 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2664 else 2665 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2666 } 2667 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2668 2669 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2670 { 2671 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2672 u32 macmode; 2673 2674 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2675 macmode = AR_2040_JOINED_RX_CLEAR; 2676 else 2677 macmode = 0; 2678 2679 REG_WRITE(ah, AR_2040_MODE, macmode); 2680 } 2681 2682 /* HW Generic timers configuration */ 2683 2684 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2685 { 2686 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2687 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2688 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2689 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2690 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2691 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2692 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2693 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2694 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2695 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2696 AR_NDP2_TIMER_MODE, 0x0002}, 2697 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2698 AR_NDP2_TIMER_MODE, 0x0004}, 2699 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2700 AR_NDP2_TIMER_MODE, 0x0008}, 2701 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2702 AR_NDP2_TIMER_MODE, 0x0010}, 2703 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2704 AR_NDP2_TIMER_MODE, 0x0020}, 2705 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2706 AR_NDP2_TIMER_MODE, 0x0040}, 2707 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2708 AR_NDP2_TIMER_MODE, 0x0080} 2709 }; 2710 2711 /* HW generic timer primitives */ 2712 2713 /* compute and clear index of rightmost 1 */ 2714 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2715 { 2716 u32 b; 2717 2718 b = *mask; 2719 b &= (0-b); 2720 *mask &= ~b; 2721 b *= debruijn32; 2722 b >>= 27; 2723 2724 return timer_table->gen_timer_index[b]; 2725 } 2726 2727 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2728 { 2729 return REG_READ(ah, AR_TSF_L32); 2730 } 2731 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2732 2733 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2734 void (*trigger)(void *), 2735 void (*overflow)(void *), 2736 void *arg, 2737 u8 timer_index) 2738 { 2739 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2740 struct ath_gen_timer *timer; 2741 2742 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2743 2744 if (timer == NULL) { 2745 ath_err(ath9k_hw_common(ah), 2746 "Failed to allocate memory for hw timer[%d]\n", 2747 timer_index); 2748 return NULL; 2749 } 2750 2751 /* allocate a hardware generic timer slot */ 2752 timer_table->timers[timer_index] = timer; 2753 timer->index = timer_index; 2754 timer->trigger = trigger; 2755 timer->overflow = overflow; 2756 timer->arg = arg; 2757 2758 return timer; 2759 } 2760 EXPORT_SYMBOL(ath_gen_timer_alloc); 2761 2762 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2763 struct ath_gen_timer *timer, 2764 u32 trig_timeout, 2765 u32 timer_period) 2766 { 2767 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2768 u32 tsf, timer_next; 2769 2770 BUG_ON(!timer_period); 2771 2772 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2773 2774 tsf = ath9k_hw_gettsf32(ah); 2775 2776 timer_next = tsf + trig_timeout; 2777 2778 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2779 "current tsf %x period %x timer_next %x\n", 2780 tsf, timer_period, timer_next); 2781 2782 /* 2783 * Program generic timer registers 2784 */ 2785 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2786 timer_next); 2787 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2788 timer_period); 2789 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2790 gen_tmr_configuration[timer->index].mode_mask); 2791 2792 if (AR_SREV_9462(ah)) { 2793 /* 2794 * Starting from AR9462, each generic timer can select which tsf 2795 * to use. But we still follow the old rule, 0 - 7 use tsf and 2796 * 8 - 15 use tsf2. 2797 */ 2798 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2799 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2800 (1 << timer->index)); 2801 else 2802 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2803 (1 << timer->index)); 2804 } 2805 2806 /* Enable both trigger and thresh interrupt masks */ 2807 REG_SET_BIT(ah, AR_IMR_S5, 2808 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2809 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2810 } 2811 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2812 2813 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2814 { 2815 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2816 2817 if ((timer->index < AR_FIRST_NDP_TIMER) || 2818 (timer->index >= ATH_MAX_GEN_TIMER)) { 2819 return; 2820 } 2821 2822 /* Clear generic timer enable bits. */ 2823 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2824 gen_tmr_configuration[timer->index].mode_mask); 2825 2826 /* Disable both trigger and thresh interrupt masks */ 2827 REG_CLR_BIT(ah, AR_IMR_S5, 2828 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2829 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2830 2831 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2832 } 2833 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2834 2835 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2836 { 2837 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2838 2839 /* free the hardware generic timer slot */ 2840 timer_table->timers[timer->index] = NULL; 2841 kfree(timer); 2842 } 2843 EXPORT_SYMBOL(ath_gen_timer_free); 2844 2845 /* 2846 * Generic Timer Interrupts handling 2847 */ 2848 void ath_gen_timer_isr(struct ath_hw *ah) 2849 { 2850 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2851 struct ath_gen_timer *timer; 2852 struct ath_common *common = ath9k_hw_common(ah); 2853 u32 trigger_mask, thresh_mask, index; 2854 2855 /* get hardware generic timer interrupt status */ 2856 trigger_mask = ah->intr_gen_timer_trigger; 2857 thresh_mask = ah->intr_gen_timer_thresh; 2858 trigger_mask &= timer_table->timer_mask.val; 2859 thresh_mask &= timer_table->timer_mask.val; 2860 2861 trigger_mask &= ~thresh_mask; 2862 2863 while (thresh_mask) { 2864 index = rightmost_index(timer_table, &thresh_mask); 2865 timer = timer_table->timers[index]; 2866 BUG_ON(!timer); 2867 ath_dbg(common, ATH_DBG_HWTIMER, 2868 "TSF overflow for Gen timer %d\n", index); 2869 timer->overflow(timer->arg); 2870 } 2871 2872 while (trigger_mask) { 2873 index = rightmost_index(timer_table, &trigger_mask); 2874 timer = timer_table->timers[index]; 2875 BUG_ON(!timer); 2876 ath_dbg(common, ATH_DBG_HWTIMER, 2877 "Gen timer[%d] trigger\n", index); 2878 timer->trigger(timer->arg); 2879 } 2880 } 2881 EXPORT_SYMBOL(ath_gen_timer_isr); 2882 2883 /********/ 2884 /* HTC */ 2885 /********/ 2886 2887 void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2888 { 2889 ah->htc_reset_init = true; 2890 } 2891 EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2892 2893 static struct { 2894 u32 version; 2895 const char * name; 2896 } ath_mac_bb_names[] = { 2897 /* Devices with external radios */ 2898 { AR_SREV_VERSION_5416_PCI, "5416" }, 2899 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2900 { AR_SREV_VERSION_9100, "9100" }, 2901 { AR_SREV_VERSION_9160, "9160" }, 2902 /* Single-chip solutions */ 2903 { AR_SREV_VERSION_9280, "9280" }, 2904 { AR_SREV_VERSION_9285, "9285" }, 2905 { AR_SREV_VERSION_9287, "9287" }, 2906 { AR_SREV_VERSION_9271, "9271" }, 2907 { AR_SREV_VERSION_9300, "9300" }, 2908 { AR_SREV_VERSION_9330, "9330" }, 2909 { AR_SREV_VERSION_9340, "9340" }, 2910 { AR_SREV_VERSION_9485, "9485" }, 2911 { AR_SREV_VERSION_9462, "9462" }, 2912 }; 2913 2914 /* For devices with external radios */ 2915 static struct { 2916 u16 version; 2917 const char * name; 2918 } ath_rf_names[] = { 2919 { 0, "5133" }, 2920 { AR_RAD5133_SREV_MAJOR, "5133" }, 2921 { AR_RAD5122_SREV_MAJOR, "5122" }, 2922 { AR_RAD2133_SREV_MAJOR, "2133" }, 2923 { AR_RAD2122_SREV_MAJOR, "2122" } 2924 }; 2925 2926 /* 2927 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2928 */ 2929 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2930 { 2931 int i; 2932 2933 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2934 if (ath_mac_bb_names[i].version == mac_bb_version) { 2935 return ath_mac_bb_names[i].name; 2936 } 2937 } 2938 2939 return "????"; 2940 } 2941 2942 /* 2943 * Return the RF name. "????" is returned if the RF is unknown. 2944 * Used for devices with external radios. 2945 */ 2946 static const char *ath9k_hw_rf_name(u16 rf_version) 2947 { 2948 int i; 2949 2950 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2951 if (ath_rf_names[i].version == rf_version) { 2952 return ath_rf_names[i].name; 2953 } 2954 } 2955 2956 return "????"; 2957 } 2958 2959 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2960 { 2961 int used; 2962 2963 /* chipsets >= AR9280 are single-chip */ 2964 if (AR_SREV_9280_20_OR_LATER(ah)) { 2965 used = snprintf(hw_name, len, 2966 "Atheros AR%s Rev:%x", 2967 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2968 ah->hw_version.macRev); 2969 } 2970 else { 2971 used = snprintf(hw_name, len, 2972 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2973 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2974 ah->hw_version.macRev, 2975 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2976 AR_RADIO_SREV_MAJOR)), 2977 ah->hw_version.phyRev); 2978 } 2979 2980 hw_name[used] = '\0'; 2981 } 2982 EXPORT_SYMBOL(ath9k_hw_name); 2983