1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 27 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 28 29 MODULE_AUTHOR("Atheros Communications"); 30 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 31 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 32 MODULE_LICENSE("Dual BSD/GPL"); 33 34 static int __init ath9k_init(void) 35 { 36 return 0; 37 } 38 module_init(ath9k_init); 39 40 static void __exit ath9k_exit(void) 41 { 42 return; 43 } 44 module_exit(ath9k_exit); 45 46 /* Private hardware callbacks */ 47 48 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 49 { 50 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 51 } 52 53 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 54 { 55 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 56 } 57 58 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 59 struct ath9k_channel *chan) 60 { 61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 62 } 63 64 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 65 { 66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 67 return; 68 69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 70 } 71 72 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 73 { 74 /* You will not have this callback if using the old ANI */ 75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 76 return; 77 78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 79 } 80 81 /********************/ 82 /* Helper Functions */ 83 /********************/ 84 85 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 86 { 87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 88 struct ath_common *common = ath9k_hw_common(ah); 89 unsigned int clockrate; 90 91 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 93 clockrate = 117; 94 else if (!ah->curchan) /* should really check for CCK instead */ 95 clockrate = ATH9K_CLOCK_RATE_CCK; 96 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 100 else 101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 102 103 if (conf_is_ht40(conf)) 104 clockrate *= 2; 105 106 if (ah->curchan) { 107 if (IS_CHAN_HALF_RATE(ah->curchan)) 108 clockrate /= 2; 109 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 110 clockrate /= 4; 111 } 112 113 common->clockrate = clockrate; 114 } 115 116 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 117 { 118 struct ath_common *common = ath9k_hw_common(ah); 119 120 return usecs * common->clockrate; 121 } 122 123 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 124 { 125 int i; 126 127 BUG_ON(timeout < AH_TIME_QUANTUM); 128 129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 130 if ((REG_READ(ah, reg) & mask) == val) 131 return true; 132 133 udelay(AH_TIME_QUANTUM); 134 } 135 136 ath_dbg(ath9k_hw_common(ah), ANY, 137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 138 timeout, reg, REG_READ(ah, reg), mask, val); 139 140 return false; 141 } 142 EXPORT_SYMBOL(ath9k_hw_wait); 143 144 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 145 int column, unsigned int *writecnt) 146 { 147 int r; 148 149 ENABLE_REGWRITE_BUFFER(ah); 150 for (r = 0; r < array->ia_rows; r++) { 151 REG_WRITE(ah, INI_RA(array, r, 0), 152 INI_RA(array, r, column)); 153 DO_DELAY(*writecnt); 154 } 155 REGWRITE_BUFFER_FLUSH(ah); 156 } 157 158 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 159 { 160 u32 retval; 161 int i; 162 163 for (i = 0, retval = 0; i < n; i++) { 164 retval = (retval << 1) | (val & 1); 165 val >>= 1; 166 } 167 return retval; 168 } 169 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 171 u8 phy, int kbps, 172 u32 frameLen, u16 rateix, 173 bool shortPreamble) 174 { 175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 176 177 if (kbps == 0) 178 return 0; 179 180 switch (phy) { 181 case WLAN_RC_PHY_CCK: 182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 183 if (shortPreamble) 184 phyTime >>= 1; 185 numBits = frameLen << 3; 186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 187 break; 188 case WLAN_RC_PHY_OFDM: 189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 191 numBits = OFDM_PLCP_BITS + (frameLen << 3); 192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 193 txTime = OFDM_SIFS_TIME_QUARTER 194 + OFDM_PREAMBLE_TIME_QUARTER 195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 196 } else if (ah->curchan && 197 IS_CHAN_HALF_RATE(ah->curchan)) { 198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 199 numBits = OFDM_PLCP_BITS + (frameLen << 3); 200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 201 txTime = OFDM_SIFS_TIME_HALF + 202 OFDM_PREAMBLE_TIME_HALF 203 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 204 } else { 205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 206 numBits = OFDM_PLCP_BITS + (frameLen << 3); 207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 209 + (numSymbols * OFDM_SYMBOL_TIME); 210 } 211 break; 212 default: 213 ath_err(ath9k_hw_common(ah), 214 "Unknown phy %u (rate ix %u)\n", phy, rateix); 215 txTime = 0; 216 break; 217 } 218 219 return txTime; 220 } 221 EXPORT_SYMBOL(ath9k_hw_computetxtime); 222 223 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 224 struct ath9k_channel *chan, 225 struct chan_centers *centers) 226 { 227 int8_t extoff; 228 229 if (!IS_CHAN_HT40(chan)) { 230 centers->ctl_center = centers->ext_center = 231 centers->synth_center = chan->channel; 232 return; 233 } 234 235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 236 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 237 centers->synth_center = 238 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 239 extoff = 1; 240 } else { 241 centers->synth_center = 242 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 243 extoff = -1; 244 } 245 246 centers->ctl_center = 247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 248 /* 25 MHz spacing is supported by hw but not on upper layers */ 249 centers->ext_center = 250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 251 } 252 253 /******************/ 254 /* Chip Revisions */ 255 /******************/ 256 257 static void ath9k_hw_read_revisions(struct ath_hw *ah) 258 { 259 u32 val; 260 261 switch (ah->hw_version.devid) { 262 case AR5416_AR9100_DEVID: 263 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 264 break; 265 case AR9300_DEVID_AR9330: 266 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 267 if (ah->get_mac_revision) { 268 ah->hw_version.macRev = ah->get_mac_revision(); 269 } else { 270 val = REG_READ(ah, AR_SREV); 271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 272 } 273 return; 274 case AR9300_DEVID_AR9340: 275 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 276 val = REG_READ(ah, AR_SREV); 277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 278 return; 279 } 280 281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 282 283 if (val == 0xFF) { 284 val = REG_READ(ah, AR_SREV); 285 ah->hw_version.macVersion = 286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 288 289 if (AR_SREV_9462(ah)) 290 ah->is_pciexpress = true; 291 else 292 ah->is_pciexpress = (val & 293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 294 } else { 295 if (!AR_SREV_9100(ah)) 296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 297 298 ah->hw_version.macRev = val & AR_SREV_REVISION; 299 300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 301 ah->is_pciexpress = true; 302 } 303 } 304 305 /************************************/ 306 /* HW Attach, Detach, Init Routines */ 307 /************************************/ 308 309 static void ath9k_hw_disablepcie(struct ath_hw *ah) 310 { 311 if (!AR_SREV_5416(ah)) 312 return; 313 314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 323 324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 325 } 326 327 static void ath9k_hw_aspm_init(struct ath_hw *ah) 328 { 329 struct ath_common *common = ath9k_hw_common(ah); 330 331 if (common->bus_ops->aspm_init) 332 common->bus_ops->aspm_init(common); 333 } 334 335 /* This should work for all families including legacy */ 336 static bool ath9k_hw_chip_test(struct ath_hw *ah) 337 { 338 struct ath_common *common = ath9k_hw_common(ah); 339 u32 regAddr[2] = { AR_STA_ID0 }; 340 u32 regHold[2]; 341 static const u32 patternData[4] = { 342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 343 }; 344 int i, j, loop_max; 345 346 if (!AR_SREV_9300_20_OR_LATER(ah)) { 347 loop_max = 2; 348 regAddr[1] = AR_PHY_BASE + (8 << 2); 349 } else 350 loop_max = 1; 351 352 for (i = 0; i < loop_max; i++) { 353 u32 addr = regAddr[i]; 354 u32 wrData, rdData; 355 356 regHold[i] = REG_READ(ah, addr); 357 for (j = 0; j < 0x100; j++) { 358 wrData = (j << 16) | j; 359 REG_WRITE(ah, addr, wrData); 360 rdData = REG_READ(ah, addr); 361 if (rdData != wrData) { 362 ath_err(common, 363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 364 addr, wrData, rdData); 365 return false; 366 } 367 } 368 for (j = 0; j < 4; j++) { 369 wrData = patternData[j]; 370 REG_WRITE(ah, addr, wrData); 371 rdData = REG_READ(ah, addr); 372 if (wrData != rdData) { 373 ath_err(common, 374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 375 addr, wrData, rdData); 376 return false; 377 } 378 } 379 REG_WRITE(ah, regAddr[i], regHold[i]); 380 } 381 udelay(100); 382 383 return true; 384 } 385 386 static void ath9k_hw_init_config(struct ath_hw *ah) 387 { 388 int i; 389 390 ah->config.dma_beacon_response_time = 2; 391 ah->config.sw_beacon_response_time = 10; 392 ah->config.additional_swba_backoff = 0; 393 ah->config.ack_6mb = 0x0; 394 ah->config.cwm_ignore_extcca = 0; 395 ah->config.pcie_clock_req = 0; 396 ah->config.pcie_waen = 0; 397 ah->config.analog_shiftreg = 1; 398 ah->config.enable_ani = true; 399 400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 401 ah->config.spurchans[i][0] = AR_NO_SPUR; 402 ah->config.spurchans[i][1] = AR_NO_SPUR; 403 } 404 405 /* PAPRD needs some more work to be enabled */ 406 ah->config.paprd_disable = 1; 407 408 ah->config.rx_intr_mitigation = true; 409 ah->config.pcieSerDesWrite = true; 410 411 /* 412 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 414 * This means we use it for all AR5416 devices, and the few 415 * minor PCI AR9280 devices out there. 416 * 417 * Serialization is required because these devices do not handle 418 * well the case of two concurrent reads/writes due to the latency 419 * involved. During one read/write another read/write can be issued 420 * on another CPU while the previous read/write may still be working 421 * on our hardware, if we hit this case the hardware poops in a loop. 422 * We prevent this by serializing reads and writes. 423 * 424 * This issue is not present on PCI-Express devices or pre-AR5416 425 * devices (legacy, 802.11abg). 426 */ 427 if (num_possible_cpus() > 1) 428 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 429 } 430 431 static void ath9k_hw_init_defaults(struct ath_hw *ah) 432 { 433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 434 435 regulatory->country_code = CTRY_DEFAULT; 436 regulatory->power_limit = MAX_RATE_POWER; 437 438 ah->hw_version.magic = AR5416_MAGIC; 439 ah->hw_version.subvendorid = 0; 440 441 ah->atim_window = 0; 442 ah->sta_id1_defaults = 443 AR_STA_ID1_CRPT_MIC_ENABLE | 444 AR_STA_ID1_MCAST_KSRCH; 445 if (AR_SREV_9100(ah)) 446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 447 ah->enable_32kHz_clock = DONT_USE_32KHZ; 448 ah->slottime = ATH9K_SLOT_TIME_9; 449 ah->globaltxtimeout = (u32) -1; 450 ah->power_mode = ATH9K_PM_UNDEFINED; 451 } 452 453 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 454 { 455 struct ath_common *common = ath9k_hw_common(ah); 456 u32 sum; 457 int i; 458 u16 eeval; 459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 460 461 sum = 0; 462 for (i = 0; i < 3; i++) { 463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 464 sum += eeval; 465 common->macaddr[2 * i] = eeval >> 8; 466 common->macaddr[2 * i + 1] = eeval & 0xff; 467 } 468 if (sum == 0 || sum == 0xffff * 3) 469 return -EADDRNOTAVAIL; 470 471 return 0; 472 } 473 474 static int ath9k_hw_post_init(struct ath_hw *ah) 475 { 476 struct ath_common *common = ath9k_hw_common(ah); 477 int ecode; 478 479 if (common->bus_ops->ath_bus_type != ATH_USB) { 480 if (!ath9k_hw_chip_test(ah)) 481 return -ENODEV; 482 } 483 484 if (!AR_SREV_9300_20_OR_LATER(ah)) { 485 ecode = ar9002_hw_rf_claim(ah); 486 if (ecode != 0) 487 return ecode; 488 } 489 490 ecode = ath9k_hw_eeprom_init(ah); 491 if (ecode != 0) 492 return ecode; 493 494 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 495 ah->eep_ops->get_eeprom_ver(ah), 496 ah->eep_ops->get_eeprom_rev(ah)); 497 498 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 499 if (ecode) { 500 ath_err(ath9k_hw_common(ah), 501 "Failed allocating banks for external radio\n"); 502 ath9k_hw_rf_free_ext_banks(ah); 503 return ecode; 504 } 505 506 if (ah->config.enable_ani) { 507 ath9k_hw_ani_setup(ah); 508 ath9k_hw_ani_init(ah); 509 } 510 511 return 0; 512 } 513 514 static void ath9k_hw_attach_ops(struct ath_hw *ah) 515 { 516 if (AR_SREV_9300_20_OR_LATER(ah)) 517 ar9003_hw_attach_ops(ah); 518 else 519 ar9002_hw_attach_ops(ah); 520 } 521 522 /* Called for all hardware families */ 523 static int __ath9k_hw_init(struct ath_hw *ah) 524 { 525 struct ath_common *common = ath9k_hw_common(ah); 526 int r = 0; 527 528 ath9k_hw_read_revisions(ah); 529 530 /* 531 * Read back AR_WA into a permanent copy and set bits 14 and 17. 532 * We need to do this to avoid RMW of this register. We cannot 533 * read the reg when chip is asleep. 534 */ 535 ah->WARegVal = REG_READ(ah, AR_WA); 536 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 537 AR_WA_ASPM_TIMER_BASED_DISABLE); 538 539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 540 ath_err(common, "Couldn't reset chip\n"); 541 return -EIO; 542 } 543 544 if (AR_SREV_9462(ah)) 545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 546 547 ath9k_hw_init_defaults(ah); 548 ath9k_hw_init_config(ah); 549 550 ath9k_hw_attach_ops(ah); 551 552 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 553 ath_err(common, "Couldn't wakeup chip\n"); 554 return -EIO; 555 } 556 557 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 558 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 559 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 560 !ah->is_pciexpress)) { 561 ah->config.serialize_regmode = 562 SER_REG_MODE_ON; 563 } else { 564 ah->config.serialize_regmode = 565 SER_REG_MODE_OFF; 566 } 567 } 568 569 ath_dbg(common, RESET, "serialize_regmode is %d\n", 570 ah->config.serialize_regmode); 571 572 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 573 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 574 else 575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 576 577 switch (ah->hw_version.macVersion) { 578 case AR_SREV_VERSION_5416_PCI: 579 case AR_SREV_VERSION_5416_PCIE: 580 case AR_SREV_VERSION_9160: 581 case AR_SREV_VERSION_9100: 582 case AR_SREV_VERSION_9280: 583 case AR_SREV_VERSION_9285: 584 case AR_SREV_VERSION_9287: 585 case AR_SREV_VERSION_9271: 586 case AR_SREV_VERSION_9300: 587 case AR_SREV_VERSION_9330: 588 case AR_SREV_VERSION_9485: 589 case AR_SREV_VERSION_9340: 590 case AR_SREV_VERSION_9462: 591 break; 592 default: 593 ath_err(common, 594 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 595 ah->hw_version.macVersion, ah->hw_version.macRev); 596 return -EOPNOTSUPP; 597 } 598 599 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 600 AR_SREV_9330(ah)) 601 ah->is_pciexpress = false; 602 603 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 604 ath9k_hw_init_cal_settings(ah); 605 606 ah->ani_function = ATH9K_ANI_ALL; 607 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 608 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 609 if (!AR_SREV_9300_20_OR_LATER(ah)) 610 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 611 612 /* disable ANI for 9340 */ 613 if (AR_SREV_9340(ah)) 614 ah->config.enable_ani = false; 615 616 ath9k_hw_init_mode_regs(ah); 617 618 if (!ah->is_pciexpress) 619 ath9k_hw_disablepcie(ah); 620 621 if (!AR_SREV_9300_20_OR_LATER(ah)) 622 ar9002_hw_cck_chan14_spread(ah); 623 624 r = ath9k_hw_post_init(ah); 625 if (r) 626 return r; 627 628 ath9k_hw_init_mode_gain_regs(ah); 629 r = ath9k_hw_fill_cap_info(ah); 630 if (r) 631 return r; 632 633 if (ah->is_pciexpress) 634 ath9k_hw_aspm_init(ah); 635 636 r = ath9k_hw_init_macaddr(ah); 637 if (r) { 638 ath_err(common, "Failed to initialize MAC address\n"); 639 return r; 640 } 641 642 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 643 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 644 else 645 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 646 647 if (AR_SREV_9330(ah)) 648 ah->bb_watchdog_timeout_ms = 85; 649 else 650 ah->bb_watchdog_timeout_ms = 25; 651 652 common->state = ATH_HW_INITIALIZED; 653 654 return 0; 655 } 656 657 int ath9k_hw_init(struct ath_hw *ah) 658 { 659 int ret; 660 struct ath_common *common = ath9k_hw_common(ah); 661 662 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 663 switch (ah->hw_version.devid) { 664 case AR5416_DEVID_PCI: 665 case AR5416_DEVID_PCIE: 666 case AR5416_AR9100_DEVID: 667 case AR9160_DEVID_PCI: 668 case AR9280_DEVID_PCI: 669 case AR9280_DEVID_PCIE: 670 case AR9285_DEVID_PCIE: 671 case AR9287_DEVID_PCI: 672 case AR9287_DEVID_PCIE: 673 case AR2427_DEVID_PCIE: 674 case AR9300_DEVID_PCIE: 675 case AR9300_DEVID_AR9485_PCIE: 676 case AR9300_DEVID_AR9330: 677 case AR9300_DEVID_AR9340: 678 case AR9300_DEVID_AR9580: 679 case AR9300_DEVID_AR9462: 680 break; 681 default: 682 if (common->bus_ops->ath_bus_type == ATH_USB) 683 break; 684 ath_err(common, "Hardware device ID 0x%04x not supported\n", 685 ah->hw_version.devid); 686 return -EOPNOTSUPP; 687 } 688 689 ret = __ath9k_hw_init(ah); 690 if (ret) { 691 ath_err(common, 692 "Unable to initialize hardware; initialization status: %d\n", 693 ret); 694 return ret; 695 } 696 697 return 0; 698 } 699 EXPORT_SYMBOL(ath9k_hw_init); 700 701 static void ath9k_hw_init_qos(struct ath_hw *ah) 702 { 703 ENABLE_REGWRITE_BUFFER(ah); 704 705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 707 708 REG_WRITE(ah, AR_QOS_NO_ACK, 709 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 710 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 711 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 712 713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 718 719 REGWRITE_BUFFER_FLUSH(ah); 720 } 721 722 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 723 { 724 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 725 udelay(100); 726 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 727 728 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 729 udelay(100); 730 731 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 732 } 733 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 734 735 static void ath9k_hw_init_pll(struct ath_hw *ah, 736 struct ath9k_channel *chan) 737 { 738 u32 pll; 739 740 if (AR_SREV_9485(ah)) { 741 742 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 744 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 746 AR_CH0_DPLL2_KD, 0x40); 747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 748 AR_CH0_DPLL2_KI, 0x4); 749 750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 751 AR_CH0_BB_DPLL1_REFDIV, 0x5); 752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 753 AR_CH0_BB_DPLL1_NINI, 0x58); 754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 755 AR_CH0_BB_DPLL1_NFRAC, 0x0); 756 757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 758 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 760 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 762 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 763 764 /* program BB PLL phase_shift to 0x6 */ 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 766 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 767 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 769 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 770 udelay(1000); 771 } else if (AR_SREV_9330(ah)) { 772 u32 ddr_dpll2, pll_control2, kd; 773 774 if (ah->is_clk_25mhz) { 775 ddr_dpll2 = 0x18e82f01; 776 pll_control2 = 0xe04a3d; 777 kd = 0x1d; 778 } else { 779 ddr_dpll2 = 0x19e82f01; 780 pll_control2 = 0x886666; 781 kd = 0x3d; 782 } 783 784 /* program DDR PLL ki and kd value */ 785 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 786 787 /* program DDR PLL phase_shift */ 788 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 789 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 790 791 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 792 udelay(1000); 793 794 /* program refdiv, nint, frac to RTC register */ 795 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 796 797 /* program BB PLL kd and ki value */ 798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 800 801 /* program BB PLL phase_shift */ 802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 803 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 804 } else if (AR_SREV_9340(ah)) { 805 u32 regval, pll2_divint, pll2_divfrac, refdiv; 806 807 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 808 udelay(1000); 809 810 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 811 udelay(100); 812 813 if (ah->is_clk_25mhz) { 814 pll2_divint = 0x54; 815 pll2_divfrac = 0x1eb85; 816 refdiv = 3; 817 } else { 818 pll2_divint = 88; 819 pll2_divfrac = 0; 820 refdiv = 5; 821 } 822 823 regval = REG_READ(ah, AR_PHY_PLL_MODE); 824 regval |= (0x1 << 16); 825 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 826 udelay(100); 827 828 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 829 (pll2_divint << 18) | pll2_divfrac); 830 udelay(100); 831 832 regval = REG_READ(ah, AR_PHY_PLL_MODE); 833 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 834 (0x4 << 26) | (0x18 << 19); 835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 836 REG_WRITE(ah, AR_PHY_PLL_MODE, 837 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 838 udelay(1000); 839 } 840 841 pll = ath9k_hw_compute_pll_control(ah, chan); 842 843 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 844 845 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 846 udelay(1000); 847 848 /* Switch the core clock for ar9271 to 117Mhz */ 849 if (AR_SREV_9271(ah)) { 850 udelay(500); 851 REG_WRITE(ah, 0x50040, 0x304); 852 } 853 854 udelay(RTC_PLL_SETTLE_DELAY); 855 856 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 857 858 if (AR_SREV_9340(ah)) { 859 if (ah->is_clk_25mhz) { 860 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 861 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 862 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 863 } else { 864 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 865 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 866 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 867 } 868 udelay(100); 869 } 870 } 871 872 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 873 enum nl80211_iftype opmode) 874 { 875 u32 sync_default = AR_INTR_SYNC_DEFAULT; 876 u32 imr_reg = AR_IMR_TXERR | 877 AR_IMR_TXURN | 878 AR_IMR_RXERR | 879 AR_IMR_RXORN | 880 AR_IMR_BCNMISC; 881 882 if (AR_SREV_9340(ah)) 883 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 884 885 if (AR_SREV_9300_20_OR_LATER(ah)) { 886 imr_reg |= AR_IMR_RXOK_HP; 887 if (ah->config.rx_intr_mitigation) 888 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 889 else 890 imr_reg |= AR_IMR_RXOK_LP; 891 892 } else { 893 if (ah->config.rx_intr_mitigation) 894 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 895 else 896 imr_reg |= AR_IMR_RXOK; 897 } 898 899 if (ah->config.tx_intr_mitigation) 900 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 901 else 902 imr_reg |= AR_IMR_TXOK; 903 904 if (opmode == NL80211_IFTYPE_AP) 905 imr_reg |= AR_IMR_MIB; 906 907 ENABLE_REGWRITE_BUFFER(ah); 908 909 REG_WRITE(ah, AR_IMR, imr_reg); 910 ah->imrs2_reg |= AR_IMR_S2_GTT; 911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 912 913 if (!AR_SREV_9100(ah)) { 914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 917 } 918 919 REGWRITE_BUFFER_FLUSH(ah); 920 921 if (AR_SREV_9300_20_OR_LATER(ah)) { 922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 926 } 927 } 928 929 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 930 { 931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 932 val = min(val, (u32) 0xFFFF); 933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 934 } 935 936 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 937 { 938 u32 val = ath9k_hw_mac_to_clks(ah, us); 939 val = min(val, (u32) 0xFFFF); 940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 941 } 942 943 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 944 { 945 u32 val = ath9k_hw_mac_to_clks(ah, us); 946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 948 } 949 950 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 951 { 952 u32 val = ath9k_hw_mac_to_clks(ah, us); 953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 955 } 956 957 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 958 { 959 if (tu > 0xFFFF) { 960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 961 tu); 962 ah->globaltxtimeout = (u32) -1; 963 return false; 964 } else { 965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 966 ah->globaltxtimeout = tu; 967 return true; 968 } 969 } 970 971 void ath9k_hw_init_global_settings(struct ath_hw *ah) 972 { 973 struct ath_common *common = ath9k_hw_common(ah); 974 struct ieee80211_conf *conf = &common->hw->conf; 975 const struct ath9k_channel *chan = ah->curchan; 976 int acktimeout, ctstimeout; 977 int slottime; 978 int sifstime; 979 int rx_lat = 0, tx_lat = 0, eifs = 0; 980 u32 reg; 981 982 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 983 ah->misc_mode); 984 985 if (!chan) 986 return; 987 988 if (ah->misc_mode != 0) 989 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 990 991 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 992 rx_lat = 41; 993 else 994 rx_lat = 37; 995 tx_lat = 54; 996 997 if (IS_CHAN_HALF_RATE(chan)) { 998 eifs = 175; 999 rx_lat *= 2; 1000 tx_lat *= 2; 1001 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1002 tx_lat += 11; 1003 1004 slottime = 13; 1005 sifstime = 32; 1006 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1007 eifs = 340; 1008 rx_lat = (rx_lat * 4) - 1; 1009 tx_lat *= 4; 1010 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1011 tx_lat += 22; 1012 1013 slottime = 21; 1014 sifstime = 64; 1015 } else { 1016 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1017 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1018 reg = AR_USEC_ASYNC_FIFO; 1019 } else { 1020 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1021 common->clockrate; 1022 reg = REG_READ(ah, AR_USEC); 1023 } 1024 rx_lat = MS(reg, AR_USEC_RX_LAT); 1025 tx_lat = MS(reg, AR_USEC_TX_LAT); 1026 1027 slottime = ah->slottime; 1028 if (IS_CHAN_5GHZ(chan)) 1029 sifstime = 16; 1030 else 1031 sifstime = 10; 1032 } 1033 1034 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1035 acktimeout = slottime + sifstime + 3 * ah->coverage_class; 1036 ctstimeout = acktimeout; 1037 1038 /* 1039 * Workaround for early ACK timeouts, add an offset to match the 1040 * initval's 64us ack timeout value. 1041 * This was initially only meant to work around an issue with delayed 1042 * BA frames in some implementations, but it has been found to fix ACK 1043 * timeout issues in other cases as well. 1044 */ 1045 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 1046 acktimeout += 64 - sifstime - ah->slottime; 1047 1048 ath9k_hw_set_sifs_time(ah, sifstime); 1049 ath9k_hw_setslottime(ah, slottime); 1050 ath9k_hw_set_ack_timeout(ah, acktimeout); 1051 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1052 if (ah->globaltxtimeout != (u32) -1) 1053 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1054 1055 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1056 REG_RMW(ah, AR_USEC, 1057 (common->clockrate - 1) | 1058 SM(rx_lat, AR_USEC_RX_LAT) | 1059 SM(tx_lat, AR_USEC_TX_LAT), 1060 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1061 1062 } 1063 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1064 1065 void ath9k_hw_deinit(struct ath_hw *ah) 1066 { 1067 struct ath_common *common = ath9k_hw_common(ah); 1068 1069 if (common->state < ATH_HW_INITIALIZED) 1070 goto free_hw; 1071 1072 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1073 1074 free_hw: 1075 ath9k_hw_rf_free_ext_banks(ah); 1076 } 1077 EXPORT_SYMBOL(ath9k_hw_deinit); 1078 1079 /*******/ 1080 /* INI */ 1081 /*******/ 1082 1083 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1084 { 1085 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1086 1087 if (IS_CHAN_B(chan)) 1088 ctl |= CTL_11B; 1089 else if (IS_CHAN_G(chan)) 1090 ctl |= CTL_11G; 1091 else 1092 ctl |= CTL_11A; 1093 1094 return ctl; 1095 } 1096 1097 /****************************************/ 1098 /* Reset and Channel Switching Routines */ 1099 /****************************************/ 1100 1101 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1102 { 1103 struct ath_common *common = ath9k_hw_common(ah); 1104 1105 ENABLE_REGWRITE_BUFFER(ah); 1106 1107 /* 1108 * set AHB_MODE not to do cacheline prefetches 1109 */ 1110 if (!AR_SREV_9300_20_OR_LATER(ah)) 1111 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1112 1113 /* 1114 * let mac dma reads be in 128 byte chunks 1115 */ 1116 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1117 1118 REGWRITE_BUFFER_FLUSH(ah); 1119 1120 /* 1121 * Restore TX Trigger Level to its pre-reset value. 1122 * The initial value depends on whether aggregation is enabled, and is 1123 * adjusted whenever underruns are detected. 1124 */ 1125 if (!AR_SREV_9300_20_OR_LATER(ah)) 1126 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1127 1128 ENABLE_REGWRITE_BUFFER(ah); 1129 1130 /* 1131 * let mac dma writes be in 128 byte chunks 1132 */ 1133 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1134 1135 /* 1136 * Setup receive FIFO threshold to hold off TX activities 1137 */ 1138 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1139 1140 if (AR_SREV_9300_20_OR_LATER(ah)) { 1141 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1142 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1143 1144 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1145 ah->caps.rx_status_len); 1146 } 1147 1148 /* 1149 * reduce the number of usable entries in PCU TXBUF to avoid 1150 * wrap around issues. 1151 */ 1152 if (AR_SREV_9285(ah)) { 1153 /* For AR9285 the number of Fifos are reduced to half. 1154 * So set the usable tx buf size also to half to 1155 * avoid data/delimiter underruns 1156 */ 1157 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1158 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1159 } else if (!AR_SREV_9271(ah)) { 1160 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1161 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1162 } 1163 1164 REGWRITE_BUFFER_FLUSH(ah); 1165 1166 if (AR_SREV_9300_20_OR_LATER(ah)) 1167 ath9k_hw_reset_txstatus_ring(ah); 1168 } 1169 1170 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1171 { 1172 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1173 u32 set = AR_STA_ID1_KSRCH_MODE; 1174 1175 switch (opmode) { 1176 case NL80211_IFTYPE_ADHOC: 1177 case NL80211_IFTYPE_MESH_POINT: 1178 set |= AR_STA_ID1_ADHOC; 1179 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1180 break; 1181 case NL80211_IFTYPE_AP: 1182 set |= AR_STA_ID1_STA_AP; 1183 /* fall through */ 1184 case NL80211_IFTYPE_STATION: 1185 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1186 break; 1187 default: 1188 if (!ah->is_monitoring) 1189 set = 0; 1190 break; 1191 } 1192 REG_RMW(ah, AR_STA_ID1, set, mask); 1193 } 1194 1195 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1196 u32 *coef_mantissa, u32 *coef_exponent) 1197 { 1198 u32 coef_exp, coef_man; 1199 1200 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1201 if ((coef_scaled >> coef_exp) & 0x1) 1202 break; 1203 1204 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1205 1206 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1207 1208 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1209 *coef_exponent = coef_exp - 16; 1210 } 1211 1212 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1213 { 1214 u32 rst_flags; 1215 u32 tmpReg; 1216 1217 if (AR_SREV_9100(ah)) { 1218 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1219 AR_RTC_DERIVED_CLK_PERIOD, 1); 1220 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1221 } 1222 1223 ENABLE_REGWRITE_BUFFER(ah); 1224 1225 if (AR_SREV_9300_20_OR_LATER(ah)) { 1226 REG_WRITE(ah, AR_WA, ah->WARegVal); 1227 udelay(10); 1228 } 1229 1230 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1231 AR_RTC_FORCE_WAKE_ON_INT); 1232 1233 if (AR_SREV_9100(ah)) { 1234 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1235 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1236 } else { 1237 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1238 if (tmpReg & 1239 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1240 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1241 u32 val; 1242 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1243 1244 val = AR_RC_HOSTIF; 1245 if (!AR_SREV_9300_20_OR_LATER(ah)) 1246 val |= AR_RC_AHB; 1247 REG_WRITE(ah, AR_RC, val); 1248 1249 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1250 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1251 1252 rst_flags = AR_RTC_RC_MAC_WARM; 1253 if (type == ATH9K_RESET_COLD) 1254 rst_flags |= AR_RTC_RC_MAC_COLD; 1255 } 1256 1257 if (AR_SREV_9330(ah)) { 1258 int npend = 0; 1259 int i; 1260 1261 /* AR9330 WAR: 1262 * call external reset function to reset WMAC if: 1263 * - doing a cold reset 1264 * - we have pending frames in the TX queues 1265 */ 1266 1267 for (i = 0; i < AR_NUM_QCU; i++) { 1268 npend = ath9k_hw_numtxpending(ah, i); 1269 if (npend) 1270 break; 1271 } 1272 1273 if (ah->external_reset && 1274 (npend || type == ATH9K_RESET_COLD)) { 1275 int reset_err = 0; 1276 1277 ath_dbg(ath9k_hw_common(ah), RESET, 1278 "reset MAC via external reset\n"); 1279 1280 reset_err = ah->external_reset(); 1281 if (reset_err) { 1282 ath_err(ath9k_hw_common(ah), 1283 "External reset failed, err=%d\n", 1284 reset_err); 1285 return false; 1286 } 1287 1288 REG_WRITE(ah, AR_RTC_RESET, 1); 1289 } 1290 } 1291 1292 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1293 1294 REGWRITE_BUFFER_FLUSH(ah); 1295 1296 udelay(50); 1297 1298 REG_WRITE(ah, AR_RTC_RC, 0); 1299 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1300 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1301 return false; 1302 } 1303 1304 if (!AR_SREV_9100(ah)) 1305 REG_WRITE(ah, AR_RC, 0); 1306 1307 if (AR_SREV_9100(ah)) 1308 udelay(50); 1309 1310 return true; 1311 } 1312 1313 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1314 { 1315 ENABLE_REGWRITE_BUFFER(ah); 1316 1317 if (AR_SREV_9300_20_OR_LATER(ah)) { 1318 REG_WRITE(ah, AR_WA, ah->WARegVal); 1319 udelay(10); 1320 } 1321 1322 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1323 AR_RTC_FORCE_WAKE_ON_INT); 1324 1325 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1326 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1327 1328 REG_WRITE(ah, AR_RTC_RESET, 0); 1329 1330 REGWRITE_BUFFER_FLUSH(ah); 1331 1332 if (!AR_SREV_9300_20_OR_LATER(ah)) 1333 udelay(2); 1334 1335 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1336 REG_WRITE(ah, AR_RC, 0); 1337 1338 REG_WRITE(ah, AR_RTC_RESET, 1); 1339 1340 if (!ath9k_hw_wait(ah, 1341 AR_RTC_STATUS, 1342 AR_RTC_STATUS_M, 1343 AR_RTC_STATUS_ON, 1344 AH_WAIT_TIMEOUT)) { 1345 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1346 return false; 1347 } 1348 1349 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1350 } 1351 1352 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1353 { 1354 bool ret = false; 1355 1356 if (AR_SREV_9300_20_OR_LATER(ah)) { 1357 REG_WRITE(ah, AR_WA, ah->WARegVal); 1358 udelay(10); 1359 } 1360 1361 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1362 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1363 1364 switch (type) { 1365 case ATH9K_RESET_POWER_ON: 1366 ret = ath9k_hw_set_reset_power_on(ah); 1367 break; 1368 case ATH9K_RESET_WARM: 1369 case ATH9K_RESET_COLD: 1370 ret = ath9k_hw_set_reset(ah, type); 1371 break; 1372 default: 1373 break; 1374 } 1375 1376 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 1377 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 1378 1379 return ret; 1380 } 1381 1382 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1383 struct ath9k_channel *chan) 1384 { 1385 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1386 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1387 return false; 1388 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1389 return false; 1390 1391 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1392 return false; 1393 1394 ah->chip_fullsleep = false; 1395 ath9k_hw_init_pll(ah, chan); 1396 ath9k_hw_set_rfmode(ah, chan); 1397 1398 return true; 1399 } 1400 1401 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1402 struct ath9k_channel *chan) 1403 { 1404 struct ath_common *common = ath9k_hw_common(ah); 1405 u32 qnum; 1406 int r; 1407 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1408 bool band_switch, mode_diff; 1409 u8 ini_reloaded; 1410 1411 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1412 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1413 CHANNEL_5GHZ)); 1414 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1415 1416 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1417 if (ath9k_hw_numtxpending(ah, qnum)) { 1418 ath_dbg(common, QUEUE, 1419 "Transmit frames pending on queue %d\n", qnum); 1420 return false; 1421 } 1422 } 1423 1424 if (!ath9k_hw_rfbus_req(ah)) { 1425 ath_err(common, "Could not kill baseband RX\n"); 1426 return false; 1427 } 1428 1429 if (edma && (band_switch || mode_diff)) { 1430 ath9k_hw_mark_phy_inactive(ah); 1431 udelay(5); 1432 1433 ath9k_hw_init_pll(ah, NULL); 1434 1435 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1436 ath_err(common, "Failed to do fast channel change\n"); 1437 return false; 1438 } 1439 } 1440 1441 ath9k_hw_set_channel_regs(ah, chan); 1442 1443 r = ath9k_hw_rf_set_freq(ah, chan); 1444 if (r) { 1445 ath_err(common, "Failed to set channel\n"); 1446 return false; 1447 } 1448 ath9k_hw_set_clockrate(ah); 1449 ath9k_hw_apply_txpower(ah, chan); 1450 ath9k_hw_rfbus_done(ah); 1451 1452 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1453 ath9k_hw_set_delta_slope(ah, chan); 1454 1455 ath9k_hw_spur_mitigate_freq(ah, chan); 1456 1457 if (edma && (band_switch || mode_diff)) { 1458 ah->ah_flags |= AH_FASTCC; 1459 if (band_switch || ini_reloaded) 1460 ah->eep_ops->set_board_values(ah, chan); 1461 1462 ath9k_hw_init_bb(ah, chan); 1463 1464 if (band_switch || ini_reloaded) 1465 ath9k_hw_init_cal(ah, chan); 1466 ah->ah_flags &= ~AH_FASTCC; 1467 } 1468 1469 return true; 1470 } 1471 1472 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1473 { 1474 u32 gpio_mask = ah->gpio_mask; 1475 int i; 1476 1477 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1478 if (!(gpio_mask & 1)) 1479 continue; 1480 1481 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1482 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1483 } 1484 } 1485 1486 bool ath9k_hw_check_alive(struct ath_hw *ah) 1487 { 1488 int count = 50; 1489 u32 reg; 1490 1491 if (AR_SREV_9285_12_OR_LATER(ah)) 1492 return true; 1493 1494 do { 1495 reg = REG_READ(ah, AR_OBS_BUS_1); 1496 1497 if ((reg & 0x7E7FFFEF) == 0x00702400) 1498 continue; 1499 1500 switch (reg & 0x7E000B00) { 1501 case 0x1E000000: 1502 case 0x52000B00: 1503 case 0x18000B00: 1504 continue; 1505 default: 1506 return true; 1507 } 1508 } while (count-- > 0); 1509 1510 return false; 1511 } 1512 EXPORT_SYMBOL(ath9k_hw_check_alive); 1513 1514 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1515 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1516 { 1517 struct ath_common *common = ath9k_hw_common(ah); 1518 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 1519 u32 saveLedState; 1520 struct ath9k_channel *curchan = ah->curchan; 1521 u32 saveDefAntenna; 1522 u32 macStaId1; 1523 u64 tsf = 0; 1524 int i, r; 1525 bool allow_fbs = false; 1526 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1527 bool save_fullsleep = ah->chip_fullsleep; 1528 1529 if (mci) { 1530 1531 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan)); 1532 1533 if (mci_hw->bt_state == MCI_BT_CAL_START) { 1534 u32 payload[4] = {0, 0, 0, 0}; 1535 1536 ath_dbg(common, MCI, "MCI stop rx for BT CAL\n"); 1537 1538 mci_hw->bt_state = MCI_BT_CAL; 1539 1540 /* 1541 * MCI FIX: disable mci interrupt here. This is to avoid 1542 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and 1543 * lead to mci_intr reentry. 1544 */ 1545 1546 ar9003_mci_disable_interrupt(ah); 1547 1548 ath_dbg(common, MCI, "send WLAN_CAL_GRANT\n"); 1549 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT); 1550 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 1551 16, true, false); 1552 1553 ath_dbg(common, MCI, "\nMCI BT is calibrating\n"); 1554 1555 /* Wait BT calibration to be completed for 25ms */ 1556 1557 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE, 1558 0, 25000)) 1559 ath_dbg(common, MCI, 1560 "MCI got BT_CAL_DONE\n"); 1561 else 1562 ath_dbg(common, MCI, 1563 "MCI ### BT cal takes to long, force bt_state to be bt_awake\n"); 1564 mci_hw->bt_state = MCI_BT_AWAKE; 1565 /* MCI FIX: enable mci interrupt here */ 1566 ar9003_mci_enable_interrupt(ah); 1567 1568 return true; 1569 } 1570 } 1571 1572 1573 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1574 return -EIO; 1575 1576 if (curchan && !ah->chip_fullsleep) 1577 ath9k_hw_getnf(ah, curchan); 1578 1579 ah->caldata = caldata; 1580 if (caldata && 1581 (chan->channel != caldata->channel || 1582 (chan->channelFlags & ~CHANNEL_CW_INT) != 1583 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1584 /* Operating channel changed, reset channel calibration data */ 1585 memset(caldata, 0, sizeof(*caldata)); 1586 ath9k_init_nfcal_hist_buffer(ah, chan); 1587 } 1588 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1589 1590 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1591 bChannelChange = false; 1592 1593 if (caldata && 1594 caldata->done_txiqcal_once && 1595 caldata->done_txclcal_once && 1596 caldata->rtt_hist.num_readings) 1597 allow_fbs = true; 1598 1599 if (bChannelChange && 1600 (ah->chip_fullsleep != true) && 1601 (ah->curchan != NULL) && 1602 (chan->channel != ah->curchan->channel) && 1603 (allow_fbs || 1604 ((chan->channelFlags & CHANNEL_ALL) == 1605 (ah->curchan->channelFlags & CHANNEL_ALL)))) { 1606 if (ath9k_hw_channel_change(ah, chan)) { 1607 ath9k_hw_loadnf(ah, ah->curchan); 1608 ath9k_hw_start_nfcal(ah, true); 1609 if (mci && mci_hw->ready) 1610 ar9003_mci_2g5g_switch(ah, true); 1611 1612 if (AR_SREV_9271(ah)) 1613 ar9002_hw_load_ani_reg(ah, chan); 1614 return 0; 1615 } 1616 } 1617 1618 if (mci) { 1619 ar9003_mci_disable_interrupt(ah); 1620 1621 if (mci_hw->ready && !save_fullsleep) { 1622 ar9003_mci_mute_bt(ah); 1623 udelay(20); 1624 REG_WRITE(ah, AR_BTCOEX_CTRL, 0); 1625 } 1626 1627 mci_hw->bt_state = MCI_BT_SLEEP; 1628 mci_hw->ready = false; 1629 } 1630 1631 1632 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1633 if (saveDefAntenna == 0) 1634 saveDefAntenna = 1; 1635 1636 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1637 1638 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1639 if (AR_SREV_9100(ah) || 1640 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1641 tsf = ath9k_hw_gettsf64(ah); 1642 1643 saveLedState = REG_READ(ah, AR_CFG_LED) & 1644 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1645 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1646 1647 ath9k_hw_mark_phy_inactive(ah); 1648 1649 ah->paprd_table_write_done = false; 1650 1651 /* Only required on the first reset */ 1652 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1653 REG_WRITE(ah, 1654 AR9271_RESET_POWER_DOWN_CONTROL, 1655 AR9271_RADIO_RF_RST); 1656 udelay(50); 1657 } 1658 1659 if (!ath9k_hw_chip_reset(ah, chan)) { 1660 ath_err(common, "Chip reset failed\n"); 1661 return -EINVAL; 1662 } 1663 1664 /* Only required on the first reset */ 1665 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1666 ah->htc_reset_init = false; 1667 REG_WRITE(ah, 1668 AR9271_RESET_POWER_DOWN_CONTROL, 1669 AR9271_GATE_MAC_CTL); 1670 udelay(50); 1671 } 1672 1673 /* Restore TSF */ 1674 if (tsf) 1675 ath9k_hw_settsf64(ah, tsf); 1676 1677 if (AR_SREV_9280_20_OR_LATER(ah)) 1678 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1679 1680 if (!AR_SREV_9300_20_OR_LATER(ah)) 1681 ar9002_hw_enable_async_fifo(ah); 1682 1683 r = ath9k_hw_process_ini(ah, chan); 1684 if (r) 1685 return r; 1686 1687 if (mci) 1688 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1689 1690 /* 1691 * Some AR91xx SoC devices frequently fail to accept TSF writes 1692 * right after the chip reset. When that happens, write a new 1693 * value after the initvals have been applied, with an offset 1694 * based on measured time difference 1695 */ 1696 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1697 tsf += 1500; 1698 ath9k_hw_settsf64(ah, tsf); 1699 } 1700 1701 /* Setup MFP options for CCMP */ 1702 if (AR_SREV_9280_20_OR_LATER(ah)) { 1703 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1704 * frames when constructing CCMP AAD. */ 1705 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1706 0xc7ff); 1707 ah->sw_mgmt_crypto = false; 1708 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1709 /* Disable hardware crypto for management frames */ 1710 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1711 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1712 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1713 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1714 ah->sw_mgmt_crypto = true; 1715 } else 1716 ah->sw_mgmt_crypto = true; 1717 1718 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1719 ath9k_hw_set_delta_slope(ah, chan); 1720 1721 ath9k_hw_spur_mitigate_freq(ah, chan); 1722 ah->eep_ops->set_board_values(ah, chan); 1723 1724 ENABLE_REGWRITE_BUFFER(ah); 1725 1726 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1727 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1728 | macStaId1 1729 | AR_STA_ID1_RTS_USE_DEF 1730 | (ah->config. 1731 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1732 | ah->sta_id1_defaults); 1733 ath_hw_setbssidmask(common); 1734 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1735 ath9k_hw_write_associd(ah); 1736 REG_WRITE(ah, AR_ISR, ~0); 1737 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1738 1739 REGWRITE_BUFFER_FLUSH(ah); 1740 1741 ath9k_hw_set_operating_mode(ah, ah->opmode); 1742 1743 r = ath9k_hw_rf_set_freq(ah, chan); 1744 if (r) 1745 return r; 1746 1747 ath9k_hw_set_clockrate(ah); 1748 1749 ENABLE_REGWRITE_BUFFER(ah); 1750 1751 for (i = 0; i < AR_NUM_DCU; i++) 1752 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1753 1754 REGWRITE_BUFFER_FLUSH(ah); 1755 1756 ah->intr_txqs = 0; 1757 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1758 ath9k_hw_resettxqueue(ah, i); 1759 1760 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1761 ath9k_hw_ani_cache_ini_regs(ah); 1762 ath9k_hw_init_qos(ah); 1763 1764 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1765 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1766 1767 ath9k_hw_init_global_settings(ah); 1768 1769 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1770 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1771 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1772 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1773 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1774 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1775 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1776 } 1777 1778 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1779 1780 ath9k_hw_set_dma(ah); 1781 1782 REG_WRITE(ah, AR_OBS, 8); 1783 1784 if (ah->config.rx_intr_mitigation) { 1785 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1786 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1787 } 1788 1789 if (ah->config.tx_intr_mitigation) { 1790 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1791 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1792 } 1793 1794 ath9k_hw_init_bb(ah, chan); 1795 1796 if (caldata) { 1797 caldata->done_txiqcal_once = false; 1798 caldata->done_txclcal_once = false; 1799 caldata->rtt_hist.num_readings = 0; 1800 } 1801 if (!ath9k_hw_init_cal(ah, chan)) 1802 return -EIO; 1803 1804 ath9k_hw_loadnf(ah, chan); 1805 ath9k_hw_start_nfcal(ah, true); 1806 1807 if (mci && mci_hw->ready) { 1808 1809 if (IS_CHAN_2GHZ(chan) && 1810 (mci_hw->bt_state == MCI_BT_SLEEP)) { 1811 1812 if (ar9003_mci_check_int(ah, 1813 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) || 1814 ar9003_mci_check_int(ah, 1815 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) { 1816 1817 /* 1818 * BT is sleeping. Check if BT wakes up during 1819 * WLAN calibration. If BT wakes up during 1820 * WLAN calibration, need to go through all 1821 * message exchanges again and recal. 1822 */ 1823 1824 ath_dbg(common, MCI, 1825 "MCI BT wakes up during WLAN calibration\n"); 1826 1827 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 1828 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | 1829 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE); 1830 ath_dbg(common, MCI, "MCI send REMOTE_RESET\n"); 1831 ar9003_mci_remote_reset(ah, true); 1832 ar9003_mci_send_sys_waking(ah, true); 1833 udelay(1); 1834 if (IS_CHAN_2GHZ(chan)) 1835 ar9003_mci_send_lna_transfer(ah, true); 1836 1837 mci_hw->bt_state = MCI_BT_AWAKE; 1838 1839 ath_dbg(common, MCI, "MCI re-cal\n"); 1840 1841 if (caldata) { 1842 caldata->done_txiqcal_once = false; 1843 caldata->done_txclcal_once = false; 1844 caldata->rtt_hist.num_readings = 0; 1845 } 1846 1847 if (!ath9k_hw_init_cal(ah, chan)) 1848 return -EIO; 1849 1850 } 1851 } 1852 ar9003_mci_enable_interrupt(ah); 1853 } 1854 1855 ENABLE_REGWRITE_BUFFER(ah); 1856 1857 ath9k_hw_restore_chainmask(ah); 1858 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1859 1860 REGWRITE_BUFFER_FLUSH(ah); 1861 1862 /* 1863 * For big endian systems turn on swapping for descriptors 1864 */ 1865 if (AR_SREV_9100(ah)) { 1866 u32 mask; 1867 mask = REG_READ(ah, AR_CFG); 1868 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1869 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1870 mask); 1871 } else { 1872 mask = 1873 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1874 REG_WRITE(ah, AR_CFG, mask); 1875 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1876 REG_READ(ah, AR_CFG)); 1877 } 1878 } else { 1879 if (common->bus_ops->ath_bus_type == ATH_USB) { 1880 /* Configure AR9271 target WLAN */ 1881 if (AR_SREV_9271(ah)) 1882 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1883 else 1884 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1885 } 1886 #ifdef __BIG_ENDIAN 1887 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1888 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1889 else 1890 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1891 #endif 1892 } 1893 1894 if (ah->btcoex_hw.enabled && 1895 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) 1896 ath9k_hw_btcoex_enable(ah); 1897 1898 if (mci && mci_hw->ready) { 1899 /* 1900 * check BT state again to make 1901 * sure it's not changed. 1902 */ 1903 1904 ar9003_mci_sync_bt_state(ah); 1905 ar9003_mci_2g5g_switch(ah, true); 1906 1907 if ((mci_hw->bt_state == MCI_BT_AWAKE) && 1908 (mci_hw->query_bt == true)) { 1909 mci_hw->need_flush_btinfo = true; 1910 } 1911 } 1912 1913 if (AR_SREV_9300_20_OR_LATER(ah)) { 1914 ar9003_hw_bb_watchdog_config(ah); 1915 1916 ar9003_hw_disable_phy_restart(ah); 1917 } 1918 1919 ath9k_hw_apply_gpio_override(ah); 1920 1921 return 0; 1922 } 1923 EXPORT_SYMBOL(ath9k_hw_reset); 1924 1925 /******************************/ 1926 /* Power Management (Chipset) */ 1927 /******************************/ 1928 1929 /* 1930 * Notify Power Mgt is disabled in self-generated frames. 1931 * If requested, force chip to sleep. 1932 */ 1933 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1934 { 1935 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1936 if (setChip) { 1937 if (AR_SREV_9462(ah)) { 1938 REG_WRITE(ah, AR_TIMER_MODE, 1939 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 1940 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, 1941 AR_NDP2_TIMER_MODE) & 0xFFFFFF00); 1942 REG_WRITE(ah, AR_SLP32_INC, 1943 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); 1944 /* xxx Required for WLAN only case ? */ 1945 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1946 udelay(100); 1947 } 1948 1949 /* 1950 * Clear the RTC force wake bit to allow the 1951 * mac to go to sleep. 1952 */ 1953 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1954 1955 if (AR_SREV_9462(ah)) 1956 udelay(100); 1957 1958 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1959 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1960 1961 /* Shutdown chip. Active low */ 1962 if (!AR_SREV_5416(ah) && 1963 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) { 1964 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 1965 udelay(2); 1966 } 1967 } 1968 1969 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1970 if (AR_SREV_9300_20_OR_LATER(ah)) 1971 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1972 } 1973 1974 /* 1975 * Notify Power Management is enabled in self-generating 1976 * frames. If request, set power mode of chip to 1977 * auto/normal. Duration in units of 128us (1/8 TU). 1978 */ 1979 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1980 { 1981 u32 val; 1982 1983 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1984 if (setChip) { 1985 struct ath9k_hw_capabilities *pCap = &ah->caps; 1986 1987 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1988 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1989 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1990 AR_RTC_FORCE_WAKE_ON_INT); 1991 } else { 1992 1993 /* When chip goes into network sleep, it could be waken 1994 * up by MCI_INT interrupt caused by BT's HW messages 1995 * (LNA_xxx, CONT_xxx) which chould be in a very fast 1996 * rate (~100us). This will cause chip to leave and 1997 * re-enter network sleep mode frequently, which in 1998 * consequence will have WLAN MCI HW to generate lots of 1999 * SYS_WAKING and SYS_SLEEPING messages which will make 2000 * BT CPU to busy to process. 2001 */ 2002 if (AR_SREV_9462(ah)) { 2003 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 2004 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 2005 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 2006 } 2007 /* 2008 * Clear the RTC force wake bit to allow the 2009 * mac to go to sleep. 2010 */ 2011 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2012 AR_RTC_FORCE_WAKE_EN); 2013 2014 if (AR_SREV_9462(ah)) 2015 udelay(30); 2016 } 2017 } 2018 2019 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2020 if (AR_SREV_9300_20_OR_LATER(ah)) 2021 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2022 } 2023 2024 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2025 { 2026 u32 val; 2027 int i; 2028 2029 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2030 if (AR_SREV_9300_20_OR_LATER(ah)) { 2031 REG_WRITE(ah, AR_WA, ah->WARegVal); 2032 udelay(10); 2033 } 2034 2035 if (setChip) { 2036 if ((REG_READ(ah, AR_RTC_STATUS) & 2037 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2038 if (ath9k_hw_set_reset_reg(ah, 2039 ATH9K_RESET_POWER_ON) != true) { 2040 return false; 2041 } 2042 if (!AR_SREV_9300_20_OR_LATER(ah)) 2043 ath9k_hw_init_pll(ah, NULL); 2044 } 2045 if (AR_SREV_9100(ah)) 2046 REG_SET_BIT(ah, AR_RTC_RESET, 2047 AR_RTC_RESET_EN); 2048 2049 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2050 AR_RTC_FORCE_WAKE_EN); 2051 udelay(50); 2052 2053 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2054 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2055 if (val == AR_RTC_STATUS_ON) 2056 break; 2057 udelay(50); 2058 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2059 AR_RTC_FORCE_WAKE_EN); 2060 } 2061 if (i == 0) { 2062 ath_err(ath9k_hw_common(ah), 2063 "Failed to wakeup in %uus\n", 2064 POWER_UP_TIME / 20); 2065 return false; 2066 } 2067 } 2068 2069 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2070 2071 return true; 2072 } 2073 2074 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2075 { 2076 struct ath_common *common = ath9k_hw_common(ah); 2077 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 2078 int status = true, setChip = true; 2079 static const char *modes[] = { 2080 "AWAKE", 2081 "FULL-SLEEP", 2082 "NETWORK SLEEP", 2083 "UNDEFINED" 2084 }; 2085 2086 if (ah->power_mode == mode) 2087 return status; 2088 2089 ath_dbg(common, RESET, "%s -> %s\n", 2090 modes[ah->power_mode], modes[mode]); 2091 2092 switch (mode) { 2093 case ATH9K_PM_AWAKE: 2094 status = ath9k_hw_set_power_awake(ah, setChip); 2095 2096 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2097 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2098 2099 break; 2100 case ATH9K_PM_FULL_SLEEP: 2101 2102 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) { 2103 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) && 2104 (mci->bt_state != MCI_BT_SLEEP) && 2105 !mci->halted_bt_gpm) { 2106 ath_dbg(common, MCI, 2107 "MCI halt BT GPM (full_sleep)\n"); 2108 ar9003_mci_send_coex_halt_bt_gpm(ah, 2109 true, true); 2110 } 2111 2112 mci->ready = false; 2113 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2114 } 2115 2116 ath9k_set_power_sleep(ah, setChip); 2117 ah->chip_fullsleep = true; 2118 break; 2119 case ATH9K_PM_NETWORK_SLEEP: 2120 2121 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2122 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2123 2124 ath9k_set_power_network_sleep(ah, setChip); 2125 break; 2126 default: 2127 ath_err(common, "Unknown power mode %u\n", mode); 2128 return false; 2129 } 2130 ah->power_mode = mode; 2131 2132 /* 2133 * XXX: If this warning never comes up after a while then 2134 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2135 * ath9k_hw_setpower() return type void. 2136 */ 2137 2138 if (!(ah->ah_flags & AH_UNPLUGGED)) 2139 ATH_DBG_WARN_ON_ONCE(!status); 2140 2141 return status; 2142 } 2143 EXPORT_SYMBOL(ath9k_hw_setpower); 2144 2145 /*******************/ 2146 /* Beacon Handling */ 2147 /*******************/ 2148 2149 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2150 { 2151 int flags = 0; 2152 2153 ENABLE_REGWRITE_BUFFER(ah); 2154 2155 switch (ah->opmode) { 2156 case NL80211_IFTYPE_ADHOC: 2157 case NL80211_IFTYPE_MESH_POINT: 2158 REG_SET_BIT(ah, AR_TXCFG, 2159 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2160 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2161 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2162 flags |= AR_NDP_TIMER_EN; 2163 case NL80211_IFTYPE_AP: 2164 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2165 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2166 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2167 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2168 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2169 flags |= 2170 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2171 break; 2172 default: 2173 ath_dbg(ath9k_hw_common(ah), BEACON, 2174 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2175 return; 2176 break; 2177 } 2178 2179 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2180 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2181 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2182 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2183 2184 REGWRITE_BUFFER_FLUSH(ah); 2185 2186 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2187 } 2188 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2189 2190 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2191 const struct ath9k_beacon_state *bs) 2192 { 2193 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2194 struct ath9k_hw_capabilities *pCap = &ah->caps; 2195 struct ath_common *common = ath9k_hw_common(ah); 2196 2197 ENABLE_REGWRITE_BUFFER(ah); 2198 2199 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2200 2201 REG_WRITE(ah, AR_BEACON_PERIOD, 2202 TU_TO_USEC(bs->bs_intval)); 2203 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2204 TU_TO_USEC(bs->bs_intval)); 2205 2206 REGWRITE_BUFFER_FLUSH(ah); 2207 2208 REG_RMW_FIELD(ah, AR_RSSI_THR, 2209 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2210 2211 beaconintval = bs->bs_intval; 2212 2213 if (bs->bs_sleepduration > beaconintval) 2214 beaconintval = bs->bs_sleepduration; 2215 2216 dtimperiod = bs->bs_dtimperiod; 2217 if (bs->bs_sleepduration > dtimperiod) 2218 dtimperiod = bs->bs_sleepduration; 2219 2220 if (beaconintval == dtimperiod) 2221 nextTbtt = bs->bs_nextdtim; 2222 else 2223 nextTbtt = bs->bs_nexttbtt; 2224 2225 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2226 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2227 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2228 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2229 2230 ENABLE_REGWRITE_BUFFER(ah); 2231 2232 REG_WRITE(ah, AR_NEXT_DTIM, 2233 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2234 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2235 2236 REG_WRITE(ah, AR_SLEEP1, 2237 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2238 | AR_SLEEP1_ASSUME_DTIM); 2239 2240 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2241 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2242 else 2243 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2244 2245 REG_WRITE(ah, AR_SLEEP2, 2246 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2247 2248 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2249 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2250 2251 REGWRITE_BUFFER_FLUSH(ah); 2252 2253 REG_SET_BIT(ah, AR_TIMER_MODE, 2254 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2255 AR_DTIM_TIMER_EN); 2256 2257 /* TSF Out of Range Threshold */ 2258 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2259 } 2260 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2261 2262 /*******************/ 2263 /* HW Capabilities */ 2264 /*******************/ 2265 2266 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2267 { 2268 eeprom_chainmask &= chip_chainmask; 2269 if (eeprom_chainmask) 2270 return eeprom_chainmask; 2271 else 2272 return chip_chainmask; 2273 } 2274 2275 /** 2276 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2277 * @ah: the atheros hardware data structure 2278 * 2279 * We enable DFS support upstream on chipsets which have passed a series 2280 * of tests. The testing requirements are going to be documented. Desired 2281 * test requirements are documented at: 2282 * 2283 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2284 * 2285 * Once a new chipset gets properly tested an individual commit can be used 2286 * to document the testing for DFS for that chipset. 2287 */ 2288 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2289 { 2290 2291 switch (ah->hw_version.macVersion) { 2292 /* AR9580 will likely be our first target to get testing on */ 2293 case AR_SREV_VERSION_9580: 2294 default: 2295 return false; 2296 } 2297 } 2298 2299 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2300 { 2301 struct ath9k_hw_capabilities *pCap = &ah->caps; 2302 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2303 struct ath_common *common = ath9k_hw_common(ah); 2304 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2305 unsigned int chip_chainmask; 2306 2307 u16 eeval; 2308 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2309 2310 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2311 regulatory->current_rd = eeval; 2312 2313 if (ah->opmode != NL80211_IFTYPE_AP && 2314 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2315 if (regulatory->current_rd == 0x64 || 2316 regulatory->current_rd == 0x65) 2317 regulatory->current_rd += 5; 2318 else if (regulatory->current_rd == 0x41) 2319 regulatory->current_rd = 0x43; 2320 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2321 regulatory->current_rd); 2322 } 2323 2324 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2325 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2326 ath_err(common, 2327 "no band has been marked as supported in EEPROM\n"); 2328 return -EINVAL; 2329 } 2330 2331 if (eeval & AR5416_OPFLAGS_11A) 2332 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2333 2334 if (eeval & AR5416_OPFLAGS_11G) 2335 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2336 2337 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2338 chip_chainmask = 1; 2339 else if (AR_SREV_9462(ah)) 2340 chip_chainmask = 3; 2341 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2342 chip_chainmask = 7; 2343 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2344 chip_chainmask = 3; 2345 else 2346 chip_chainmask = 7; 2347 2348 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2349 /* 2350 * For AR9271 we will temporarilly uses the rx chainmax as read from 2351 * the EEPROM. 2352 */ 2353 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2354 !(eeval & AR5416_OPFLAGS_11A) && 2355 !(AR_SREV_9271(ah))) 2356 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2357 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2358 else if (AR_SREV_9100(ah)) 2359 pCap->rx_chainmask = 0x7; 2360 else 2361 /* Use rx_chainmask from EEPROM. */ 2362 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2363 2364 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2365 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2366 ah->txchainmask = pCap->tx_chainmask; 2367 ah->rxchainmask = pCap->rx_chainmask; 2368 2369 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2370 2371 /* enable key search for every frame in an aggregate */ 2372 if (AR_SREV_9300_20_OR_LATER(ah)) 2373 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2374 2375 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2376 2377 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2378 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2379 else 2380 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2381 2382 if (AR_SREV_9271(ah)) 2383 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2384 else if (AR_DEVID_7010(ah)) 2385 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2386 else if (AR_SREV_9300_20_OR_LATER(ah)) 2387 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2388 else if (AR_SREV_9287_11_OR_LATER(ah)) 2389 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2390 else if (AR_SREV_9285_12_OR_LATER(ah)) 2391 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2392 else if (AR_SREV_9280_20_OR_LATER(ah)) 2393 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2394 else 2395 pCap->num_gpio_pins = AR_NUM_GPIO; 2396 2397 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2398 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2399 else 2400 pCap->rts_aggr_limit = (8 * 1024); 2401 2402 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2403 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2404 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2405 ah->rfkill_gpio = 2406 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2407 ah->rfkill_polarity = 2408 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2409 2410 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2411 } 2412 #endif 2413 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2414 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2415 else 2416 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2417 2418 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2419 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2420 else 2421 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2422 2423 if (common->btcoex_enabled) { 2424 if (AR_SREV_9462(ah)) 2425 btcoex_hw->scheme = ATH_BTCOEX_CFG_MCI; 2426 else if (AR_SREV_9300_20_OR_LATER(ah)) { 2427 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2428 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300; 2429 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300; 2430 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300; 2431 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 2432 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280; 2433 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280; 2434 2435 if (AR_SREV_9285(ah)) { 2436 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2437 btcoex_hw->btpriority_gpio = 2438 ATH_BTPRIORITY_GPIO_9285; 2439 } else { 2440 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2441 } 2442 } 2443 } else { 2444 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2445 } 2446 2447 if (AR_SREV_9300_20_OR_LATER(ah)) { 2448 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2449 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2450 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2451 2452 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2453 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2454 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2455 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2456 pCap->txs_len = sizeof(struct ar9003_txs); 2457 if (!ah->config.paprd_disable && 2458 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2459 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2460 } else { 2461 pCap->tx_desc_len = sizeof(struct ath_desc); 2462 if (AR_SREV_9280_20(ah)) 2463 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2464 } 2465 2466 if (AR_SREV_9300_20_OR_LATER(ah)) 2467 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2468 2469 if (AR_SREV_9300_20_OR_LATER(ah)) 2470 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2471 2472 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2473 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2474 2475 if (AR_SREV_9285(ah)) 2476 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2477 ant_div_ctl1 = 2478 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2479 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2480 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2481 } 2482 if (AR_SREV_9300_20_OR_LATER(ah)) { 2483 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2484 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2485 } 2486 2487 2488 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2489 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2490 /* 2491 * enable the diversity-combining algorithm only when 2492 * both enable_lna_div and enable_fast_div are set 2493 * Table for Diversity 2494 * ant_div_alt_lnaconf bit 0-1 2495 * ant_div_main_lnaconf bit 2-3 2496 * ant_div_alt_gaintb bit 4 2497 * ant_div_main_gaintb bit 5 2498 * enable_ant_div_lnadiv bit 6 2499 * enable_ant_fast_div bit 7 2500 */ 2501 if ((ant_div_ctl1 >> 0x6) == 0x3) 2502 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2503 } 2504 2505 if (AR_SREV_9485_10(ah)) { 2506 pCap->pcie_lcr_extsync_en = true; 2507 pCap->pcie_lcr_offset = 0x80; 2508 } 2509 2510 if (ath9k_hw_dfs_tested(ah)) 2511 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2512 2513 tx_chainmask = pCap->tx_chainmask; 2514 rx_chainmask = pCap->rx_chainmask; 2515 while (tx_chainmask || rx_chainmask) { 2516 if (tx_chainmask & BIT(0)) 2517 pCap->max_txchains++; 2518 if (rx_chainmask & BIT(0)) 2519 pCap->max_rxchains++; 2520 2521 tx_chainmask >>= 1; 2522 rx_chainmask >>= 1; 2523 } 2524 2525 if (AR_SREV_9300_20_OR_LATER(ah)) { 2526 ah->enabled_cals |= TX_IQ_CAL; 2527 if (AR_SREV_9485_OR_LATER(ah)) 2528 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2529 } 2530 if (AR_SREV_9462(ah)) 2531 pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI; 2532 2533 return 0; 2534 } 2535 2536 /****************************/ 2537 /* GPIO / RFKILL / Antennae */ 2538 /****************************/ 2539 2540 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2541 u32 gpio, u32 type) 2542 { 2543 int addr; 2544 u32 gpio_shift, tmp; 2545 2546 if (gpio > 11) 2547 addr = AR_GPIO_OUTPUT_MUX3; 2548 else if (gpio > 5) 2549 addr = AR_GPIO_OUTPUT_MUX2; 2550 else 2551 addr = AR_GPIO_OUTPUT_MUX1; 2552 2553 gpio_shift = (gpio % 6) * 5; 2554 2555 if (AR_SREV_9280_20_OR_LATER(ah) 2556 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2557 REG_RMW(ah, addr, (type << gpio_shift), 2558 (0x1f << gpio_shift)); 2559 } else { 2560 tmp = REG_READ(ah, addr); 2561 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2562 tmp &= ~(0x1f << gpio_shift); 2563 tmp |= (type << gpio_shift); 2564 REG_WRITE(ah, addr, tmp); 2565 } 2566 } 2567 2568 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2569 { 2570 u32 gpio_shift; 2571 2572 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2573 2574 if (AR_DEVID_7010(ah)) { 2575 gpio_shift = gpio; 2576 REG_RMW(ah, AR7010_GPIO_OE, 2577 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2578 (AR7010_GPIO_OE_MASK << gpio_shift)); 2579 return; 2580 } 2581 2582 gpio_shift = gpio << 1; 2583 REG_RMW(ah, 2584 AR_GPIO_OE_OUT, 2585 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2586 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2587 } 2588 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2589 2590 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2591 { 2592 #define MS_REG_READ(x, y) \ 2593 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2594 2595 if (gpio >= ah->caps.num_gpio_pins) 2596 return 0xffffffff; 2597 2598 if (AR_DEVID_7010(ah)) { 2599 u32 val; 2600 val = REG_READ(ah, AR7010_GPIO_IN); 2601 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2602 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2603 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2604 AR_GPIO_BIT(gpio)) != 0; 2605 else if (AR_SREV_9271(ah)) 2606 return MS_REG_READ(AR9271, gpio) != 0; 2607 else if (AR_SREV_9287_11_OR_LATER(ah)) 2608 return MS_REG_READ(AR9287, gpio) != 0; 2609 else if (AR_SREV_9285_12_OR_LATER(ah)) 2610 return MS_REG_READ(AR9285, gpio) != 0; 2611 else if (AR_SREV_9280_20_OR_LATER(ah)) 2612 return MS_REG_READ(AR928X, gpio) != 0; 2613 else 2614 return MS_REG_READ(AR, gpio) != 0; 2615 } 2616 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2617 2618 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2619 u32 ah_signal_type) 2620 { 2621 u32 gpio_shift; 2622 2623 if (AR_DEVID_7010(ah)) { 2624 gpio_shift = gpio; 2625 REG_RMW(ah, AR7010_GPIO_OE, 2626 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2627 (AR7010_GPIO_OE_MASK << gpio_shift)); 2628 return; 2629 } 2630 2631 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2632 gpio_shift = 2 * gpio; 2633 REG_RMW(ah, 2634 AR_GPIO_OE_OUT, 2635 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2636 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2637 } 2638 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2639 2640 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2641 { 2642 if (AR_DEVID_7010(ah)) { 2643 val = val ? 0 : 1; 2644 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2645 AR_GPIO_BIT(gpio)); 2646 return; 2647 } 2648 2649 if (AR_SREV_9271(ah)) 2650 val = ~val; 2651 2652 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2653 AR_GPIO_BIT(gpio)); 2654 } 2655 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2656 2657 u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2658 { 2659 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2660 } 2661 EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2662 2663 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2664 { 2665 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2666 } 2667 EXPORT_SYMBOL(ath9k_hw_setantenna); 2668 2669 /*********************/ 2670 /* General Operation */ 2671 /*********************/ 2672 2673 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2674 { 2675 u32 bits = REG_READ(ah, AR_RX_FILTER); 2676 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2677 2678 if (phybits & AR_PHY_ERR_RADAR) 2679 bits |= ATH9K_RX_FILTER_PHYRADAR; 2680 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2681 bits |= ATH9K_RX_FILTER_PHYERR; 2682 2683 return bits; 2684 } 2685 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2686 2687 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2688 { 2689 u32 phybits; 2690 2691 ENABLE_REGWRITE_BUFFER(ah); 2692 2693 if (AR_SREV_9462(ah)) 2694 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2695 2696 REG_WRITE(ah, AR_RX_FILTER, bits); 2697 2698 phybits = 0; 2699 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2700 phybits |= AR_PHY_ERR_RADAR; 2701 if (bits & ATH9K_RX_FILTER_PHYERR) 2702 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2703 REG_WRITE(ah, AR_PHY_ERR, phybits); 2704 2705 if (phybits) 2706 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2707 else 2708 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2709 2710 REGWRITE_BUFFER_FLUSH(ah); 2711 } 2712 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2713 2714 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2715 { 2716 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2717 return false; 2718 2719 ath9k_hw_init_pll(ah, NULL); 2720 return true; 2721 } 2722 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2723 2724 bool ath9k_hw_disable(struct ath_hw *ah) 2725 { 2726 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2727 return false; 2728 2729 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2730 return false; 2731 2732 ath9k_hw_init_pll(ah, NULL); 2733 return true; 2734 } 2735 EXPORT_SYMBOL(ath9k_hw_disable); 2736 2737 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2738 { 2739 enum eeprom_param gain_param; 2740 2741 if (IS_CHAN_2GHZ(chan)) 2742 gain_param = EEP_ANTENNA_GAIN_2G; 2743 else 2744 gain_param = EEP_ANTENNA_GAIN_5G; 2745 2746 return ah->eep_ops->get_eeprom(ah, gain_param); 2747 } 2748 2749 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan) 2750 { 2751 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2752 struct ieee80211_channel *channel; 2753 int chan_pwr, new_pwr, max_gain; 2754 int ant_gain, ant_reduction = 0; 2755 2756 if (!chan) 2757 return; 2758 2759 channel = chan->chan; 2760 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2761 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2762 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2763 2764 ant_gain = get_antenna_gain(ah, chan); 2765 if (ant_gain > max_gain) 2766 ant_reduction = ant_gain - max_gain; 2767 2768 ah->eep_ops->set_txpower(ah, chan, 2769 ath9k_regd_get_ctl(reg, chan), 2770 ant_reduction, new_pwr, false); 2771 } 2772 2773 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2774 { 2775 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2776 struct ath9k_channel *chan = ah->curchan; 2777 struct ieee80211_channel *channel = chan->chan; 2778 2779 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2780 if (test) 2781 channel->max_power = MAX_RATE_POWER / 2; 2782 2783 ath9k_hw_apply_txpower(ah, chan); 2784 2785 if (test) 2786 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2787 } 2788 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2789 2790 void ath9k_hw_setopmode(struct ath_hw *ah) 2791 { 2792 ath9k_hw_set_operating_mode(ah, ah->opmode); 2793 } 2794 EXPORT_SYMBOL(ath9k_hw_setopmode); 2795 2796 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2797 { 2798 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2799 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2800 } 2801 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2802 2803 void ath9k_hw_write_associd(struct ath_hw *ah) 2804 { 2805 struct ath_common *common = ath9k_hw_common(ah); 2806 2807 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2808 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2809 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2810 } 2811 EXPORT_SYMBOL(ath9k_hw_write_associd); 2812 2813 #define ATH9K_MAX_TSF_READ 10 2814 2815 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2816 { 2817 u32 tsf_lower, tsf_upper1, tsf_upper2; 2818 int i; 2819 2820 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2821 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2822 tsf_lower = REG_READ(ah, AR_TSF_L32); 2823 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2824 if (tsf_upper2 == tsf_upper1) 2825 break; 2826 tsf_upper1 = tsf_upper2; 2827 } 2828 2829 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2830 2831 return (((u64)tsf_upper1 << 32) | tsf_lower); 2832 } 2833 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2834 2835 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2836 { 2837 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2838 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2839 } 2840 EXPORT_SYMBOL(ath9k_hw_settsf64); 2841 2842 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2843 { 2844 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2845 AH_TSF_WRITE_TIMEOUT)) 2846 ath_dbg(ath9k_hw_common(ah), RESET, 2847 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2848 2849 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2850 } 2851 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2852 2853 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2854 { 2855 if (setting) 2856 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2857 else 2858 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2859 } 2860 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2861 2862 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2863 { 2864 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2865 u32 macmode; 2866 2867 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2868 macmode = AR_2040_JOINED_RX_CLEAR; 2869 else 2870 macmode = 0; 2871 2872 REG_WRITE(ah, AR_2040_MODE, macmode); 2873 } 2874 2875 /* HW Generic timers configuration */ 2876 2877 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2878 { 2879 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2880 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2881 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2882 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2883 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2884 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2885 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2886 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2887 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2888 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2889 AR_NDP2_TIMER_MODE, 0x0002}, 2890 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2891 AR_NDP2_TIMER_MODE, 0x0004}, 2892 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2893 AR_NDP2_TIMER_MODE, 0x0008}, 2894 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2895 AR_NDP2_TIMER_MODE, 0x0010}, 2896 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2897 AR_NDP2_TIMER_MODE, 0x0020}, 2898 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2899 AR_NDP2_TIMER_MODE, 0x0040}, 2900 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2901 AR_NDP2_TIMER_MODE, 0x0080} 2902 }; 2903 2904 /* HW generic timer primitives */ 2905 2906 /* compute and clear index of rightmost 1 */ 2907 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2908 { 2909 u32 b; 2910 2911 b = *mask; 2912 b &= (0-b); 2913 *mask &= ~b; 2914 b *= debruijn32; 2915 b >>= 27; 2916 2917 return timer_table->gen_timer_index[b]; 2918 } 2919 2920 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2921 { 2922 return REG_READ(ah, AR_TSF_L32); 2923 } 2924 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2925 2926 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2927 void (*trigger)(void *), 2928 void (*overflow)(void *), 2929 void *arg, 2930 u8 timer_index) 2931 { 2932 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2933 struct ath_gen_timer *timer; 2934 2935 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2936 2937 if (timer == NULL) { 2938 ath_err(ath9k_hw_common(ah), 2939 "Failed to allocate memory for hw timer[%d]\n", 2940 timer_index); 2941 return NULL; 2942 } 2943 2944 /* allocate a hardware generic timer slot */ 2945 timer_table->timers[timer_index] = timer; 2946 timer->index = timer_index; 2947 timer->trigger = trigger; 2948 timer->overflow = overflow; 2949 timer->arg = arg; 2950 2951 return timer; 2952 } 2953 EXPORT_SYMBOL(ath_gen_timer_alloc); 2954 2955 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2956 struct ath_gen_timer *timer, 2957 u32 trig_timeout, 2958 u32 timer_period) 2959 { 2960 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2961 u32 tsf, timer_next; 2962 2963 BUG_ON(!timer_period); 2964 2965 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2966 2967 tsf = ath9k_hw_gettsf32(ah); 2968 2969 timer_next = tsf + trig_timeout; 2970 2971 ath_dbg(ath9k_hw_common(ah), HWTIMER, 2972 "current tsf %x period %x timer_next %x\n", 2973 tsf, timer_period, timer_next); 2974 2975 /* 2976 * Program generic timer registers 2977 */ 2978 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2979 timer_next); 2980 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2981 timer_period); 2982 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2983 gen_tmr_configuration[timer->index].mode_mask); 2984 2985 if (AR_SREV_9462(ah)) { 2986 /* 2987 * Starting from AR9462, each generic timer can select which tsf 2988 * to use. But we still follow the old rule, 0 - 7 use tsf and 2989 * 8 - 15 use tsf2. 2990 */ 2991 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2992 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2993 (1 << timer->index)); 2994 else 2995 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2996 (1 << timer->index)); 2997 } 2998 2999 /* Enable both trigger and thresh interrupt masks */ 3000 REG_SET_BIT(ah, AR_IMR_S5, 3001 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3002 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3003 } 3004 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3005 3006 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3007 { 3008 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3009 3010 if ((timer->index < AR_FIRST_NDP_TIMER) || 3011 (timer->index >= ATH_MAX_GEN_TIMER)) { 3012 return; 3013 } 3014 3015 /* Clear generic timer enable bits. */ 3016 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3017 gen_tmr_configuration[timer->index].mode_mask); 3018 3019 /* Disable both trigger and thresh interrupt masks */ 3020 REG_CLR_BIT(ah, AR_IMR_S5, 3021 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3022 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3023 3024 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3025 } 3026 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3027 3028 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3029 { 3030 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3031 3032 /* free the hardware generic timer slot */ 3033 timer_table->timers[timer->index] = NULL; 3034 kfree(timer); 3035 } 3036 EXPORT_SYMBOL(ath_gen_timer_free); 3037 3038 /* 3039 * Generic Timer Interrupts handling 3040 */ 3041 void ath_gen_timer_isr(struct ath_hw *ah) 3042 { 3043 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3044 struct ath_gen_timer *timer; 3045 struct ath_common *common = ath9k_hw_common(ah); 3046 u32 trigger_mask, thresh_mask, index; 3047 3048 /* get hardware generic timer interrupt status */ 3049 trigger_mask = ah->intr_gen_timer_trigger; 3050 thresh_mask = ah->intr_gen_timer_thresh; 3051 trigger_mask &= timer_table->timer_mask.val; 3052 thresh_mask &= timer_table->timer_mask.val; 3053 3054 trigger_mask &= ~thresh_mask; 3055 3056 while (thresh_mask) { 3057 index = rightmost_index(timer_table, &thresh_mask); 3058 timer = timer_table->timers[index]; 3059 BUG_ON(!timer); 3060 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 3061 index); 3062 timer->overflow(timer->arg); 3063 } 3064 3065 while (trigger_mask) { 3066 index = rightmost_index(timer_table, &trigger_mask); 3067 timer = timer_table->timers[index]; 3068 BUG_ON(!timer); 3069 ath_dbg(common, HWTIMER, 3070 "Gen timer[%d] trigger\n", index); 3071 timer->trigger(timer->arg); 3072 } 3073 } 3074 EXPORT_SYMBOL(ath_gen_timer_isr); 3075 3076 /********/ 3077 /* HTC */ 3078 /********/ 3079 3080 void ath9k_hw_htc_resetinit(struct ath_hw *ah) 3081 { 3082 ah->htc_reset_init = true; 3083 } 3084 EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 3085 3086 static struct { 3087 u32 version; 3088 const char * name; 3089 } ath_mac_bb_names[] = { 3090 /* Devices with external radios */ 3091 { AR_SREV_VERSION_5416_PCI, "5416" }, 3092 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3093 { AR_SREV_VERSION_9100, "9100" }, 3094 { AR_SREV_VERSION_9160, "9160" }, 3095 /* Single-chip solutions */ 3096 { AR_SREV_VERSION_9280, "9280" }, 3097 { AR_SREV_VERSION_9285, "9285" }, 3098 { AR_SREV_VERSION_9287, "9287" }, 3099 { AR_SREV_VERSION_9271, "9271" }, 3100 { AR_SREV_VERSION_9300, "9300" }, 3101 { AR_SREV_VERSION_9330, "9330" }, 3102 { AR_SREV_VERSION_9340, "9340" }, 3103 { AR_SREV_VERSION_9485, "9485" }, 3104 { AR_SREV_VERSION_9462, "9462" }, 3105 }; 3106 3107 /* For devices with external radios */ 3108 static struct { 3109 u16 version; 3110 const char * name; 3111 } ath_rf_names[] = { 3112 { 0, "5133" }, 3113 { AR_RAD5133_SREV_MAJOR, "5133" }, 3114 { AR_RAD5122_SREV_MAJOR, "5122" }, 3115 { AR_RAD2133_SREV_MAJOR, "2133" }, 3116 { AR_RAD2122_SREV_MAJOR, "2122" } 3117 }; 3118 3119 /* 3120 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3121 */ 3122 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3123 { 3124 int i; 3125 3126 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3127 if (ath_mac_bb_names[i].version == mac_bb_version) { 3128 return ath_mac_bb_names[i].name; 3129 } 3130 } 3131 3132 return "????"; 3133 } 3134 3135 /* 3136 * Return the RF name. "????" is returned if the RF is unknown. 3137 * Used for devices with external radios. 3138 */ 3139 static const char *ath9k_hw_rf_name(u16 rf_version) 3140 { 3141 int i; 3142 3143 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3144 if (ath_rf_names[i].version == rf_version) { 3145 return ath_rf_names[i].name; 3146 } 3147 } 3148 3149 return "????"; 3150 } 3151 3152 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3153 { 3154 int used; 3155 3156 /* chipsets >= AR9280 are single-chip */ 3157 if (AR_SREV_9280_20_OR_LATER(ah)) { 3158 used = snprintf(hw_name, len, 3159 "Atheros AR%s Rev:%x", 3160 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3161 ah->hw_version.macRev); 3162 } 3163 else { 3164 used = snprintf(hw_name, len, 3165 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3166 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3167 ah->hw_version.macRev, 3168 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3169 AR_RADIO_SREV_MAJOR)), 3170 ah->hw_version.phyRev); 3171 } 3172 3173 hw_name[used] = '\0'; 3174 } 3175 EXPORT_SYMBOL(ath9k_hw_name); 3176