1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 #include "ar9003_mci.h" 27 #include "debug.h" 28 #include "ath9k.h" 29 30 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 31 32 MODULE_AUTHOR("Atheros Communications"); 33 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 34 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 35 MODULE_LICENSE("Dual BSD/GPL"); 36 37 static int __init ath9k_init(void) 38 { 39 return 0; 40 } 41 module_init(ath9k_init); 42 43 static void __exit ath9k_exit(void) 44 { 45 return; 46 } 47 module_exit(ath9k_exit); 48 49 /* Private hardware callbacks */ 50 51 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 52 { 53 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 54 } 55 56 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 57 { 58 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 59 } 60 61 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 62 struct ath9k_channel *chan) 63 { 64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 65 } 66 67 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 68 { 69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 70 return; 71 72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 73 } 74 75 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 76 { 77 /* You will not have this callback if using the old ANI */ 78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 79 return; 80 81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 82 } 83 84 /********************/ 85 /* Helper Functions */ 86 /********************/ 87 88 #ifdef CONFIG_ATH9K_DEBUGFS 89 90 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 91 { 92 struct ath_softc *sc = common->priv; 93 if (sync_cause) 94 sc->debug.stats.istats.sync_cause_all++; 95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 96 sc->debug.stats.istats.sync_rtc_irq++; 97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 98 sc->debug.stats.istats.sync_mac_irq++; 99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 100 sc->debug.stats.istats.eeprom_illegal_access++; 101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 102 sc->debug.stats.istats.apb_timeout++; 103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 104 sc->debug.stats.istats.pci_mode_conflict++; 105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 106 sc->debug.stats.istats.host1_fatal++; 107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 108 sc->debug.stats.istats.host1_perr++; 109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 110 sc->debug.stats.istats.trcv_fifo_perr++; 111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 112 sc->debug.stats.istats.radm_cpl_ep++; 113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 114 sc->debug.stats.istats.radm_cpl_dllp_abort++; 115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 116 sc->debug.stats.istats.radm_cpl_tlp_abort++; 117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 118 sc->debug.stats.istats.radm_cpl_ecrc_err++; 119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 120 sc->debug.stats.istats.radm_cpl_timeout++; 121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 122 sc->debug.stats.istats.local_timeout++; 123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 124 sc->debug.stats.istats.pm_access++; 125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 126 sc->debug.stats.istats.mac_awake++; 127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 128 sc->debug.stats.istats.mac_asleep++; 129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 130 sc->debug.stats.istats.mac_sleep_access++; 131 } 132 #endif 133 134 135 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 136 { 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 138 struct ath_common *common = ath9k_hw_common(ah); 139 unsigned int clockrate; 140 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 143 clockrate = 117; 144 else if (!ah->curchan) /* should really check for CCK instead */ 145 clockrate = ATH9K_CLOCK_RATE_CCK; 146 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 150 else 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 152 153 if (conf_is_ht40(conf)) 154 clockrate *= 2; 155 156 if (ah->curchan) { 157 if (IS_CHAN_HALF_RATE(ah->curchan)) 158 clockrate /= 2; 159 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 160 clockrate /= 4; 161 } 162 163 common->clockrate = clockrate; 164 } 165 166 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 167 { 168 struct ath_common *common = ath9k_hw_common(ah); 169 170 return usecs * common->clockrate; 171 } 172 173 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 174 { 175 int i; 176 177 BUG_ON(timeout < AH_TIME_QUANTUM); 178 179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 180 if ((REG_READ(ah, reg) & mask) == val) 181 return true; 182 183 udelay(AH_TIME_QUANTUM); 184 } 185 186 ath_dbg(ath9k_hw_common(ah), ANY, 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 188 timeout, reg, REG_READ(ah, reg), mask, val); 189 190 return false; 191 } 192 EXPORT_SYMBOL(ath9k_hw_wait); 193 194 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 195 int hw_delay) 196 { 197 if (IS_CHAN_B(chan)) 198 hw_delay = (4 * hw_delay) / 22; 199 else 200 hw_delay /= 10; 201 202 if (IS_CHAN_HALF_RATE(chan)) 203 hw_delay *= 2; 204 else if (IS_CHAN_QUARTER_RATE(chan)) 205 hw_delay *= 4; 206 207 udelay(hw_delay + BASE_ACTIVATE_DELAY); 208 } 209 210 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 211 int column, unsigned int *writecnt) 212 { 213 int r; 214 215 ENABLE_REGWRITE_BUFFER(ah); 216 for (r = 0; r < array->ia_rows; r++) { 217 REG_WRITE(ah, INI_RA(array, r, 0), 218 INI_RA(array, r, column)); 219 DO_DELAY(*writecnt); 220 } 221 REGWRITE_BUFFER_FLUSH(ah); 222 } 223 224 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 225 { 226 u32 retval; 227 int i; 228 229 for (i = 0, retval = 0; i < n; i++) { 230 retval = (retval << 1) | (val & 1); 231 val >>= 1; 232 } 233 return retval; 234 } 235 236 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 237 u8 phy, int kbps, 238 u32 frameLen, u16 rateix, 239 bool shortPreamble) 240 { 241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 242 243 if (kbps == 0) 244 return 0; 245 246 switch (phy) { 247 case WLAN_RC_PHY_CCK: 248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 249 if (shortPreamble) 250 phyTime >>= 1; 251 numBits = frameLen << 3; 252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 253 break; 254 case WLAN_RC_PHY_OFDM: 255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 257 numBits = OFDM_PLCP_BITS + (frameLen << 3); 258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 259 txTime = OFDM_SIFS_TIME_QUARTER 260 + OFDM_PREAMBLE_TIME_QUARTER 261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 262 } else if (ah->curchan && 263 IS_CHAN_HALF_RATE(ah->curchan)) { 264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 265 numBits = OFDM_PLCP_BITS + (frameLen << 3); 266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 267 txTime = OFDM_SIFS_TIME_HALF + 268 OFDM_PREAMBLE_TIME_HALF 269 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 270 } else { 271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 272 numBits = OFDM_PLCP_BITS + (frameLen << 3); 273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 275 + (numSymbols * OFDM_SYMBOL_TIME); 276 } 277 break; 278 default: 279 ath_err(ath9k_hw_common(ah), 280 "Unknown phy %u (rate ix %u)\n", phy, rateix); 281 txTime = 0; 282 break; 283 } 284 285 return txTime; 286 } 287 EXPORT_SYMBOL(ath9k_hw_computetxtime); 288 289 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 290 struct ath9k_channel *chan, 291 struct chan_centers *centers) 292 { 293 int8_t extoff; 294 295 if (!IS_CHAN_HT40(chan)) { 296 centers->ctl_center = centers->ext_center = 297 centers->synth_center = chan->channel; 298 return; 299 } 300 301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 302 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 303 centers->synth_center = 304 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 305 extoff = 1; 306 } else { 307 centers->synth_center = 308 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 309 extoff = -1; 310 } 311 312 centers->ctl_center = 313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 314 /* 25 MHz spacing is supported by hw but not on upper layers */ 315 centers->ext_center = 316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 317 } 318 319 /******************/ 320 /* Chip Revisions */ 321 /******************/ 322 323 static void ath9k_hw_read_revisions(struct ath_hw *ah) 324 { 325 u32 val; 326 327 switch (ah->hw_version.devid) { 328 case AR5416_AR9100_DEVID: 329 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 330 break; 331 case AR9300_DEVID_AR9330: 332 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 333 if (ah->get_mac_revision) { 334 ah->hw_version.macRev = ah->get_mac_revision(); 335 } else { 336 val = REG_READ(ah, AR_SREV); 337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 338 } 339 return; 340 case AR9300_DEVID_AR9340: 341 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 342 val = REG_READ(ah, AR_SREV); 343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 344 return; 345 } 346 347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 348 349 if (val == 0xFF) { 350 val = REG_READ(ah, AR_SREV); 351 ah->hw_version.macVersion = 352 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 353 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 354 355 if (AR_SREV_9462(ah)) 356 ah->is_pciexpress = true; 357 else 358 ah->is_pciexpress = (val & 359 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 360 } else { 361 if (!AR_SREV_9100(ah)) 362 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 363 364 ah->hw_version.macRev = val & AR_SREV_REVISION; 365 366 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 367 ah->is_pciexpress = true; 368 } 369 } 370 371 /************************************/ 372 /* HW Attach, Detach, Init Routines */ 373 /************************************/ 374 375 static void ath9k_hw_disablepcie(struct ath_hw *ah) 376 { 377 if (!AR_SREV_5416(ah)) 378 return; 379 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 381 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 382 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 388 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 389 390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 391 } 392 393 static void ath9k_hw_aspm_init(struct ath_hw *ah) 394 { 395 struct ath_common *common = ath9k_hw_common(ah); 396 397 if (common->bus_ops->aspm_init) 398 common->bus_ops->aspm_init(common); 399 } 400 401 /* This should work for all families including legacy */ 402 static bool ath9k_hw_chip_test(struct ath_hw *ah) 403 { 404 struct ath_common *common = ath9k_hw_common(ah); 405 u32 regAddr[2] = { AR_STA_ID0 }; 406 u32 regHold[2]; 407 static const u32 patternData[4] = { 408 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 409 }; 410 int i, j, loop_max; 411 412 if (!AR_SREV_9300_20_OR_LATER(ah)) { 413 loop_max = 2; 414 regAddr[1] = AR_PHY_BASE + (8 << 2); 415 } else 416 loop_max = 1; 417 418 for (i = 0; i < loop_max; i++) { 419 u32 addr = regAddr[i]; 420 u32 wrData, rdData; 421 422 regHold[i] = REG_READ(ah, addr); 423 for (j = 0; j < 0x100; j++) { 424 wrData = (j << 16) | j; 425 REG_WRITE(ah, addr, wrData); 426 rdData = REG_READ(ah, addr); 427 if (rdData != wrData) { 428 ath_err(common, 429 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 430 addr, wrData, rdData); 431 return false; 432 } 433 } 434 for (j = 0; j < 4; j++) { 435 wrData = patternData[j]; 436 REG_WRITE(ah, addr, wrData); 437 rdData = REG_READ(ah, addr); 438 if (wrData != rdData) { 439 ath_err(common, 440 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 441 addr, wrData, rdData); 442 return false; 443 } 444 } 445 REG_WRITE(ah, regAddr[i], regHold[i]); 446 } 447 udelay(100); 448 449 return true; 450 } 451 452 static void ath9k_hw_init_config(struct ath_hw *ah) 453 { 454 int i; 455 456 ah->config.dma_beacon_response_time = 1; 457 ah->config.sw_beacon_response_time = 6; 458 ah->config.additional_swba_backoff = 0; 459 ah->config.ack_6mb = 0x0; 460 ah->config.cwm_ignore_extcca = 0; 461 ah->config.pcie_clock_req = 0; 462 ah->config.pcie_waen = 0; 463 ah->config.analog_shiftreg = 1; 464 ah->config.enable_ani = true; 465 466 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 467 ah->config.spurchans[i][0] = AR_NO_SPUR; 468 ah->config.spurchans[i][1] = AR_NO_SPUR; 469 } 470 471 /* PAPRD needs some more work to be enabled */ 472 ah->config.paprd_disable = 1; 473 474 ah->config.rx_intr_mitigation = true; 475 ah->config.pcieSerDesWrite = true; 476 477 /* 478 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 479 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 480 * This means we use it for all AR5416 devices, and the few 481 * minor PCI AR9280 devices out there. 482 * 483 * Serialization is required because these devices do not handle 484 * well the case of two concurrent reads/writes due to the latency 485 * involved. During one read/write another read/write can be issued 486 * on another CPU while the previous read/write may still be working 487 * on our hardware, if we hit this case the hardware poops in a loop. 488 * We prevent this by serializing reads and writes. 489 * 490 * This issue is not present on PCI-Express devices or pre-AR5416 491 * devices (legacy, 802.11abg). 492 */ 493 if (num_possible_cpus() > 1) 494 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 495 } 496 497 static void ath9k_hw_init_defaults(struct ath_hw *ah) 498 { 499 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 500 501 regulatory->country_code = CTRY_DEFAULT; 502 regulatory->power_limit = MAX_RATE_POWER; 503 504 ah->hw_version.magic = AR5416_MAGIC; 505 ah->hw_version.subvendorid = 0; 506 507 ah->atim_window = 0; 508 ah->sta_id1_defaults = 509 AR_STA_ID1_CRPT_MIC_ENABLE | 510 AR_STA_ID1_MCAST_KSRCH; 511 if (AR_SREV_9100(ah)) 512 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 513 ah->slottime = ATH9K_SLOT_TIME_9; 514 ah->globaltxtimeout = (u32) -1; 515 ah->power_mode = ATH9K_PM_UNDEFINED; 516 ah->htc_reset_init = true; 517 } 518 519 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 520 { 521 struct ath_common *common = ath9k_hw_common(ah); 522 u32 sum; 523 int i; 524 u16 eeval; 525 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 526 527 sum = 0; 528 for (i = 0; i < 3; i++) { 529 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 530 sum += eeval; 531 common->macaddr[2 * i] = eeval >> 8; 532 common->macaddr[2 * i + 1] = eeval & 0xff; 533 } 534 if (sum == 0 || sum == 0xffff * 3) 535 return -EADDRNOTAVAIL; 536 537 return 0; 538 } 539 540 static int ath9k_hw_post_init(struct ath_hw *ah) 541 { 542 struct ath_common *common = ath9k_hw_common(ah); 543 int ecode; 544 545 if (common->bus_ops->ath_bus_type != ATH_USB) { 546 if (!ath9k_hw_chip_test(ah)) 547 return -ENODEV; 548 } 549 550 if (!AR_SREV_9300_20_OR_LATER(ah)) { 551 ecode = ar9002_hw_rf_claim(ah); 552 if (ecode != 0) 553 return ecode; 554 } 555 556 ecode = ath9k_hw_eeprom_init(ah); 557 if (ecode != 0) 558 return ecode; 559 560 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 561 ah->eep_ops->get_eeprom_ver(ah), 562 ah->eep_ops->get_eeprom_rev(ah)); 563 564 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 565 if (ecode) { 566 ath_err(ath9k_hw_common(ah), 567 "Failed allocating banks for external radio\n"); 568 ath9k_hw_rf_free_ext_banks(ah); 569 return ecode; 570 } 571 572 if (ah->config.enable_ani) { 573 ath9k_hw_ani_setup(ah); 574 ath9k_hw_ani_init(ah); 575 } 576 577 return 0; 578 } 579 580 static void ath9k_hw_attach_ops(struct ath_hw *ah) 581 { 582 if (AR_SREV_9300_20_OR_LATER(ah)) 583 ar9003_hw_attach_ops(ah); 584 else 585 ar9002_hw_attach_ops(ah); 586 } 587 588 /* Called for all hardware families */ 589 static int __ath9k_hw_init(struct ath_hw *ah) 590 { 591 struct ath_common *common = ath9k_hw_common(ah); 592 int r = 0; 593 594 ath9k_hw_read_revisions(ah); 595 596 /* 597 * Read back AR_WA into a permanent copy and set bits 14 and 17. 598 * We need to do this to avoid RMW of this register. We cannot 599 * read the reg when chip is asleep. 600 */ 601 ah->WARegVal = REG_READ(ah, AR_WA); 602 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 603 AR_WA_ASPM_TIMER_BASED_DISABLE); 604 605 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 606 ath_err(common, "Couldn't reset chip\n"); 607 return -EIO; 608 } 609 610 if (AR_SREV_9462(ah)) 611 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 612 613 ath9k_hw_init_defaults(ah); 614 ath9k_hw_init_config(ah); 615 616 ath9k_hw_attach_ops(ah); 617 618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 619 ath_err(common, "Couldn't wakeup chip\n"); 620 return -EIO; 621 } 622 623 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 624 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 625 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 626 !ah->is_pciexpress)) { 627 ah->config.serialize_regmode = 628 SER_REG_MODE_ON; 629 } else { 630 ah->config.serialize_regmode = 631 SER_REG_MODE_OFF; 632 } 633 } 634 635 ath_dbg(common, RESET, "serialize_regmode is %d\n", 636 ah->config.serialize_regmode); 637 638 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 639 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 640 else 641 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 642 643 switch (ah->hw_version.macVersion) { 644 case AR_SREV_VERSION_5416_PCI: 645 case AR_SREV_VERSION_5416_PCIE: 646 case AR_SREV_VERSION_9160: 647 case AR_SREV_VERSION_9100: 648 case AR_SREV_VERSION_9280: 649 case AR_SREV_VERSION_9285: 650 case AR_SREV_VERSION_9287: 651 case AR_SREV_VERSION_9271: 652 case AR_SREV_VERSION_9300: 653 case AR_SREV_VERSION_9330: 654 case AR_SREV_VERSION_9485: 655 case AR_SREV_VERSION_9340: 656 case AR_SREV_VERSION_9462: 657 break; 658 default: 659 ath_err(common, 660 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 661 ah->hw_version.macVersion, ah->hw_version.macRev); 662 return -EOPNOTSUPP; 663 } 664 665 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 666 AR_SREV_9330(ah)) 667 ah->is_pciexpress = false; 668 669 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 670 ath9k_hw_init_cal_settings(ah); 671 672 ah->ani_function = ATH9K_ANI_ALL; 673 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 674 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 675 if (!AR_SREV_9300_20_OR_LATER(ah)) 676 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 677 678 /* disable ANI for 9340 */ 679 if (AR_SREV_9340(ah)) 680 ah->config.enable_ani = false; 681 682 ath9k_hw_init_mode_regs(ah); 683 684 if (!ah->is_pciexpress) 685 ath9k_hw_disablepcie(ah); 686 687 r = ath9k_hw_post_init(ah); 688 if (r) 689 return r; 690 691 ath9k_hw_init_mode_gain_regs(ah); 692 r = ath9k_hw_fill_cap_info(ah); 693 if (r) 694 return r; 695 696 if (ah->is_pciexpress) 697 ath9k_hw_aspm_init(ah); 698 699 r = ath9k_hw_init_macaddr(ah); 700 if (r) { 701 ath_err(common, "Failed to initialize MAC address\n"); 702 return r; 703 } 704 705 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 706 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 707 else 708 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 709 710 if (AR_SREV_9330(ah)) 711 ah->bb_watchdog_timeout_ms = 85; 712 else 713 ah->bb_watchdog_timeout_ms = 25; 714 715 common->state = ATH_HW_INITIALIZED; 716 717 return 0; 718 } 719 720 int ath9k_hw_init(struct ath_hw *ah) 721 { 722 int ret; 723 struct ath_common *common = ath9k_hw_common(ah); 724 725 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 726 switch (ah->hw_version.devid) { 727 case AR5416_DEVID_PCI: 728 case AR5416_DEVID_PCIE: 729 case AR5416_AR9100_DEVID: 730 case AR9160_DEVID_PCI: 731 case AR9280_DEVID_PCI: 732 case AR9280_DEVID_PCIE: 733 case AR9285_DEVID_PCIE: 734 case AR9287_DEVID_PCI: 735 case AR9287_DEVID_PCIE: 736 case AR2427_DEVID_PCIE: 737 case AR9300_DEVID_PCIE: 738 case AR9300_DEVID_AR9485_PCIE: 739 case AR9300_DEVID_AR9330: 740 case AR9300_DEVID_AR9340: 741 case AR9300_DEVID_AR9580: 742 case AR9300_DEVID_AR9462: 743 break; 744 default: 745 if (common->bus_ops->ath_bus_type == ATH_USB) 746 break; 747 ath_err(common, "Hardware device ID 0x%04x not supported\n", 748 ah->hw_version.devid); 749 return -EOPNOTSUPP; 750 } 751 752 ret = __ath9k_hw_init(ah); 753 if (ret) { 754 ath_err(common, 755 "Unable to initialize hardware; initialization status: %d\n", 756 ret); 757 return ret; 758 } 759 760 return 0; 761 } 762 EXPORT_SYMBOL(ath9k_hw_init); 763 764 static void ath9k_hw_init_qos(struct ath_hw *ah) 765 { 766 ENABLE_REGWRITE_BUFFER(ah); 767 768 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 769 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 770 771 REG_WRITE(ah, AR_QOS_NO_ACK, 772 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 773 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 774 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 775 776 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 777 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 778 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 779 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 780 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 781 782 REGWRITE_BUFFER_FLUSH(ah); 783 } 784 785 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 786 { 787 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 788 udelay(100); 789 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 790 791 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 792 udelay(100); 793 794 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 795 } 796 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 797 798 static void ath9k_hw_init_pll(struct ath_hw *ah, 799 struct ath9k_channel *chan) 800 { 801 u32 pll; 802 803 if (AR_SREV_9485(ah)) { 804 805 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 806 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 807 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 808 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 809 AR_CH0_DPLL2_KD, 0x40); 810 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 811 AR_CH0_DPLL2_KI, 0x4); 812 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 814 AR_CH0_BB_DPLL1_REFDIV, 0x5); 815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 816 AR_CH0_BB_DPLL1_NINI, 0x58); 817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 818 AR_CH0_BB_DPLL1_NFRAC, 0x0); 819 820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 821 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 823 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 825 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 826 827 /* program BB PLL phase_shift to 0x6 */ 828 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 829 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 830 831 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 832 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 833 udelay(1000); 834 } else if (AR_SREV_9330(ah)) { 835 u32 ddr_dpll2, pll_control2, kd; 836 837 if (ah->is_clk_25mhz) { 838 ddr_dpll2 = 0x18e82f01; 839 pll_control2 = 0xe04a3d; 840 kd = 0x1d; 841 } else { 842 ddr_dpll2 = 0x19e82f01; 843 pll_control2 = 0x886666; 844 kd = 0x3d; 845 } 846 847 /* program DDR PLL ki and kd value */ 848 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 849 850 /* program DDR PLL phase_shift */ 851 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 852 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 853 854 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 855 udelay(1000); 856 857 /* program refdiv, nint, frac to RTC register */ 858 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 859 860 /* program BB PLL kd and ki value */ 861 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 862 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 863 864 /* program BB PLL phase_shift */ 865 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 866 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 867 } else if (AR_SREV_9340(ah)) { 868 u32 regval, pll2_divint, pll2_divfrac, refdiv; 869 870 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 871 udelay(1000); 872 873 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 874 udelay(100); 875 876 if (ah->is_clk_25mhz) { 877 pll2_divint = 0x54; 878 pll2_divfrac = 0x1eb85; 879 refdiv = 3; 880 } else { 881 pll2_divint = 88; 882 pll2_divfrac = 0; 883 refdiv = 5; 884 } 885 886 regval = REG_READ(ah, AR_PHY_PLL_MODE); 887 regval |= (0x1 << 16); 888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 889 udelay(100); 890 891 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 892 (pll2_divint << 18) | pll2_divfrac); 893 udelay(100); 894 895 regval = REG_READ(ah, AR_PHY_PLL_MODE); 896 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 897 (0x4 << 26) | (0x18 << 19); 898 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 899 REG_WRITE(ah, AR_PHY_PLL_MODE, 900 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 901 udelay(1000); 902 } 903 904 pll = ath9k_hw_compute_pll_control(ah, chan); 905 906 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 907 908 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 909 udelay(1000); 910 911 /* Switch the core clock for ar9271 to 117Mhz */ 912 if (AR_SREV_9271(ah)) { 913 udelay(500); 914 REG_WRITE(ah, 0x50040, 0x304); 915 } 916 917 udelay(RTC_PLL_SETTLE_DELAY); 918 919 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 920 921 if (AR_SREV_9340(ah)) { 922 if (ah->is_clk_25mhz) { 923 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 924 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 925 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 926 } else { 927 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 928 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 929 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 930 } 931 udelay(100); 932 } 933 } 934 935 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 936 enum nl80211_iftype opmode) 937 { 938 u32 sync_default = AR_INTR_SYNC_DEFAULT; 939 u32 imr_reg = AR_IMR_TXERR | 940 AR_IMR_TXURN | 941 AR_IMR_RXERR | 942 AR_IMR_RXORN | 943 AR_IMR_BCNMISC; 944 945 if (AR_SREV_9340(ah)) 946 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 947 948 if (AR_SREV_9300_20_OR_LATER(ah)) { 949 imr_reg |= AR_IMR_RXOK_HP; 950 if (ah->config.rx_intr_mitigation) 951 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 952 else 953 imr_reg |= AR_IMR_RXOK_LP; 954 955 } else { 956 if (ah->config.rx_intr_mitigation) 957 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 958 else 959 imr_reg |= AR_IMR_RXOK; 960 } 961 962 if (ah->config.tx_intr_mitigation) 963 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 964 else 965 imr_reg |= AR_IMR_TXOK; 966 967 if (opmode == NL80211_IFTYPE_AP) 968 imr_reg |= AR_IMR_MIB; 969 970 ENABLE_REGWRITE_BUFFER(ah); 971 972 REG_WRITE(ah, AR_IMR, imr_reg); 973 ah->imrs2_reg |= AR_IMR_S2_GTT; 974 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 975 976 if (!AR_SREV_9100(ah)) { 977 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 978 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 979 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 980 } 981 982 REGWRITE_BUFFER_FLUSH(ah); 983 984 if (AR_SREV_9300_20_OR_LATER(ah)) { 985 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 986 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 987 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 988 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 989 } 990 } 991 992 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 993 { 994 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 995 val = min(val, (u32) 0xFFFF); 996 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 997 } 998 999 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1000 { 1001 u32 val = ath9k_hw_mac_to_clks(ah, us); 1002 val = min(val, (u32) 0xFFFF); 1003 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1004 } 1005 1006 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1007 { 1008 u32 val = ath9k_hw_mac_to_clks(ah, us); 1009 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1010 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1011 } 1012 1013 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1014 { 1015 u32 val = ath9k_hw_mac_to_clks(ah, us); 1016 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1017 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1018 } 1019 1020 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1021 { 1022 if (tu > 0xFFFF) { 1023 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1024 tu); 1025 ah->globaltxtimeout = (u32) -1; 1026 return false; 1027 } else { 1028 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1029 ah->globaltxtimeout = tu; 1030 return true; 1031 } 1032 } 1033 1034 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1035 { 1036 struct ath_common *common = ath9k_hw_common(ah); 1037 struct ieee80211_conf *conf = &common->hw->conf; 1038 const struct ath9k_channel *chan = ah->curchan; 1039 int acktimeout, ctstimeout, ack_offset = 0; 1040 int slottime; 1041 int sifstime; 1042 int rx_lat = 0, tx_lat = 0, eifs = 0; 1043 u32 reg; 1044 1045 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1046 ah->misc_mode); 1047 1048 if (!chan) 1049 return; 1050 1051 if (ah->misc_mode != 0) 1052 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1053 1054 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1055 rx_lat = 41; 1056 else 1057 rx_lat = 37; 1058 tx_lat = 54; 1059 1060 if (IS_CHAN_5GHZ(chan)) 1061 sifstime = 16; 1062 else 1063 sifstime = 10; 1064 1065 if (IS_CHAN_HALF_RATE(chan)) { 1066 eifs = 175; 1067 rx_lat *= 2; 1068 tx_lat *= 2; 1069 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1070 tx_lat += 11; 1071 1072 sifstime *= 2; 1073 ack_offset = 16; 1074 slottime = 13; 1075 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1076 eifs = 340; 1077 rx_lat = (rx_lat * 4) - 1; 1078 tx_lat *= 4; 1079 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1080 tx_lat += 22; 1081 1082 sifstime *= 4; 1083 ack_offset = 32; 1084 slottime = 21; 1085 } else { 1086 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1087 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1088 reg = AR_USEC_ASYNC_FIFO; 1089 } else { 1090 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1091 common->clockrate; 1092 reg = REG_READ(ah, AR_USEC); 1093 } 1094 rx_lat = MS(reg, AR_USEC_RX_LAT); 1095 tx_lat = MS(reg, AR_USEC_TX_LAT); 1096 1097 slottime = ah->slottime; 1098 } 1099 1100 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1101 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset; 1102 ctstimeout = acktimeout; 1103 1104 /* 1105 * Workaround for early ACK timeouts, add an offset to match the 1106 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1107 * This was initially only meant to work around an issue with delayed 1108 * BA frames in some implementations, but it has been found to fix ACK 1109 * timeout issues in other cases as well. 1110 */ 1111 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ && 1112 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1113 acktimeout += 64 - sifstime - ah->slottime; 1114 ctstimeout += 48 - sifstime - ah->slottime; 1115 } 1116 1117 1118 ath9k_hw_set_sifs_time(ah, sifstime); 1119 ath9k_hw_setslottime(ah, slottime); 1120 ath9k_hw_set_ack_timeout(ah, acktimeout); 1121 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1122 if (ah->globaltxtimeout != (u32) -1) 1123 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1124 1125 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1126 REG_RMW(ah, AR_USEC, 1127 (common->clockrate - 1) | 1128 SM(rx_lat, AR_USEC_RX_LAT) | 1129 SM(tx_lat, AR_USEC_TX_LAT), 1130 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1131 1132 } 1133 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1134 1135 void ath9k_hw_deinit(struct ath_hw *ah) 1136 { 1137 struct ath_common *common = ath9k_hw_common(ah); 1138 1139 if (common->state < ATH_HW_INITIALIZED) 1140 goto free_hw; 1141 1142 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1143 1144 free_hw: 1145 ath9k_hw_rf_free_ext_banks(ah); 1146 } 1147 EXPORT_SYMBOL(ath9k_hw_deinit); 1148 1149 /*******/ 1150 /* INI */ 1151 /*******/ 1152 1153 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1154 { 1155 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1156 1157 if (IS_CHAN_B(chan)) 1158 ctl |= CTL_11B; 1159 else if (IS_CHAN_G(chan)) 1160 ctl |= CTL_11G; 1161 else 1162 ctl |= CTL_11A; 1163 1164 return ctl; 1165 } 1166 1167 /****************************************/ 1168 /* Reset and Channel Switching Routines */ 1169 /****************************************/ 1170 1171 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1172 { 1173 struct ath_common *common = ath9k_hw_common(ah); 1174 1175 ENABLE_REGWRITE_BUFFER(ah); 1176 1177 /* 1178 * set AHB_MODE not to do cacheline prefetches 1179 */ 1180 if (!AR_SREV_9300_20_OR_LATER(ah)) 1181 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1182 1183 /* 1184 * let mac dma reads be in 128 byte chunks 1185 */ 1186 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1187 1188 REGWRITE_BUFFER_FLUSH(ah); 1189 1190 /* 1191 * Restore TX Trigger Level to its pre-reset value. 1192 * The initial value depends on whether aggregation is enabled, and is 1193 * adjusted whenever underruns are detected. 1194 */ 1195 if (!AR_SREV_9300_20_OR_LATER(ah)) 1196 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1197 1198 ENABLE_REGWRITE_BUFFER(ah); 1199 1200 /* 1201 * let mac dma writes be in 128 byte chunks 1202 */ 1203 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1204 1205 /* 1206 * Setup receive FIFO threshold to hold off TX activities 1207 */ 1208 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1209 1210 if (AR_SREV_9300_20_OR_LATER(ah)) { 1211 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1212 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1213 1214 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1215 ah->caps.rx_status_len); 1216 } 1217 1218 /* 1219 * reduce the number of usable entries in PCU TXBUF to avoid 1220 * wrap around issues. 1221 */ 1222 if (AR_SREV_9285(ah)) { 1223 /* For AR9285 the number of Fifos are reduced to half. 1224 * So set the usable tx buf size also to half to 1225 * avoid data/delimiter underruns 1226 */ 1227 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1228 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1229 } else if (!AR_SREV_9271(ah)) { 1230 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1231 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1232 } 1233 1234 REGWRITE_BUFFER_FLUSH(ah); 1235 1236 if (AR_SREV_9300_20_OR_LATER(ah)) 1237 ath9k_hw_reset_txstatus_ring(ah); 1238 } 1239 1240 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1241 { 1242 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1243 u32 set = AR_STA_ID1_KSRCH_MODE; 1244 1245 switch (opmode) { 1246 case NL80211_IFTYPE_ADHOC: 1247 case NL80211_IFTYPE_MESH_POINT: 1248 set |= AR_STA_ID1_ADHOC; 1249 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1250 break; 1251 case NL80211_IFTYPE_AP: 1252 set |= AR_STA_ID1_STA_AP; 1253 /* fall through */ 1254 case NL80211_IFTYPE_STATION: 1255 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1256 break; 1257 default: 1258 if (!ah->is_monitoring) 1259 set = 0; 1260 break; 1261 } 1262 REG_RMW(ah, AR_STA_ID1, set, mask); 1263 } 1264 1265 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1266 u32 *coef_mantissa, u32 *coef_exponent) 1267 { 1268 u32 coef_exp, coef_man; 1269 1270 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1271 if ((coef_scaled >> coef_exp) & 0x1) 1272 break; 1273 1274 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1275 1276 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1277 1278 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1279 *coef_exponent = coef_exp - 16; 1280 } 1281 1282 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1283 { 1284 u32 rst_flags; 1285 u32 tmpReg; 1286 1287 if (AR_SREV_9100(ah)) { 1288 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1289 AR_RTC_DERIVED_CLK_PERIOD, 1); 1290 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1291 } 1292 1293 ENABLE_REGWRITE_BUFFER(ah); 1294 1295 if (AR_SREV_9300_20_OR_LATER(ah)) { 1296 REG_WRITE(ah, AR_WA, ah->WARegVal); 1297 udelay(10); 1298 } 1299 1300 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1301 AR_RTC_FORCE_WAKE_ON_INT); 1302 1303 if (AR_SREV_9100(ah)) { 1304 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1305 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1306 } else { 1307 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1308 if (tmpReg & 1309 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1310 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1311 u32 val; 1312 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1313 1314 val = AR_RC_HOSTIF; 1315 if (!AR_SREV_9300_20_OR_LATER(ah)) 1316 val |= AR_RC_AHB; 1317 REG_WRITE(ah, AR_RC, val); 1318 1319 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1320 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1321 1322 rst_flags = AR_RTC_RC_MAC_WARM; 1323 if (type == ATH9K_RESET_COLD) 1324 rst_flags |= AR_RTC_RC_MAC_COLD; 1325 } 1326 1327 if (AR_SREV_9330(ah)) { 1328 int npend = 0; 1329 int i; 1330 1331 /* AR9330 WAR: 1332 * call external reset function to reset WMAC if: 1333 * - doing a cold reset 1334 * - we have pending frames in the TX queues 1335 */ 1336 1337 for (i = 0; i < AR_NUM_QCU; i++) { 1338 npend = ath9k_hw_numtxpending(ah, i); 1339 if (npend) 1340 break; 1341 } 1342 1343 if (ah->external_reset && 1344 (npend || type == ATH9K_RESET_COLD)) { 1345 int reset_err = 0; 1346 1347 ath_dbg(ath9k_hw_common(ah), RESET, 1348 "reset MAC via external reset\n"); 1349 1350 reset_err = ah->external_reset(); 1351 if (reset_err) { 1352 ath_err(ath9k_hw_common(ah), 1353 "External reset failed, err=%d\n", 1354 reset_err); 1355 return false; 1356 } 1357 1358 REG_WRITE(ah, AR_RTC_RESET, 1); 1359 } 1360 } 1361 1362 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1363 1364 REGWRITE_BUFFER_FLUSH(ah); 1365 1366 udelay(50); 1367 1368 REG_WRITE(ah, AR_RTC_RC, 0); 1369 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1371 return false; 1372 } 1373 1374 if (!AR_SREV_9100(ah)) 1375 REG_WRITE(ah, AR_RC, 0); 1376 1377 if (AR_SREV_9100(ah)) 1378 udelay(50); 1379 1380 return true; 1381 } 1382 1383 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1384 { 1385 ENABLE_REGWRITE_BUFFER(ah); 1386 1387 if (AR_SREV_9300_20_OR_LATER(ah)) { 1388 REG_WRITE(ah, AR_WA, ah->WARegVal); 1389 udelay(10); 1390 } 1391 1392 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1393 AR_RTC_FORCE_WAKE_ON_INT); 1394 1395 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1396 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1397 1398 REG_WRITE(ah, AR_RTC_RESET, 0); 1399 1400 REGWRITE_BUFFER_FLUSH(ah); 1401 1402 if (!AR_SREV_9300_20_OR_LATER(ah)) 1403 udelay(2); 1404 1405 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1406 REG_WRITE(ah, AR_RC, 0); 1407 1408 REG_WRITE(ah, AR_RTC_RESET, 1); 1409 1410 if (!ath9k_hw_wait(ah, 1411 AR_RTC_STATUS, 1412 AR_RTC_STATUS_M, 1413 AR_RTC_STATUS_ON, 1414 AH_WAIT_TIMEOUT)) { 1415 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1416 return false; 1417 } 1418 1419 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1420 } 1421 1422 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1423 { 1424 bool ret = false; 1425 1426 if (AR_SREV_9300_20_OR_LATER(ah)) { 1427 REG_WRITE(ah, AR_WA, ah->WARegVal); 1428 udelay(10); 1429 } 1430 1431 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1432 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1433 1434 switch (type) { 1435 case ATH9K_RESET_POWER_ON: 1436 ret = ath9k_hw_set_reset_power_on(ah); 1437 break; 1438 case ATH9K_RESET_WARM: 1439 case ATH9K_RESET_COLD: 1440 ret = ath9k_hw_set_reset(ah, type); 1441 break; 1442 default: 1443 break; 1444 } 1445 1446 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 1447 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 1448 1449 return ret; 1450 } 1451 1452 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1453 struct ath9k_channel *chan) 1454 { 1455 int reset_type = ATH9K_RESET_WARM; 1456 1457 if (AR_SREV_9280(ah)) { 1458 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1459 reset_type = ATH9K_RESET_POWER_ON; 1460 else 1461 reset_type = ATH9K_RESET_COLD; 1462 } 1463 1464 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1465 return false; 1466 1467 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1468 return false; 1469 1470 ah->chip_fullsleep = false; 1471 ath9k_hw_init_pll(ah, chan); 1472 ath9k_hw_set_rfmode(ah, chan); 1473 1474 return true; 1475 } 1476 1477 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1478 struct ath9k_channel *chan) 1479 { 1480 struct ath_common *common = ath9k_hw_common(ah); 1481 u32 qnum; 1482 int r; 1483 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1484 bool band_switch, mode_diff; 1485 u8 ini_reloaded; 1486 1487 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1488 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1489 CHANNEL_5GHZ)); 1490 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1491 1492 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1493 if (ath9k_hw_numtxpending(ah, qnum)) { 1494 ath_dbg(common, QUEUE, 1495 "Transmit frames pending on queue %d\n", qnum); 1496 return false; 1497 } 1498 } 1499 1500 if (!ath9k_hw_rfbus_req(ah)) { 1501 ath_err(common, "Could not kill baseband RX\n"); 1502 return false; 1503 } 1504 1505 if (edma && (band_switch || mode_diff)) { 1506 ath9k_hw_mark_phy_inactive(ah); 1507 udelay(5); 1508 1509 ath9k_hw_init_pll(ah, NULL); 1510 1511 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1512 ath_err(common, "Failed to do fast channel change\n"); 1513 return false; 1514 } 1515 } 1516 1517 ath9k_hw_set_channel_regs(ah, chan); 1518 1519 r = ath9k_hw_rf_set_freq(ah, chan); 1520 if (r) { 1521 ath_err(common, "Failed to set channel\n"); 1522 return false; 1523 } 1524 ath9k_hw_set_clockrate(ah); 1525 ath9k_hw_apply_txpower(ah, chan, false); 1526 ath9k_hw_rfbus_done(ah); 1527 1528 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1529 ath9k_hw_set_delta_slope(ah, chan); 1530 1531 ath9k_hw_spur_mitigate_freq(ah, chan); 1532 1533 if (edma && (band_switch || mode_diff)) { 1534 ah->ah_flags |= AH_FASTCC; 1535 if (band_switch || ini_reloaded) 1536 ah->eep_ops->set_board_values(ah, chan); 1537 1538 ath9k_hw_init_bb(ah, chan); 1539 1540 if (band_switch || ini_reloaded) 1541 ath9k_hw_init_cal(ah, chan); 1542 ah->ah_flags &= ~AH_FASTCC; 1543 } 1544 1545 return true; 1546 } 1547 1548 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1549 { 1550 u32 gpio_mask = ah->gpio_mask; 1551 int i; 1552 1553 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1554 if (!(gpio_mask & 1)) 1555 continue; 1556 1557 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1558 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1559 } 1560 } 1561 1562 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1563 int *hang_state, int *hang_pos) 1564 { 1565 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1566 u32 chain_state, dcs_pos, i; 1567 1568 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1569 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1570 for (i = 0; i < 3; i++) { 1571 if (chain_state == dcu_chain_state[i]) { 1572 *hang_state = chain_state; 1573 *hang_pos = dcs_pos; 1574 return true; 1575 } 1576 } 1577 } 1578 return false; 1579 } 1580 1581 #define DCU_COMPLETE_STATE 1 1582 #define DCU_COMPLETE_STATE_MASK 0x3 1583 #define NUM_STATUS_READS 50 1584 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1585 { 1586 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1587 u32 i, hang_pos, hang_state, num_state = 6; 1588 1589 comp_state = REG_READ(ah, AR_DMADBG_6); 1590 1591 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1592 ath_dbg(ath9k_hw_common(ah), RESET, 1593 "MAC Hang signature not found at DCU complete\n"); 1594 return false; 1595 } 1596 1597 chain_state = REG_READ(ah, dcs_reg); 1598 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1599 goto hang_check_iter; 1600 1601 dcs_reg = AR_DMADBG_5; 1602 num_state = 4; 1603 chain_state = REG_READ(ah, dcs_reg); 1604 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1605 goto hang_check_iter; 1606 1607 ath_dbg(ath9k_hw_common(ah), RESET, 1608 "MAC Hang signature 1 not found\n"); 1609 return false; 1610 1611 hang_check_iter: 1612 ath_dbg(ath9k_hw_common(ah), RESET, 1613 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1614 chain_state, comp_state, hang_state, hang_pos); 1615 1616 for (i = 0; i < NUM_STATUS_READS; i++) { 1617 chain_state = REG_READ(ah, dcs_reg); 1618 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1619 comp_state = REG_READ(ah, AR_DMADBG_6); 1620 1621 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1622 DCU_COMPLETE_STATE) || 1623 (chain_state != hang_state)) 1624 return false; 1625 } 1626 1627 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1628 1629 return true; 1630 } 1631 1632 bool ath9k_hw_check_alive(struct ath_hw *ah) 1633 { 1634 int count = 50; 1635 u32 reg; 1636 1637 if (AR_SREV_9300(ah)) 1638 return !ath9k_hw_detect_mac_hang(ah); 1639 1640 if (AR_SREV_9285_12_OR_LATER(ah)) 1641 return true; 1642 1643 do { 1644 reg = REG_READ(ah, AR_OBS_BUS_1); 1645 1646 if ((reg & 0x7E7FFFEF) == 0x00702400) 1647 continue; 1648 1649 switch (reg & 0x7E000B00) { 1650 case 0x1E000000: 1651 case 0x52000B00: 1652 case 0x18000B00: 1653 continue; 1654 default: 1655 return true; 1656 } 1657 } while (count-- > 0); 1658 1659 return false; 1660 } 1661 EXPORT_SYMBOL(ath9k_hw_check_alive); 1662 1663 /* 1664 * Fast channel change: 1665 * (Change synthesizer based on channel freq without resetting chip) 1666 * 1667 * Don't do FCC when 1668 * - Flag is not set 1669 * - Chip is just coming out of full sleep 1670 * - Channel to be set is same as current channel 1671 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel) 1672 */ 1673 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1674 { 1675 struct ath_common *common = ath9k_hw_common(ah); 1676 int ret; 1677 1678 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1679 goto fail; 1680 1681 if (ah->chip_fullsleep) 1682 goto fail; 1683 1684 if (!ah->curchan) 1685 goto fail; 1686 1687 if (chan->channel == ah->curchan->channel) 1688 goto fail; 1689 1690 if ((ah->curchan->channelFlags | chan->channelFlags) & 1691 (CHANNEL_HALF | CHANNEL_QUARTER)) 1692 goto fail; 1693 1694 if ((chan->channelFlags & CHANNEL_ALL) != 1695 (ah->curchan->channelFlags & CHANNEL_ALL)) 1696 goto fail; 1697 1698 if (!ath9k_hw_check_alive(ah)) 1699 goto fail; 1700 1701 /* 1702 * For AR9462, make sure that calibration data for 1703 * re-using are present. 1704 */ 1705 if (AR_SREV_9462(ah) && (!ah->caldata || 1706 !ah->caldata->done_txiqcal_once || 1707 !ah->caldata->done_txclcal_once || 1708 !ah->caldata->rtt_hist.num_readings)) 1709 goto fail; 1710 1711 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1712 ah->curchan->channel, chan->channel); 1713 1714 ret = ath9k_hw_channel_change(ah, chan); 1715 if (!ret) 1716 goto fail; 1717 1718 ath9k_hw_loadnf(ah, ah->curchan); 1719 ath9k_hw_start_nfcal(ah, true); 1720 1721 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah)) 1722 ar9003_mci_2g5g_switch(ah, true); 1723 1724 if (AR_SREV_9271(ah)) 1725 ar9002_hw_load_ani_reg(ah, chan); 1726 1727 return 0; 1728 fail: 1729 return -EINVAL; 1730 } 1731 1732 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1733 struct ath9k_hw_cal_data *caldata, bool fastcc) 1734 { 1735 struct ath_common *common = ath9k_hw_common(ah); 1736 u32 saveLedState; 1737 u32 saveDefAntenna; 1738 u32 macStaId1; 1739 u64 tsf = 0; 1740 int i, r; 1741 bool start_mci_reset = false; 1742 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1743 bool save_fullsleep = ah->chip_fullsleep; 1744 1745 if (mci) { 1746 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1747 if (start_mci_reset) 1748 return 0; 1749 } 1750 1751 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1752 return -EIO; 1753 1754 if (ah->curchan && !ah->chip_fullsleep) 1755 ath9k_hw_getnf(ah, ah->curchan); 1756 1757 ah->caldata = caldata; 1758 if (caldata && 1759 (chan->channel != caldata->channel || 1760 (chan->channelFlags & ~CHANNEL_CW_INT) != 1761 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1762 /* Operating channel changed, reset channel calibration data */ 1763 memset(caldata, 0, sizeof(*caldata)); 1764 ath9k_init_nfcal_hist_buffer(ah, chan); 1765 } 1766 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1767 1768 if (fastcc) { 1769 r = ath9k_hw_do_fastcc(ah, chan); 1770 if (!r) 1771 return r; 1772 } 1773 1774 if (mci) 1775 ar9003_mci_stop_bt(ah, save_fullsleep); 1776 1777 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1778 if (saveDefAntenna == 0) 1779 saveDefAntenna = 1; 1780 1781 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1782 1783 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1784 if (AR_SREV_9100(ah) || 1785 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1786 tsf = ath9k_hw_gettsf64(ah); 1787 1788 saveLedState = REG_READ(ah, AR_CFG_LED) & 1789 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1790 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1791 1792 ath9k_hw_mark_phy_inactive(ah); 1793 1794 ah->paprd_table_write_done = false; 1795 1796 /* Only required on the first reset */ 1797 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1798 REG_WRITE(ah, 1799 AR9271_RESET_POWER_DOWN_CONTROL, 1800 AR9271_RADIO_RF_RST); 1801 udelay(50); 1802 } 1803 1804 if (!ath9k_hw_chip_reset(ah, chan)) { 1805 ath_err(common, "Chip reset failed\n"); 1806 return -EINVAL; 1807 } 1808 1809 /* Only required on the first reset */ 1810 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1811 ah->htc_reset_init = false; 1812 REG_WRITE(ah, 1813 AR9271_RESET_POWER_DOWN_CONTROL, 1814 AR9271_GATE_MAC_CTL); 1815 udelay(50); 1816 } 1817 1818 /* Restore TSF */ 1819 if (tsf) 1820 ath9k_hw_settsf64(ah, tsf); 1821 1822 if (AR_SREV_9280_20_OR_LATER(ah)) 1823 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1824 1825 if (!AR_SREV_9300_20_OR_LATER(ah)) 1826 ar9002_hw_enable_async_fifo(ah); 1827 1828 r = ath9k_hw_process_ini(ah, chan); 1829 if (r) 1830 return r; 1831 1832 if (mci) 1833 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1834 1835 /* 1836 * Some AR91xx SoC devices frequently fail to accept TSF writes 1837 * right after the chip reset. When that happens, write a new 1838 * value after the initvals have been applied, with an offset 1839 * based on measured time difference 1840 */ 1841 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1842 tsf += 1500; 1843 ath9k_hw_settsf64(ah, tsf); 1844 } 1845 1846 /* Setup MFP options for CCMP */ 1847 if (AR_SREV_9280_20_OR_LATER(ah)) { 1848 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1849 * frames when constructing CCMP AAD. */ 1850 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1851 0xc7ff); 1852 ah->sw_mgmt_crypto = false; 1853 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1854 /* Disable hardware crypto for management frames */ 1855 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1856 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1857 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1858 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1859 ah->sw_mgmt_crypto = true; 1860 } else 1861 ah->sw_mgmt_crypto = true; 1862 1863 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1864 ath9k_hw_set_delta_slope(ah, chan); 1865 1866 ath9k_hw_spur_mitigate_freq(ah, chan); 1867 ah->eep_ops->set_board_values(ah, chan); 1868 1869 ENABLE_REGWRITE_BUFFER(ah); 1870 1871 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1872 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1873 | macStaId1 1874 | AR_STA_ID1_RTS_USE_DEF 1875 | (ah->config. 1876 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1877 | ah->sta_id1_defaults); 1878 ath_hw_setbssidmask(common); 1879 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1880 ath9k_hw_write_associd(ah); 1881 REG_WRITE(ah, AR_ISR, ~0); 1882 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1883 1884 REGWRITE_BUFFER_FLUSH(ah); 1885 1886 ath9k_hw_set_operating_mode(ah, ah->opmode); 1887 1888 r = ath9k_hw_rf_set_freq(ah, chan); 1889 if (r) 1890 return r; 1891 1892 ath9k_hw_set_clockrate(ah); 1893 1894 ENABLE_REGWRITE_BUFFER(ah); 1895 1896 for (i = 0; i < AR_NUM_DCU; i++) 1897 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1898 1899 REGWRITE_BUFFER_FLUSH(ah); 1900 1901 ah->intr_txqs = 0; 1902 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1903 ath9k_hw_resettxqueue(ah, i); 1904 1905 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1906 ath9k_hw_ani_cache_ini_regs(ah); 1907 ath9k_hw_init_qos(ah); 1908 1909 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1910 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1911 1912 ath9k_hw_init_global_settings(ah); 1913 1914 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1915 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1916 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1917 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1918 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1919 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1920 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1921 } 1922 1923 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1924 1925 ath9k_hw_set_dma(ah); 1926 1927 REG_WRITE(ah, AR_OBS, 8); 1928 1929 if (ah->config.rx_intr_mitigation) { 1930 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1931 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1932 } 1933 1934 if (ah->config.tx_intr_mitigation) { 1935 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1936 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1937 } 1938 1939 ath9k_hw_init_bb(ah, chan); 1940 1941 if (caldata) { 1942 caldata->done_txiqcal_once = false; 1943 caldata->done_txclcal_once = false; 1944 caldata->rtt_hist.num_readings = 0; 1945 } 1946 if (!ath9k_hw_init_cal(ah, chan)) 1947 return -EIO; 1948 1949 ath9k_hw_loadnf(ah, chan); 1950 ath9k_hw_start_nfcal(ah, true); 1951 1952 if (mci && ar9003_mci_end_reset(ah, chan, caldata)) 1953 return -EIO; 1954 1955 ENABLE_REGWRITE_BUFFER(ah); 1956 1957 ath9k_hw_restore_chainmask(ah); 1958 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1959 1960 REGWRITE_BUFFER_FLUSH(ah); 1961 1962 /* 1963 * For big endian systems turn on swapping for descriptors 1964 */ 1965 if (AR_SREV_9100(ah)) { 1966 u32 mask; 1967 mask = REG_READ(ah, AR_CFG); 1968 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1969 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1970 mask); 1971 } else { 1972 mask = 1973 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1974 REG_WRITE(ah, AR_CFG, mask); 1975 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1976 REG_READ(ah, AR_CFG)); 1977 } 1978 } else { 1979 if (common->bus_ops->ath_bus_type == ATH_USB) { 1980 /* Configure AR9271 target WLAN */ 1981 if (AR_SREV_9271(ah)) 1982 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1983 else 1984 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1985 } 1986 #ifdef __BIG_ENDIAN 1987 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1988 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1989 else 1990 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1991 #endif 1992 } 1993 1994 if (ath9k_hw_btcoex_is_enabled(ah)) 1995 ath9k_hw_btcoex_enable(ah); 1996 1997 if (mci) 1998 ar9003_mci_check_bt(ah); 1999 2000 if (AR_SREV_9300_20_OR_LATER(ah)) { 2001 ar9003_hw_bb_watchdog_config(ah); 2002 2003 ar9003_hw_disable_phy_restart(ah); 2004 } 2005 2006 ath9k_hw_apply_gpio_override(ah); 2007 2008 return 0; 2009 } 2010 EXPORT_SYMBOL(ath9k_hw_reset); 2011 2012 /******************************/ 2013 /* Power Management (Chipset) */ 2014 /******************************/ 2015 2016 /* 2017 * Notify Power Mgt is disabled in self-generated frames. 2018 * If requested, force chip to sleep. 2019 */ 2020 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 2021 { 2022 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2023 if (setChip) { 2024 if (AR_SREV_9462(ah)) { 2025 REG_WRITE(ah, AR_TIMER_MODE, 2026 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 2027 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, 2028 AR_NDP2_TIMER_MODE) & 0xFFFFFF00); 2029 REG_WRITE(ah, AR_SLP32_INC, 2030 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); 2031 /* xxx Required for WLAN only case ? */ 2032 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2033 udelay(100); 2034 } 2035 2036 /* 2037 * Clear the RTC force wake bit to allow the 2038 * mac to go to sleep. 2039 */ 2040 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2041 2042 if (AR_SREV_9462(ah)) 2043 udelay(100); 2044 2045 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2046 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2047 2048 /* Shutdown chip. Active low */ 2049 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2050 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2051 udelay(2); 2052 } 2053 } 2054 2055 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2056 if (AR_SREV_9300_20_OR_LATER(ah)) 2057 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2058 } 2059 2060 /* 2061 * Notify Power Management is enabled in self-generating 2062 * frames. If request, set power mode of chip to 2063 * auto/normal. Duration in units of 128us (1/8 TU). 2064 */ 2065 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 2066 { 2067 u32 val; 2068 2069 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2070 if (setChip) { 2071 struct ath9k_hw_capabilities *pCap = &ah->caps; 2072 2073 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2074 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2075 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2076 AR_RTC_FORCE_WAKE_ON_INT); 2077 } else { 2078 2079 /* When chip goes into network sleep, it could be waken 2080 * up by MCI_INT interrupt caused by BT's HW messages 2081 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2082 * rate (~100us). This will cause chip to leave and 2083 * re-enter network sleep mode frequently, which in 2084 * consequence will have WLAN MCI HW to generate lots of 2085 * SYS_WAKING and SYS_SLEEPING messages which will make 2086 * BT CPU to busy to process. 2087 */ 2088 if (AR_SREV_9462(ah)) { 2089 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 2090 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 2091 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 2092 } 2093 /* 2094 * Clear the RTC force wake bit to allow the 2095 * mac to go to sleep. 2096 */ 2097 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2098 AR_RTC_FORCE_WAKE_EN); 2099 2100 if (AR_SREV_9462(ah)) 2101 udelay(30); 2102 } 2103 } 2104 2105 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2106 if (AR_SREV_9300_20_OR_LATER(ah)) 2107 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2108 } 2109 2110 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2111 { 2112 u32 val; 2113 int i; 2114 2115 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2116 if (AR_SREV_9300_20_OR_LATER(ah)) { 2117 REG_WRITE(ah, AR_WA, ah->WARegVal); 2118 udelay(10); 2119 } 2120 2121 if (setChip) { 2122 if ((REG_READ(ah, AR_RTC_STATUS) & 2123 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2124 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2125 return false; 2126 } 2127 if (!AR_SREV_9300_20_OR_LATER(ah)) 2128 ath9k_hw_init_pll(ah, NULL); 2129 } 2130 if (AR_SREV_9100(ah)) 2131 REG_SET_BIT(ah, AR_RTC_RESET, 2132 AR_RTC_RESET_EN); 2133 2134 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2135 AR_RTC_FORCE_WAKE_EN); 2136 udelay(50); 2137 2138 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2139 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2140 if (val == AR_RTC_STATUS_ON) 2141 break; 2142 udelay(50); 2143 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2144 AR_RTC_FORCE_WAKE_EN); 2145 } 2146 if (i == 0) { 2147 ath_err(ath9k_hw_common(ah), 2148 "Failed to wakeup in %uus\n", 2149 POWER_UP_TIME / 20); 2150 return false; 2151 } 2152 } 2153 2154 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2155 2156 return true; 2157 } 2158 2159 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2160 { 2161 struct ath_common *common = ath9k_hw_common(ah); 2162 int status = true, setChip = true; 2163 static const char *modes[] = { 2164 "AWAKE", 2165 "FULL-SLEEP", 2166 "NETWORK SLEEP", 2167 "UNDEFINED" 2168 }; 2169 2170 if (ah->power_mode == mode) 2171 return status; 2172 2173 ath_dbg(common, RESET, "%s -> %s\n", 2174 modes[ah->power_mode], modes[mode]); 2175 2176 switch (mode) { 2177 case ATH9K_PM_AWAKE: 2178 status = ath9k_hw_set_power_awake(ah, setChip); 2179 2180 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2181 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2182 2183 break; 2184 case ATH9K_PM_FULL_SLEEP: 2185 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2186 ar9003_mci_set_full_sleep(ah); 2187 2188 ath9k_set_power_sleep(ah, setChip); 2189 ah->chip_fullsleep = true; 2190 break; 2191 case ATH9K_PM_NETWORK_SLEEP: 2192 2193 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2194 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2195 2196 ath9k_set_power_network_sleep(ah, setChip); 2197 break; 2198 default: 2199 ath_err(common, "Unknown power mode %u\n", mode); 2200 return false; 2201 } 2202 ah->power_mode = mode; 2203 2204 /* 2205 * XXX: If this warning never comes up after a while then 2206 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2207 * ath9k_hw_setpower() return type void. 2208 */ 2209 2210 if (!(ah->ah_flags & AH_UNPLUGGED)) 2211 ATH_DBG_WARN_ON_ONCE(!status); 2212 2213 return status; 2214 } 2215 EXPORT_SYMBOL(ath9k_hw_setpower); 2216 2217 /*******************/ 2218 /* Beacon Handling */ 2219 /*******************/ 2220 2221 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2222 { 2223 int flags = 0; 2224 2225 ENABLE_REGWRITE_BUFFER(ah); 2226 2227 switch (ah->opmode) { 2228 case NL80211_IFTYPE_ADHOC: 2229 case NL80211_IFTYPE_MESH_POINT: 2230 REG_SET_BIT(ah, AR_TXCFG, 2231 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2232 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2233 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2234 flags |= AR_NDP_TIMER_EN; 2235 case NL80211_IFTYPE_AP: 2236 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2237 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2238 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2239 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2240 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2241 flags |= 2242 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2243 break; 2244 default: 2245 ath_dbg(ath9k_hw_common(ah), BEACON, 2246 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2247 return; 2248 break; 2249 } 2250 2251 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2252 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2253 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2254 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2255 2256 REGWRITE_BUFFER_FLUSH(ah); 2257 2258 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2259 } 2260 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2261 2262 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2263 const struct ath9k_beacon_state *bs) 2264 { 2265 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2266 struct ath9k_hw_capabilities *pCap = &ah->caps; 2267 struct ath_common *common = ath9k_hw_common(ah); 2268 2269 ENABLE_REGWRITE_BUFFER(ah); 2270 2271 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2272 2273 REG_WRITE(ah, AR_BEACON_PERIOD, 2274 TU_TO_USEC(bs->bs_intval)); 2275 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2276 TU_TO_USEC(bs->bs_intval)); 2277 2278 REGWRITE_BUFFER_FLUSH(ah); 2279 2280 REG_RMW_FIELD(ah, AR_RSSI_THR, 2281 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2282 2283 beaconintval = bs->bs_intval; 2284 2285 if (bs->bs_sleepduration > beaconintval) 2286 beaconintval = bs->bs_sleepduration; 2287 2288 dtimperiod = bs->bs_dtimperiod; 2289 if (bs->bs_sleepduration > dtimperiod) 2290 dtimperiod = bs->bs_sleepduration; 2291 2292 if (beaconintval == dtimperiod) 2293 nextTbtt = bs->bs_nextdtim; 2294 else 2295 nextTbtt = bs->bs_nexttbtt; 2296 2297 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2298 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2299 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2300 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2301 2302 ENABLE_REGWRITE_BUFFER(ah); 2303 2304 REG_WRITE(ah, AR_NEXT_DTIM, 2305 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2306 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2307 2308 REG_WRITE(ah, AR_SLEEP1, 2309 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2310 | AR_SLEEP1_ASSUME_DTIM); 2311 2312 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2313 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2314 else 2315 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2316 2317 REG_WRITE(ah, AR_SLEEP2, 2318 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2319 2320 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2321 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2322 2323 REGWRITE_BUFFER_FLUSH(ah); 2324 2325 REG_SET_BIT(ah, AR_TIMER_MODE, 2326 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2327 AR_DTIM_TIMER_EN); 2328 2329 /* TSF Out of Range Threshold */ 2330 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2331 } 2332 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2333 2334 /*******************/ 2335 /* HW Capabilities */ 2336 /*******************/ 2337 2338 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2339 { 2340 eeprom_chainmask &= chip_chainmask; 2341 if (eeprom_chainmask) 2342 return eeprom_chainmask; 2343 else 2344 return chip_chainmask; 2345 } 2346 2347 /** 2348 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2349 * @ah: the atheros hardware data structure 2350 * 2351 * We enable DFS support upstream on chipsets which have passed a series 2352 * of tests. The testing requirements are going to be documented. Desired 2353 * test requirements are documented at: 2354 * 2355 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2356 * 2357 * Once a new chipset gets properly tested an individual commit can be used 2358 * to document the testing for DFS for that chipset. 2359 */ 2360 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2361 { 2362 2363 switch (ah->hw_version.macVersion) { 2364 /* AR9580 will likely be our first target to get testing on */ 2365 case AR_SREV_VERSION_9580: 2366 default: 2367 return false; 2368 } 2369 } 2370 2371 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2372 { 2373 struct ath9k_hw_capabilities *pCap = &ah->caps; 2374 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2375 struct ath_common *common = ath9k_hw_common(ah); 2376 unsigned int chip_chainmask; 2377 2378 u16 eeval; 2379 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2380 2381 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2382 regulatory->current_rd = eeval; 2383 2384 if (ah->opmode != NL80211_IFTYPE_AP && 2385 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2386 if (regulatory->current_rd == 0x64 || 2387 regulatory->current_rd == 0x65) 2388 regulatory->current_rd += 5; 2389 else if (regulatory->current_rd == 0x41) 2390 regulatory->current_rd = 0x43; 2391 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2392 regulatory->current_rd); 2393 } 2394 2395 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2396 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2397 ath_err(common, 2398 "no band has been marked as supported in EEPROM\n"); 2399 return -EINVAL; 2400 } 2401 2402 if (eeval & AR5416_OPFLAGS_11A) 2403 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2404 2405 if (eeval & AR5416_OPFLAGS_11G) 2406 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2407 2408 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2409 chip_chainmask = 1; 2410 else if (AR_SREV_9462(ah)) 2411 chip_chainmask = 3; 2412 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2413 chip_chainmask = 7; 2414 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2415 chip_chainmask = 3; 2416 else 2417 chip_chainmask = 7; 2418 2419 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2420 /* 2421 * For AR9271 we will temporarilly uses the rx chainmax as read from 2422 * the EEPROM. 2423 */ 2424 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2425 !(eeval & AR5416_OPFLAGS_11A) && 2426 !(AR_SREV_9271(ah))) 2427 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2428 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2429 else if (AR_SREV_9100(ah)) 2430 pCap->rx_chainmask = 0x7; 2431 else 2432 /* Use rx_chainmask from EEPROM. */ 2433 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2434 2435 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2436 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2437 ah->txchainmask = pCap->tx_chainmask; 2438 ah->rxchainmask = pCap->rx_chainmask; 2439 2440 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2441 2442 /* enable key search for every frame in an aggregate */ 2443 if (AR_SREV_9300_20_OR_LATER(ah)) 2444 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2445 2446 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2447 2448 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2449 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2450 else 2451 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2452 2453 if (AR_SREV_9271(ah)) 2454 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2455 else if (AR_DEVID_7010(ah)) 2456 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2457 else if (AR_SREV_9300_20_OR_LATER(ah)) 2458 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2459 else if (AR_SREV_9287_11_OR_LATER(ah)) 2460 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2461 else if (AR_SREV_9285_12_OR_LATER(ah)) 2462 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2463 else if (AR_SREV_9280_20_OR_LATER(ah)) 2464 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2465 else 2466 pCap->num_gpio_pins = AR_NUM_GPIO; 2467 2468 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2469 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2470 else 2471 pCap->rts_aggr_limit = (8 * 1024); 2472 2473 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2474 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2475 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2476 ah->rfkill_gpio = 2477 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2478 ah->rfkill_polarity = 2479 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2480 2481 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2482 } 2483 #endif 2484 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2485 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2486 else 2487 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2488 2489 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2490 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2491 else 2492 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2493 2494 if (AR_SREV_9300_20_OR_LATER(ah)) { 2495 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2496 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2497 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2498 2499 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2500 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2501 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2502 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2503 pCap->txs_len = sizeof(struct ar9003_txs); 2504 if (!ah->config.paprd_disable && 2505 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2506 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2507 } else { 2508 pCap->tx_desc_len = sizeof(struct ath_desc); 2509 if (AR_SREV_9280_20(ah)) 2510 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2511 } 2512 2513 if (AR_SREV_9300_20_OR_LATER(ah)) 2514 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2515 2516 if (AR_SREV_9300_20_OR_LATER(ah)) 2517 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2518 2519 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2520 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2521 2522 if (AR_SREV_9285(ah)) 2523 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2524 ant_div_ctl1 = 2525 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2526 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2527 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2528 } 2529 if (AR_SREV_9300_20_OR_LATER(ah)) { 2530 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2531 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2532 } 2533 2534 2535 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2536 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2537 /* 2538 * enable the diversity-combining algorithm only when 2539 * both enable_lna_div and enable_fast_div are set 2540 * Table for Diversity 2541 * ant_div_alt_lnaconf bit 0-1 2542 * ant_div_main_lnaconf bit 2-3 2543 * ant_div_alt_gaintb bit 4 2544 * ant_div_main_gaintb bit 5 2545 * enable_ant_div_lnadiv bit 6 2546 * enable_ant_fast_div bit 7 2547 */ 2548 if ((ant_div_ctl1 >> 0x6) == 0x3) 2549 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2550 } 2551 2552 if (AR_SREV_9485_10(ah)) { 2553 pCap->pcie_lcr_extsync_en = true; 2554 pCap->pcie_lcr_offset = 0x80; 2555 } 2556 2557 if (ath9k_hw_dfs_tested(ah)) 2558 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2559 2560 tx_chainmask = pCap->tx_chainmask; 2561 rx_chainmask = pCap->rx_chainmask; 2562 while (tx_chainmask || rx_chainmask) { 2563 if (tx_chainmask & BIT(0)) 2564 pCap->max_txchains++; 2565 if (rx_chainmask & BIT(0)) 2566 pCap->max_rxchains++; 2567 2568 tx_chainmask >>= 1; 2569 rx_chainmask >>= 1; 2570 } 2571 2572 if (AR_SREV_9300_20_OR_LATER(ah)) { 2573 ah->enabled_cals |= TX_IQ_CAL; 2574 if (AR_SREV_9485_OR_LATER(ah)) 2575 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2576 } 2577 2578 if (AR_SREV_9462(ah)) { 2579 2580 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2581 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2582 2583 if (AR_SREV_9462_20(ah)) 2584 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2585 2586 } 2587 2588 2589 return 0; 2590 } 2591 2592 /****************************/ 2593 /* GPIO / RFKILL / Antennae */ 2594 /****************************/ 2595 2596 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2597 u32 gpio, u32 type) 2598 { 2599 int addr; 2600 u32 gpio_shift, tmp; 2601 2602 if (gpio > 11) 2603 addr = AR_GPIO_OUTPUT_MUX3; 2604 else if (gpio > 5) 2605 addr = AR_GPIO_OUTPUT_MUX2; 2606 else 2607 addr = AR_GPIO_OUTPUT_MUX1; 2608 2609 gpio_shift = (gpio % 6) * 5; 2610 2611 if (AR_SREV_9280_20_OR_LATER(ah) 2612 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2613 REG_RMW(ah, addr, (type << gpio_shift), 2614 (0x1f << gpio_shift)); 2615 } else { 2616 tmp = REG_READ(ah, addr); 2617 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2618 tmp &= ~(0x1f << gpio_shift); 2619 tmp |= (type << gpio_shift); 2620 REG_WRITE(ah, addr, tmp); 2621 } 2622 } 2623 2624 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2625 { 2626 u32 gpio_shift; 2627 2628 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2629 2630 if (AR_DEVID_7010(ah)) { 2631 gpio_shift = gpio; 2632 REG_RMW(ah, AR7010_GPIO_OE, 2633 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2634 (AR7010_GPIO_OE_MASK << gpio_shift)); 2635 return; 2636 } 2637 2638 gpio_shift = gpio << 1; 2639 REG_RMW(ah, 2640 AR_GPIO_OE_OUT, 2641 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2642 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2643 } 2644 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2645 2646 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2647 { 2648 #define MS_REG_READ(x, y) \ 2649 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2650 2651 if (gpio >= ah->caps.num_gpio_pins) 2652 return 0xffffffff; 2653 2654 if (AR_DEVID_7010(ah)) { 2655 u32 val; 2656 val = REG_READ(ah, AR7010_GPIO_IN); 2657 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2658 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2659 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2660 AR_GPIO_BIT(gpio)) != 0; 2661 else if (AR_SREV_9271(ah)) 2662 return MS_REG_READ(AR9271, gpio) != 0; 2663 else if (AR_SREV_9287_11_OR_LATER(ah)) 2664 return MS_REG_READ(AR9287, gpio) != 0; 2665 else if (AR_SREV_9285_12_OR_LATER(ah)) 2666 return MS_REG_READ(AR9285, gpio) != 0; 2667 else if (AR_SREV_9280_20_OR_LATER(ah)) 2668 return MS_REG_READ(AR928X, gpio) != 0; 2669 else 2670 return MS_REG_READ(AR, gpio) != 0; 2671 } 2672 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2673 2674 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2675 u32 ah_signal_type) 2676 { 2677 u32 gpio_shift; 2678 2679 if (AR_DEVID_7010(ah)) { 2680 gpio_shift = gpio; 2681 REG_RMW(ah, AR7010_GPIO_OE, 2682 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2683 (AR7010_GPIO_OE_MASK << gpio_shift)); 2684 return; 2685 } 2686 2687 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2688 gpio_shift = 2 * gpio; 2689 REG_RMW(ah, 2690 AR_GPIO_OE_OUT, 2691 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2692 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2693 } 2694 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2695 2696 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2697 { 2698 if (AR_DEVID_7010(ah)) { 2699 val = val ? 0 : 1; 2700 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2701 AR_GPIO_BIT(gpio)); 2702 return; 2703 } 2704 2705 if (AR_SREV_9271(ah)) 2706 val = ~val; 2707 2708 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2709 AR_GPIO_BIT(gpio)); 2710 } 2711 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2712 2713 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2714 { 2715 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2716 } 2717 EXPORT_SYMBOL(ath9k_hw_setantenna); 2718 2719 /*********************/ 2720 /* General Operation */ 2721 /*********************/ 2722 2723 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2724 { 2725 u32 bits = REG_READ(ah, AR_RX_FILTER); 2726 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2727 2728 if (phybits & AR_PHY_ERR_RADAR) 2729 bits |= ATH9K_RX_FILTER_PHYRADAR; 2730 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2731 bits |= ATH9K_RX_FILTER_PHYERR; 2732 2733 return bits; 2734 } 2735 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2736 2737 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2738 { 2739 u32 phybits; 2740 2741 ENABLE_REGWRITE_BUFFER(ah); 2742 2743 if (AR_SREV_9462(ah)) 2744 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2745 2746 REG_WRITE(ah, AR_RX_FILTER, bits); 2747 2748 phybits = 0; 2749 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2750 phybits |= AR_PHY_ERR_RADAR; 2751 if (bits & ATH9K_RX_FILTER_PHYERR) 2752 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2753 REG_WRITE(ah, AR_PHY_ERR, phybits); 2754 2755 if (phybits) 2756 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2757 else 2758 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2759 2760 REGWRITE_BUFFER_FLUSH(ah); 2761 } 2762 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2763 2764 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2765 { 2766 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2767 return false; 2768 2769 ath9k_hw_init_pll(ah, NULL); 2770 ah->htc_reset_init = true; 2771 return true; 2772 } 2773 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2774 2775 bool ath9k_hw_disable(struct ath_hw *ah) 2776 { 2777 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2778 return false; 2779 2780 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2781 return false; 2782 2783 ath9k_hw_init_pll(ah, NULL); 2784 return true; 2785 } 2786 EXPORT_SYMBOL(ath9k_hw_disable); 2787 2788 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2789 { 2790 enum eeprom_param gain_param; 2791 2792 if (IS_CHAN_2GHZ(chan)) 2793 gain_param = EEP_ANTENNA_GAIN_2G; 2794 else 2795 gain_param = EEP_ANTENNA_GAIN_5G; 2796 2797 return ah->eep_ops->get_eeprom(ah, gain_param); 2798 } 2799 2800 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2801 bool test) 2802 { 2803 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2804 struct ieee80211_channel *channel; 2805 int chan_pwr, new_pwr, max_gain; 2806 int ant_gain, ant_reduction = 0; 2807 2808 if (!chan) 2809 return; 2810 2811 channel = chan->chan; 2812 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2813 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2814 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2815 2816 ant_gain = get_antenna_gain(ah, chan); 2817 if (ant_gain > max_gain) 2818 ant_reduction = ant_gain - max_gain; 2819 2820 ah->eep_ops->set_txpower(ah, chan, 2821 ath9k_regd_get_ctl(reg, chan), 2822 ant_reduction, new_pwr, test); 2823 } 2824 2825 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2826 { 2827 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2828 struct ath9k_channel *chan = ah->curchan; 2829 struct ieee80211_channel *channel = chan->chan; 2830 2831 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2832 if (test) 2833 channel->max_power = MAX_RATE_POWER / 2; 2834 2835 ath9k_hw_apply_txpower(ah, chan, test); 2836 2837 if (test) 2838 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2839 } 2840 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2841 2842 void ath9k_hw_setopmode(struct ath_hw *ah) 2843 { 2844 ath9k_hw_set_operating_mode(ah, ah->opmode); 2845 } 2846 EXPORT_SYMBOL(ath9k_hw_setopmode); 2847 2848 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2849 { 2850 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2851 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2852 } 2853 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2854 2855 void ath9k_hw_write_associd(struct ath_hw *ah) 2856 { 2857 struct ath_common *common = ath9k_hw_common(ah); 2858 2859 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2860 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2861 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2862 } 2863 EXPORT_SYMBOL(ath9k_hw_write_associd); 2864 2865 #define ATH9K_MAX_TSF_READ 10 2866 2867 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2868 { 2869 u32 tsf_lower, tsf_upper1, tsf_upper2; 2870 int i; 2871 2872 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2873 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2874 tsf_lower = REG_READ(ah, AR_TSF_L32); 2875 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2876 if (tsf_upper2 == tsf_upper1) 2877 break; 2878 tsf_upper1 = tsf_upper2; 2879 } 2880 2881 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2882 2883 return (((u64)tsf_upper1 << 32) | tsf_lower); 2884 } 2885 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2886 2887 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2888 { 2889 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2890 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2891 } 2892 EXPORT_SYMBOL(ath9k_hw_settsf64); 2893 2894 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2895 { 2896 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2897 AH_TSF_WRITE_TIMEOUT)) 2898 ath_dbg(ath9k_hw_common(ah), RESET, 2899 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2900 2901 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2902 } 2903 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2904 2905 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2906 { 2907 if (setting) 2908 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2909 else 2910 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2911 } 2912 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2913 2914 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2915 { 2916 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2917 u32 macmode; 2918 2919 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2920 macmode = AR_2040_JOINED_RX_CLEAR; 2921 else 2922 macmode = 0; 2923 2924 REG_WRITE(ah, AR_2040_MODE, macmode); 2925 } 2926 2927 /* HW Generic timers configuration */ 2928 2929 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2930 { 2931 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2932 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2933 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2934 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2935 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2936 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2937 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2938 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2939 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2940 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2941 AR_NDP2_TIMER_MODE, 0x0002}, 2942 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2943 AR_NDP2_TIMER_MODE, 0x0004}, 2944 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2945 AR_NDP2_TIMER_MODE, 0x0008}, 2946 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2947 AR_NDP2_TIMER_MODE, 0x0010}, 2948 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2949 AR_NDP2_TIMER_MODE, 0x0020}, 2950 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2951 AR_NDP2_TIMER_MODE, 0x0040}, 2952 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2953 AR_NDP2_TIMER_MODE, 0x0080} 2954 }; 2955 2956 /* HW generic timer primitives */ 2957 2958 /* compute and clear index of rightmost 1 */ 2959 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2960 { 2961 u32 b; 2962 2963 b = *mask; 2964 b &= (0-b); 2965 *mask &= ~b; 2966 b *= debruijn32; 2967 b >>= 27; 2968 2969 return timer_table->gen_timer_index[b]; 2970 } 2971 2972 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2973 { 2974 return REG_READ(ah, AR_TSF_L32); 2975 } 2976 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2977 2978 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2979 void (*trigger)(void *), 2980 void (*overflow)(void *), 2981 void *arg, 2982 u8 timer_index) 2983 { 2984 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2985 struct ath_gen_timer *timer; 2986 2987 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2988 2989 if (timer == NULL) { 2990 ath_err(ath9k_hw_common(ah), 2991 "Failed to allocate memory for hw timer[%d]\n", 2992 timer_index); 2993 return NULL; 2994 } 2995 2996 /* allocate a hardware generic timer slot */ 2997 timer_table->timers[timer_index] = timer; 2998 timer->index = timer_index; 2999 timer->trigger = trigger; 3000 timer->overflow = overflow; 3001 timer->arg = arg; 3002 3003 return timer; 3004 } 3005 EXPORT_SYMBOL(ath_gen_timer_alloc); 3006 3007 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3008 struct ath_gen_timer *timer, 3009 u32 trig_timeout, 3010 u32 timer_period) 3011 { 3012 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3013 u32 tsf, timer_next; 3014 3015 BUG_ON(!timer_period); 3016 3017 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3018 3019 tsf = ath9k_hw_gettsf32(ah); 3020 3021 timer_next = tsf + trig_timeout; 3022 3023 ath_dbg(ath9k_hw_common(ah), HWTIMER, 3024 "current tsf %x period %x timer_next %x\n", 3025 tsf, timer_period, timer_next); 3026 3027 /* 3028 * Program generic timer registers 3029 */ 3030 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3031 timer_next); 3032 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3033 timer_period); 3034 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3035 gen_tmr_configuration[timer->index].mode_mask); 3036 3037 if (AR_SREV_9462(ah)) { 3038 /* 3039 * Starting from AR9462, each generic timer can select which tsf 3040 * to use. But we still follow the old rule, 0 - 7 use tsf and 3041 * 8 - 15 use tsf2. 3042 */ 3043 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3044 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3045 (1 << timer->index)); 3046 else 3047 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3048 (1 << timer->index)); 3049 } 3050 3051 /* Enable both trigger and thresh interrupt masks */ 3052 REG_SET_BIT(ah, AR_IMR_S5, 3053 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3054 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3055 } 3056 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3057 3058 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3059 { 3060 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3061 3062 if ((timer->index < AR_FIRST_NDP_TIMER) || 3063 (timer->index >= ATH_MAX_GEN_TIMER)) { 3064 return; 3065 } 3066 3067 /* Clear generic timer enable bits. */ 3068 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3069 gen_tmr_configuration[timer->index].mode_mask); 3070 3071 /* Disable both trigger and thresh interrupt masks */ 3072 REG_CLR_BIT(ah, AR_IMR_S5, 3073 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3074 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3075 3076 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3077 } 3078 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3079 3080 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3081 { 3082 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3083 3084 /* free the hardware generic timer slot */ 3085 timer_table->timers[timer->index] = NULL; 3086 kfree(timer); 3087 } 3088 EXPORT_SYMBOL(ath_gen_timer_free); 3089 3090 /* 3091 * Generic Timer Interrupts handling 3092 */ 3093 void ath_gen_timer_isr(struct ath_hw *ah) 3094 { 3095 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3096 struct ath_gen_timer *timer; 3097 struct ath_common *common = ath9k_hw_common(ah); 3098 u32 trigger_mask, thresh_mask, index; 3099 3100 /* get hardware generic timer interrupt status */ 3101 trigger_mask = ah->intr_gen_timer_trigger; 3102 thresh_mask = ah->intr_gen_timer_thresh; 3103 trigger_mask &= timer_table->timer_mask.val; 3104 thresh_mask &= timer_table->timer_mask.val; 3105 3106 trigger_mask &= ~thresh_mask; 3107 3108 while (thresh_mask) { 3109 index = rightmost_index(timer_table, &thresh_mask); 3110 timer = timer_table->timers[index]; 3111 BUG_ON(!timer); 3112 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 3113 index); 3114 timer->overflow(timer->arg); 3115 } 3116 3117 while (trigger_mask) { 3118 index = rightmost_index(timer_table, &trigger_mask); 3119 timer = timer_table->timers[index]; 3120 BUG_ON(!timer); 3121 ath_dbg(common, HWTIMER, 3122 "Gen timer[%d] trigger\n", index); 3123 timer->trigger(timer->arg); 3124 } 3125 } 3126 EXPORT_SYMBOL(ath_gen_timer_isr); 3127 3128 /********/ 3129 /* HTC */ 3130 /********/ 3131 3132 static struct { 3133 u32 version; 3134 const char * name; 3135 } ath_mac_bb_names[] = { 3136 /* Devices with external radios */ 3137 { AR_SREV_VERSION_5416_PCI, "5416" }, 3138 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3139 { AR_SREV_VERSION_9100, "9100" }, 3140 { AR_SREV_VERSION_9160, "9160" }, 3141 /* Single-chip solutions */ 3142 { AR_SREV_VERSION_9280, "9280" }, 3143 { AR_SREV_VERSION_9285, "9285" }, 3144 { AR_SREV_VERSION_9287, "9287" }, 3145 { AR_SREV_VERSION_9271, "9271" }, 3146 { AR_SREV_VERSION_9300, "9300" }, 3147 { AR_SREV_VERSION_9330, "9330" }, 3148 { AR_SREV_VERSION_9340, "9340" }, 3149 { AR_SREV_VERSION_9485, "9485" }, 3150 { AR_SREV_VERSION_9462, "9462" }, 3151 }; 3152 3153 /* For devices with external radios */ 3154 static struct { 3155 u16 version; 3156 const char * name; 3157 } ath_rf_names[] = { 3158 { 0, "5133" }, 3159 { AR_RAD5133_SREV_MAJOR, "5133" }, 3160 { AR_RAD5122_SREV_MAJOR, "5122" }, 3161 { AR_RAD2133_SREV_MAJOR, "2133" }, 3162 { AR_RAD2122_SREV_MAJOR, "2122" } 3163 }; 3164 3165 /* 3166 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3167 */ 3168 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3169 { 3170 int i; 3171 3172 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3173 if (ath_mac_bb_names[i].version == mac_bb_version) { 3174 return ath_mac_bb_names[i].name; 3175 } 3176 } 3177 3178 return "????"; 3179 } 3180 3181 /* 3182 * Return the RF name. "????" is returned if the RF is unknown. 3183 * Used for devices with external radios. 3184 */ 3185 static const char *ath9k_hw_rf_name(u16 rf_version) 3186 { 3187 int i; 3188 3189 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3190 if (ath_rf_names[i].version == rf_version) { 3191 return ath_rf_names[i].name; 3192 } 3193 } 3194 3195 return "????"; 3196 } 3197 3198 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3199 { 3200 int used; 3201 3202 /* chipsets >= AR9280 are single-chip */ 3203 if (AR_SREV_9280_20_OR_LATER(ah)) { 3204 used = snprintf(hw_name, len, 3205 "Atheros AR%s Rev:%x", 3206 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3207 ah->hw_version.macRev); 3208 } 3209 else { 3210 used = snprintf(hw_name, len, 3211 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3212 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3213 ah->hw_version.macRev, 3214 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3215 AR_RADIO_SREV_MAJOR)), 3216 ah->hw_version.phyRev); 3217 } 3218 3219 hw_name[used] = '\0'; 3220 } 3221 EXPORT_SYMBOL(ath9k_hw_name); 3222