1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 #include "ar9003_mci.h" 27 #include "debug.h" 28 #include "ath9k.h" 29 30 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 31 32 MODULE_AUTHOR("Atheros Communications"); 33 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 34 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 35 MODULE_LICENSE("Dual BSD/GPL"); 36 37 static int __init ath9k_init(void) 38 { 39 return 0; 40 } 41 module_init(ath9k_init); 42 43 static void __exit ath9k_exit(void) 44 { 45 return; 46 } 47 module_exit(ath9k_exit); 48 49 /* Private hardware callbacks */ 50 51 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 52 { 53 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 54 } 55 56 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 57 { 58 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 59 } 60 61 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 62 struct ath9k_channel *chan) 63 { 64 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 65 } 66 67 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 68 { 69 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 70 return; 71 72 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 73 } 74 75 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 76 { 77 /* You will not have this callback if using the old ANI */ 78 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 79 return; 80 81 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 82 } 83 84 /********************/ 85 /* Helper Functions */ 86 /********************/ 87 88 #ifdef CONFIG_ATH9K_DEBUGFS 89 90 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 91 { 92 struct ath_softc *sc = common->priv; 93 if (sync_cause) 94 sc->debug.stats.istats.sync_cause_all++; 95 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 96 sc->debug.stats.istats.sync_rtc_irq++; 97 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 98 sc->debug.stats.istats.sync_mac_irq++; 99 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 100 sc->debug.stats.istats.eeprom_illegal_access++; 101 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 102 sc->debug.stats.istats.apb_timeout++; 103 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 104 sc->debug.stats.istats.pci_mode_conflict++; 105 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 106 sc->debug.stats.istats.host1_fatal++; 107 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 108 sc->debug.stats.istats.host1_perr++; 109 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 110 sc->debug.stats.istats.trcv_fifo_perr++; 111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 112 sc->debug.stats.istats.radm_cpl_ep++; 113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 114 sc->debug.stats.istats.radm_cpl_dllp_abort++; 115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 116 sc->debug.stats.istats.radm_cpl_tlp_abort++; 117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 118 sc->debug.stats.istats.radm_cpl_ecrc_err++; 119 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 120 sc->debug.stats.istats.radm_cpl_timeout++; 121 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 122 sc->debug.stats.istats.local_timeout++; 123 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 124 sc->debug.stats.istats.pm_access++; 125 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 126 sc->debug.stats.istats.mac_awake++; 127 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 128 sc->debug.stats.istats.mac_asleep++; 129 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 130 sc->debug.stats.istats.mac_sleep_access++; 131 } 132 #endif 133 134 135 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 136 { 137 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 138 struct ath_common *common = ath9k_hw_common(ah); 139 unsigned int clockrate; 140 141 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 142 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 143 clockrate = 117; 144 else if (!ah->curchan) /* should really check for CCK instead */ 145 clockrate = ATH9K_CLOCK_RATE_CCK; 146 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 147 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 148 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 149 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 150 else 151 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 152 153 if (conf_is_ht40(conf)) 154 clockrate *= 2; 155 156 if (ah->curchan) { 157 if (IS_CHAN_HALF_RATE(ah->curchan)) 158 clockrate /= 2; 159 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 160 clockrate /= 4; 161 } 162 163 common->clockrate = clockrate; 164 } 165 166 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 167 { 168 struct ath_common *common = ath9k_hw_common(ah); 169 170 return usecs * common->clockrate; 171 } 172 173 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 174 { 175 int i; 176 177 BUG_ON(timeout < AH_TIME_QUANTUM); 178 179 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 180 if ((REG_READ(ah, reg) & mask) == val) 181 return true; 182 183 udelay(AH_TIME_QUANTUM); 184 } 185 186 ath_dbg(ath9k_hw_common(ah), ANY, 187 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 188 timeout, reg, REG_READ(ah, reg), mask, val); 189 190 return false; 191 } 192 EXPORT_SYMBOL(ath9k_hw_wait); 193 194 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 195 int hw_delay) 196 { 197 if (IS_CHAN_B(chan)) 198 hw_delay = (4 * hw_delay) / 22; 199 else 200 hw_delay /= 10; 201 202 if (IS_CHAN_HALF_RATE(chan)) 203 hw_delay *= 2; 204 else if (IS_CHAN_QUARTER_RATE(chan)) 205 hw_delay *= 4; 206 207 udelay(hw_delay + BASE_ACTIVATE_DELAY); 208 } 209 210 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 211 int column, unsigned int *writecnt) 212 { 213 int r; 214 215 ENABLE_REGWRITE_BUFFER(ah); 216 for (r = 0; r < array->ia_rows; r++) { 217 REG_WRITE(ah, INI_RA(array, r, 0), 218 INI_RA(array, r, column)); 219 DO_DELAY(*writecnt); 220 } 221 REGWRITE_BUFFER_FLUSH(ah); 222 } 223 224 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 225 { 226 u32 retval; 227 int i; 228 229 for (i = 0, retval = 0; i < n; i++) { 230 retval = (retval << 1) | (val & 1); 231 val >>= 1; 232 } 233 return retval; 234 } 235 236 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 237 u8 phy, int kbps, 238 u32 frameLen, u16 rateix, 239 bool shortPreamble) 240 { 241 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 242 243 if (kbps == 0) 244 return 0; 245 246 switch (phy) { 247 case WLAN_RC_PHY_CCK: 248 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 249 if (shortPreamble) 250 phyTime >>= 1; 251 numBits = frameLen << 3; 252 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 253 break; 254 case WLAN_RC_PHY_OFDM: 255 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 256 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 257 numBits = OFDM_PLCP_BITS + (frameLen << 3); 258 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 259 txTime = OFDM_SIFS_TIME_QUARTER 260 + OFDM_PREAMBLE_TIME_QUARTER 261 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 262 } else if (ah->curchan && 263 IS_CHAN_HALF_RATE(ah->curchan)) { 264 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 265 numBits = OFDM_PLCP_BITS + (frameLen << 3); 266 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 267 txTime = OFDM_SIFS_TIME_HALF + 268 OFDM_PREAMBLE_TIME_HALF 269 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 270 } else { 271 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 272 numBits = OFDM_PLCP_BITS + (frameLen << 3); 273 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 274 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 275 + (numSymbols * OFDM_SYMBOL_TIME); 276 } 277 break; 278 default: 279 ath_err(ath9k_hw_common(ah), 280 "Unknown phy %u (rate ix %u)\n", phy, rateix); 281 txTime = 0; 282 break; 283 } 284 285 return txTime; 286 } 287 EXPORT_SYMBOL(ath9k_hw_computetxtime); 288 289 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 290 struct ath9k_channel *chan, 291 struct chan_centers *centers) 292 { 293 int8_t extoff; 294 295 if (!IS_CHAN_HT40(chan)) { 296 centers->ctl_center = centers->ext_center = 297 centers->synth_center = chan->channel; 298 return; 299 } 300 301 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 302 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 303 centers->synth_center = 304 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 305 extoff = 1; 306 } else { 307 centers->synth_center = 308 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 309 extoff = -1; 310 } 311 312 centers->ctl_center = 313 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 314 /* 25 MHz spacing is supported by hw but not on upper layers */ 315 centers->ext_center = 316 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 317 } 318 319 /******************/ 320 /* Chip Revisions */ 321 /******************/ 322 323 static void ath9k_hw_read_revisions(struct ath_hw *ah) 324 { 325 u32 val; 326 327 switch (ah->hw_version.devid) { 328 case AR5416_AR9100_DEVID: 329 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 330 break; 331 case AR9300_DEVID_AR9330: 332 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 333 if (ah->get_mac_revision) { 334 ah->hw_version.macRev = ah->get_mac_revision(); 335 } else { 336 val = REG_READ(ah, AR_SREV); 337 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 338 } 339 return; 340 case AR9300_DEVID_AR9340: 341 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 342 val = REG_READ(ah, AR_SREV); 343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 344 return; 345 case AR9300_DEVID_QCA955X: 346 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 347 return; 348 } 349 350 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 351 352 if (val == 0xFF) { 353 val = REG_READ(ah, AR_SREV); 354 ah->hw_version.macVersion = 355 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 356 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 357 358 if (AR_SREV_9462(ah)) 359 ah->is_pciexpress = true; 360 else 361 ah->is_pciexpress = (val & 362 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 363 } else { 364 if (!AR_SREV_9100(ah)) 365 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 366 367 ah->hw_version.macRev = val & AR_SREV_REVISION; 368 369 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 370 ah->is_pciexpress = true; 371 } 372 } 373 374 /************************************/ 375 /* HW Attach, Detach, Init Routines */ 376 /************************************/ 377 378 static void ath9k_hw_disablepcie(struct ath_hw *ah) 379 { 380 if (!AR_SREV_5416(ah)) 381 return; 382 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 388 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 389 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 390 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 391 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 392 393 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 394 } 395 396 /* This should work for all families including legacy */ 397 static bool ath9k_hw_chip_test(struct ath_hw *ah) 398 { 399 struct ath_common *common = ath9k_hw_common(ah); 400 u32 regAddr[2] = { AR_STA_ID0 }; 401 u32 regHold[2]; 402 static const u32 patternData[4] = { 403 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 404 }; 405 int i, j, loop_max; 406 407 if (!AR_SREV_9300_20_OR_LATER(ah)) { 408 loop_max = 2; 409 regAddr[1] = AR_PHY_BASE + (8 << 2); 410 } else 411 loop_max = 1; 412 413 for (i = 0; i < loop_max; i++) { 414 u32 addr = regAddr[i]; 415 u32 wrData, rdData; 416 417 regHold[i] = REG_READ(ah, addr); 418 for (j = 0; j < 0x100; j++) { 419 wrData = (j << 16) | j; 420 REG_WRITE(ah, addr, wrData); 421 rdData = REG_READ(ah, addr); 422 if (rdData != wrData) { 423 ath_err(common, 424 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 425 addr, wrData, rdData); 426 return false; 427 } 428 } 429 for (j = 0; j < 4; j++) { 430 wrData = patternData[j]; 431 REG_WRITE(ah, addr, wrData); 432 rdData = REG_READ(ah, addr); 433 if (wrData != rdData) { 434 ath_err(common, 435 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 436 addr, wrData, rdData); 437 return false; 438 } 439 } 440 REG_WRITE(ah, regAddr[i], regHold[i]); 441 } 442 udelay(100); 443 444 return true; 445 } 446 447 static void ath9k_hw_init_config(struct ath_hw *ah) 448 { 449 int i; 450 451 ah->config.dma_beacon_response_time = 1; 452 ah->config.sw_beacon_response_time = 6; 453 ah->config.additional_swba_backoff = 0; 454 ah->config.ack_6mb = 0x0; 455 ah->config.cwm_ignore_extcca = 0; 456 ah->config.pcie_clock_req = 0; 457 ah->config.pcie_waen = 0; 458 ah->config.analog_shiftreg = 1; 459 ah->config.enable_ani = true; 460 461 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 462 ah->config.spurchans[i][0] = AR_NO_SPUR; 463 ah->config.spurchans[i][1] = AR_NO_SPUR; 464 } 465 466 /* PAPRD needs some more work to be enabled */ 467 ah->config.paprd_disable = 1; 468 469 ah->config.rx_intr_mitigation = true; 470 ah->config.pcieSerDesWrite = true; 471 472 /* 473 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 474 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 475 * This means we use it for all AR5416 devices, and the few 476 * minor PCI AR9280 devices out there. 477 * 478 * Serialization is required because these devices do not handle 479 * well the case of two concurrent reads/writes due to the latency 480 * involved. During one read/write another read/write can be issued 481 * on another CPU while the previous read/write may still be working 482 * on our hardware, if we hit this case the hardware poops in a loop. 483 * We prevent this by serializing reads and writes. 484 * 485 * This issue is not present on PCI-Express devices or pre-AR5416 486 * devices (legacy, 802.11abg). 487 */ 488 if (num_possible_cpus() > 1) 489 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 490 } 491 492 static void ath9k_hw_init_defaults(struct ath_hw *ah) 493 { 494 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 495 496 regulatory->country_code = CTRY_DEFAULT; 497 regulatory->power_limit = MAX_RATE_POWER; 498 499 ah->hw_version.magic = AR5416_MAGIC; 500 ah->hw_version.subvendorid = 0; 501 502 ah->atim_window = 0; 503 ah->sta_id1_defaults = 504 AR_STA_ID1_CRPT_MIC_ENABLE | 505 AR_STA_ID1_MCAST_KSRCH; 506 if (AR_SREV_9100(ah)) 507 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 508 ah->slottime = ATH9K_SLOT_TIME_9; 509 ah->globaltxtimeout = (u32) -1; 510 ah->power_mode = ATH9K_PM_UNDEFINED; 511 ah->htc_reset_init = true; 512 } 513 514 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 515 { 516 struct ath_common *common = ath9k_hw_common(ah); 517 u32 sum; 518 int i; 519 u16 eeval; 520 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 521 522 sum = 0; 523 for (i = 0; i < 3; i++) { 524 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 525 sum += eeval; 526 common->macaddr[2 * i] = eeval >> 8; 527 common->macaddr[2 * i + 1] = eeval & 0xff; 528 } 529 if (sum == 0 || sum == 0xffff * 3) 530 return -EADDRNOTAVAIL; 531 532 return 0; 533 } 534 535 static int ath9k_hw_post_init(struct ath_hw *ah) 536 { 537 struct ath_common *common = ath9k_hw_common(ah); 538 int ecode; 539 540 if (common->bus_ops->ath_bus_type != ATH_USB) { 541 if (!ath9k_hw_chip_test(ah)) 542 return -ENODEV; 543 } 544 545 if (!AR_SREV_9300_20_OR_LATER(ah)) { 546 ecode = ar9002_hw_rf_claim(ah); 547 if (ecode != 0) 548 return ecode; 549 } 550 551 ecode = ath9k_hw_eeprom_init(ah); 552 if (ecode != 0) 553 return ecode; 554 555 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 556 ah->eep_ops->get_eeprom_ver(ah), 557 ah->eep_ops->get_eeprom_rev(ah)); 558 559 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 560 if (ecode) { 561 ath_err(ath9k_hw_common(ah), 562 "Failed allocating banks for external radio\n"); 563 ath9k_hw_rf_free_ext_banks(ah); 564 return ecode; 565 } 566 567 if (ah->config.enable_ani) { 568 ath9k_hw_ani_setup(ah); 569 ath9k_hw_ani_init(ah); 570 } 571 572 return 0; 573 } 574 575 static void ath9k_hw_attach_ops(struct ath_hw *ah) 576 { 577 if (AR_SREV_9300_20_OR_LATER(ah)) 578 ar9003_hw_attach_ops(ah); 579 else 580 ar9002_hw_attach_ops(ah); 581 } 582 583 /* Called for all hardware families */ 584 static int __ath9k_hw_init(struct ath_hw *ah) 585 { 586 struct ath_common *common = ath9k_hw_common(ah); 587 int r = 0; 588 589 ath9k_hw_read_revisions(ah); 590 591 /* 592 * Read back AR_WA into a permanent copy and set bits 14 and 17. 593 * We need to do this to avoid RMW of this register. We cannot 594 * read the reg when chip is asleep. 595 */ 596 ah->WARegVal = REG_READ(ah, AR_WA); 597 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 598 AR_WA_ASPM_TIMER_BASED_DISABLE); 599 600 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 601 ath_err(common, "Couldn't reset chip\n"); 602 return -EIO; 603 } 604 605 if (AR_SREV_9462(ah)) 606 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 607 608 ath9k_hw_init_defaults(ah); 609 ath9k_hw_init_config(ah); 610 611 ath9k_hw_attach_ops(ah); 612 613 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 614 ath_err(common, "Couldn't wakeup chip\n"); 615 return -EIO; 616 } 617 618 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 619 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 620 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 621 !ah->is_pciexpress)) { 622 ah->config.serialize_regmode = 623 SER_REG_MODE_ON; 624 } else { 625 ah->config.serialize_regmode = 626 SER_REG_MODE_OFF; 627 } 628 } 629 630 ath_dbg(common, RESET, "serialize_regmode is %d\n", 631 ah->config.serialize_regmode); 632 633 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 634 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 635 else 636 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 637 638 switch (ah->hw_version.macVersion) { 639 case AR_SREV_VERSION_5416_PCI: 640 case AR_SREV_VERSION_5416_PCIE: 641 case AR_SREV_VERSION_9160: 642 case AR_SREV_VERSION_9100: 643 case AR_SREV_VERSION_9280: 644 case AR_SREV_VERSION_9285: 645 case AR_SREV_VERSION_9287: 646 case AR_SREV_VERSION_9271: 647 case AR_SREV_VERSION_9300: 648 case AR_SREV_VERSION_9330: 649 case AR_SREV_VERSION_9485: 650 case AR_SREV_VERSION_9340: 651 case AR_SREV_VERSION_9462: 652 case AR_SREV_VERSION_9550: 653 break; 654 default: 655 ath_err(common, 656 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 657 ah->hw_version.macVersion, ah->hw_version.macRev); 658 return -EOPNOTSUPP; 659 } 660 661 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 662 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 663 ah->is_pciexpress = false; 664 665 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 666 ath9k_hw_init_cal_settings(ah); 667 668 ah->ani_function = ATH9K_ANI_ALL; 669 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 671 if (!AR_SREV_9300_20_OR_LATER(ah)) 672 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 673 674 ath9k_hw_init_mode_regs(ah); 675 676 if (!ah->is_pciexpress) 677 ath9k_hw_disablepcie(ah); 678 679 r = ath9k_hw_post_init(ah); 680 if (r) 681 return r; 682 683 ath9k_hw_init_mode_gain_regs(ah); 684 r = ath9k_hw_fill_cap_info(ah); 685 if (r) 686 return r; 687 688 r = ath9k_hw_init_macaddr(ah); 689 if (r) { 690 ath_err(common, "Failed to initialize MAC address\n"); 691 return r; 692 } 693 694 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 695 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 696 else 697 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 698 699 if (AR_SREV_9330(ah)) 700 ah->bb_watchdog_timeout_ms = 85; 701 else 702 ah->bb_watchdog_timeout_ms = 25; 703 704 common->state = ATH_HW_INITIALIZED; 705 706 return 0; 707 } 708 709 int ath9k_hw_init(struct ath_hw *ah) 710 { 711 int ret; 712 struct ath_common *common = ath9k_hw_common(ah); 713 714 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 715 switch (ah->hw_version.devid) { 716 case AR5416_DEVID_PCI: 717 case AR5416_DEVID_PCIE: 718 case AR5416_AR9100_DEVID: 719 case AR9160_DEVID_PCI: 720 case AR9280_DEVID_PCI: 721 case AR9280_DEVID_PCIE: 722 case AR9285_DEVID_PCIE: 723 case AR9287_DEVID_PCI: 724 case AR9287_DEVID_PCIE: 725 case AR2427_DEVID_PCIE: 726 case AR9300_DEVID_PCIE: 727 case AR9300_DEVID_AR9485_PCIE: 728 case AR9300_DEVID_AR9330: 729 case AR9300_DEVID_AR9340: 730 case AR9300_DEVID_QCA955X: 731 case AR9300_DEVID_AR9580: 732 case AR9300_DEVID_AR9462: 733 case AR9485_DEVID_AR1111: 734 break; 735 default: 736 if (common->bus_ops->ath_bus_type == ATH_USB) 737 break; 738 ath_err(common, "Hardware device ID 0x%04x not supported\n", 739 ah->hw_version.devid); 740 return -EOPNOTSUPP; 741 } 742 743 ret = __ath9k_hw_init(ah); 744 if (ret) { 745 ath_err(common, 746 "Unable to initialize hardware; initialization status: %d\n", 747 ret); 748 return ret; 749 } 750 751 return 0; 752 } 753 EXPORT_SYMBOL(ath9k_hw_init); 754 755 static void ath9k_hw_init_qos(struct ath_hw *ah) 756 { 757 ENABLE_REGWRITE_BUFFER(ah); 758 759 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 760 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 761 762 REG_WRITE(ah, AR_QOS_NO_ACK, 763 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 764 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 765 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 766 767 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 768 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 769 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 770 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 771 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 772 773 REGWRITE_BUFFER_FLUSH(ah); 774 } 775 776 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 777 { 778 struct ath_common *common = ath9k_hw_common(ah); 779 int i = 0; 780 781 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 782 udelay(100); 783 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 784 785 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 786 787 udelay(100); 788 789 if (WARN_ON_ONCE(i >= 100)) { 790 ath_err(common, "PLL4 meaurement not done\n"); 791 break; 792 } 793 794 i++; 795 } 796 797 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 798 } 799 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 800 801 static void ath9k_hw_init_pll(struct ath_hw *ah, 802 struct ath9k_channel *chan) 803 { 804 u32 pll; 805 806 if (AR_SREV_9485(ah)) { 807 808 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 810 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 811 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 812 AR_CH0_DPLL2_KD, 0x40); 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 814 AR_CH0_DPLL2_KI, 0x4); 815 816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 817 AR_CH0_BB_DPLL1_REFDIV, 0x5); 818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 819 AR_CH0_BB_DPLL1_NINI, 0x58); 820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 821 AR_CH0_BB_DPLL1_NFRAC, 0x0); 822 823 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 824 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 826 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 828 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 829 830 /* program BB PLL phase_shift to 0x6 */ 831 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 832 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 833 834 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 835 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 836 udelay(1000); 837 } else if (AR_SREV_9330(ah)) { 838 u32 ddr_dpll2, pll_control2, kd; 839 840 if (ah->is_clk_25mhz) { 841 ddr_dpll2 = 0x18e82f01; 842 pll_control2 = 0xe04a3d; 843 kd = 0x1d; 844 } else { 845 ddr_dpll2 = 0x19e82f01; 846 pll_control2 = 0x886666; 847 kd = 0x3d; 848 } 849 850 /* program DDR PLL ki and kd value */ 851 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 852 853 /* program DDR PLL phase_shift */ 854 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 855 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 856 857 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 858 udelay(1000); 859 860 /* program refdiv, nint, frac to RTC register */ 861 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 862 863 /* program BB PLL kd and ki value */ 864 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 865 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 866 867 /* program BB PLL phase_shift */ 868 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 869 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 870 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 871 u32 regval, pll2_divint, pll2_divfrac, refdiv; 872 873 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 874 udelay(1000); 875 876 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 877 udelay(100); 878 879 if (ah->is_clk_25mhz) { 880 pll2_divint = 0x54; 881 pll2_divfrac = 0x1eb85; 882 refdiv = 3; 883 } else { 884 if (AR_SREV_9340(ah)) { 885 pll2_divint = 88; 886 pll2_divfrac = 0; 887 refdiv = 5; 888 } else { 889 pll2_divint = 0x11; 890 pll2_divfrac = 0x26666; 891 refdiv = 1; 892 } 893 } 894 895 regval = REG_READ(ah, AR_PHY_PLL_MODE); 896 regval |= (0x1 << 16); 897 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 898 udelay(100); 899 900 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 901 (pll2_divint << 18) | pll2_divfrac); 902 udelay(100); 903 904 regval = REG_READ(ah, AR_PHY_PLL_MODE); 905 if (AR_SREV_9340(ah)) 906 regval = (regval & 0x80071fff) | (0x1 << 30) | 907 (0x1 << 13) | (0x4 << 26) | (0x18 << 19); 908 else 909 regval = (regval & 0x80071fff) | (0x3 << 30) | 910 (0x1 << 13) | (0x4 << 26) | (0x60 << 19); 911 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 912 REG_WRITE(ah, AR_PHY_PLL_MODE, 913 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 914 udelay(1000); 915 } 916 917 pll = ath9k_hw_compute_pll_control(ah, chan); 918 919 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 920 921 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 922 AR_SREV_9550(ah)) 923 udelay(1000); 924 925 /* Switch the core clock for ar9271 to 117Mhz */ 926 if (AR_SREV_9271(ah)) { 927 udelay(500); 928 REG_WRITE(ah, 0x50040, 0x304); 929 } 930 931 udelay(RTC_PLL_SETTLE_DELAY); 932 933 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 934 935 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 936 if (ah->is_clk_25mhz) { 937 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 938 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 939 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 940 } else { 941 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 942 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 943 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 944 } 945 udelay(100); 946 } 947 } 948 949 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 950 enum nl80211_iftype opmode) 951 { 952 u32 sync_default = AR_INTR_SYNC_DEFAULT; 953 u32 imr_reg = AR_IMR_TXERR | 954 AR_IMR_TXURN | 955 AR_IMR_RXERR | 956 AR_IMR_RXORN | 957 AR_IMR_BCNMISC; 958 959 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) 960 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 961 962 if (AR_SREV_9300_20_OR_LATER(ah)) { 963 imr_reg |= AR_IMR_RXOK_HP; 964 if (ah->config.rx_intr_mitigation) 965 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 966 else 967 imr_reg |= AR_IMR_RXOK_LP; 968 969 } else { 970 if (ah->config.rx_intr_mitigation) 971 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 972 else 973 imr_reg |= AR_IMR_RXOK; 974 } 975 976 if (ah->config.tx_intr_mitigation) 977 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 978 else 979 imr_reg |= AR_IMR_TXOK; 980 981 if (opmode == NL80211_IFTYPE_AP) 982 imr_reg |= AR_IMR_MIB; 983 984 ENABLE_REGWRITE_BUFFER(ah); 985 986 REG_WRITE(ah, AR_IMR, imr_reg); 987 ah->imrs2_reg |= AR_IMR_S2_GTT; 988 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 989 990 if (!AR_SREV_9100(ah)) { 991 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 992 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 993 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 994 } 995 996 REGWRITE_BUFFER_FLUSH(ah); 997 998 if (AR_SREV_9300_20_OR_LATER(ah)) { 999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 1000 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 1002 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 1003 } 1004 } 1005 1006 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 1007 { 1008 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 1009 val = min(val, (u32) 0xFFFF); 1010 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 1011 } 1012 1013 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1014 { 1015 u32 val = ath9k_hw_mac_to_clks(ah, us); 1016 val = min(val, (u32) 0xFFFF); 1017 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1018 } 1019 1020 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1021 { 1022 u32 val = ath9k_hw_mac_to_clks(ah, us); 1023 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1024 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1025 } 1026 1027 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1028 { 1029 u32 val = ath9k_hw_mac_to_clks(ah, us); 1030 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1031 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1032 } 1033 1034 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1035 { 1036 if (tu > 0xFFFF) { 1037 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1038 tu); 1039 ah->globaltxtimeout = (u32) -1; 1040 return false; 1041 } else { 1042 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1043 ah->globaltxtimeout = tu; 1044 return true; 1045 } 1046 } 1047 1048 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1049 { 1050 struct ath_common *common = ath9k_hw_common(ah); 1051 struct ieee80211_conf *conf = &common->hw->conf; 1052 const struct ath9k_channel *chan = ah->curchan; 1053 int acktimeout, ctstimeout, ack_offset = 0; 1054 int slottime; 1055 int sifstime; 1056 int rx_lat = 0, tx_lat = 0, eifs = 0; 1057 u32 reg; 1058 1059 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1060 ah->misc_mode); 1061 1062 if (!chan) 1063 return; 1064 1065 if (ah->misc_mode != 0) 1066 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1067 1068 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1069 rx_lat = 41; 1070 else 1071 rx_lat = 37; 1072 tx_lat = 54; 1073 1074 if (IS_CHAN_5GHZ(chan)) 1075 sifstime = 16; 1076 else 1077 sifstime = 10; 1078 1079 if (IS_CHAN_HALF_RATE(chan)) { 1080 eifs = 175; 1081 rx_lat *= 2; 1082 tx_lat *= 2; 1083 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1084 tx_lat += 11; 1085 1086 sifstime *= 2; 1087 ack_offset = 16; 1088 slottime = 13; 1089 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1090 eifs = 340; 1091 rx_lat = (rx_lat * 4) - 1; 1092 tx_lat *= 4; 1093 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1094 tx_lat += 22; 1095 1096 sifstime *= 4; 1097 ack_offset = 32; 1098 slottime = 21; 1099 } else { 1100 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1101 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1102 reg = AR_USEC_ASYNC_FIFO; 1103 } else { 1104 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1105 common->clockrate; 1106 reg = REG_READ(ah, AR_USEC); 1107 } 1108 rx_lat = MS(reg, AR_USEC_RX_LAT); 1109 tx_lat = MS(reg, AR_USEC_TX_LAT); 1110 1111 slottime = ah->slottime; 1112 } 1113 1114 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1115 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset; 1116 ctstimeout = acktimeout; 1117 1118 /* 1119 * Workaround for early ACK timeouts, add an offset to match the 1120 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1121 * This was initially only meant to work around an issue with delayed 1122 * BA frames in some implementations, but it has been found to fix ACK 1123 * timeout issues in other cases as well. 1124 */ 1125 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ && 1126 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1127 acktimeout += 64 - sifstime - ah->slottime; 1128 ctstimeout += 48 - sifstime - ah->slottime; 1129 } 1130 1131 1132 ath9k_hw_set_sifs_time(ah, sifstime); 1133 ath9k_hw_setslottime(ah, slottime); 1134 ath9k_hw_set_ack_timeout(ah, acktimeout); 1135 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1136 if (ah->globaltxtimeout != (u32) -1) 1137 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1138 1139 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1140 REG_RMW(ah, AR_USEC, 1141 (common->clockrate - 1) | 1142 SM(rx_lat, AR_USEC_RX_LAT) | 1143 SM(tx_lat, AR_USEC_TX_LAT), 1144 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1145 1146 } 1147 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1148 1149 void ath9k_hw_deinit(struct ath_hw *ah) 1150 { 1151 struct ath_common *common = ath9k_hw_common(ah); 1152 1153 if (common->state < ATH_HW_INITIALIZED) 1154 goto free_hw; 1155 1156 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1157 1158 free_hw: 1159 ath9k_hw_rf_free_ext_banks(ah); 1160 } 1161 EXPORT_SYMBOL(ath9k_hw_deinit); 1162 1163 /*******/ 1164 /* INI */ 1165 /*******/ 1166 1167 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1168 { 1169 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1170 1171 if (IS_CHAN_B(chan)) 1172 ctl |= CTL_11B; 1173 else if (IS_CHAN_G(chan)) 1174 ctl |= CTL_11G; 1175 else 1176 ctl |= CTL_11A; 1177 1178 return ctl; 1179 } 1180 1181 /****************************************/ 1182 /* Reset and Channel Switching Routines */ 1183 /****************************************/ 1184 1185 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1186 { 1187 struct ath_common *common = ath9k_hw_common(ah); 1188 1189 ENABLE_REGWRITE_BUFFER(ah); 1190 1191 /* 1192 * set AHB_MODE not to do cacheline prefetches 1193 */ 1194 if (!AR_SREV_9300_20_OR_LATER(ah)) 1195 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1196 1197 /* 1198 * let mac dma reads be in 128 byte chunks 1199 */ 1200 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1201 1202 REGWRITE_BUFFER_FLUSH(ah); 1203 1204 /* 1205 * Restore TX Trigger Level to its pre-reset value. 1206 * The initial value depends on whether aggregation is enabled, and is 1207 * adjusted whenever underruns are detected. 1208 */ 1209 if (!AR_SREV_9300_20_OR_LATER(ah)) 1210 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1211 1212 ENABLE_REGWRITE_BUFFER(ah); 1213 1214 /* 1215 * let mac dma writes be in 128 byte chunks 1216 */ 1217 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1218 1219 /* 1220 * Setup receive FIFO threshold to hold off TX activities 1221 */ 1222 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1223 1224 if (AR_SREV_9300_20_OR_LATER(ah)) { 1225 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1226 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1227 1228 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1229 ah->caps.rx_status_len); 1230 } 1231 1232 /* 1233 * reduce the number of usable entries in PCU TXBUF to avoid 1234 * wrap around issues. 1235 */ 1236 if (AR_SREV_9285(ah)) { 1237 /* For AR9285 the number of Fifos are reduced to half. 1238 * So set the usable tx buf size also to half to 1239 * avoid data/delimiter underruns 1240 */ 1241 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1242 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1243 } else if (!AR_SREV_9271(ah)) { 1244 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1245 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1246 } 1247 1248 REGWRITE_BUFFER_FLUSH(ah); 1249 1250 if (AR_SREV_9300_20_OR_LATER(ah)) 1251 ath9k_hw_reset_txstatus_ring(ah); 1252 } 1253 1254 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1255 { 1256 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1257 u32 set = AR_STA_ID1_KSRCH_MODE; 1258 1259 switch (opmode) { 1260 case NL80211_IFTYPE_ADHOC: 1261 case NL80211_IFTYPE_MESH_POINT: 1262 set |= AR_STA_ID1_ADHOC; 1263 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1264 break; 1265 case NL80211_IFTYPE_AP: 1266 set |= AR_STA_ID1_STA_AP; 1267 /* fall through */ 1268 case NL80211_IFTYPE_STATION: 1269 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1270 break; 1271 default: 1272 if (!ah->is_monitoring) 1273 set = 0; 1274 break; 1275 } 1276 REG_RMW(ah, AR_STA_ID1, set, mask); 1277 } 1278 1279 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1280 u32 *coef_mantissa, u32 *coef_exponent) 1281 { 1282 u32 coef_exp, coef_man; 1283 1284 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1285 if ((coef_scaled >> coef_exp) & 0x1) 1286 break; 1287 1288 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1289 1290 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1291 1292 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1293 *coef_exponent = coef_exp - 16; 1294 } 1295 1296 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1297 { 1298 u32 rst_flags; 1299 u32 tmpReg; 1300 1301 if (AR_SREV_9100(ah)) { 1302 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1303 AR_RTC_DERIVED_CLK_PERIOD, 1); 1304 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1305 } 1306 1307 ENABLE_REGWRITE_BUFFER(ah); 1308 1309 if (AR_SREV_9300_20_OR_LATER(ah)) { 1310 REG_WRITE(ah, AR_WA, ah->WARegVal); 1311 udelay(10); 1312 } 1313 1314 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1315 AR_RTC_FORCE_WAKE_ON_INT); 1316 1317 if (AR_SREV_9100(ah)) { 1318 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1319 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1320 } else { 1321 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1322 if (tmpReg & 1323 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1324 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1325 u32 val; 1326 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1327 1328 val = AR_RC_HOSTIF; 1329 if (!AR_SREV_9300_20_OR_LATER(ah)) 1330 val |= AR_RC_AHB; 1331 REG_WRITE(ah, AR_RC, val); 1332 1333 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1334 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1335 1336 rst_flags = AR_RTC_RC_MAC_WARM; 1337 if (type == ATH9K_RESET_COLD) 1338 rst_flags |= AR_RTC_RC_MAC_COLD; 1339 } 1340 1341 if (AR_SREV_9330(ah)) { 1342 int npend = 0; 1343 int i; 1344 1345 /* AR9330 WAR: 1346 * call external reset function to reset WMAC if: 1347 * - doing a cold reset 1348 * - we have pending frames in the TX queues 1349 */ 1350 1351 for (i = 0; i < AR_NUM_QCU; i++) { 1352 npend = ath9k_hw_numtxpending(ah, i); 1353 if (npend) 1354 break; 1355 } 1356 1357 if (ah->external_reset && 1358 (npend || type == ATH9K_RESET_COLD)) { 1359 int reset_err = 0; 1360 1361 ath_dbg(ath9k_hw_common(ah), RESET, 1362 "reset MAC via external reset\n"); 1363 1364 reset_err = ah->external_reset(); 1365 if (reset_err) { 1366 ath_err(ath9k_hw_common(ah), 1367 "External reset failed, err=%d\n", 1368 reset_err); 1369 return false; 1370 } 1371 1372 REG_WRITE(ah, AR_RTC_RESET, 1); 1373 } 1374 } 1375 1376 if (ath9k_hw_mci_is_enabled(ah)) 1377 ar9003_mci_check_gpm_offset(ah); 1378 1379 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1380 1381 REGWRITE_BUFFER_FLUSH(ah); 1382 1383 udelay(50); 1384 1385 REG_WRITE(ah, AR_RTC_RC, 0); 1386 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1387 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1388 return false; 1389 } 1390 1391 if (!AR_SREV_9100(ah)) 1392 REG_WRITE(ah, AR_RC, 0); 1393 1394 if (AR_SREV_9100(ah)) 1395 udelay(50); 1396 1397 return true; 1398 } 1399 1400 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1401 { 1402 ENABLE_REGWRITE_BUFFER(ah); 1403 1404 if (AR_SREV_9300_20_OR_LATER(ah)) { 1405 REG_WRITE(ah, AR_WA, ah->WARegVal); 1406 udelay(10); 1407 } 1408 1409 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1410 AR_RTC_FORCE_WAKE_ON_INT); 1411 1412 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1413 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1414 1415 REG_WRITE(ah, AR_RTC_RESET, 0); 1416 1417 REGWRITE_BUFFER_FLUSH(ah); 1418 1419 if (!AR_SREV_9300_20_OR_LATER(ah)) 1420 udelay(2); 1421 1422 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1423 REG_WRITE(ah, AR_RC, 0); 1424 1425 REG_WRITE(ah, AR_RTC_RESET, 1); 1426 1427 if (!ath9k_hw_wait(ah, 1428 AR_RTC_STATUS, 1429 AR_RTC_STATUS_M, 1430 AR_RTC_STATUS_ON, 1431 AH_WAIT_TIMEOUT)) { 1432 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1433 return false; 1434 } 1435 1436 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1437 } 1438 1439 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1440 { 1441 bool ret = false; 1442 1443 if (AR_SREV_9300_20_OR_LATER(ah)) { 1444 REG_WRITE(ah, AR_WA, ah->WARegVal); 1445 udelay(10); 1446 } 1447 1448 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1449 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1450 1451 switch (type) { 1452 case ATH9K_RESET_POWER_ON: 1453 ret = ath9k_hw_set_reset_power_on(ah); 1454 break; 1455 case ATH9K_RESET_WARM: 1456 case ATH9K_RESET_COLD: 1457 ret = ath9k_hw_set_reset(ah, type); 1458 break; 1459 default: 1460 break; 1461 } 1462 1463 return ret; 1464 } 1465 1466 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1467 struct ath9k_channel *chan) 1468 { 1469 int reset_type = ATH9K_RESET_WARM; 1470 1471 if (AR_SREV_9280(ah)) { 1472 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1473 reset_type = ATH9K_RESET_POWER_ON; 1474 else 1475 reset_type = ATH9K_RESET_COLD; 1476 } 1477 1478 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1479 return false; 1480 1481 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1482 return false; 1483 1484 ah->chip_fullsleep = false; 1485 1486 if (AR_SREV_9330(ah)) 1487 ar9003_hw_internal_regulator_apply(ah); 1488 ath9k_hw_init_pll(ah, chan); 1489 ath9k_hw_set_rfmode(ah, chan); 1490 1491 return true; 1492 } 1493 1494 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1495 struct ath9k_channel *chan) 1496 { 1497 struct ath_common *common = ath9k_hw_common(ah); 1498 u32 qnum; 1499 int r; 1500 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1501 bool band_switch, mode_diff; 1502 u8 ini_reloaded; 1503 1504 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1505 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1506 CHANNEL_5GHZ)); 1507 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1508 1509 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1510 if (ath9k_hw_numtxpending(ah, qnum)) { 1511 ath_dbg(common, QUEUE, 1512 "Transmit frames pending on queue %d\n", qnum); 1513 return false; 1514 } 1515 } 1516 1517 if (!ath9k_hw_rfbus_req(ah)) { 1518 ath_err(common, "Could not kill baseband RX\n"); 1519 return false; 1520 } 1521 1522 if (edma && (band_switch || mode_diff)) { 1523 ath9k_hw_mark_phy_inactive(ah); 1524 udelay(5); 1525 1526 ath9k_hw_init_pll(ah, NULL); 1527 1528 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1529 ath_err(common, "Failed to do fast channel change\n"); 1530 return false; 1531 } 1532 } 1533 1534 ath9k_hw_set_channel_regs(ah, chan); 1535 1536 r = ath9k_hw_rf_set_freq(ah, chan); 1537 if (r) { 1538 ath_err(common, "Failed to set channel\n"); 1539 return false; 1540 } 1541 ath9k_hw_set_clockrate(ah); 1542 ath9k_hw_apply_txpower(ah, chan, false); 1543 ath9k_hw_rfbus_done(ah); 1544 1545 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1546 ath9k_hw_set_delta_slope(ah, chan); 1547 1548 ath9k_hw_spur_mitigate_freq(ah, chan); 1549 1550 if (edma && (band_switch || mode_diff)) { 1551 ah->ah_flags |= AH_FASTCC; 1552 if (band_switch || ini_reloaded) 1553 ah->eep_ops->set_board_values(ah, chan); 1554 1555 ath9k_hw_init_bb(ah, chan); 1556 1557 if (band_switch || ini_reloaded) 1558 ath9k_hw_init_cal(ah, chan); 1559 ah->ah_flags &= ~AH_FASTCC; 1560 } 1561 1562 return true; 1563 } 1564 1565 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1566 { 1567 u32 gpio_mask = ah->gpio_mask; 1568 int i; 1569 1570 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1571 if (!(gpio_mask & 1)) 1572 continue; 1573 1574 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1575 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1576 } 1577 } 1578 1579 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1580 int *hang_state, int *hang_pos) 1581 { 1582 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1583 u32 chain_state, dcs_pos, i; 1584 1585 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1586 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1587 for (i = 0; i < 3; i++) { 1588 if (chain_state == dcu_chain_state[i]) { 1589 *hang_state = chain_state; 1590 *hang_pos = dcs_pos; 1591 return true; 1592 } 1593 } 1594 } 1595 return false; 1596 } 1597 1598 #define DCU_COMPLETE_STATE 1 1599 #define DCU_COMPLETE_STATE_MASK 0x3 1600 #define NUM_STATUS_READS 50 1601 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1602 { 1603 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1604 u32 i, hang_pos, hang_state, num_state = 6; 1605 1606 comp_state = REG_READ(ah, AR_DMADBG_6); 1607 1608 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1609 ath_dbg(ath9k_hw_common(ah), RESET, 1610 "MAC Hang signature not found at DCU complete\n"); 1611 return false; 1612 } 1613 1614 chain_state = REG_READ(ah, dcs_reg); 1615 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1616 goto hang_check_iter; 1617 1618 dcs_reg = AR_DMADBG_5; 1619 num_state = 4; 1620 chain_state = REG_READ(ah, dcs_reg); 1621 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1622 goto hang_check_iter; 1623 1624 ath_dbg(ath9k_hw_common(ah), RESET, 1625 "MAC Hang signature 1 not found\n"); 1626 return false; 1627 1628 hang_check_iter: 1629 ath_dbg(ath9k_hw_common(ah), RESET, 1630 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1631 chain_state, comp_state, hang_state, hang_pos); 1632 1633 for (i = 0; i < NUM_STATUS_READS; i++) { 1634 chain_state = REG_READ(ah, dcs_reg); 1635 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1636 comp_state = REG_READ(ah, AR_DMADBG_6); 1637 1638 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1639 DCU_COMPLETE_STATE) || 1640 (chain_state != hang_state)) 1641 return false; 1642 } 1643 1644 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1645 1646 return true; 1647 } 1648 1649 bool ath9k_hw_check_alive(struct ath_hw *ah) 1650 { 1651 int count = 50; 1652 u32 reg; 1653 1654 if (AR_SREV_9300(ah)) 1655 return !ath9k_hw_detect_mac_hang(ah); 1656 1657 if (AR_SREV_9285_12_OR_LATER(ah)) 1658 return true; 1659 1660 do { 1661 reg = REG_READ(ah, AR_OBS_BUS_1); 1662 1663 if ((reg & 0x7E7FFFEF) == 0x00702400) 1664 continue; 1665 1666 switch (reg & 0x7E000B00) { 1667 case 0x1E000000: 1668 case 0x52000B00: 1669 case 0x18000B00: 1670 continue; 1671 default: 1672 return true; 1673 } 1674 } while (count-- > 0); 1675 1676 return false; 1677 } 1678 EXPORT_SYMBOL(ath9k_hw_check_alive); 1679 1680 /* 1681 * Fast channel change: 1682 * (Change synthesizer based on channel freq without resetting chip) 1683 * 1684 * Don't do FCC when 1685 * - Flag is not set 1686 * - Chip is just coming out of full sleep 1687 * - Channel to be set is same as current channel 1688 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel) 1689 */ 1690 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1691 { 1692 struct ath_common *common = ath9k_hw_common(ah); 1693 int ret; 1694 1695 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1696 goto fail; 1697 1698 if (ah->chip_fullsleep) 1699 goto fail; 1700 1701 if (!ah->curchan) 1702 goto fail; 1703 1704 if (chan->channel == ah->curchan->channel) 1705 goto fail; 1706 1707 if ((ah->curchan->channelFlags | chan->channelFlags) & 1708 (CHANNEL_HALF | CHANNEL_QUARTER)) 1709 goto fail; 1710 1711 if ((chan->channelFlags & CHANNEL_ALL) != 1712 (ah->curchan->channelFlags & CHANNEL_ALL)) 1713 goto fail; 1714 1715 if (!ath9k_hw_check_alive(ah)) 1716 goto fail; 1717 1718 /* 1719 * For AR9462, make sure that calibration data for 1720 * re-using are present. 1721 */ 1722 if (AR_SREV_9462(ah) && (ah->caldata && 1723 (!ah->caldata->done_txiqcal_once || 1724 !ah->caldata->done_txclcal_once || 1725 !ah->caldata->rtt_done))) 1726 goto fail; 1727 1728 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1729 ah->curchan->channel, chan->channel); 1730 1731 ret = ath9k_hw_channel_change(ah, chan); 1732 if (!ret) 1733 goto fail; 1734 1735 ath9k_hw_loadnf(ah, ah->curchan); 1736 ath9k_hw_start_nfcal(ah, true); 1737 1738 if (ath9k_hw_mci_is_enabled(ah)) 1739 ar9003_mci_2g5g_switch(ah, false); 1740 1741 if (AR_SREV_9271(ah)) 1742 ar9002_hw_load_ani_reg(ah, chan); 1743 1744 return 0; 1745 fail: 1746 return -EINVAL; 1747 } 1748 1749 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1750 struct ath9k_hw_cal_data *caldata, bool fastcc) 1751 { 1752 struct ath_common *common = ath9k_hw_common(ah); 1753 u32 saveLedState; 1754 u32 saveDefAntenna; 1755 u32 macStaId1; 1756 u64 tsf = 0; 1757 int i, r; 1758 bool start_mci_reset = false; 1759 bool save_fullsleep = ah->chip_fullsleep; 1760 1761 if (ath9k_hw_mci_is_enabled(ah)) { 1762 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1763 if (start_mci_reset) 1764 return 0; 1765 } 1766 1767 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1768 return -EIO; 1769 1770 if (ah->curchan && !ah->chip_fullsleep) 1771 ath9k_hw_getnf(ah, ah->curchan); 1772 1773 ah->caldata = caldata; 1774 if (caldata && 1775 (chan->channel != caldata->channel || 1776 (chan->channelFlags & ~CHANNEL_CW_INT) != 1777 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1778 /* Operating channel changed, reset channel calibration data */ 1779 memset(caldata, 0, sizeof(*caldata)); 1780 ath9k_init_nfcal_hist_buffer(ah, chan); 1781 } 1782 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1783 1784 if (fastcc) { 1785 r = ath9k_hw_do_fastcc(ah, chan); 1786 if (!r) 1787 return r; 1788 } 1789 1790 if (ath9k_hw_mci_is_enabled(ah)) 1791 ar9003_mci_stop_bt(ah, save_fullsleep); 1792 1793 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1794 if (saveDefAntenna == 0) 1795 saveDefAntenna = 1; 1796 1797 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1798 1799 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1800 if (AR_SREV_9100(ah) || 1801 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1802 tsf = ath9k_hw_gettsf64(ah); 1803 1804 saveLedState = REG_READ(ah, AR_CFG_LED) & 1805 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1806 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1807 1808 ath9k_hw_mark_phy_inactive(ah); 1809 1810 ah->paprd_table_write_done = false; 1811 1812 /* Only required on the first reset */ 1813 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1814 REG_WRITE(ah, 1815 AR9271_RESET_POWER_DOWN_CONTROL, 1816 AR9271_RADIO_RF_RST); 1817 udelay(50); 1818 } 1819 1820 if (!ath9k_hw_chip_reset(ah, chan)) { 1821 ath_err(common, "Chip reset failed\n"); 1822 return -EINVAL; 1823 } 1824 1825 /* Only required on the first reset */ 1826 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1827 ah->htc_reset_init = false; 1828 REG_WRITE(ah, 1829 AR9271_RESET_POWER_DOWN_CONTROL, 1830 AR9271_GATE_MAC_CTL); 1831 udelay(50); 1832 } 1833 1834 /* Restore TSF */ 1835 if (tsf) 1836 ath9k_hw_settsf64(ah, tsf); 1837 1838 if (AR_SREV_9280_20_OR_LATER(ah)) 1839 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1840 1841 if (!AR_SREV_9300_20_OR_LATER(ah)) 1842 ar9002_hw_enable_async_fifo(ah); 1843 1844 r = ath9k_hw_process_ini(ah, chan); 1845 if (r) 1846 return r; 1847 1848 if (ath9k_hw_mci_is_enabled(ah)) 1849 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1850 1851 /* 1852 * Some AR91xx SoC devices frequently fail to accept TSF writes 1853 * right after the chip reset. When that happens, write a new 1854 * value after the initvals have been applied, with an offset 1855 * based on measured time difference 1856 */ 1857 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1858 tsf += 1500; 1859 ath9k_hw_settsf64(ah, tsf); 1860 } 1861 1862 /* Setup MFP options for CCMP */ 1863 if (AR_SREV_9280_20_OR_LATER(ah)) { 1864 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1865 * frames when constructing CCMP AAD. */ 1866 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1867 0xc7ff); 1868 ah->sw_mgmt_crypto = false; 1869 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1870 /* Disable hardware crypto for management frames */ 1871 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1872 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1873 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1874 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1875 ah->sw_mgmt_crypto = true; 1876 } else 1877 ah->sw_mgmt_crypto = true; 1878 1879 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1880 ath9k_hw_set_delta_slope(ah, chan); 1881 1882 ath9k_hw_spur_mitigate_freq(ah, chan); 1883 ah->eep_ops->set_board_values(ah, chan); 1884 1885 ENABLE_REGWRITE_BUFFER(ah); 1886 1887 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1888 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1889 | macStaId1 1890 | AR_STA_ID1_RTS_USE_DEF 1891 | (ah->config. 1892 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1893 | ah->sta_id1_defaults); 1894 ath_hw_setbssidmask(common); 1895 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1896 ath9k_hw_write_associd(ah); 1897 REG_WRITE(ah, AR_ISR, ~0); 1898 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1899 1900 REGWRITE_BUFFER_FLUSH(ah); 1901 1902 ath9k_hw_set_operating_mode(ah, ah->opmode); 1903 1904 r = ath9k_hw_rf_set_freq(ah, chan); 1905 if (r) 1906 return r; 1907 1908 ath9k_hw_set_clockrate(ah); 1909 1910 ENABLE_REGWRITE_BUFFER(ah); 1911 1912 for (i = 0; i < AR_NUM_DCU; i++) 1913 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1914 1915 REGWRITE_BUFFER_FLUSH(ah); 1916 1917 ah->intr_txqs = 0; 1918 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1919 ath9k_hw_resettxqueue(ah, i); 1920 1921 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1922 ath9k_hw_ani_cache_ini_regs(ah); 1923 ath9k_hw_init_qos(ah); 1924 1925 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1926 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1927 1928 ath9k_hw_init_global_settings(ah); 1929 1930 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1931 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1932 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1933 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1934 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1935 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1936 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1937 } 1938 1939 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1940 1941 ath9k_hw_set_dma(ah); 1942 1943 if (!ath9k_hw_mci_is_enabled(ah)) 1944 REG_WRITE(ah, AR_OBS, 8); 1945 1946 if (ah->config.rx_intr_mitigation) { 1947 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1948 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1949 } 1950 1951 if (ah->config.tx_intr_mitigation) { 1952 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1953 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1954 } 1955 1956 ath9k_hw_init_bb(ah, chan); 1957 1958 if (caldata) { 1959 caldata->done_txiqcal_once = false; 1960 caldata->done_txclcal_once = false; 1961 } 1962 if (!ath9k_hw_init_cal(ah, chan)) 1963 return -EIO; 1964 1965 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1966 return -EIO; 1967 1968 ENABLE_REGWRITE_BUFFER(ah); 1969 1970 ath9k_hw_restore_chainmask(ah); 1971 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1972 1973 REGWRITE_BUFFER_FLUSH(ah); 1974 1975 /* 1976 * For big endian systems turn on swapping for descriptors 1977 */ 1978 if (AR_SREV_9100(ah)) { 1979 u32 mask; 1980 mask = REG_READ(ah, AR_CFG); 1981 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1982 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1983 mask); 1984 } else { 1985 mask = 1986 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1987 REG_WRITE(ah, AR_CFG, mask); 1988 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1989 REG_READ(ah, AR_CFG)); 1990 } 1991 } else { 1992 if (common->bus_ops->ath_bus_type == ATH_USB) { 1993 /* Configure AR9271 target WLAN */ 1994 if (AR_SREV_9271(ah)) 1995 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1996 else 1997 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1998 } 1999 #ifdef __BIG_ENDIAN 2000 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 2001 AR_SREV_9550(ah)) 2002 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 2003 else 2004 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2005 #endif 2006 } 2007 2008 if (ath9k_hw_btcoex_is_enabled(ah)) 2009 ath9k_hw_btcoex_enable(ah); 2010 2011 if (ath9k_hw_mci_is_enabled(ah)) 2012 ar9003_mci_check_bt(ah); 2013 2014 ath9k_hw_loadnf(ah, chan); 2015 ath9k_hw_start_nfcal(ah, true); 2016 2017 if (AR_SREV_9300_20_OR_LATER(ah)) { 2018 ar9003_hw_bb_watchdog_config(ah); 2019 2020 ar9003_hw_disable_phy_restart(ah); 2021 } 2022 2023 ath9k_hw_apply_gpio_override(ah); 2024 2025 return 0; 2026 } 2027 EXPORT_SYMBOL(ath9k_hw_reset); 2028 2029 /******************************/ 2030 /* Power Management (Chipset) */ 2031 /******************************/ 2032 2033 /* 2034 * Notify Power Mgt is disabled in self-generated frames. 2035 * If requested, force chip to sleep. 2036 */ 2037 static void ath9k_set_power_sleep(struct ath_hw *ah) 2038 { 2039 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2040 2041 if (AR_SREV_9462(ah)) { 2042 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2043 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2044 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2045 /* xxx Required for WLAN only case ? */ 2046 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2047 udelay(100); 2048 } 2049 2050 /* 2051 * Clear the RTC force wake bit to allow the 2052 * mac to go to sleep. 2053 */ 2054 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2055 2056 if (ath9k_hw_mci_is_enabled(ah)) 2057 udelay(100); 2058 2059 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2060 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2061 2062 /* Shutdown chip. Active low */ 2063 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2064 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2065 udelay(2); 2066 } 2067 2068 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2069 if (AR_SREV_9300_20_OR_LATER(ah)) 2070 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2071 } 2072 2073 /* 2074 * Notify Power Management is enabled in self-generating 2075 * frames. If request, set power mode of chip to 2076 * auto/normal. Duration in units of 128us (1/8 TU). 2077 */ 2078 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2079 { 2080 struct ath9k_hw_capabilities *pCap = &ah->caps; 2081 2082 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2083 2084 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2085 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2086 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2087 AR_RTC_FORCE_WAKE_ON_INT); 2088 } else { 2089 2090 /* When chip goes into network sleep, it could be waken 2091 * up by MCI_INT interrupt caused by BT's HW messages 2092 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2093 * rate (~100us). This will cause chip to leave and 2094 * re-enter network sleep mode frequently, which in 2095 * consequence will have WLAN MCI HW to generate lots of 2096 * SYS_WAKING and SYS_SLEEPING messages which will make 2097 * BT CPU to busy to process. 2098 */ 2099 if (ath9k_hw_mci_is_enabled(ah)) 2100 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2101 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2102 /* 2103 * Clear the RTC force wake bit to allow the 2104 * mac to go to sleep. 2105 */ 2106 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2107 2108 if (ath9k_hw_mci_is_enabled(ah)) 2109 udelay(30); 2110 } 2111 2112 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2113 if (AR_SREV_9300_20_OR_LATER(ah)) 2114 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2115 } 2116 2117 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2118 { 2119 u32 val; 2120 int i; 2121 2122 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2123 if (AR_SREV_9300_20_OR_LATER(ah)) { 2124 REG_WRITE(ah, AR_WA, ah->WARegVal); 2125 udelay(10); 2126 } 2127 2128 if ((REG_READ(ah, AR_RTC_STATUS) & 2129 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2130 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2131 return false; 2132 } 2133 if (!AR_SREV_9300_20_OR_LATER(ah)) 2134 ath9k_hw_init_pll(ah, NULL); 2135 } 2136 if (AR_SREV_9100(ah)) 2137 REG_SET_BIT(ah, AR_RTC_RESET, 2138 AR_RTC_RESET_EN); 2139 2140 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2141 AR_RTC_FORCE_WAKE_EN); 2142 udelay(50); 2143 2144 if (ath9k_hw_mci_is_enabled(ah)) 2145 ar9003_mci_set_power_awake(ah); 2146 2147 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2148 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2149 if (val == AR_RTC_STATUS_ON) 2150 break; 2151 udelay(50); 2152 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2153 AR_RTC_FORCE_WAKE_EN); 2154 } 2155 if (i == 0) { 2156 ath_err(ath9k_hw_common(ah), 2157 "Failed to wakeup in %uus\n", 2158 POWER_UP_TIME / 20); 2159 return false; 2160 } 2161 2162 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2163 2164 return true; 2165 } 2166 2167 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2168 { 2169 struct ath_common *common = ath9k_hw_common(ah); 2170 int status = true; 2171 static const char *modes[] = { 2172 "AWAKE", 2173 "FULL-SLEEP", 2174 "NETWORK SLEEP", 2175 "UNDEFINED" 2176 }; 2177 2178 if (ah->power_mode == mode) 2179 return status; 2180 2181 ath_dbg(common, RESET, "%s -> %s\n", 2182 modes[ah->power_mode], modes[mode]); 2183 2184 switch (mode) { 2185 case ATH9K_PM_AWAKE: 2186 status = ath9k_hw_set_power_awake(ah); 2187 break; 2188 case ATH9K_PM_FULL_SLEEP: 2189 if (ath9k_hw_mci_is_enabled(ah)) 2190 ar9003_mci_set_full_sleep(ah); 2191 2192 ath9k_set_power_sleep(ah); 2193 ah->chip_fullsleep = true; 2194 break; 2195 case ATH9K_PM_NETWORK_SLEEP: 2196 ath9k_set_power_network_sleep(ah); 2197 break; 2198 default: 2199 ath_err(common, "Unknown power mode %u\n", mode); 2200 return false; 2201 } 2202 ah->power_mode = mode; 2203 2204 /* 2205 * XXX: If this warning never comes up after a while then 2206 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2207 * ath9k_hw_setpower() return type void. 2208 */ 2209 2210 if (!(ah->ah_flags & AH_UNPLUGGED)) 2211 ATH_DBG_WARN_ON_ONCE(!status); 2212 2213 return status; 2214 } 2215 EXPORT_SYMBOL(ath9k_hw_setpower); 2216 2217 /*******************/ 2218 /* Beacon Handling */ 2219 /*******************/ 2220 2221 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2222 { 2223 int flags = 0; 2224 2225 ENABLE_REGWRITE_BUFFER(ah); 2226 2227 switch (ah->opmode) { 2228 case NL80211_IFTYPE_ADHOC: 2229 case NL80211_IFTYPE_MESH_POINT: 2230 REG_SET_BIT(ah, AR_TXCFG, 2231 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2232 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2233 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2234 flags |= AR_NDP_TIMER_EN; 2235 case NL80211_IFTYPE_AP: 2236 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2237 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2238 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2239 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2240 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2241 flags |= 2242 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2243 break; 2244 default: 2245 ath_dbg(ath9k_hw_common(ah), BEACON, 2246 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2247 return; 2248 break; 2249 } 2250 2251 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2252 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2253 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2254 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2255 2256 REGWRITE_BUFFER_FLUSH(ah); 2257 2258 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2259 } 2260 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2261 2262 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2263 const struct ath9k_beacon_state *bs) 2264 { 2265 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2266 struct ath9k_hw_capabilities *pCap = &ah->caps; 2267 struct ath_common *common = ath9k_hw_common(ah); 2268 2269 ENABLE_REGWRITE_BUFFER(ah); 2270 2271 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2272 2273 REG_WRITE(ah, AR_BEACON_PERIOD, 2274 TU_TO_USEC(bs->bs_intval)); 2275 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2276 TU_TO_USEC(bs->bs_intval)); 2277 2278 REGWRITE_BUFFER_FLUSH(ah); 2279 2280 REG_RMW_FIELD(ah, AR_RSSI_THR, 2281 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2282 2283 beaconintval = bs->bs_intval; 2284 2285 if (bs->bs_sleepduration > beaconintval) 2286 beaconintval = bs->bs_sleepduration; 2287 2288 dtimperiod = bs->bs_dtimperiod; 2289 if (bs->bs_sleepduration > dtimperiod) 2290 dtimperiod = bs->bs_sleepduration; 2291 2292 if (beaconintval == dtimperiod) 2293 nextTbtt = bs->bs_nextdtim; 2294 else 2295 nextTbtt = bs->bs_nexttbtt; 2296 2297 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2298 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2299 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2300 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2301 2302 ENABLE_REGWRITE_BUFFER(ah); 2303 2304 REG_WRITE(ah, AR_NEXT_DTIM, 2305 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2306 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2307 2308 REG_WRITE(ah, AR_SLEEP1, 2309 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2310 | AR_SLEEP1_ASSUME_DTIM); 2311 2312 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2313 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2314 else 2315 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2316 2317 REG_WRITE(ah, AR_SLEEP2, 2318 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2319 2320 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2321 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2322 2323 REGWRITE_BUFFER_FLUSH(ah); 2324 2325 REG_SET_BIT(ah, AR_TIMER_MODE, 2326 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2327 AR_DTIM_TIMER_EN); 2328 2329 /* TSF Out of Range Threshold */ 2330 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2331 } 2332 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2333 2334 /*******************/ 2335 /* HW Capabilities */ 2336 /*******************/ 2337 2338 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2339 { 2340 eeprom_chainmask &= chip_chainmask; 2341 if (eeprom_chainmask) 2342 return eeprom_chainmask; 2343 else 2344 return chip_chainmask; 2345 } 2346 2347 /** 2348 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2349 * @ah: the atheros hardware data structure 2350 * 2351 * We enable DFS support upstream on chipsets which have passed a series 2352 * of tests. The testing requirements are going to be documented. Desired 2353 * test requirements are documented at: 2354 * 2355 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2356 * 2357 * Once a new chipset gets properly tested an individual commit can be used 2358 * to document the testing for DFS for that chipset. 2359 */ 2360 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2361 { 2362 2363 switch (ah->hw_version.macVersion) { 2364 /* AR9580 will likely be our first target to get testing on */ 2365 case AR_SREV_VERSION_9580: 2366 default: 2367 return false; 2368 } 2369 } 2370 2371 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2372 { 2373 struct ath9k_hw_capabilities *pCap = &ah->caps; 2374 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2375 struct ath_common *common = ath9k_hw_common(ah); 2376 unsigned int chip_chainmask; 2377 2378 u16 eeval; 2379 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2380 2381 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2382 regulatory->current_rd = eeval; 2383 2384 if (ah->opmode != NL80211_IFTYPE_AP && 2385 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2386 if (regulatory->current_rd == 0x64 || 2387 regulatory->current_rd == 0x65) 2388 regulatory->current_rd += 5; 2389 else if (regulatory->current_rd == 0x41) 2390 regulatory->current_rd = 0x43; 2391 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2392 regulatory->current_rd); 2393 } 2394 2395 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2396 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2397 ath_err(common, 2398 "no band has been marked as supported in EEPROM\n"); 2399 return -EINVAL; 2400 } 2401 2402 if (eeval & AR5416_OPFLAGS_11A) 2403 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2404 2405 if (eeval & AR5416_OPFLAGS_11G) 2406 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2407 2408 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2409 chip_chainmask = 1; 2410 else if (AR_SREV_9462(ah)) 2411 chip_chainmask = 3; 2412 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2413 chip_chainmask = 7; 2414 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2415 chip_chainmask = 3; 2416 else 2417 chip_chainmask = 7; 2418 2419 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2420 /* 2421 * For AR9271 we will temporarilly uses the rx chainmax as read from 2422 * the EEPROM. 2423 */ 2424 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2425 !(eeval & AR5416_OPFLAGS_11A) && 2426 !(AR_SREV_9271(ah))) 2427 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2428 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2429 else if (AR_SREV_9100(ah)) 2430 pCap->rx_chainmask = 0x7; 2431 else 2432 /* Use rx_chainmask from EEPROM. */ 2433 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2434 2435 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2436 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2437 ah->txchainmask = pCap->tx_chainmask; 2438 ah->rxchainmask = pCap->rx_chainmask; 2439 2440 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2441 2442 /* enable key search for every frame in an aggregate */ 2443 if (AR_SREV_9300_20_OR_LATER(ah)) 2444 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2445 2446 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2447 2448 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2449 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2450 else 2451 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2452 2453 if (AR_SREV_9271(ah)) 2454 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2455 else if (AR_DEVID_7010(ah)) 2456 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2457 else if (AR_SREV_9300_20_OR_LATER(ah)) 2458 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2459 else if (AR_SREV_9287_11_OR_LATER(ah)) 2460 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2461 else if (AR_SREV_9285_12_OR_LATER(ah)) 2462 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2463 else if (AR_SREV_9280_20_OR_LATER(ah)) 2464 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2465 else 2466 pCap->num_gpio_pins = AR_NUM_GPIO; 2467 2468 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2469 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2470 else 2471 pCap->rts_aggr_limit = (8 * 1024); 2472 2473 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2474 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2475 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2476 ah->rfkill_gpio = 2477 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2478 ah->rfkill_polarity = 2479 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2480 2481 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2482 } 2483 #endif 2484 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2485 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2486 else 2487 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2488 2489 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2490 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2491 else 2492 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2493 2494 if (AR_SREV_9300_20_OR_LATER(ah)) { 2495 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2496 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2497 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2498 2499 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2500 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2501 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2502 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2503 pCap->txs_len = sizeof(struct ar9003_txs); 2504 if (!ah->config.paprd_disable && 2505 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2506 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2507 } else { 2508 pCap->tx_desc_len = sizeof(struct ath_desc); 2509 if (AR_SREV_9280_20(ah)) 2510 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2511 } 2512 2513 if (AR_SREV_9300_20_OR_LATER(ah)) 2514 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2515 2516 if (AR_SREV_9300_20_OR_LATER(ah)) 2517 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2518 2519 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2520 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2521 2522 if (AR_SREV_9285(ah)) 2523 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2524 ant_div_ctl1 = 2525 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2526 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2527 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2528 } 2529 if (AR_SREV_9300_20_OR_LATER(ah)) { 2530 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2531 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2532 } 2533 2534 2535 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2536 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2537 /* 2538 * enable the diversity-combining algorithm only when 2539 * both enable_lna_div and enable_fast_div are set 2540 * Table for Diversity 2541 * ant_div_alt_lnaconf bit 0-1 2542 * ant_div_main_lnaconf bit 2-3 2543 * ant_div_alt_gaintb bit 4 2544 * ant_div_main_gaintb bit 5 2545 * enable_ant_div_lnadiv bit 6 2546 * enable_ant_fast_div bit 7 2547 */ 2548 if ((ant_div_ctl1 >> 0x6) == 0x3) 2549 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2550 } 2551 2552 if (AR_SREV_9485_10(ah)) { 2553 pCap->pcie_lcr_extsync_en = true; 2554 pCap->pcie_lcr_offset = 0x80; 2555 } 2556 2557 if (ath9k_hw_dfs_tested(ah)) 2558 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2559 2560 tx_chainmask = pCap->tx_chainmask; 2561 rx_chainmask = pCap->rx_chainmask; 2562 while (tx_chainmask || rx_chainmask) { 2563 if (tx_chainmask & BIT(0)) 2564 pCap->max_txchains++; 2565 if (rx_chainmask & BIT(0)) 2566 pCap->max_rxchains++; 2567 2568 tx_chainmask >>= 1; 2569 rx_chainmask >>= 1; 2570 } 2571 2572 if (AR_SREV_9300_20_OR_LATER(ah)) { 2573 ah->enabled_cals |= TX_IQ_CAL; 2574 if (AR_SREV_9485_OR_LATER(ah)) 2575 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2576 } 2577 2578 if (AR_SREV_9462(ah)) { 2579 2580 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2581 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2582 2583 if (AR_SREV_9462_20(ah)) 2584 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2585 2586 } 2587 2588 2589 if (AR_SREV_9280_20_OR_LATER(ah)) { 2590 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE | 2591 ATH9K_HW_WOW_PATTERN_MATCH_EXACT; 2592 2593 if (AR_SREV_9280(ah)) 2594 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD; 2595 } 2596 2597 return 0; 2598 } 2599 2600 /****************************/ 2601 /* GPIO / RFKILL / Antennae */ 2602 /****************************/ 2603 2604 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2605 u32 gpio, u32 type) 2606 { 2607 int addr; 2608 u32 gpio_shift, tmp; 2609 2610 if (gpio > 11) 2611 addr = AR_GPIO_OUTPUT_MUX3; 2612 else if (gpio > 5) 2613 addr = AR_GPIO_OUTPUT_MUX2; 2614 else 2615 addr = AR_GPIO_OUTPUT_MUX1; 2616 2617 gpio_shift = (gpio % 6) * 5; 2618 2619 if (AR_SREV_9280_20_OR_LATER(ah) 2620 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2621 REG_RMW(ah, addr, (type << gpio_shift), 2622 (0x1f << gpio_shift)); 2623 } else { 2624 tmp = REG_READ(ah, addr); 2625 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2626 tmp &= ~(0x1f << gpio_shift); 2627 tmp |= (type << gpio_shift); 2628 REG_WRITE(ah, addr, tmp); 2629 } 2630 } 2631 2632 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2633 { 2634 u32 gpio_shift; 2635 2636 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2637 2638 if (AR_DEVID_7010(ah)) { 2639 gpio_shift = gpio; 2640 REG_RMW(ah, AR7010_GPIO_OE, 2641 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2642 (AR7010_GPIO_OE_MASK << gpio_shift)); 2643 return; 2644 } 2645 2646 gpio_shift = gpio << 1; 2647 REG_RMW(ah, 2648 AR_GPIO_OE_OUT, 2649 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2650 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2651 } 2652 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2653 2654 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2655 { 2656 #define MS_REG_READ(x, y) \ 2657 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2658 2659 if (gpio >= ah->caps.num_gpio_pins) 2660 return 0xffffffff; 2661 2662 if (AR_DEVID_7010(ah)) { 2663 u32 val; 2664 val = REG_READ(ah, AR7010_GPIO_IN); 2665 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2666 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2667 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2668 AR_GPIO_BIT(gpio)) != 0; 2669 else if (AR_SREV_9271(ah)) 2670 return MS_REG_READ(AR9271, gpio) != 0; 2671 else if (AR_SREV_9287_11_OR_LATER(ah)) 2672 return MS_REG_READ(AR9287, gpio) != 0; 2673 else if (AR_SREV_9285_12_OR_LATER(ah)) 2674 return MS_REG_READ(AR9285, gpio) != 0; 2675 else if (AR_SREV_9280_20_OR_LATER(ah)) 2676 return MS_REG_READ(AR928X, gpio) != 0; 2677 else 2678 return MS_REG_READ(AR, gpio) != 0; 2679 } 2680 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2681 2682 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2683 u32 ah_signal_type) 2684 { 2685 u32 gpio_shift; 2686 2687 if (AR_DEVID_7010(ah)) { 2688 gpio_shift = gpio; 2689 REG_RMW(ah, AR7010_GPIO_OE, 2690 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2691 (AR7010_GPIO_OE_MASK << gpio_shift)); 2692 return; 2693 } 2694 2695 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2696 gpio_shift = 2 * gpio; 2697 REG_RMW(ah, 2698 AR_GPIO_OE_OUT, 2699 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2700 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2701 } 2702 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2703 2704 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2705 { 2706 if (AR_DEVID_7010(ah)) { 2707 val = val ? 0 : 1; 2708 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2709 AR_GPIO_BIT(gpio)); 2710 return; 2711 } 2712 2713 if (AR_SREV_9271(ah)) 2714 val = ~val; 2715 2716 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2717 AR_GPIO_BIT(gpio)); 2718 } 2719 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2720 2721 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2722 { 2723 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2724 } 2725 EXPORT_SYMBOL(ath9k_hw_setantenna); 2726 2727 /*********************/ 2728 /* General Operation */ 2729 /*********************/ 2730 2731 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2732 { 2733 u32 bits = REG_READ(ah, AR_RX_FILTER); 2734 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2735 2736 if (phybits & AR_PHY_ERR_RADAR) 2737 bits |= ATH9K_RX_FILTER_PHYRADAR; 2738 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2739 bits |= ATH9K_RX_FILTER_PHYERR; 2740 2741 return bits; 2742 } 2743 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2744 2745 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2746 { 2747 u32 phybits; 2748 2749 ENABLE_REGWRITE_BUFFER(ah); 2750 2751 if (AR_SREV_9462(ah)) 2752 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2753 2754 REG_WRITE(ah, AR_RX_FILTER, bits); 2755 2756 phybits = 0; 2757 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2758 phybits |= AR_PHY_ERR_RADAR; 2759 if (bits & ATH9K_RX_FILTER_PHYERR) 2760 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2761 REG_WRITE(ah, AR_PHY_ERR, phybits); 2762 2763 if (phybits) 2764 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2765 else 2766 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2767 2768 REGWRITE_BUFFER_FLUSH(ah); 2769 } 2770 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2771 2772 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2773 { 2774 if (ath9k_hw_mci_is_enabled(ah)) 2775 ar9003_mci_bt_gain_ctrl(ah); 2776 2777 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2778 return false; 2779 2780 ath9k_hw_init_pll(ah, NULL); 2781 ah->htc_reset_init = true; 2782 return true; 2783 } 2784 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2785 2786 bool ath9k_hw_disable(struct ath_hw *ah) 2787 { 2788 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2789 return false; 2790 2791 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2792 return false; 2793 2794 ath9k_hw_init_pll(ah, NULL); 2795 return true; 2796 } 2797 EXPORT_SYMBOL(ath9k_hw_disable); 2798 2799 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2800 { 2801 enum eeprom_param gain_param; 2802 2803 if (IS_CHAN_2GHZ(chan)) 2804 gain_param = EEP_ANTENNA_GAIN_2G; 2805 else 2806 gain_param = EEP_ANTENNA_GAIN_5G; 2807 2808 return ah->eep_ops->get_eeprom(ah, gain_param); 2809 } 2810 2811 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2812 bool test) 2813 { 2814 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2815 struct ieee80211_channel *channel; 2816 int chan_pwr, new_pwr, max_gain; 2817 int ant_gain, ant_reduction = 0; 2818 2819 if (!chan) 2820 return; 2821 2822 channel = chan->chan; 2823 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2824 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2825 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2826 2827 ant_gain = get_antenna_gain(ah, chan); 2828 if (ant_gain > max_gain) 2829 ant_reduction = ant_gain - max_gain; 2830 2831 ah->eep_ops->set_txpower(ah, chan, 2832 ath9k_regd_get_ctl(reg, chan), 2833 ant_reduction, new_pwr, test); 2834 } 2835 2836 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2837 { 2838 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2839 struct ath9k_channel *chan = ah->curchan; 2840 struct ieee80211_channel *channel = chan->chan; 2841 2842 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2843 if (test) 2844 channel->max_power = MAX_RATE_POWER / 2; 2845 2846 ath9k_hw_apply_txpower(ah, chan, test); 2847 2848 if (test) 2849 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2850 } 2851 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2852 2853 void ath9k_hw_setopmode(struct ath_hw *ah) 2854 { 2855 ath9k_hw_set_operating_mode(ah, ah->opmode); 2856 } 2857 EXPORT_SYMBOL(ath9k_hw_setopmode); 2858 2859 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2860 { 2861 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2862 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2863 } 2864 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2865 2866 void ath9k_hw_write_associd(struct ath_hw *ah) 2867 { 2868 struct ath_common *common = ath9k_hw_common(ah); 2869 2870 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2871 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2872 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2873 } 2874 EXPORT_SYMBOL(ath9k_hw_write_associd); 2875 2876 #define ATH9K_MAX_TSF_READ 10 2877 2878 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2879 { 2880 u32 tsf_lower, tsf_upper1, tsf_upper2; 2881 int i; 2882 2883 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2884 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2885 tsf_lower = REG_READ(ah, AR_TSF_L32); 2886 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2887 if (tsf_upper2 == tsf_upper1) 2888 break; 2889 tsf_upper1 = tsf_upper2; 2890 } 2891 2892 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2893 2894 return (((u64)tsf_upper1 << 32) | tsf_lower); 2895 } 2896 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2897 2898 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2899 { 2900 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2901 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2902 } 2903 EXPORT_SYMBOL(ath9k_hw_settsf64); 2904 2905 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2906 { 2907 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2908 AH_TSF_WRITE_TIMEOUT)) 2909 ath_dbg(ath9k_hw_common(ah), RESET, 2910 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2911 2912 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2913 } 2914 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2915 2916 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2917 { 2918 if (set) 2919 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2920 else 2921 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2922 } 2923 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2924 2925 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2926 { 2927 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2928 u32 macmode; 2929 2930 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2931 macmode = AR_2040_JOINED_RX_CLEAR; 2932 else 2933 macmode = 0; 2934 2935 REG_WRITE(ah, AR_2040_MODE, macmode); 2936 } 2937 2938 /* HW Generic timers configuration */ 2939 2940 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2941 { 2942 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2943 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2944 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2945 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2946 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2947 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2948 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2949 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2950 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2951 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2952 AR_NDP2_TIMER_MODE, 0x0002}, 2953 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2954 AR_NDP2_TIMER_MODE, 0x0004}, 2955 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2956 AR_NDP2_TIMER_MODE, 0x0008}, 2957 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2958 AR_NDP2_TIMER_MODE, 0x0010}, 2959 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2960 AR_NDP2_TIMER_MODE, 0x0020}, 2961 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2962 AR_NDP2_TIMER_MODE, 0x0040}, 2963 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2964 AR_NDP2_TIMER_MODE, 0x0080} 2965 }; 2966 2967 /* HW generic timer primitives */ 2968 2969 /* compute and clear index of rightmost 1 */ 2970 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2971 { 2972 u32 b; 2973 2974 b = *mask; 2975 b &= (0-b); 2976 *mask &= ~b; 2977 b *= debruijn32; 2978 b >>= 27; 2979 2980 return timer_table->gen_timer_index[b]; 2981 } 2982 2983 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2984 { 2985 return REG_READ(ah, AR_TSF_L32); 2986 } 2987 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2988 2989 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2990 void (*trigger)(void *), 2991 void (*overflow)(void *), 2992 void *arg, 2993 u8 timer_index) 2994 { 2995 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2996 struct ath_gen_timer *timer; 2997 2998 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2999 3000 if (timer == NULL) { 3001 ath_err(ath9k_hw_common(ah), 3002 "Failed to allocate memory for hw timer[%d]\n", 3003 timer_index); 3004 return NULL; 3005 } 3006 3007 /* allocate a hardware generic timer slot */ 3008 timer_table->timers[timer_index] = timer; 3009 timer->index = timer_index; 3010 timer->trigger = trigger; 3011 timer->overflow = overflow; 3012 timer->arg = arg; 3013 3014 return timer; 3015 } 3016 EXPORT_SYMBOL(ath_gen_timer_alloc); 3017 3018 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3019 struct ath_gen_timer *timer, 3020 u32 trig_timeout, 3021 u32 timer_period) 3022 { 3023 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3024 u32 tsf, timer_next; 3025 3026 BUG_ON(!timer_period); 3027 3028 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3029 3030 tsf = ath9k_hw_gettsf32(ah); 3031 3032 timer_next = tsf + trig_timeout; 3033 3034 ath_dbg(ath9k_hw_common(ah), HWTIMER, 3035 "current tsf %x period %x timer_next %x\n", 3036 tsf, timer_period, timer_next); 3037 3038 /* 3039 * Program generic timer registers 3040 */ 3041 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3042 timer_next); 3043 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3044 timer_period); 3045 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3046 gen_tmr_configuration[timer->index].mode_mask); 3047 3048 if (AR_SREV_9462(ah)) { 3049 /* 3050 * Starting from AR9462, each generic timer can select which tsf 3051 * to use. But we still follow the old rule, 0 - 7 use tsf and 3052 * 8 - 15 use tsf2. 3053 */ 3054 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3055 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3056 (1 << timer->index)); 3057 else 3058 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3059 (1 << timer->index)); 3060 } 3061 3062 /* Enable both trigger and thresh interrupt masks */ 3063 REG_SET_BIT(ah, AR_IMR_S5, 3064 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3065 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3066 } 3067 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3068 3069 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3070 { 3071 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3072 3073 if ((timer->index < AR_FIRST_NDP_TIMER) || 3074 (timer->index >= ATH_MAX_GEN_TIMER)) { 3075 return; 3076 } 3077 3078 /* Clear generic timer enable bits. */ 3079 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3080 gen_tmr_configuration[timer->index].mode_mask); 3081 3082 /* Disable both trigger and thresh interrupt masks */ 3083 REG_CLR_BIT(ah, AR_IMR_S5, 3084 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3085 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3086 3087 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3088 } 3089 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3090 3091 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3092 { 3093 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3094 3095 /* free the hardware generic timer slot */ 3096 timer_table->timers[timer->index] = NULL; 3097 kfree(timer); 3098 } 3099 EXPORT_SYMBOL(ath_gen_timer_free); 3100 3101 /* 3102 * Generic Timer Interrupts handling 3103 */ 3104 void ath_gen_timer_isr(struct ath_hw *ah) 3105 { 3106 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3107 struct ath_gen_timer *timer; 3108 struct ath_common *common = ath9k_hw_common(ah); 3109 u32 trigger_mask, thresh_mask, index; 3110 3111 /* get hardware generic timer interrupt status */ 3112 trigger_mask = ah->intr_gen_timer_trigger; 3113 thresh_mask = ah->intr_gen_timer_thresh; 3114 trigger_mask &= timer_table->timer_mask.val; 3115 thresh_mask &= timer_table->timer_mask.val; 3116 3117 trigger_mask &= ~thresh_mask; 3118 3119 while (thresh_mask) { 3120 index = rightmost_index(timer_table, &thresh_mask); 3121 timer = timer_table->timers[index]; 3122 BUG_ON(!timer); 3123 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 3124 index); 3125 timer->overflow(timer->arg); 3126 } 3127 3128 while (trigger_mask) { 3129 index = rightmost_index(timer_table, &trigger_mask); 3130 timer = timer_table->timers[index]; 3131 BUG_ON(!timer); 3132 ath_dbg(common, HWTIMER, 3133 "Gen timer[%d] trigger\n", index); 3134 timer->trigger(timer->arg); 3135 } 3136 } 3137 EXPORT_SYMBOL(ath_gen_timer_isr); 3138 3139 /********/ 3140 /* HTC */ 3141 /********/ 3142 3143 static struct { 3144 u32 version; 3145 const char * name; 3146 } ath_mac_bb_names[] = { 3147 /* Devices with external radios */ 3148 { AR_SREV_VERSION_5416_PCI, "5416" }, 3149 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3150 { AR_SREV_VERSION_9100, "9100" }, 3151 { AR_SREV_VERSION_9160, "9160" }, 3152 /* Single-chip solutions */ 3153 { AR_SREV_VERSION_9280, "9280" }, 3154 { AR_SREV_VERSION_9285, "9285" }, 3155 { AR_SREV_VERSION_9287, "9287" }, 3156 { AR_SREV_VERSION_9271, "9271" }, 3157 { AR_SREV_VERSION_9300, "9300" }, 3158 { AR_SREV_VERSION_9330, "9330" }, 3159 { AR_SREV_VERSION_9340, "9340" }, 3160 { AR_SREV_VERSION_9485, "9485" }, 3161 { AR_SREV_VERSION_9462, "9462" }, 3162 { AR_SREV_VERSION_9550, "9550" }, 3163 }; 3164 3165 /* For devices with external radios */ 3166 static struct { 3167 u16 version; 3168 const char * name; 3169 } ath_rf_names[] = { 3170 { 0, "5133" }, 3171 { AR_RAD5133_SREV_MAJOR, "5133" }, 3172 { AR_RAD5122_SREV_MAJOR, "5122" }, 3173 { AR_RAD2133_SREV_MAJOR, "2133" }, 3174 { AR_RAD2122_SREV_MAJOR, "2122" } 3175 }; 3176 3177 /* 3178 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3179 */ 3180 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3181 { 3182 int i; 3183 3184 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3185 if (ath_mac_bb_names[i].version == mac_bb_version) { 3186 return ath_mac_bb_names[i].name; 3187 } 3188 } 3189 3190 return "????"; 3191 } 3192 3193 /* 3194 * Return the RF name. "????" is returned if the RF is unknown. 3195 * Used for devices with external radios. 3196 */ 3197 static const char *ath9k_hw_rf_name(u16 rf_version) 3198 { 3199 int i; 3200 3201 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3202 if (ath_rf_names[i].version == rf_version) { 3203 return ath_rf_names[i].name; 3204 } 3205 } 3206 3207 return "????"; 3208 } 3209 3210 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3211 { 3212 int used; 3213 3214 /* chipsets >= AR9280 are single-chip */ 3215 if (AR_SREV_9280_20_OR_LATER(ah)) { 3216 used = snprintf(hw_name, len, 3217 "Atheros AR%s Rev:%x", 3218 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3219 ah->hw_version.macRev); 3220 } 3221 else { 3222 used = snprintf(hw_name, len, 3223 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3224 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3225 ah->hw_version.macRev, 3226 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3227 AR_RADIO_SREV_MAJOR)), 3228 ah->hw_version.phyRev); 3229 } 3230 3231 hw_name[used] = '\0'; 3232 } 3233 EXPORT_SYMBOL(ath9k_hw_name); 3234