1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 27 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 28 29 MODULE_AUTHOR("Atheros Communications"); 30 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 31 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 32 MODULE_LICENSE("Dual BSD/GPL"); 33 34 static int __init ath9k_init(void) 35 { 36 return 0; 37 } 38 module_init(ath9k_init); 39 40 static void __exit ath9k_exit(void) 41 { 42 return; 43 } 44 module_exit(ath9k_exit); 45 46 /* Private hardware callbacks */ 47 48 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 49 { 50 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 51 } 52 53 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 54 { 55 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 56 } 57 58 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 59 struct ath9k_channel *chan) 60 { 61 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 62 } 63 64 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 65 { 66 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 67 return; 68 69 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 70 } 71 72 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 73 { 74 /* You will not have this callback if using the old ANI */ 75 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 76 return; 77 78 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 79 } 80 81 /********************/ 82 /* Helper Functions */ 83 /********************/ 84 85 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 86 { 87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 88 struct ath_common *common = ath9k_hw_common(ah); 89 unsigned int clockrate; 90 91 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 92 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 93 clockrate = 117; 94 else if (!ah->curchan) /* should really check for CCK instead */ 95 clockrate = ATH9K_CLOCK_RATE_CCK; 96 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 97 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 98 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 99 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 100 else 101 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 102 103 if (conf_is_ht40(conf)) 104 clockrate *= 2; 105 106 if (ah->curchan) { 107 if (IS_CHAN_HALF_RATE(ah->curchan)) 108 clockrate /= 2; 109 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 110 clockrate /= 4; 111 } 112 113 common->clockrate = clockrate; 114 } 115 116 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 117 { 118 struct ath_common *common = ath9k_hw_common(ah); 119 120 return usecs * common->clockrate; 121 } 122 123 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 124 { 125 int i; 126 127 BUG_ON(timeout < AH_TIME_QUANTUM); 128 129 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 130 if ((REG_READ(ah, reg) & mask) == val) 131 return true; 132 133 udelay(AH_TIME_QUANTUM); 134 } 135 136 ath_dbg(ath9k_hw_common(ah), ANY, 137 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 138 timeout, reg, REG_READ(ah, reg), mask, val); 139 140 return false; 141 } 142 EXPORT_SYMBOL(ath9k_hw_wait); 143 144 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 145 int column, unsigned int *writecnt) 146 { 147 int r; 148 149 ENABLE_REGWRITE_BUFFER(ah); 150 for (r = 0; r < array->ia_rows; r++) { 151 REG_WRITE(ah, INI_RA(array, r, 0), 152 INI_RA(array, r, column)); 153 DO_DELAY(*writecnt); 154 } 155 REGWRITE_BUFFER_FLUSH(ah); 156 } 157 158 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 159 { 160 u32 retval; 161 int i; 162 163 for (i = 0, retval = 0; i < n; i++) { 164 retval = (retval << 1) | (val & 1); 165 val >>= 1; 166 } 167 return retval; 168 } 169 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 171 u8 phy, int kbps, 172 u32 frameLen, u16 rateix, 173 bool shortPreamble) 174 { 175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 176 177 if (kbps == 0) 178 return 0; 179 180 switch (phy) { 181 case WLAN_RC_PHY_CCK: 182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 183 if (shortPreamble) 184 phyTime >>= 1; 185 numBits = frameLen << 3; 186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 187 break; 188 case WLAN_RC_PHY_OFDM: 189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 191 numBits = OFDM_PLCP_BITS + (frameLen << 3); 192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 193 txTime = OFDM_SIFS_TIME_QUARTER 194 + OFDM_PREAMBLE_TIME_QUARTER 195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 196 } else if (ah->curchan && 197 IS_CHAN_HALF_RATE(ah->curchan)) { 198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 199 numBits = OFDM_PLCP_BITS + (frameLen << 3); 200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 201 txTime = OFDM_SIFS_TIME_HALF + 202 OFDM_PREAMBLE_TIME_HALF 203 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 204 } else { 205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 206 numBits = OFDM_PLCP_BITS + (frameLen << 3); 207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 209 + (numSymbols * OFDM_SYMBOL_TIME); 210 } 211 break; 212 default: 213 ath_err(ath9k_hw_common(ah), 214 "Unknown phy %u (rate ix %u)\n", phy, rateix); 215 txTime = 0; 216 break; 217 } 218 219 return txTime; 220 } 221 EXPORT_SYMBOL(ath9k_hw_computetxtime); 222 223 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 224 struct ath9k_channel *chan, 225 struct chan_centers *centers) 226 { 227 int8_t extoff; 228 229 if (!IS_CHAN_HT40(chan)) { 230 centers->ctl_center = centers->ext_center = 231 centers->synth_center = chan->channel; 232 return; 233 } 234 235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 236 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 237 centers->synth_center = 238 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 239 extoff = 1; 240 } else { 241 centers->synth_center = 242 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 243 extoff = -1; 244 } 245 246 centers->ctl_center = 247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 248 /* 25 MHz spacing is supported by hw but not on upper layers */ 249 centers->ext_center = 250 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 251 } 252 253 /******************/ 254 /* Chip Revisions */ 255 /******************/ 256 257 static void ath9k_hw_read_revisions(struct ath_hw *ah) 258 { 259 u32 val; 260 261 switch (ah->hw_version.devid) { 262 case AR5416_AR9100_DEVID: 263 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 264 break; 265 case AR9300_DEVID_AR9330: 266 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 267 if (ah->get_mac_revision) { 268 ah->hw_version.macRev = ah->get_mac_revision(); 269 } else { 270 val = REG_READ(ah, AR_SREV); 271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 272 } 273 return; 274 case AR9300_DEVID_AR9340: 275 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 276 val = REG_READ(ah, AR_SREV); 277 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 278 return; 279 } 280 281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 282 283 if (val == 0xFF) { 284 val = REG_READ(ah, AR_SREV); 285 ah->hw_version.macVersion = 286 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 287 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 288 289 if (AR_SREV_9462(ah)) 290 ah->is_pciexpress = true; 291 else 292 ah->is_pciexpress = (val & 293 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 294 } else { 295 if (!AR_SREV_9100(ah)) 296 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 297 298 ah->hw_version.macRev = val & AR_SREV_REVISION; 299 300 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 301 ah->is_pciexpress = true; 302 } 303 } 304 305 /************************************/ 306 /* HW Attach, Detach, Init Routines */ 307 /************************************/ 308 309 static void ath9k_hw_disablepcie(struct ath_hw *ah) 310 { 311 if (!AR_SREV_5416(ah)) 312 return; 313 314 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 315 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 316 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 317 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 319 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 323 324 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 325 } 326 327 static void ath9k_hw_aspm_init(struct ath_hw *ah) 328 { 329 struct ath_common *common = ath9k_hw_common(ah); 330 331 if (common->bus_ops->aspm_init) 332 common->bus_ops->aspm_init(common); 333 } 334 335 /* This should work for all families including legacy */ 336 static bool ath9k_hw_chip_test(struct ath_hw *ah) 337 { 338 struct ath_common *common = ath9k_hw_common(ah); 339 u32 regAddr[2] = { AR_STA_ID0 }; 340 u32 regHold[2]; 341 static const u32 patternData[4] = { 342 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 343 }; 344 int i, j, loop_max; 345 346 if (!AR_SREV_9300_20_OR_LATER(ah)) { 347 loop_max = 2; 348 regAddr[1] = AR_PHY_BASE + (8 << 2); 349 } else 350 loop_max = 1; 351 352 for (i = 0; i < loop_max; i++) { 353 u32 addr = regAddr[i]; 354 u32 wrData, rdData; 355 356 regHold[i] = REG_READ(ah, addr); 357 for (j = 0; j < 0x100; j++) { 358 wrData = (j << 16) | j; 359 REG_WRITE(ah, addr, wrData); 360 rdData = REG_READ(ah, addr); 361 if (rdData != wrData) { 362 ath_err(common, 363 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 364 addr, wrData, rdData); 365 return false; 366 } 367 } 368 for (j = 0; j < 4; j++) { 369 wrData = patternData[j]; 370 REG_WRITE(ah, addr, wrData); 371 rdData = REG_READ(ah, addr); 372 if (wrData != rdData) { 373 ath_err(common, 374 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 375 addr, wrData, rdData); 376 return false; 377 } 378 } 379 REG_WRITE(ah, regAddr[i], regHold[i]); 380 } 381 udelay(100); 382 383 return true; 384 } 385 386 static void ath9k_hw_init_config(struct ath_hw *ah) 387 { 388 int i; 389 390 ah->config.dma_beacon_response_time = 2; 391 ah->config.sw_beacon_response_time = 10; 392 ah->config.additional_swba_backoff = 0; 393 ah->config.ack_6mb = 0x0; 394 ah->config.cwm_ignore_extcca = 0; 395 ah->config.pcie_clock_req = 0; 396 ah->config.pcie_waen = 0; 397 ah->config.analog_shiftreg = 1; 398 ah->config.enable_ani = true; 399 400 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 401 ah->config.spurchans[i][0] = AR_NO_SPUR; 402 ah->config.spurchans[i][1] = AR_NO_SPUR; 403 } 404 405 /* PAPRD needs some more work to be enabled */ 406 ah->config.paprd_disable = 1; 407 408 ah->config.rx_intr_mitigation = true; 409 ah->config.pcieSerDesWrite = true; 410 411 /* 412 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 413 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 414 * This means we use it for all AR5416 devices, and the few 415 * minor PCI AR9280 devices out there. 416 * 417 * Serialization is required because these devices do not handle 418 * well the case of two concurrent reads/writes due to the latency 419 * involved. During one read/write another read/write can be issued 420 * on another CPU while the previous read/write may still be working 421 * on our hardware, if we hit this case the hardware poops in a loop. 422 * We prevent this by serializing reads and writes. 423 * 424 * This issue is not present on PCI-Express devices or pre-AR5416 425 * devices (legacy, 802.11abg). 426 */ 427 if (num_possible_cpus() > 1) 428 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 429 } 430 431 static void ath9k_hw_init_defaults(struct ath_hw *ah) 432 { 433 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 434 435 regulatory->country_code = CTRY_DEFAULT; 436 regulatory->power_limit = MAX_RATE_POWER; 437 438 ah->hw_version.magic = AR5416_MAGIC; 439 ah->hw_version.subvendorid = 0; 440 441 ah->atim_window = 0; 442 ah->sta_id1_defaults = 443 AR_STA_ID1_CRPT_MIC_ENABLE | 444 AR_STA_ID1_MCAST_KSRCH; 445 if (AR_SREV_9100(ah)) 446 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 447 ah->enable_32kHz_clock = DONT_USE_32KHZ; 448 ah->slottime = ATH9K_SLOT_TIME_9; 449 ah->globaltxtimeout = (u32) -1; 450 ah->power_mode = ATH9K_PM_UNDEFINED; 451 } 452 453 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 454 { 455 struct ath_common *common = ath9k_hw_common(ah); 456 u32 sum; 457 int i; 458 u16 eeval; 459 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 460 461 sum = 0; 462 for (i = 0; i < 3; i++) { 463 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 464 sum += eeval; 465 common->macaddr[2 * i] = eeval >> 8; 466 common->macaddr[2 * i + 1] = eeval & 0xff; 467 } 468 if (sum == 0 || sum == 0xffff * 3) 469 return -EADDRNOTAVAIL; 470 471 return 0; 472 } 473 474 static int ath9k_hw_post_init(struct ath_hw *ah) 475 { 476 struct ath_common *common = ath9k_hw_common(ah); 477 int ecode; 478 479 if (common->bus_ops->ath_bus_type != ATH_USB) { 480 if (!ath9k_hw_chip_test(ah)) 481 return -ENODEV; 482 } 483 484 if (!AR_SREV_9300_20_OR_LATER(ah)) { 485 ecode = ar9002_hw_rf_claim(ah); 486 if (ecode != 0) 487 return ecode; 488 } 489 490 ecode = ath9k_hw_eeprom_init(ah); 491 if (ecode != 0) 492 return ecode; 493 494 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 495 ah->eep_ops->get_eeprom_ver(ah), 496 ah->eep_ops->get_eeprom_rev(ah)); 497 498 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 499 if (ecode) { 500 ath_err(ath9k_hw_common(ah), 501 "Failed allocating banks for external radio\n"); 502 ath9k_hw_rf_free_ext_banks(ah); 503 return ecode; 504 } 505 506 if (ah->config.enable_ani) { 507 ath9k_hw_ani_setup(ah); 508 ath9k_hw_ani_init(ah); 509 } 510 511 return 0; 512 } 513 514 static void ath9k_hw_attach_ops(struct ath_hw *ah) 515 { 516 if (AR_SREV_9300_20_OR_LATER(ah)) 517 ar9003_hw_attach_ops(ah); 518 else 519 ar9002_hw_attach_ops(ah); 520 } 521 522 /* Called for all hardware families */ 523 static int __ath9k_hw_init(struct ath_hw *ah) 524 { 525 struct ath_common *common = ath9k_hw_common(ah); 526 int r = 0; 527 528 ath9k_hw_read_revisions(ah); 529 530 /* 531 * Read back AR_WA into a permanent copy and set bits 14 and 17. 532 * We need to do this to avoid RMW of this register. We cannot 533 * read the reg when chip is asleep. 534 */ 535 ah->WARegVal = REG_READ(ah, AR_WA); 536 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 537 AR_WA_ASPM_TIMER_BASED_DISABLE); 538 539 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 540 ath_err(common, "Couldn't reset chip\n"); 541 return -EIO; 542 } 543 544 if (AR_SREV_9462(ah)) 545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 546 547 ath9k_hw_init_defaults(ah); 548 ath9k_hw_init_config(ah); 549 550 ath9k_hw_attach_ops(ah); 551 552 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 553 ath_err(common, "Couldn't wakeup chip\n"); 554 return -EIO; 555 } 556 557 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 558 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 559 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 560 !ah->is_pciexpress)) { 561 ah->config.serialize_regmode = 562 SER_REG_MODE_ON; 563 } else { 564 ah->config.serialize_regmode = 565 SER_REG_MODE_OFF; 566 } 567 } 568 569 ath_dbg(common, RESET, "serialize_regmode is %d\n", 570 ah->config.serialize_regmode); 571 572 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 573 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 574 else 575 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 576 577 switch (ah->hw_version.macVersion) { 578 case AR_SREV_VERSION_5416_PCI: 579 case AR_SREV_VERSION_5416_PCIE: 580 case AR_SREV_VERSION_9160: 581 case AR_SREV_VERSION_9100: 582 case AR_SREV_VERSION_9280: 583 case AR_SREV_VERSION_9285: 584 case AR_SREV_VERSION_9287: 585 case AR_SREV_VERSION_9271: 586 case AR_SREV_VERSION_9300: 587 case AR_SREV_VERSION_9330: 588 case AR_SREV_VERSION_9485: 589 case AR_SREV_VERSION_9340: 590 case AR_SREV_VERSION_9462: 591 break; 592 default: 593 ath_err(common, 594 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 595 ah->hw_version.macVersion, ah->hw_version.macRev); 596 return -EOPNOTSUPP; 597 } 598 599 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 600 AR_SREV_9330(ah)) 601 ah->is_pciexpress = false; 602 603 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 604 ath9k_hw_init_cal_settings(ah); 605 606 ah->ani_function = ATH9K_ANI_ALL; 607 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 608 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 609 if (!AR_SREV_9300_20_OR_LATER(ah)) 610 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 611 612 /* disable ANI for 9340 */ 613 if (AR_SREV_9340(ah)) 614 ah->config.enable_ani = false; 615 616 ath9k_hw_init_mode_regs(ah); 617 618 if (!ah->is_pciexpress) 619 ath9k_hw_disablepcie(ah); 620 621 if (!AR_SREV_9300_20_OR_LATER(ah)) 622 ar9002_hw_cck_chan14_spread(ah); 623 624 r = ath9k_hw_post_init(ah); 625 if (r) 626 return r; 627 628 ath9k_hw_init_mode_gain_regs(ah); 629 r = ath9k_hw_fill_cap_info(ah); 630 if (r) 631 return r; 632 633 if (ah->is_pciexpress) 634 ath9k_hw_aspm_init(ah); 635 636 r = ath9k_hw_init_macaddr(ah); 637 if (r) { 638 ath_err(common, "Failed to initialize MAC address\n"); 639 return r; 640 } 641 642 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 643 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 644 else 645 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 646 647 if (AR_SREV_9330(ah)) 648 ah->bb_watchdog_timeout_ms = 85; 649 else 650 ah->bb_watchdog_timeout_ms = 25; 651 652 common->state = ATH_HW_INITIALIZED; 653 654 return 0; 655 } 656 657 int ath9k_hw_init(struct ath_hw *ah) 658 { 659 int ret; 660 struct ath_common *common = ath9k_hw_common(ah); 661 662 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 663 switch (ah->hw_version.devid) { 664 case AR5416_DEVID_PCI: 665 case AR5416_DEVID_PCIE: 666 case AR5416_AR9100_DEVID: 667 case AR9160_DEVID_PCI: 668 case AR9280_DEVID_PCI: 669 case AR9280_DEVID_PCIE: 670 case AR9285_DEVID_PCIE: 671 case AR9287_DEVID_PCI: 672 case AR9287_DEVID_PCIE: 673 case AR2427_DEVID_PCIE: 674 case AR9300_DEVID_PCIE: 675 case AR9300_DEVID_AR9485_PCIE: 676 case AR9300_DEVID_AR9330: 677 case AR9300_DEVID_AR9340: 678 case AR9300_DEVID_AR9580: 679 case AR9300_DEVID_AR9462: 680 break; 681 default: 682 if (common->bus_ops->ath_bus_type == ATH_USB) 683 break; 684 ath_err(common, "Hardware device ID 0x%04x not supported\n", 685 ah->hw_version.devid); 686 return -EOPNOTSUPP; 687 } 688 689 ret = __ath9k_hw_init(ah); 690 if (ret) { 691 ath_err(common, 692 "Unable to initialize hardware; initialization status: %d\n", 693 ret); 694 return ret; 695 } 696 697 return 0; 698 } 699 EXPORT_SYMBOL(ath9k_hw_init); 700 701 static void ath9k_hw_init_qos(struct ath_hw *ah) 702 { 703 ENABLE_REGWRITE_BUFFER(ah); 704 705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 707 708 REG_WRITE(ah, AR_QOS_NO_ACK, 709 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 710 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 711 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 712 713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 718 719 REGWRITE_BUFFER_FLUSH(ah); 720 } 721 722 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 723 { 724 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 725 udelay(100); 726 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 727 728 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 729 udelay(100); 730 731 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 732 } 733 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 734 735 static void ath9k_hw_init_pll(struct ath_hw *ah, 736 struct ath9k_channel *chan) 737 { 738 u32 pll; 739 740 if (AR_SREV_9485(ah)) { 741 742 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 744 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 746 AR_CH0_DPLL2_KD, 0x40); 747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 748 AR_CH0_DPLL2_KI, 0x4); 749 750 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 751 AR_CH0_BB_DPLL1_REFDIV, 0x5); 752 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 753 AR_CH0_BB_DPLL1_NINI, 0x58); 754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 755 AR_CH0_BB_DPLL1_NFRAC, 0x0); 756 757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 758 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 760 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 762 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 763 764 /* program BB PLL phase_shift to 0x6 */ 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 766 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 767 768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 769 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 770 udelay(1000); 771 } else if (AR_SREV_9330(ah)) { 772 u32 ddr_dpll2, pll_control2, kd; 773 774 if (ah->is_clk_25mhz) { 775 ddr_dpll2 = 0x18e82f01; 776 pll_control2 = 0xe04a3d; 777 kd = 0x1d; 778 } else { 779 ddr_dpll2 = 0x19e82f01; 780 pll_control2 = 0x886666; 781 kd = 0x3d; 782 } 783 784 /* program DDR PLL ki and kd value */ 785 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 786 787 /* program DDR PLL phase_shift */ 788 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 789 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 790 791 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 792 udelay(1000); 793 794 /* program refdiv, nint, frac to RTC register */ 795 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 796 797 /* program BB PLL kd and ki value */ 798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 799 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 800 801 /* program BB PLL phase_shift */ 802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 803 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 804 } else if (AR_SREV_9340(ah)) { 805 u32 regval, pll2_divint, pll2_divfrac, refdiv; 806 807 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 808 udelay(1000); 809 810 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 811 udelay(100); 812 813 if (ah->is_clk_25mhz) { 814 pll2_divint = 0x54; 815 pll2_divfrac = 0x1eb85; 816 refdiv = 3; 817 } else { 818 pll2_divint = 88; 819 pll2_divfrac = 0; 820 refdiv = 5; 821 } 822 823 regval = REG_READ(ah, AR_PHY_PLL_MODE); 824 regval |= (0x1 << 16); 825 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 826 udelay(100); 827 828 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 829 (pll2_divint << 18) | pll2_divfrac); 830 udelay(100); 831 832 regval = REG_READ(ah, AR_PHY_PLL_MODE); 833 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 834 (0x4 << 26) | (0x18 << 19); 835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 836 REG_WRITE(ah, AR_PHY_PLL_MODE, 837 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 838 udelay(1000); 839 } 840 841 pll = ath9k_hw_compute_pll_control(ah, chan); 842 843 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 844 845 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 846 udelay(1000); 847 848 /* Switch the core clock for ar9271 to 117Mhz */ 849 if (AR_SREV_9271(ah)) { 850 udelay(500); 851 REG_WRITE(ah, 0x50040, 0x304); 852 } 853 854 udelay(RTC_PLL_SETTLE_DELAY); 855 856 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 857 858 if (AR_SREV_9340(ah)) { 859 if (ah->is_clk_25mhz) { 860 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 861 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 862 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 863 } else { 864 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 865 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 866 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 867 } 868 udelay(100); 869 } 870 } 871 872 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 873 enum nl80211_iftype opmode) 874 { 875 u32 sync_default = AR_INTR_SYNC_DEFAULT; 876 u32 imr_reg = AR_IMR_TXERR | 877 AR_IMR_TXURN | 878 AR_IMR_RXERR | 879 AR_IMR_RXORN | 880 AR_IMR_BCNMISC; 881 882 if (AR_SREV_9340(ah)) 883 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 884 885 if (AR_SREV_9300_20_OR_LATER(ah)) { 886 imr_reg |= AR_IMR_RXOK_HP; 887 if (ah->config.rx_intr_mitigation) 888 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 889 else 890 imr_reg |= AR_IMR_RXOK_LP; 891 892 } else { 893 if (ah->config.rx_intr_mitigation) 894 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 895 else 896 imr_reg |= AR_IMR_RXOK; 897 } 898 899 if (ah->config.tx_intr_mitigation) 900 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 901 else 902 imr_reg |= AR_IMR_TXOK; 903 904 if (opmode == NL80211_IFTYPE_AP) 905 imr_reg |= AR_IMR_MIB; 906 907 ENABLE_REGWRITE_BUFFER(ah); 908 909 REG_WRITE(ah, AR_IMR, imr_reg); 910 ah->imrs2_reg |= AR_IMR_S2_GTT; 911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 912 913 if (!AR_SREV_9100(ah)) { 914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 917 } 918 919 REGWRITE_BUFFER_FLUSH(ah); 920 921 if (AR_SREV_9300_20_OR_LATER(ah)) { 922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 926 } 927 } 928 929 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 930 { 931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 932 val = min(val, (u32) 0xFFFF); 933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 934 } 935 936 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 937 { 938 u32 val = ath9k_hw_mac_to_clks(ah, us); 939 val = min(val, (u32) 0xFFFF); 940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 941 } 942 943 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 944 { 945 u32 val = ath9k_hw_mac_to_clks(ah, us); 946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 948 } 949 950 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 951 { 952 u32 val = ath9k_hw_mac_to_clks(ah, us); 953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 955 } 956 957 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 958 { 959 if (tu > 0xFFFF) { 960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 961 tu); 962 ah->globaltxtimeout = (u32) -1; 963 return false; 964 } else { 965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 966 ah->globaltxtimeout = tu; 967 return true; 968 } 969 } 970 971 void ath9k_hw_init_global_settings(struct ath_hw *ah) 972 { 973 struct ath_common *common = ath9k_hw_common(ah); 974 struct ieee80211_conf *conf = &common->hw->conf; 975 const struct ath9k_channel *chan = ah->curchan; 976 int acktimeout, ctstimeout; 977 int slottime; 978 int sifstime; 979 int rx_lat = 0, tx_lat = 0, eifs = 0; 980 u32 reg; 981 982 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 983 ah->misc_mode); 984 985 if (!chan) 986 return; 987 988 if (ah->misc_mode != 0) 989 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 990 991 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 992 rx_lat = 41; 993 else 994 rx_lat = 37; 995 tx_lat = 54; 996 997 if (IS_CHAN_HALF_RATE(chan)) { 998 eifs = 175; 999 rx_lat *= 2; 1000 tx_lat *= 2; 1001 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1002 tx_lat += 11; 1003 1004 slottime = 13; 1005 sifstime = 32; 1006 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1007 eifs = 340; 1008 rx_lat = (rx_lat * 4) - 1; 1009 tx_lat *= 4; 1010 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1011 tx_lat += 22; 1012 1013 slottime = 21; 1014 sifstime = 64; 1015 } else { 1016 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1017 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1018 reg = AR_USEC_ASYNC_FIFO; 1019 } else { 1020 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1021 common->clockrate; 1022 reg = REG_READ(ah, AR_USEC); 1023 } 1024 rx_lat = MS(reg, AR_USEC_RX_LAT); 1025 tx_lat = MS(reg, AR_USEC_TX_LAT); 1026 1027 slottime = ah->slottime; 1028 if (IS_CHAN_5GHZ(chan)) 1029 sifstime = 16; 1030 else 1031 sifstime = 10; 1032 } 1033 1034 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1035 acktimeout = slottime + sifstime + 3 * ah->coverage_class; 1036 ctstimeout = acktimeout; 1037 1038 /* 1039 * Workaround for early ACK timeouts, add an offset to match the 1040 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1041 * This was initially only meant to work around an issue with delayed 1042 * BA frames in some implementations, but it has been found to fix ACK 1043 * timeout issues in other cases as well. 1044 */ 1045 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) { 1046 acktimeout += 64 - sifstime - ah->slottime; 1047 ctstimeout += 48 - sifstime - ah->slottime; 1048 } 1049 1050 1051 ath9k_hw_set_sifs_time(ah, sifstime); 1052 ath9k_hw_setslottime(ah, slottime); 1053 ath9k_hw_set_ack_timeout(ah, acktimeout); 1054 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1055 if (ah->globaltxtimeout != (u32) -1) 1056 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1057 1058 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1059 REG_RMW(ah, AR_USEC, 1060 (common->clockrate - 1) | 1061 SM(rx_lat, AR_USEC_RX_LAT) | 1062 SM(tx_lat, AR_USEC_TX_LAT), 1063 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1064 1065 } 1066 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1067 1068 void ath9k_hw_deinit(struct ath_hw *ah) 1069 { 1070 struct ath_common *common = ath9k_hw_common(ah); 1071 1072 if (common->state < ATH_HW_INITIALIZED) 1073 goto free_hw; 1074 1075 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1076 1077 free_hw: 1078 ath9k_hw_rf_free_ext_banks(ah); 1079 } 1080 EXPORT_SYMBOL(ath9k_hw_deinit); 1081 1082 /*******/ 1083 /* INI */ 1084 /*******/ 1085 1086 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1087 { 1088 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1089 1090 if (IS_CHAN_B(chan)) 1091 ctl |= CTL_11B; 1092 else if (IS_CHAN_G(chan)) 1093 ctl |= CTL_11G; 1094 else 1095 ctl |= CTL_11A; 1096 1097 return ctl; 1098 } 1099 1100 /****************************************/ 1101 /* Reset and Channel Switching Routines */ 1102 /****************************************/ 1103 1104 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1105 { 1106 struct ath_common *common = ath9k_hw_common(ah); 1107 1108 ENABLE_REGWRITE_BUFFER(ah); 1109 1110 /* 1111 * set AHB_MODE not to do cacheline prefetches 1112 */ 1113 if (!AR_SREV_9300_20_OR_LATER(ah)) 1114 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1115 1116 /* 1117 * let mac dma reads be in 128 byte chunks 1118 */ 1119 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1120 1121 REGWRITE_BUFFER_FLUSH(ah); 1122 1123 /* 1124 * Restore TX Trigger Level to its pre-reset value. 1125 * The initial value depends on whether aggregation is enabled, and is 1126 * adjusted whenever underruns are detected. 1127 */ 1128 if (!AR_SREV_9300_20_OR_LATER(ah)) 1129 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1130 1131 ENABLE_REGWRITE_BUFFER(ah); 1132 1133 /* 1134 * let mac dma writes be in 128 byte chunks 1135 */ 1136 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1137 1138 /* 1139 * Setup receive FIFO threshold to hold off TX activities 1140 */ 1141 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1142 1143 if (AR_SREV_9300_20_OR_LATER(ah)) { 1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1145 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1146 1147 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1148 ah->caps.rx_status_len); 1149 } 1150 1151 /* 1152 * reduce the number of usable entries in PCU TXBUF to avoid 1153 * wrap around issues. 1154 */ 1155 if (AR_SREV_9285(ah)) { 1156 /* For AR9285 the number of Fifos are reduced to half. 1157 * So set the usable tx buf size also to half to 1158 * avoid data/delimiter underruns 1159 */ 1160 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1161 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1162 } else if (!AR_SREV_9271(ah)) { 1163 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1164 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1165 } 1166 1167 REGWRITE_BUFFER_FLUSH(ah); 1168 1169 if (AR_SREV_9300_20_OR_LATER(ah)) 1170 ath9k_hw_reset_txstatus_ring(ah); 1171 } 1172 1173 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1174 { 1175 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1176 u32 set = AR_STA_ID1_KSRCH_MODE; 1177 1178 switch (opmode) { 1179 case NL80211_IFTYPE_ADHOC: 1180 case NL80211_IFTYPE_MESH_POINT: 1181 set |= AR_STA_ID1_ADHOC; 1182 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1183 break; 1184 case NL80211_IFTYPE_AP: 1185 set |= AR_STA_ID1_STA_AP; 1186 /* fall through */ 1187 case NL80211_IFTYPE_STATION: 1188 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1189 break; 1190 default: 1191 if (!ah->is_monitoring) 1192 set = 0; 1193 break; 1194 } 1195 REG_RMW(ah, AR_STA_ID1, set, mask); 1196 } 1197 1198 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1199 u32 *coef_mantissa, u32 *coef_exponent) 1200 { 1201 u32 coef_exp, coef_man; 1202 1203 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1204 if ((coef_scaled >> coef_exp) & 0x1) 1205 break; 1206 1207 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1208 1209 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1210 1211 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1212 *coef_exponent = coef_exp - 16; 1213 } 1214 1215 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1216 { 1217 u32 rst_flags; 1218 u32 tmpReg; 1219 1220 if (AR_SREV_9100(ah)) { 1221 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1222 AR_RTC_DERIVED_CLK_PERIOD, 1); 1223 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1224 } 1225 1226 ENABLE_REGWRITE_BUFFER(ah); 1227 1228 if (AR_SREV_9300_20_OR_LATER(ah)) { 1229 REG_WRITE(ah, AR_WA, ah->WARegVal); 1230 udelay(10); 1231 } 1232 1233 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1234 AR_RTC_FORCE_WAKE_ON_INT); 1235 1236 if (AR_SREV_9100(ah)) { 1237 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1238 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1239 } else { 1240 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1241 if (tmpReg & 1242 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1243 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1244 u32 val; 1245 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1246 1247 val = AR_RC_HOSTIF; 1248 if (!AR_SREV_9300_20_OR_LATER(ah)) 1249 val |= AR_RC_AHB; 1250 REG_WRITE(ah, AR_RC, val); 1251 1252 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1253 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1254 1255 rst_flags = AR_RTC_RC_MAC_WARM; 1256 if (type == ATH9K_RESET_COLD) 1257 rst_flags |= AR_RTC_RC_MAC_COLD; 1258 } 1259 1260 if (AR_SREV_9330(ah)) { 1261 int npend = 0; 1262 int i; 1263 1264 /* AR9330 WAR: 1265 * call external reset function to reset WMAC if: 1266 * - doing a cold reset 1267 * - we have pending frames in the TX queues 1268 */ 1269 1270 for (i = 0; i < AR_NUM_QCU; i++) { 1271 npend = ath9k_hw_numtxpending(ah, i); 1272 if (npend) 1273 break; 1274 } 1275 1276 if (ah->external_reset && 1277 (npend || type == ATH9K_RESET_COLD)) { 1278 int reset_err = 0; 1279 1280 ath_dbg(ath9k_hw_common(ah), RESET, 1281 "reset MAC via external reset\n"); 1282 1283 reset_err = ah->external_reset(); 1284 if (reset_err) { 1285 ath_err(ath9k_hw_common(ah), 1286 "External reset failed, err=%d\n", 1287 reset_err); 1288 return false; 1289 } 1290 1291 REG_WRITE(ah, AR_RTC_RESET, 1); 1292 } 1293 } 1294 1295 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1296 1297 REGWRITE_BUFFER_FLUSH(ah); 1298 1299 udelay(50); 1300 1301 REG_WRITE(ah, AR_RTC_RC, 0); 1302 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1303 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1304 return false; 1305 } 1306 1307 if (!AR_SREV_9100(ah)) 1308 REG_WRITE(ah, AR_RC, 0); 1309 1310 if (AR_SREV_9100(ah)) 1311 udelay(50); 1312 1313 return true; 1314 } 1315 1316 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1317 { 1318 ENABLE_REGWRITE_BUFFER(ah); 1319 1320 if (AR_SREV_9300_20_OR_LATER(ah)) { 1321 REG_WRITE(ah, AR_WA, ah->WARegVal); 1322 udelay(10); 1323 } 1324 1325 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1326 AR_RTC_FORCE_WAKE_ON_INT); 1327 1328 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1329 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1330 1331 REG_WRITE(ah, AR_RTC_RESET, 0); 1332 1333 REGWRITE_BUFFER_FLUSH(ah); 1334 1335 if (!AR_SREV_9300_20_OR_LATER(ah)) 1336 udelay(2); 1337 1338 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1339 REG_WRITE(ah, AR_RC, 0); 1340 1341 REG_WRITE(ah, AR_RTC_RESET, 1); 1342 1343 if (!ath9k_hw_wait(ah, 1344 AR_RTC_STATUS, 1345 AR_RTC_STATUS_M, 1346 AR_RTC_STATUS_ON, 1347 AH_WAIT_TIMEOUT)) { 1348 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1349 return false; 1350 } 1351 1352 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1353 } 1354 1355 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1356 { 1357 bool ret = false; 1358 1359 if (AR_SREV_9300_20_OR_LATER(ah)) { 1360 REG_WRITE(ah, AR_WA, ah->WARegVal); 1361 udelay(10); 1362 } 1363 1364 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1365 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1366 1367 switch (type) { 1368 case ATH9K_RESET_POWER_ON: 1369 ret = ath9k_hw_set_reset_power_on(ah); 1370 break; 1371 case ATH9K_RESET_WARM: 1372 case ATH9K_RESET_COLD: 1373 ret = ath9k_hw_set_reset(ah, type); 1374 break; 1375 default: 1376 break; 1377 } 1378 1379 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 1380 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 1381 1382 return ret; 1383 } 1384 1385 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1386 struct ath9k_channel *chan) 1387 { 1388 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1389 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1390 return false; 1391 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1392 return false; 1393 1394 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1395 return false; 1396 1397 ah->chip_fullsleep = false; 1398 ath9k_hw_init_pll(ah, chan); 1399 ath9k_hw_set_rfmode(ah, chan); 1400 1401 return true; 1402 } 1403 1404 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1405 struct ath9k_channel *chan) 1406 { 1407 struct ath_common *common = ath9k_hw_common(ah); 1408 u32 qnum; 1409 int r; 1410 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1411 bool band_switch, mode_diff; 1412 u8 ini_reloaded; 1413 1414 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1415 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1416 CHANNEL_5GHZ)); 1417 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1418 1419 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1420 if (ath9k_hw_numtxpending(ah, qnum)) { 1421 ath_dbg(common, QUEUE, 1422 "Transmit frames pending on queue %d\n", qnum); 1423 return false; 1424 } 1425 } 1426 1427 if (!ath9k_hw_rfbus_req(ah)) { 1428 ath_err(common, "Could not kill baseband RX\n"); 1429 return false; 1430 } 1431 1432 if (edma && (band_switch || mode_diff)) { 1433 ath9k_hw_mark_phy_inactive(ah); 1434 udelay(5); 1435 1436 ath9k_hw_init_pll(ah, NULL); 1437 1438 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1439 ath_err(common, "Failed to do fast channel change\n"); 1440 return false; 1441 } 1442 } 1443 1444 ath9k_hw_set_channel_regs(ah, chan); 1445 1446 r = ath9k_hw_rf_set_freq(ah, chan); 1447 if (r) { 1448 ath_err(common, "Failed to set channel\n"); 1449 return false; 1450 } 1451 ath9k_hw_set_clockrate(ah); 1452 ath9k_hw_apply_txpower(ah, chan); 1453 ath9k_hw_rfbus_done(ah); 1454 1455 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1456 ath9k_hw_set_delta_slope(ah, chan); 1457 1458 ath9k_hw_spur_mitigate_freq(ah, chan); 1459 1460 if (edma && (band_switch || mode_diff)) { 1461 ah->ah_flags |= AH_FASTCC; 1462 if (band_switch || ini_reloaded) 1463 ah->eep_ops->set_board_values(ah, chan); 1464 1465 ath9k_hw_init_bb(ah, chan); 1466 1467 if (band_switch || ini_reloaded) 1468 ath9k_hw_init_cal(ah, chan); 1469 ah->ah_flags &= ~AH_FASTCC; 1470 } 1471 1472 return true; 1473 } 1474 1475 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1476 { 1477 u32 gpio_mask = ah->gpio_mask; 1478 int i; 1479 1480 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1481 if (!(gpio_mask & 1)) 1482 continue; 1483 1484 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1485 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1486 } 1487 } 1488 1489 bool ath9k_hw_check_alive(struct ath_hw *ah) 1490 { 1491 int count = 50; 1492 u32 reg; 1493 1494 if (AR_SREV_9285_12_OR_LATER(ah)) 1495 return true; 1496 1497 do { 1498 reg = REG_READ(ah, AR_OBS_BUS_1); 1499 1500 if ((reg & 0x7E7FFFEF) == 0x00702400) 1501 continue; 1502 1503 switch (reg & 0x7E000B00) { 1504 case 0x1E000000: 1505 case 0x52000B00: 1506 case 0x18000B00: 1507 continue; 1508 default: 1509 return true; 1510 } 1511 } while (count-- > 0); 1512 1513 return false; 1514 } 1515 EXPORT_SYMBOL(ath9k_hw_check_alive); 1516 1517 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1518 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1519 { 1520 struct ath_common *common = ath9k_hw_common(ah); 1521 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; 1522 u32 saveLedState; 1523 struct ath9k_channel *curchan = ah->curchan; 1524 u32 saveDefAntenna; 1525 u32 macStaId1; 1526 u64 tsf = 0; 1527 int i, r; 1528 bool allow_fbs = false; 1529 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1530 bool save_fullsleep = ah->chip_fullsleep; 1531 1532 if (mci) { 1533 1534 ar9003_mci_2g5g_changed(ah, IS_CHAN_2GHZ(chan)); 1535 1536 if (mci_hw->bt_state == MCI_BT_CAL_START) { 1537 u32 payload[4] = {0, 0, 0, 0}; 1538 1539 ath_dbg(common, MCI, "MCI stop rx for BT CAL\n"); 1540 1541 mci_hw->bt_state = MCI_BT_CAL; 1542 1543 /* 1544 * MCI FIX: disable mci interrupt here. This is to avoid 1545 * SW_MSG_DONE or RX_MSG bits to trigger MCI_INT and 1546 * lead to mci_intr reentry. 1547 */ 1548 1549 ar9003_mci_disable_interrupt(ah); 1550 1551 ath_dbg(common, MCI, "send WLAN_CAL_GRANT\n"); 1552 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT); 1553 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 1554 16, true, false); 1555 1556 ath_dbg(common, MCI, "\nMCI BT is calibrating\n"); 1557 1558 /* Wait BT calibration to be completed for 25ms */ 1559 1560 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE, 1561 0, 25000)) 1562 ath_dbg(common, MCI, 1563 "MCI got BT_CAL_DONE\n"); 1564 else 1565 ath_dbg(common, MCI, 1566 "MCI ### BT cal takes to long, force bt_state to be bt_awake\n"); 1567 mci_hw->bt_state = MCI_BT_AWAKE; 1568 /* MCI FIX: enable mci interrupt here */ 1569 ar9003_mci_enable_interrupt(ah); 1570 1571 return true; 1572 } 1573 } 1574 1575 1576 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1577 return -EIO; 1578 1579 if (curchan && !ah->chip_fullsleep) 1580 ath9k_hw_getnf(ah, curchan); 1581 1582 ah->caldata = caldata; 1583 if (caldata && 1584 (chan->channel != caldata->channel || 1585 (chan->channelFlags & ~CHANNEL_CW_INT) != 1586 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1587 /* Operating channel changed, reset channel calibration data */ 1588 memset(caldata, 0, sizeof(*caldata)); 1589 ath9k_init_nfcal_hist_buffer(ah, chan); 1590 } 1591 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1592 1593 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1594 bChannelChange = false; 1595 1596 if (caldata && 1597 caldata->done_txiqcal_once && 1598 caldata->done_txclcal_once && 1599 caldata->rtt_hist.num_readings) 1600 allow_fbs = true; 1601 1602 if (bChannelChange && 1603 (ah->chip_fullsleep != true) && 1604 (ah->curchan != NULL) && 1605 (chan->channel != ah->curchan->channel) && 1606 (allow_fbs || 1607 ((chan->channelFlags & CHANNEL_ALL) == 1608 (ah->curchan->channelFlags & CHANNEL_ALL)))) { 1609 if (ath9k_hw_channel_change(ah, chan)) { 1610 ath9k_hw_loadnf(ah, ah->curchan); 1611 ath9k_hw_start_nfcal(ah, true); 1612 if (mci && mci_hw->ready) 1613 ar9003_mci_2g5g_switch(ah, true); 1614 1615 if (AR_SREV_9271(ah)) 1616 ar9002_hw_load_ani_reg(ah, chan); 1617 return 0; 1618 } 1619 } 1620 1621 if (mci) { 1622 ar9003_mci_disable_interrupt(ah); 1623 1624 if (mci_hw->ready && !save_fullsleep) { 1625 ar9003_mci_mute_bt(ah); 1626 udelay(20); 1627 REG_WRITE(ah, AR_BTCOEX_CTRL, 0); 1628 } 1629 1630 mci_hw->bt_state = MCI_BT_SLEEP; 1631 mci_hw->ready = false; 1632 } 1633 1634 1635 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1636 if (saveDefAntenna == 0) 1637 saveDefAntenna = 1; 1638 1639 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1640 1641 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1642 if (AR_SREV_9100(ah) || 1643 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1644 tsf = ath9k_hw_gettsf64(ah); 1645 1646 saveLedState = REG_READ(ah, AR_CFG_LED) & 1647 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1648 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1649 1650 ath9k_hw_mark_phy_inactive(ah); 1651 1652 ah->paprd_table_write_done = false; 1653 1654 /* Only required on the first reset */ 1655 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1656 REG_WRITE(ah, 1657 AR9271_RESET_POWER_DOWN_CONTROL, 1658 AR9271_RADIO_RF_RST); 1659 udelay(50); 1660 } 1661 1662 if (!ath9k_hw_chip_reset(ah, chan)) { 1663 ath_err(common, "Chip reset failed\n"); 1664 return -EINVAL; 1665 } 1666 1667 /* Only required on the first reset */ 1668 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1669 ah->htc_reset_init = false; 1670 REG_WRITE(ah, 1671 AR9271_RESET_POWER_DOWN_CONTROL, 1672 AR9271_GATE_MAC_CTL); 1673 udelay(50); 1674 } 1675 1676 /* Restore TSF */ 1677 if (tsf) 1678 ath9k_hw_settsf64(ah, tsf); 1679 1680 if (AR_SREV_9280_20_OR_LATER(ah)) 1681 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1682 1683 if (!AR_SREV_9300_20_OR_LATER(ah)) 1684 ar9002_hw_enable_async_fifo(ah); 1685 1686 r = ath9k_hw_process_ini(ah, chan); 1687 if (r) 1688 return r; 1689 1690 if (mci) 1691 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1692 1693 /* 1694 * Some AR91xx SoC devices frequently fail to accept TSF writes 1695 * right after the chip reset. When that happens, write a new 1696 * value after the initvals have been applied, with an offset 1697 * based on measured time difference 1698 */ 1699 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1700 tsf += 1500; 1701 ath9k_hw_settsf64(ah, tsf); 1702 } 1703 1704 /* Setup MFP options for CCMP */ 1705 if (AR_SREV_9280_20_OR_LATER(ah)) { 1706 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1707 * frames when constructing CCMP AAD. */ 1708 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1709 0xc7ff); 1710 ah->sw_mgmt_crypto = false; 1711 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1712 /* Disable hardware crypto for management frames */ 1713 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1714 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1715 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1716 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1717 ah->sw_mgmt_crypto = true; 1718 } else 1719 ah->sw_mgmt_crypto = true; 1720 1721 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1722 ath9k_hw_set_delta_slope(ah, chan); 1723 1724 ath9k_hw_spur_mitigate_freq(ah, chan); 1725 ah->eep_ops->set_board_values(ah, chan); 1726 1727 ENABLE_REGWRITE_BUFFER(ah); 1728 1729 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1730 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1731 | macStaId1 1732 | AR_STA_ID1_RTS_USE_DEF 1733 | (ah->config. 1734 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1735 | ah->sta_id1_defaults); 1736 ath_hw_setbssidmask(common); 1737 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1738 ath9k_hw_write_associd(ah); 1739 REG_WRITE(ah, AR_ISR, ~0); 1740 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1741 1742 REGWRITE_BUFFER_FLUSH(ah); 1743 1744 ath9k_hw_set_operating_mode(ah, ah->opmode); 1745 1746 r = ath9k_hw_rf_set_freq(ah, chan); 1747 if (r) 1748 return r; 1749 1750 ath9k_hw_set_clockrate(ah); 1751 1752 ENABLE_REGWRITE_BUFFER(ah); 1753 1754 for (i = 0; i < AR_NUM_DCU; i++) 1755 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1756 1757 REGWRITE_BUFFER_FLUSH(ah); 1758 1759 ah->intr_txqs = 0; 1760 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1761 ath9k_hw_resettxqueue(ah, i); 1762 1763 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1764 ath9k_hw_ani_cache_ini_regs(ah); 1765 ath9k_hw_init_qos(ah); 1766 1767 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1768 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1769 1770 ath9k_hw_init_global_settings(ah); 1771 1772 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1773 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1774 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1775 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1776 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1777 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1778 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1779 } 1780 1781 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1782 1783 ath9k_hw_set_dma(ah); 1784 1785 REG_WRITE(ah, AR_OBS, 8); 1786 1787 if (ah->config.rx_intr_mitigation) { 1788 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1789 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1790 } 1791 1792 if (ah->config.tx_intr_mitigation) { 1793 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1794 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1795 } 1796 1797 ath9k_hw_init_bb(ah, chan); 1798 1799 if (caldata) { 1800 caldata->done_txiqcal_once = false; 1801 caldata->done_txclcal_once = false; 1802 caldata->rtt_hist.num_readings = 0; 1803 } 1804 if (!ath9k_hw_init_cal(ah, chan)) 1805 return -EIO; 1806 1807 ath9k_hw_loadnf(ah, chan); 1808 ath9k_hw_start_nfcal(ah, true); 1809 1810 if (mci && mci_hw->ready) { 1811 1812 if (IS_CHAN_2GHZ(chan) && 1813 (mci_hw->bt_state == MCI_BT_SLEEP)) { 1814 1815 if (ar9003_mci_check_int(ah, 1816 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) || 1817 ar9003_mci_check_int(ah, 1818 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) { 1819 1820 /* 1821 * BT is sleeping. Check if BT wakes up during 1822 * WLAN calibration. If BT wakes up during 1823 * WLAN calibration, need to go through all 1824 * message exchanges again and recal. 1825 */ 1826 1827 ath_dbg(common, MCI, 1828 "MCI BT wakes up during WLAN calibration\n"); 1829 1830 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 1831 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | 1832 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE); 1833 ath_dbg(common, MCI, "MCI send REMOTE_RESET\n"); 1834 ar9003_mci_remote_reset(ah, true); 1835 ar9003_mci_send_sys_waking(ah, true); 1836 udelay(1); 1837 if (IS_CHAN_2GHZ(chan)) 1838 ar9003_mci_send_lna_transfer(ah, true); 1839 1840 mci_hw->bt_state = MCI_BT_AWAKE; 1841 1842 ath_dbg(common, MCI, "MCI re-cal\n"); 1843 1844 if (caldata) { 1845 caldata->done_txiqcal_once = false; 1846 caldata->done_txclcal_once = false; 1847 caldata->rtt_hist.num_readings = 0; 1848 } 1849 1850 if (!ath9k_hw_init_cal(ah, chan)) 1851 return -EIO; 1852 1853 } 1854 } 1855 ar9003_mci_enable_interrupt(ah); 1856 } 1857 1858 ENABLE_REGWRITE_BUFFER(ah); 1859 1860 ath9k_hw_restore_chainmask(ah); 1861 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1862 1863 REGWRITE_BUFFER_FLUSH(ah); 1864 1865 /* 1866 * For big endian systems turn on swapping for descriptors 1867 */ 1868 if (AR_SREV_9100(ah)) { 1869 u32 mask; 1870 mask = REG_READ(ah, AR_CFG); 1871 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1872 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1873 mask); 1874 } else { 1875 mask = 1876 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1877 REG_WRITE(ah, AR_CFG, mask); 1878 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1879 REG_READ(ah, AR_CFG)); 1880 } 1881 } else { 1882 if (common->bus_ops->ath_bus_type == ATH_USB) { 1883 /* Configure AR9271 target WLAN */ 1884 if (AR_SREV_9271(ah)) 1885 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1886 else 1887 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1888 } 1889 #ifdef __BIG_ENDIAN 1890 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 1891 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1892 else 1893 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1894 #endif 1895 } 1896 1897 if (ah->btcoex_hw.enabled && 1898 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) 1899 ath9k_hw_btcoex_enable(ah); 1900 1901 if (mci && mci_hw->ready) { 1902 /* 1903 * check BT state again to make 1904 * sure it's not changed. 1905 */ 1906 1907 ar9003_mci_sync_bt_state(ah); 1908 ar9003_mci_2g5g_switch(ah, true); 1909 1910 if ((mci_hw->bt_state == MCI_BT_AWAKE) && 1911 (mci_hw->query_bt == true)) { 1912 mci_hw->need_flush_btinfo = true; 1913 } 1914 } 1915 1916 if (AR_SREV_9300_20_OR_LATER(ah)) { 1917 ar9003_hw_bb_watchdog_config(ah); 1918 1919 ar9003_hw_disable_phy_restart(ah); 1920 } 1921 1922 ath9k_hw_apply_gpio_override(ah); 1923 1924 return 0; 1925 } 1926 EXPORT_SYMBOL(ath9k_hw_reset); 1927 1928 /******************************/ 1929 /* Power Management (Chipset) */ 1930 /******************************/ 1931 1932 /* 1933 * Notify Power Mgt is disabled in self-generated frames. 1934 * If requested, force chip to sleep. 1935 */ 1936 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1937 { 1938 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1939 if (setChip) { 1940 if (AR_SREV_9462(ah)) { 1941 REG_WRITE(ah, AR_TIMER_MODE, 1942 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 1943 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, 1944 AR_NDP2_TIMER_MODE) & 0xFFFFFF00); 1945 REG_WRITE(ah, AR_SLP32_INC, 1946 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); 1947 /* xxx Required for WLAN only case ? */ 1948 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 1949 udelay(100); 1950 } 1951 1952 /* 1953 * Clear the RTC force wake bit to allow the 1954 * mac to go to sleep. 1955 */ 1956 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1957 1958 if (AR_SREV_9462(ah)) 1959 udelay(100); 1960 1961 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1962 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1963 1964 /* Shutdown chip. Active low */ 1965 if (!AR_SREV_5416(ah) && 1966 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) { 1967 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 1968 udelay(2); 1969 } 1970 } 1971 1972 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1973 if (AR_SREV_9300_20_OR_LATER(ah)) 1974 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1975 } 1976 1977 /* 1978 * Notify Power Management is enabled in self-generating 1979 * frames. If request, set power mode of chip to 1980 * auto/normal. Duration in units of 128us (1/8 TU). 1981 */ 1982 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1983 { 1984 u32 val; 1985 1986 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1987 if (setChip) { 1988 struct ath9k_hw_capabilities *pCap = &ah->caps; 1989 1990 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1991 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1992 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1993 AR_RTC_FORCE_WAKE_ON_INT); 1994 } else { 1995 1996 /* When chip goes into network sleep, it could be waken 1997 * up by MCI_INT interrupt caused by BT's HW messages 1998 * (LNA_xxx, CONT_xxx) which chould be in a very fast 1999 * rate (~100us). This will cause chip to leave and 2000 * re-enter network sleep mode frequently, which in 2001 * consequence will have WLAN MCI HW to generate lots of 2002 * SYS_WAKING and SYS_SLEEPING messages which will make 2003 * BT CPU to busy to process. 2004 */ 2005 if (AR_SREV_9462(ah)) { 2006 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 2007 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 2008 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 2009 } 2010 /* 2011 * Clear the RTC force wake bit to allow the 2012 * mac to go to sleep. 2013 */ 2014 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2015 AR_RTC_FORCE_WAKE_EN); 2016 2017 if (AR_SREV_9462(ah)) 2018 udelay(30); 2019 } 2020 } 2021 2022 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2023 if (AR_SREV_9300_20_OR_LATER(ah)) 2024 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2025 } 2026 2027 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2028 { 2029 u32 val; 2030 int i; 2031 2032 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2033 if (AR_SREV_9300_20_OR_LATER(ah)) { 2034 REG_WRITE(ah, AR_WA, ah->WARegVal); 2035 udelay(10); 2036 } 2037 2038 if (setChip) { 2039 if ((REG_READ(ah, AR_RTC_STATUS) & 2040 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2041 if (ath9k_hw_set_reset_reg(ah, 2042 ATH9K_RESET_POWER_ON) != true) { 2043 return false; 2044 } 2045 if (!AR_SREV_9300_20_OR_LATER(ah)) 2046 ath9k_hw_init_pll(ah, NULL); 2047 } 2048 if (AR_SREV_9100(ah)) 2049 REG_SET_BIT(ah, AR_RTC_RESET, 2050 AR_RTC_RESET_EN); 2051 2052 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2053 AR_RTC_FORCE_WAKE_EN); 2054 udelay(50); 2055 2056 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2057 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2058 if (val == AR_RTC_STATUS_ON) 2059 break; 2060 udelay(50); 2061 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2062 AR_RTC_FORCE_WAKE_EN); 2063 } 2064 if (i == 0) { 2065 ath_err(ath9k_hw_common(ah), 2066 "Failed to wakeup in %uus\n", 2067 POWER_UP_TIME / 20); 2068 return false; 2069 } 2070 } 2071 2072 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2073 2074 return true; 2075 } 2076 2077 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2078 { 2079 struct ath_common *common = ath9k_hw_common(ah); 2080 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 2081 int status = true, setChip = true; 2082 static const char *modes[] = { 2083 "AWAKE", 2084 "FULL-SLEEP", 2085 "NETWORK SLEEP", 2086 "UNDEFINED" 2087 }; 2088 2089 if (ah->power_mode == mode) 2090 return status; 2091 2092 ath_dbg(common, RESET, "%s -> %s\n", 2093 modes[ah->power_mode], modes[mode]); 2094 2095 switch (mode) { 2096 case ATH9K_PM_AWAKE: 2097 status = ath9k_hw_set_power_awake(ah, setChip); 2098 2099 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2100 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2101 2102 break; 2103 case ATH9K_PM_FULL_SLEEP: 2104 2105 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) { 2106 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) && 2107 (mci->bt_state != MCI_BT_SLEEP) && 2108 !mci->halted_bt_gpm) { 2109 ath_dbg(common, MCI, 2110 "MCI halt BT GPM (full_sleep)\n"); 2111 ar9003_mci_send_coex_halt_bt_gpm(ah, 2112 true, true); 2113 } 2114 2115 mci->ready = false; 2116 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2117 } 2118 2119 ath9k_set_power_sleep(ah, setChip); 2120 ah->chip_fullsleep = true; 2121 break; 2122 case ATH9K_PM_NETWORK_SLEEP: 2123 2124 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2125 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); 2126 2127 ath9k_set_power_network_sleep(ah, setChip); 2128 break; 2129 default: 2130 ath_err(common, "Unknown power mode %u\n", mode); 2131 return false; 2132 } 2133 ah->power_mode = mode; 2134 2135 /* 2136 * XXX: If this warning never comes up after a while then 2137 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2138 * ath9k_hw_setpower() return type void. 2139 */ 2140 2141 if (!(ah->ah_flags & AH_UNPLUGGED)) 2142 ATH_DBG_WARN_ON_ONCE(!status); 2143 2144 return status; 2145 } 2146 EXPORT_SYMBOL(ath9k_hw_setpower); 2147 2148 /*******************/ 2149 /* Beacon Handling */ 2150 /*******************/ 2151 2152 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2153 { 2154 int flags = 0; 2155 2156 ENABLE_REGWRITE_BUFFER(ah); 2157 2158 switch (ah->opmode) { 2159 case NL80211_IFTYPE_ADHOC: 2160 case NL80211_IFTYPE_MESH_POINT: 2161 REG_SET_BIT(ah, AR_TXCFG, 2162 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2163 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2164 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2165 flags |= AR_NDP_TIMER_EN; 2166 case NL80211_IFTYPE_AP: 2167 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2168 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2169 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2170 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2171 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2172 flags |= 2173 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2174 break; 2175 default: 2176 ath_dbg(ath9k_hw_common(ah), BEACON, 2177 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2178 return; 2179 break; 2180 } 2181 2182 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2183 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2184 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2185 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2186 2187 REGWRITE_BUFFER_FLUSH(ah); 2188 2189 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2190 } 2191 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2192 2193 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2194 const struct ath9k_beacon_state *bs) 2195 { 2196 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2197 struct ath9k_hw_capabilities *pCap = &ah->caps; 2198 struct ath_common *common = ath9k_hw_common(ah); 2199 2200 ENABLE_REGWRITE_BUFFER(ah); 2201 2202 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2203 2204 REG_WRITE(ah, AR_BEACON_PERIOD, 2205 TU_TO_USEC(bs->bs_intval)); 2206 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2207 TU_TO_USEC(bs->bs_intval)); 2208 2209 REGWRITE_BUFFER_FLUSH(ah); 2210 2211 REG_RMW_FIELD(ah, AR_RSSI_THR, 2212 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2213 2214 beaconintval = bs->bs_intval; 2215 2216 if (bs->bs_sleepduration > beaconintval) 2217 beaconintval = bs->bs_sleepduration; 2218 2219 dtimperiod = bs->bs_dtimperiod; 2220 if (bs->bs_sleepduration > dtimperiod) 2221 dtimperiod = bs->bs_sleepduration; 2222 2223 if (beaconintval == dtimperiod) 2224 nextTbtt = bs->bs_nextdtim; 2225 else 2226 nextTbtt = bs->bs_nexttbtt; 2227 2228 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2229 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2230 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2231 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2232 2233 ENABLE_REGWRITE_BUFFER(ah); 2234 2235 REG_WRITE(ah, AR_NEXT_DTIM, 2236 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2237 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2238 2239 REG_WRITE(ah, AR_SLEEP1, 2240 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2241 | AR_SLEEP1_ASSUME_DTIM); 2242 2243 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2244 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2245 else 2246 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2247 2248 REG_WRITE(ah, AR_SLEEP2, 2249 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2250 2251 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2252 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2253 2254 REGWRITE_BUFFER_FLUSH(ah); 2255 2256 REG_SET_BIT(ah, AR_TIMER_MODE, 2257 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2258 AR_DTIM_TIMER_EN); 2259 2260 /* TSF Out of Range Threshold */ 2261 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2262 } 2263 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2264 2265 /*******************/ 2266 /* HW Capabilities */ 2267 /*******************/ 2268 2269 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2270 { 2271 eeprom_chainmask &= chip_chainmask; 2272 if (eeprom_chainmask) 2273 return eeprom_chainmask; 2274 else 2275 return chip_chainmask; 2276 } 2277 2278 /** 2279 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2280 * @ah: the atheros hardware data structure 2281 * 2282 * We enable DFS support upstream on chipsets which have passed a series 2283 * of tests. The testing requirements are going to be documented. Desired 2284 * test requirements are documented at: 2285 * 2286 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2287 * 2288 * Once a new chipset gets properly tested an individual commit can be used 2289 * to document the testing for DFS for that chipset. 2290 */ 2291 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2292 { 2293 2294 switch (ah->hw_version.macVersion) { 2295 /* AR9580 will likely be our first target to get testing on */ 2296 case AR_SREV_VERSION_9580: 2297 default: 2298 return false; 2299 } 2300 } 2301 2302 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2303 { 2304 struct ath9k_hw_capabilities *pCap = &ah->caps; 2305 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2306 struct ath_common *common = ath9k_hw_common(ah); 2307 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2308 unsigned int chip_chainmask; 2309 2310 u16 eeval; 2311 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2312 2313 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2314 regulatory->current_rd = eeval; 2315 2316 if (ah->opmode != NL80211_IFTYPE_AP && 2317 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2318 if (regulatory->current_rd == 0x64 || 2319 regulatory->current_rd == 0x65) 2320 regulatory->current_rd += 5; 2321 else if (regulatory->current_rd == 0x41) 2322 regulatory->current_rd = 0x43; 2323 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2324 regulatory->current_rd); 2325 } 2326 2327 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2328 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2329 ath_err(common, 2330 "no band has been marked as supported in EEPROM\n"); 2331 return -EINVAL; 2332 } 2333 2334 if (eeval & AR5416_OPFLAGS_11A) 2335 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2336 2337 if (eeval & AR5416_OPFLAGS_11G) 2338 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2339 2340 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) 2341 chip_chainmask = 1; 2342 else if (AR_SREV_9462(ah)) 2343 chip_chainmask = 3; 2344 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2345 chip_chainmask = 7; 2346 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2347 chip_chainmask = 3; 2348 else 2349 chip_chainmask = 7; 2350 2351 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2352 /* 2353 * For AR9271 we will temporarilly uses the rx chainmax as read from 2354 * the EEPROM. 2355 */ 2356 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2357 !(eeval & AR5416_OPFLAGS_11A) && 2358 !(AR_SREV_9271(ah))) 2359 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2360 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2361 else if (AR_SREV_9100(ah)) 2362 pCap->rx_chainmask = 0x7; 2363 else 2364 /* Use rx_chainmask from EEPROM. */ 2365 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2366 2367 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2368 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2369 ah->txchainmask = pCap->tx_chainmask; 2370 ah->rxchainmask = pCap->rx_chainmask; 2371 2372 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2373 2374 /* enable key search for every frame in an aggregate */ 2375 if (AR_SREV_9300_20_OR_LATER(ah)) 2376 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2377 2378 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2379 2380 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2381 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2382 else 2383 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2384 2385 if (AR_SREV_9271(ah)) 2386 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2387 else if (AR_DEVID_7010(ah)) 2388 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2389 else if (AR_SREV_9300_20_OR_LATER(ah)) 2390 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2391 else if (AR_SREV_9287_11_OR_LATER(ah)) 2392 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2393 else if (AR_SREV_9285_12_OR_LATER(ah)) 2394 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2395 else if (AR_SREV_9280_20_OR_LATER(ah)) 2396 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2397 else 2398 pCap->num_gpio_pins = AR_NUM_GPIO; 2399 2400 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2401 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2402 else 2403 pCap->rts_aggr_limit = (8 * 1024); 2404 2405 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2406 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2407 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2408 ah->rfkill_gpio = 2409 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2410 ah->rfkill_polarity = 2411 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2412 2413 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2414 } 2415 #endif 2416 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2417 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2418 else 2419 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2420 2421 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2422 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2423 else 2424 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2425 2426 if (common->btcoex_enabled) { 2427 if (AR_SREV_9462(ah)) 2428 btcoex_hw->scheme = ATH_BTCOEX_CFG_MCI; 2429 else if (AR_SREV_9300_20_OR_LATER(ah)) { 2430 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2431 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300; 2432 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300; 2433 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300; 2434 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 2435 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280; 2436 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280; 2437 2438 if (AR_SREV_9285(ah)) { 2439 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2440 btcoex_hw->btpriority_gpio = 2441 ATH_BTPRIORITY_GPIO_9285; 2442 } else { 2443 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2444 } 2445 } 2446 } else { 2447 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2448 } 2449 2450 if (AR_SREV_9300_20_OR_LATER(ah)) { 2451 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2452 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) 2453 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2454 2455 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2456 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2457 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2458 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2459 pCap->txs_len = sizeof(struct ar9003_txs); 2460 if (!ah->config.paprd_disable && 2461 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2462 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2463 } else { 2464 pCap->tx_desc_len = sizeof(struct ath_desc); 2465 if (AR_SREV_9280_20(ah)) 2466 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2467 } 2468 2469 if (AR_SREV_9300_20_OR_LATER(ah)) 2470 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2471 2472 if (AR_SREV_9300_20_OR_LATER(ah)) 2473 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2474 2475 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2476 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2477 2478 if (AR_SREV_9285(ah)) 2479 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2480 ant_div_ctl1 = 2481 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2482 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2483 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2484 } 2485 if (AR_SREV_9300_20_OR_LATER(ah)) { 2486 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2487 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2488 } 2489 2490 2491 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 2492 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2493 /* 2494 * enable the diversity-combining algorithm only when 2495 * both enable_lna_div and enable_fast_div are set 2496 * Table for Diversity 2497 * ant_div_alt_lnaconf bit 0-1 2498 * ant_div_main_lnaconf bit 2-3 2499 * ant_div_alt_gaintb bit 4 2500 * ant_div_main_gaintb bit 5 2501 * enable_ant_div_lnadiv bit 6 2502 * enable_ant_fast_div bit 7 2503 */ 2504 if ((ant_div_ctl1 >> 0x6) == 0x3) 2505 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2506 } 2507 2508 if (AR_SREV_9485_10(ah)) { 2509 pCap->pcie_lcr_extsync_en = true; 2510 pCap->pcie_lcr_offset = 0x80; 2511 } 2512 2513 if (ath9k_hw_dfs_tested(ah)) 2514 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2515 2516 tx_chainmask = pCap->tx_chainmask; 2517 rx_chainmask = pCap->rx_chainmask; 2518 while (tx_chainmask || rx_chainmask) { 2519 if (tx_chainmask & BIT(0)) 2520 pCap->max_txchains++; 2521 if (rx_chainmask & BIT(0)) 2522 pCap->max_rxchains++; 2523 2524 tx_chainmask >>= 1; 2525 rx_chainmask >>= 1; 2526 } 2527 2528 if (AR_SREV_9300_20_OR_LATER(ah)) { 2529 ah->enabled_cals |= TX_IQ_CAL; 2530 if (AR_SREV_9485_OR_LATER(ah)) 2531 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2532 } 2533 if (AR_SREV_9462(ah)) 2534 pCap->hw_caps |= ATH9K_HW_CAP_RTT | ATH9K_HW_CAP_MCI; 2535 2536 return 0; 2537 } 2538 2539 /****************************/ 2540 /* GPIO / RFKILL / Antennae */ 2541 /****************************/ 2542 2543 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2544 u32 gpio, u32 type) 2545 { 2546 int addr; 2547 u32 gpio_shift, tmp; 2548 2549 if (gpio > 11) 2550 addr = AR_GPIO_OUTPUT_MUX3; 2551 else if (gpio > 5) 2552 addr = AR_GPIO_OUTPUT_MUX2; 2553 else 2554 addr = AR_GPIO_OUTPUT_MUX1; 2555 2556 gpio_shift = (gpio % 6) * 5; 2557 2558 if (AR_SREV_9280_20_OR_LATER(ah) 2559 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2560 REG_RMW(ah, addr, (type << gpio_shift), 2561 (0x1f << gpio_shift)); 2562 } else { 2563 tmp = REG_READ(ah, addr); 2564 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2565 tmp &= ~(0x1f << gpio_shift); 2566 tmp |= (type << gpio_shift); 2567 REG_WRITE(ah, addr, tmp); 2568 } 2569 } 2570 2571 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2572 { 2573 u32 gpio_shift; 2574 2575 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2576 2577 if (AR_DEVID_7010(ah)) { 2578 gpio_shift = gpio; 2579 REG_RMW(ah, AR7010_GPIO_OE, 2580 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2581 (AR7010_GPIO_OE_MASK << gpio_shift)); 2582 return; 2583 } 2584 2585 gpio_shift = gpio << 1; 2586 REG_RMW(ah, 2587 AR_GPIO_OE_OUT, 2588 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2589 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2590 } 2591 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2592 2593 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2594 { 2595 #define MS_REG_READ(x, y) \ 2596 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2597 2598 if (gpio >= ah->caps.num_gpio_pins) 2599 return 0xffffffff; 2600 2601 if (AR_DEVID_7010(ah)) { 2602 u32 val; 2603 val = REG_READ(ah, AR7010_GPIO_IN); 2604 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2605 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2606 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2607 AR_GPIO_BIT(gpio)) != 0; 2608 else if (AR_SREV_9271(ah)) 2609 return MS_REG_READ(AR9271, gpio) != 0; 2610 else if (AR_SREV_9287_11_OR_LATER(ah)) 2611 return MS_REG_READ(AR9287, gpio) != 0; 2612 else if (AR_SREV_9285_12_OR_LATER(ah)) 2613 return MS_REG_READ(AR9285, gpio) != 0; 2614 else if (AR_SREV_9280_20_OR_LATER(ah)) 2615 return MS_REG_READ(AR928X, gpio) != 0; 2616 else 2617 return MS_REG_READ(AR, gpio) != 0; 2618 } 2619 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2620 2621 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2622 u32 ah_signal_type) 2623 { 2624 u32 gpio_shift; 2625 2626 if (AR_DEVID_7010(ah)) { 2627 gpio_shift = gpio; 2628 REG_RMW(ah, AR7010_GPIO_OE, 2629 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2630 (AR7010_GPIO_OE_MASK << gpio_shift)); 2631 return; 2632 } 2633 2634 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2635 gpio_shift = 2 * gpio; 2636 REG_RMW(ah, 2637 AR_GPIO_OE_OUT, 2638 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2639 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2640 } 2641 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2642 2643 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2644 { 2645 if (AR_DEVID_7010(ah)) { 2646 val = val ? 0 : 1; 2647 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2648 AR_GPIO_BIT(gpio)); 2649 return; 2650 } 2651 2652 if (AR_SREV_9271(ah)) 2653 val = ~val; 2654 2655 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2656 AR_GPIO_BIT(gpio)); 2657 } 2658 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2659 2660 u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2661 { 2662 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2663 } 2664 EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2665 2666 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2667 { 2668 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2669 } 2670 EXPORT_SYMBOL(ath9k_hw_setantenna); 2671 2672 /*********************/ 2673 /* General Operation */ 2674 /*********************/ 2675 2676 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2677 { 2678 u32 bits = REG_READ(ah, AR_RX_FILTER); 2679 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2680 2681 if (phybits & AR_PHY_ERR_RADAR) 2682 bits |= ATH9K_RX_FILTER_PHYRADAR; 2683 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2684 bits |= ATH9K_RX_FILTER_PHYERR; 2685 2686 return bits; 2687 } 2688 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2689 2690 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2691 { 2692 u32 phybits; 2693 2694 ENABLE_REGWRITE_BUFFER(ah); 2695 2696 if (AR_SREV_9462(ah)) 2697 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2698 2699 REG_WRITE(ah, AR_RX_FILTER, bits); 2700 2701 phybits = 0; 2702 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2703 phybits |= AR_PHY_ERR_RADAR; 2704 if (bits & ATH9K_RX_FILTER_PHYERR) 2705 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2706 REG_WRITE(ah, AR_PHY_ERR, phybits); 2707 2708 if (phybits) 2709 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2710 else 2711 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2712 2713 REGWRITE_BUFFER_FLUSH(ah); 2714 } 2715 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2716 2717 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2718 { 2719 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2720 return false; 2721 2722 ath9k_hw_init_pll(ah, NULL); 2723 return true; 2724 } 2725 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2726 2727 bool ath9k_hw_disable(struct ath_hw *ah) 2728 { 2729 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2730 return false; 2731 2732 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2733 return false; 2734 2735 ath9k_hw_init_pll(ah, NULL); 2736 return true; 2737 } 2738 EXPORT_SYMBOL(ath9k_hw_disable); 2739 2740 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2741 { 2742 enum eeprom_param gain_param; 2743 2744 if (IS_CHAN_2GHZ(chan)) 2745 gain_param = EEP_ANTENNA_GAIN_2G; 2746 else 2747 gain_param = EEP_ANTENNA_GAIN_5G; 2748 2749 return ah->eep_ops->get_eeprom(ah, gain_param); 2750 } 2751 2752 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan) 2753 { 2754 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2755 struct ieee80211_channel *channel; 2756 int chan_pwr, new_pwr, max_gain; 2757 int ant_gain, ant_reduction = 0; 2758 2759 if (!chan) 2760 return; 2761 2762 channel = chan->chan; 2763 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2764 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2765 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2766 2767 ant_gain = get_antenna_gain(ah, chan); 2768 if (ant_gain > max_gain) 2769 ant_reduction = ant_gain - max_gain; 2770 2771 ah->eep_ops->set_txpower(ah, chan, 2772 ath9k_regd_get_ctl(reg, chan), 2773 ant_reduction, new_pwr, false); 2774 } 2775 2776 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2777 { 2778 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2779 struct ath9k_channel *chan = ah->curchan; 2780 struct ieee80211_channel *channel = chan->chan; 2781 2782 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2783 if (test) 2784 channel->max_power = MAX_RATE_POWER / 2; 2785 2786 ath9k_hw_apply_txpower(ah, chan); 2787 2788 if (test) 2789 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2790 } 2791 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2792 2793 void ath9k_hw_setopmode(struct ath_hw *ah) 2794 { 2795 ath9k_hw_set_operating_mode(ah, ah->opmode); 2796 } 2797 EXPORT_SYMBOL(ath9k_hw_setopmode); 2798 2799 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2800 { 2801 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2802 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2803 } 2804 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2805 2806 void ath9k_hw_write_associd(struct ath_hw *ah) 2807 { 2808 struct ath_common *common = ath9k_hw_common(ah); 2809 2810 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2811 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2812 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2813 } 2814 EXPORT_SYMBOL(ath9k_hw_write_associd); 2815 2816 #define ATH9K_MAX_TSF_READ 10 2817 2818 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2819 { 2820 u32 tsf_lower, tsf_upper1, tsf_upper2; 2821 int i; 2822 2823 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2824 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2825 tsf_lower = REG_READ(ah, AR_TSF_L32); 2826 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2827 if (tsf_upper2 == tsf_upper1) 2828 break; 2829 tsf_upper1 = tsf_upper2; 2830 } 2831 2832 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2833 2834 return (((u64)tsf_upper1 << 32) | tsf_lower); 2835 } 2836 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2837 2838 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2839 { 2840 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2841 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2842 } 2843 EXPORT_SYMBOL(ath9k_hw_settsf64); 2844 2845 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2846 { 2847 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2848 AH_TSF_WRITE_TIMEOUT)) 2849 ath_dbg(ath9k_hw_common(ah), RESET, 2850 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2851 2852 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2853 } 2854 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2855 2856 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2857 { 2858 if (setting) 2859 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2860 else 2861 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2862 } 2863 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2864 2865 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2866 { 2867 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2868 u32 macmode; 2869 2870 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2871 macmode = AR_2040_JOINED_RX_CLEAR; 2872 else 2873 macmode = 0; 2874 2875 REG_WRITE(ah, AR_2040_MODE, macmode); 2876 } 2877 2878 /* HW Generic timers configuration */ 2879 2880 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2881 { 2882 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2883 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2884 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2885 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2886 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2887 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2888 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2889 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2890 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2891 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2892 AR_NDP2_TIMER_MODE, 0x0002}, 2893 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2894 AR_NDP2_TIMER_MODE, 0x0004}, 2895 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2896 AR_NDP2_TIMER_MODE, 0x0008}, 2897 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2898 AR_NDP2_TIMER_MODE, 0x0010}, 2899 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2900 AR_NDP2_TIMER_MODE, 0x0020}, 2901 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2902 AR_NDP2_TIMER_MODE, 0x0040}, 2903 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2904 AR_NDP2_TIMER_MODE, 0x0080} 2905 }; 2906 2907 /* HW generic timer primitives */ 2908 2909 /* compute and clear index of rightmost 1 */ 2910 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2911 { 2912 u32 b; 2913 2914 b = *mask; 2915 b &= (0-b); 2916 *mask &= ~b; 2917 b *= debruijn32; 2918 b >>= 27; 2919 2920 return timer_table->gen_timer_index[b]; 2921 } 2922 2923 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2924 { 2925 return REG_READ(ah, AR_TSF_L32); 2926 } 2927 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2928 2929 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2930 void (*trigger)(void *), 2931 void (*overflow)(void *), 2932 void *arg, 2933 u8 timer_index) 2934 { 2935 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2936 struct ath_gen_timer *timer; 2937 2938 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2939 2940 if (timer == NULL) { 2941 ath_err(ath9k_hw_common(ah), 2942 "Failed to allocate memory for hw timer[%d]\n", 2943 timer_index); 2944 return NULL; 2945 } 2946 2947 /* allocate a hardware generic timer slot */ 2948 timer_table->timers[timer_index] = timer; 2949 timer->index = timer_index; 2950 timer->trigger = trigger; 2951 timer->overflow = overflow; 2952 timer->arg = arg; 2953 2954 return timer; 2955 } 2956 EXPORT_SYMBOL(ath_gen_timer_alloc); 2957 2958 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2959 struct ath_gen_timer *timer, 2960 u32 trig_timeout, 2961 u32 timer_period) 2962 { 2963 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2964 u32 tsf, timer_next; 2965 2966 BUG_ON(!timer_period); 2967 2968 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2969 2970 tsf = ath9k_hw_gettsf32(ah); 2971 2972 timer_next = tsf + trig_timeout; 2973 2974 ath_dbg(ath9k_hw_common(ah), HWTIMER, 2975 "current tsf %x period %x timer_next %x\n", 2976 tsf, timer_period, timer_next); 2977 2978 /* 2979 * Program generic timer registers 2980 */ 2981 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2982 timer_next); 2983 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2984 timer_period); 2985 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2986 gen_tmr_configuration[timer->index].mode_mask); 2987 2988 if (AR_SREV_9462(ah)) { 2989 /* 2990 * Starting from AR9462, each generic timer can select which tsf 2991 * to use. But we still follow the old rule, 0 - 7 use tsf and 2992 * 8 - 15 use tsf2. 2993 */ 2994 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 2995 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2996 (1 << timer->index)); 2997 else 2998 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 2999 (1 << timer->index)); 3000 } 3001 3002 /* Enable both trigger and thresh interrupt masks */ 3003 REG_SET_BIT(ah, AR_IMR_S5, 3004 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3005 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3006 } 3007 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3008 3009 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3010 { 3011 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3012 3013 if ((timer->index < AR_FIRST_NDP_TIMER) || 3014 (timer->index >= ATH_MAX_GEN_TIMER)) { 3015 return; 3016 } 3017 3018 /* Clear generic timer enable bits. */ 3019 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3020 gen_tmr_configuration[timer->index].mode_mask); 3021 3022 /* Disable both trigger and thresh interrupt masks */ 3023 REG_CLR_BIT(ah, AR_IMR_S5, 3024 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3025 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3026 3027 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3028 } 3029 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3030 3031 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3032 { 3033 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3034 3035 /* free the hardware generic timer slot */ 3036 timer_table->timers[timer->index] = NULL; 3037 kfree(timer); 3038 } 3039 EXPORT_SYMBOL(ath_gen_timer_free); 3040 3041 /* 3042 * Generic Timer Interrupts handling 3043 */ 3044 void ath_gen_timer_isr(struct ath_hw *ah) 3045 { 3046 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3047 struct ath_gen_timer *timer; 3048 struct ath_common *common = ath9k_hw_common(ah); 3049 u32 trigger_mask, thresh_mask, index; 3050 3051 /* get hardware generic timer interrupt status */ 3052 trigger_mask = ah->intr_gen_timer_trigger; 3053 thresh_mask = ah->intr_gen_timer_thresh; 3054 trigger_mask &= timer_table->timer_mask.val; 3055 thresh_mask &= timer_table->timer_mask.val; 3056 3057 trigger_mask &= ~thresh_mask; 3058 3059 while (thresh_mask) { 3060 index = rightmost_index(timer_table, &thresh_mask); 3061 timer = timer_table->timers[index]; 3062 BUG_ON(!timer); 3063 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 3064 index); 3065 timer->overflow(timer->arg); 3066 } 3067 3068 while (trigger_mask) { 3069 index = rightmost_index(timer_table, &trigger_mask); 3070 timer = timer_table->timers[index]; 3071 BUG_ON(!timer); 3072 ath_dbg(common, HWTIMER, 3073 "Gen timer[%d] trigger\n", index); 3074 timer->trigger(timer->arg); 3075 } 3076 } 3077 EXPORT_SYMBOL(ath_gen_timer_isr); 3078 3079 /********/ 3080 /* HTC */ 3081 /********/ 3082 3083 void ath9k_hw_htc_resetinit(struct ath_hw *ah) 3084 { 3085 ah->htc_reset_init = true; 3086 } 3087 EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 3088 3089 static struct { 3090 u32 version; 3091 const char * name; 3092 } ath_mac_bb_names[] = { 3093 /* Devices with external radios */ 3094 { AR_SREV_VERSION_5416_PCI, "5416" }, 3095 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3096 { AR_SREV_VERSION_9100, "9100" }, 3097 { AR_SREV_VERSION_9160, "9160" }, 3098 /* Single-chip solutions */ 3099 { AR_SREV_VERSION_9280, "9280" }, 3100 { AR_SREV_VERSION_9285, "9285" }, 3101 { AR_SREV_VERSION_9287, "9287" }, 3102 { AR_SREV_VERSION_9271, "9271" }, 3103 { AR_SREV_VERSION_9300, "9300" }, 3104 { AR_SREV_VERSION_9330, "9330" }, 3105 { AR_SREV_VERSION_9340, "9340" }, 3106 { AR_SREV_VERSION_9485, "9485" }, 3107 { AR_SREV_VERSION_9462, "9462" }, 3108 }; 3109 3110 /* For devices with external radios */ 3111 static struct { 3112 u16 version; 3113 const char * name; 3114 } ath_rf_names[] = { 3115 { 0, "5133" }, 3116 { AR_RAD5133_SREV_MAJOR, "5133" }, 3117 { AR_RAD5122_SREV_MAJOR, "5122" }, 3118 { AR_RAD2133_SREV_MAJOR, "2133" }, 3119 { AR_RAD2122_SREV_MAJOR, "2122" } 3120 }; 3121 3122 /* 3123 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3124 */ 3125 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3126 { 3127 int i; 3128 3129 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3130 if (ath_mac_bb_names[i].version == mac_bb_version) { 3131 return ath_mac_bb_names[i].name; 3132 } 3133 } 3134 3135 return "????"; 3136 } 3137 3138 /* 3139 * Return the RF name. "????" is returned if the RF is unknown. 3140 * Used for devices with external radios. 3141 */ 3142 static const char *ath9k_hw_rf_name(u16 rf_version) 3143 { 3144 int i; 3145 3146 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3147 if (ath_rf_names[i].version == rf_version) { 3148 return ath_rf_names[i].name; 3149 } 3150 } 3151 3152 return "????"; 3153 } 3154 3155 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3156 { 3157 int used; 3158 3159 /* chipsets >= AR9280 are single-chip */ 3160 if (AR_SREV_9280_20_OR_LATER(ah)) { 3161 used = snprintf(hw_name, len, 3162 "Atheros AR%s Rev:%x", 3163 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3164 ah->hw_version.macRev); 3165 } 3166 else { 3167 used = snprintf(hw_name, len, 3168 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3169 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3170 ah->hw_version.macRev, 3171 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3172 AR_RADIO_SREV_MAJOR)), 3173 ah->hw_version.phyRev); 3174 } 3175 3176 hw_name[used] = '\0'; 3177 } 3178 EXPORT_SYMBOL(ath9k_hw_name); 3179