1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 #include "ar9003_mci.h" 27 #include "ar9003_phy.h" 28 #include "debug.h" 29 #include "ath9k.h" 30 31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33 MODULE_AUTHOR("Atheros Communications"); 34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36 MODULE_LICENSE("Dual BSD/GPL"); 37 38 static int __init ath9k_init(void) 39 { 40 return 0; 41 } 42 module_init(ath9k_init); 43 44 static void __exit ath9k_exit(void) 45 { 46 return; 47 } 48 module_exit(ath9k_exit); 49 50 /* Private hardware callbacks */ 51 52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 53 { 54 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 55 } 56 57 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 58 { 59 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 60 } 61 62 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 63 struct ath9k_channel *chan) 64 { 65 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 66 } 67 68 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 69 { 70 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 71 return; 72 73 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 74 } 75 76 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 77 { 78 /* You will not have this callback if using the old ANI */ 79 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 80 return; 81 82 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 83 } 84 85 /********************/ 86 /* Helper Functions */ 87 /********************/ 88 89 #ifdef CONFIG_ATH9K_DEBUGFS 90 91 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 92 { 93 struct ath_softc *sc = common->priv; 94 if (sync_cause) 95 sc->debug.stats.istats.sync_cause_all++; 96 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 97 sc->debug.stats.istats.sync_rtc_irq++; 98 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 99 sc->debug.stats.istats.sync_mac_irq++; 100 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 101 sc->debug.stats.istats.eeprom_illegal_access++; 102 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 103 sc->debug.stats.istats.apb_timeout++; 104 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 105 sc->debug.stats.istats.pci_mode_conflict++; 106 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 107 sc->debug.stats.istats.host1_fatal++; 108 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 109 sc->debug.stats.istats.host1_perr++; 110 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 111 sc->debug.stats.istats.trcv_fifo_perr++; 112 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 113 sc->debug.stats.istats.radm_cpl_ep++; 114 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 115 sc->debug.stats.istats.radm_cpl_dllp_abort++; 116 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 117 sc->debug.stats.istats.radm_cpl_tlp_abort++; 118 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 119 sc->debug.stats.istats.radm_cpl_ecrc_err++; 120 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 121 sc->debug.stats.istats.radm_cpl_timeout++; 122 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 123 sc->debug.stats.istats.local_timeout++; 124 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 125 sc->debug.stats.istats.pm_access++; 126 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 127 sc->debug.stats.istats.mac_awake++; 128 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 129 sc->debug.stats.istats.mac_asleep++; 130 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 131 sc->debug.stats.istats.mac_sleep_access++; 132 } 133 #endif 134 135 136 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 137 { 138 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 139 struct ath_common *common = ath9k_hw_common(ah); 140 unsigned int clockrate; 141 142 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 143 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 144 clockrate = 117; 145 else if (!ah->curchan) /* should really check for CCK instead */ 146 clockrate = ATH9K_CLOCK_RATE_CCK; 147 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 148 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 149 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 150 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 151 else 152 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 153 154 if (conf_is_ht40(conf)) 155 clockrate *= 2; 156 157 if (ah->curchan) { 158 if (IS_CHAN_HALF_RATE(ah->curchan)) 159 clockrate /= 2; 160 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 161 clockrate /= 4; 162 } 163 164 common->clockrate = clockrate; 165 } 166 167 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 168 { 169 struct ath_common *common = ath9k_hw_common(ah); 170 171 return usecs * common->clockrate; 172 } 173 174 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 175 { 176 int i; 177 178 BUG_ON(timeout < AH_TIME_QUANTUM); 179 180 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 181 if ((REG_READ(ah, reg) & mask) == val) 182 return true; 183 184 udelay(AH_TIME_QUANTUM); 185 } 186 187 ath_dbg(ath9k_hw_common(ah), ANY, 188 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 189 timeout, reg, REG_READ(ah, reg), mask, val); 190 191 return false; 192 } 193 EXPORT_SYMBOL(ath9k_hw_wait); 194 195 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 196 int hw_delay) 197 { 198 if (IS_CHAN_B(chan)) 199 hw_delay = (4 * hw_delay) / 22; 200 else 201 hw_delay /= 10; 202 203 if (IS_CHAN_HALF_RATE(chan)) 204 hw_delay *= 2; 205 else if (IS_CHAN_QUARTER_RATE(chan)) 206 hw_delay *= 4; 207 208 udelay(hw_delay + BASE_ACTIVATE_DELAY); 209 } 210 211 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, 212 int column, unsigned int *writecnt) 213 { 214 int r; 215 216 ENABLE_REGWRITE_BUFFER(ah); 217 for (r = 0; r < array->ia_rows; r++) { 218 REG_WRITE(ah, INI_RA(array, r, 0), 219 INI_RA(array, r, column)); 220 DO_DELAY(*writecnt); 221 } 222 REGWRITE_BUFFER_FLUSH(ah); 223 } 224 225 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 226 { 227 u32 retval; 228 int i; 229 230 for (i = 0, retval = 0; i < n; i++) { 231 retval = (retval << 1) | (val & 1); 232 val >>= 1; 233 } 234 return retval; 235 } 236 237 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 238 u8 phy, int kbps, 239 u32 frameLen, u16 rateix, 240 bool shortPreamble) 241 { 242 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 243 244 if (kbps == 0) 245 return 0; 246 247 switch (phy) { 248 case WLAN_RC_PHY_CCK: 249 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 250 if (shortPreamble) 251 phyTime >>= 1; 252 numBits = frameLen << 3; 253 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 254 break; 255 case WLAN_RC_PHY_OFDM: 256 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 257 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 258 numBits = OFDM_PLCP_BITS + (frameLen << 3); 259 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 260 txTime = OFDM_SIFS_TIME_QUARTER 261 + OFDM_PREAMBLE_TIME_QUARTER 262 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 263 } else if (ah->curchan && 264 IS_CHAN_HALF_RATE(ah->curchan)) { 265 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 266 numBits = OFDM_PLCP_BITS + (frameLen << 3); 267 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 268 txTime = OFDM_SIFS_TIME_HALF + 269 OFDM_PREAMBLE_TIME_HALF 270 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 271 } else { 272 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 273 numBits = OFDM_PLCP_BITS + (frameLen << 3); 274 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 275 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 276 + (numSymbols * OFDM_SYMBOL_TIME); 277 } 278 break; 279 default: 280 ath_err(ath9k_hw_common(ah), 281 "Unknown phy %u (rate ix %u)\n", phy, rateix); 282 txTime = 0; 283 break; 284 } 285 286 return txTime; 287 } 288 EXPORT_SYMBOL(ath9k_hw_computetxtime); 289 290 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 291 struct ath9k_channel *chan, 292 struct chan_centers *centers) 293 { 294 int8_t extoff; 295 296 if (!IS_CHAN_HT40(chan)) { 297 centers->ctl_center = centers->ext_center = 298 centers->synth_center = chan->channel; 299 return; 300 } 301 302 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 303 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 304 centers->synth_center = 305 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 306 extoff = 1; 307 } else { 308 centers->synth_center = 309 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 310 extoff = -1; 311 } 312 313 centers->ctl_center = 314 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 315 /* 25 MHz spacing is supported by hw but not on upper layers */ 316 centers->ext_center = 317 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 318 } 319 320 /******************/ 321 /* Chip Revisions */ 322 /******************/ 323 324 static void ath9k_hw_read_revisions(struct ath_hw *ah) 325 { 326 u32 val; 327 328 switch (ah->hw_version.devid) { 329 case AR5416_AR9100_DEVID: 330 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 331 break; 332 case AR9300_DEVID_AR9330: 333 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 334 if (ah->get_mac_revision) { 335 ah->hw_version.macRev = ah->get_mac_revision(); 336 } else { 337 val = REG_READ(ah, AR_SREV); 338 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 339 } 340 return; 341 case AR9300_DEVID_AR9340: 342 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 343 val = REG_READ(ah, AR_SREV); 344 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 345 return; 346 case AR9300_DEVID_QCA955X: 347 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 348 return; 349 } 350 351 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 352 353 if (val == 0xFF) { 354 val = REG_READ(ah, AR_SREV); 355 ah->hw_version.macVersion = 356 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 357 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 358 359 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 360 ah->is_pciexpress = true; 361 else 362 ah->is_pciexpress = (val & 363 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 364 } else { 365 if (!AR_SREV_9100(ah)) 366 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 367 368 ah->hw_version.macRev = val & AR_SREV_REVISION; 369 370 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 371 ah->is_pciexpress = true; 372 } 373 } 374 375 /************************************/ 376 /* HW Attach, Detach, Init Routines */ 377 /************************************/ 378 379 static void ath9k_hw_disablepcie(struct ath_hw *ah) 380 { 381 if (!AR_SREV_5416(ah)) 382 return; 383 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 388 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 389 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 390 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 391 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 392 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 393 394 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 395 } 396 397 /* This should work for all families including legacy */ 398 static bool ath9k_hw_chip_test(struct ath_hw *ah) 399 { 400 struct ath_common *common = ath9k_hw_common(ah); 401 u32 regAddr[2] = { AR_STA_ID0 }; 402 u32 regHold[2]; 403 static const u32 patternData[4] = { 404 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 405 }; 406 int i, j, loop_max; 407 408 if (!AR_SREV_9300_20_OR_LATER(ah)) { 409 loop_max = 2; 410 regAddr[1] = AR_PHY_BASE + (8 << 2); 411 } else 412 loop_max = 1; 413 414 for (i = 0; i < loop_max; i++) { 415 u32 addr = regAddr[i]; 416 u32 wrData, rdData; 417 418 regHold[i] = REG_READ(ah, addr); 419 for (j = 0; j < 0x100; j++) { 420 wrData = (j << 16) | j; 421 REG_WRITE(ah, addr, wrData); 422 rdData = REG_READ(ah, addr); 423 if (rdData != wrData) { 424 ath_err(common, 425 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 426 addr, wrData, rdData); 427 return false; 428 } 429 } 430 for (j = 0; j < 4; j++) { 431 wrData = patternData[j]; 432 REG_WRITE(ah, addr, wrData); 433 rdData = REG_READ(ah, addr); 434 if (wrData != rdData) { 435 ath_err(common, 436 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 437 addr, wrData, rdData); 438 return false; 439 } 440 } 441 REG_WRITE(ah, regAddr[i], regHold[i]); 442 } 443 udelay(100); 444 445 return true; 446 } 447 448 static void ath9k_hw_init_config(struct ath_hw *ah) 449 { 450 int i; 451 452 ah->config.dma_beacon_response_time = 1; 453 ah->config.sw_beacon_response_time = 6; 454 ah->config.additional_swba_backoff = 0; 455 ah->config.ack_6mb = 0x0; 456 ah->config.cwm_ignore_extcca = 0; 457 ah->config.pcie_clock_req = 0; 458 ah->config.pcie_waen = 0; 459 ah->config.analog_shiftreg = 1; 460 ah->config.enable_ani = true; 461 462 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 463 ah->config.spurchans[i][0] = AR_NO_SPUR; 464 ah->config.spurchans[i][1] = AR_NO_SPUR; 465 } 466 467 ah->config.rx_intr_mitigation = true; 468 ah->config.pcieSerDesWrite = true; 469 470 /* 471 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 472 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 473 * This means we use it for all AR5416 devices, and the few 474 * minor PCI AR9280 devices out there. 475 * 476 * Serialization is required because these devices do not handle 477 * well the case of two concurrent reads/writes due to the latency 478 * involved. During one read/write another read/write can be issued 479 * on another CPU while the previous read/write may still be working 480 * on our hardware, if we hit this case the hardware poops in a loop. 481 * We prevent this by serializing reads and writes. 482 * 483 * This issue is not present on PCI-Express devices or pre-AR5416 484 * devices (legacy, 802.11abg). 485 */ 486 if (num_possible_cpus() > 1) 487 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 488 } 489 490 static void ath9k_hw_init_defaults(struct ath_hw *ah) 491 { 492 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 493 494 regulatory->country_code = CTRY_DEFAULT; 495 regulatory->power_limit = MAX_RATE_POWER; 496 497 ah->hw_version.magic = AR5416_MAGIC; 498 ah->hw_version.subvendorid = 0; 499 500 ah->atim_window = 0; 501 ah->sta_id1_defaults = 502 AR_STA_ID1_CRPT_MIC_ENABLE | 503 AR_STA_ID1_MCAST_KSRCH; 504 if (AR_SREV_9100(ah)) 505 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 506 ah->slottime = ATH9K_SLOT_TIME_9; 507 ah->globaltxtimeout = (u32) -1; 508 ah->power_mode = ATH9K_PM_UNDEFINED; 509 ah->htc_reset_init = true; 510 } 511 512 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 513 { 514 struct ath_common *common = ath9k_hw_common(ah); 515 u32 sum; 516 int i; 517 u16 eeval; 518 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 519 520 sum = 0; 521 for (i = 0; i < 3; i++) { 522 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 523 sum += eeval; 524 common->macaddr[2 * i] = eeval >> 8; 525 common->macaddr[2 * i + 1] = eeval & 0xff; 526 } 527 if (sum == 0 || sum == 0xffff * 3) 528 return -EADDRNOTAVAIL; 529 530 return 0; 531 } 532 533 static int ath9k_hw_post_init(struct ath_hw *ah) 534 { 535 struct ath_common *common = ath9k_hw_common(ah); 536 int ecode; 537 538 if (common->bus_ops->ath_bus_type != ATH_USB) { 539 if (!ath9k_hw_chip_test(ah)) 540 return -ENODEV; 541 } 542 543 if (!AR_SREV_9300_20_OR_LATER(ah)) { 544 ecode = ar9002_hw_rf_claim(ah); 545 if (ecode != 0) 546 return ecode; 547 } 548 549 ecode = ath9k_hw_eeprom_init(ah); 550 if (ecode != 0) 551 return ecode; 552 553 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 554 ah->eep_ops->get_eeprom_ver(ah), 555 ah->eep_ops->get_eeprom_rev(ah)); 556 557 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 558 if (ecode) { 559 ath_err(ath9k_hw_common(ah), 560 "Failed allocating banks for external radio\n"); 561 ath9k_hw_rf_free_ext_banks(ah); 562 return ecode; 563 } 564 565 if (ah->config.enable_ani) { 566 ath9k_hw_ani_setup(ah); 567 ath9k_hw_ani_init(ah); 568 } 569 570 return 0; 571 } 572 573 static void ath9k_hw_attach_ops(struct ath_hw *ah) 574 { 575 if (AR_SREV_9300_20_OR_LATER(ah)) 576 ar9003_hw_attach_ops(ah); 577 else 578 ar9002_hw_attach_ops(ah); 579 } 580 581 /* Called for all hardware families */ 582 static int __ath9k_hw_init(struct ath_hw *ah) 583 { 584 struct ath_common *common = ath9k_hw_common(ah); 585 int r = 0; 586 587 ath9k_hw_read_revisions(ah); 588 589 /* 590 * Read back AR_WA into a permanent copy and set bits 14 and 17. 591 * We need to do this to avoid RMW of this register. We cannot 592 * read the reg when chip is asleep. 593 */ 594 ah->WARegVal = REG_READ(ah, AR_WA); 595 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 596 AR_WA_ASPM_TIMER_BASED_DISABLE); 597 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 599 ath_err(common, "Couldn't reset chip\n"); 600 return -EIO; 601 } 602 603 if (AR_SREV_9462(ah)) 604 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 605 606 if (AR_SREV_9565(ah)) { 607 ah->WARegVal |= AR_WA_BIT22; 608 REG_WRITE(ah, AR_WA, ah->WARegVal); 609 } 610 611 ath9k_hw_init_defaults(ah); 612 ath9k_hw_init_config(ah); 613 614 ath9k_hw_attach_ops(ah); 615 616 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 617 ath_err(common, "Couldn't wakeup chip\n"); 618 return -EIO; 619 } 620 621 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 622 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 623 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 624 !ah->is_pciexpress)) { 625 ah->config.serialize_regmode = 626 SER_REG_MODE_ON; 627 } else { 628 ah->config.serialize_regmode = 629 SER_REG_MODE_OFF; 630 } 631 } 632 633 ath_dbg(common, RESET, "serialize_regmode is %d\n", 634 ah->config.serialize_regmode); 635 636 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 637 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 638 else 639 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 640 641 switch (ah->hw_version.macVersion) { 642 case AR_SREV_VERSION_5416_PCI: 643 case AR_SREV_VERSION_5416_PCIE: 644 case AR_SREV_VERSION_9160: 645 case AR_SREV_VERSION_9100: 646 case AR_SREV_VERSION_9280: 647 case AR_SREV_VERSION_9285: 648 case AR_SREV_VERSION_9287: 649 case AR_SREV_VERSION_9271: 650 case AR_SREV_VERSION_9300: 651 case AR_SREV_VERSION_9330: 652 case AR_SREV_VERSION_9485: 653 case AR_SREV_VERSION_9340: 654 case AR_SREV_VERSION_9462: 655 case AR_SREV_VERSION_9550: 656 case AR_SREV_VERSION_9565: 657 break; 658 default: 659 ath_err(common, 660 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 661 ah->hw_version.macVersion, ah->hw_version.macRev); 662 return -EOPNOTSUPP; 663 } 664 665 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 666 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 667 ah->is_pciexpress = false; 668 669 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 670 ath9k_hw_init_cal_settings(ah); 671 672 ah->ani_function = ATH9K_ANI_ALL; 673 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 674 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 675 if (!AR_SREV_9300_20_OR_LATER(ah)) 676 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 677 678 ath9k_hw_init_mode_regs(ah); 679 680 if (!ah->is_pciexpress) 681 ath9k_hw_disablepcie(ah); 682 683 r = ath9k_hw_post_init(ah); 684 if (r) 685 return r; 686 687 ath9k_hw_init_mode_gain_regs(ah); 688 r = ath9k_hw_fill_cap_info(ah); 689 if (r) 690 return r; 691 692 r = ath9k_hw_init_macaddr(ah); 693 if (r) { 694 ath_err(common, "Failed to initialize MAC address\n"); 695 return r; 696 } 697 698 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 699 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 700 else 701 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 702 703 if (AR_SREV_9330(ah)) 704 ah->bb_watchdog_timeout_ms = 85; 705 else 706 ah->bb_watchdog_timeout_ms = 25; 707 708 common->state = ATH_HW_INITIALIZED; 709 710 return 0; 711 } 712 713 int ath9k_hw_init(struct ath_hw *ah) 714 { 715 int ret; 716 struct ath_common *common = ath9k_hw_common(ah); 717 718 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 719 switch (ah->hw_version.devid) { 720 case AR5416_DEVID_PCI: 721 case AR5416_DEVID_PCIE: 722 case AR5416_AR9100_DEVID: 723 case AR9160_DEVID_PCI: 724 case AR9280_DEVID_PCI: 725 case AR9280_DEVID_PCIE: 726 case AR9285_DEVID_PCIE: 727 case AR9287_DEVID_PCI: 728 case AR9287_DEVID_PCIE: 729 case AR2427_DEVID_PCIE: 730 case AR9300_DEVID_PCIE: 731 case AR9300_DEVID_AR9485_PCIE: 732 case AR9300_DEVID_AR9330: 733 case AR9300_DEVID_AR9340: 734 case AR9300_DEVID_QCA955X: 735 case AR9300_DEVID_AR9580: 736 case AR9300_DEVID_AR9462: 737 case AR9485_DEVID_AR1111: 738 case AR9300_DEVID_AR9565: 739 break; 740 default: 741 if (common->bus_ops->ath_bus_type == ATH_USB) 742 break; 743 ath_err(common, "Hardware device ID 0x%04x not supported\n", 744 ah->hw_version.devid); 745 return -EOPNOTSUPP; 746 } 747 748 ret = __ath9k_hw_init(ah); 749 if (ret) { 750 ath_err(common, 751 "Unable to initialize hardware; initialization status: %d\n", 752 ret); 753 return ret; 754 } 755 756 return 0; 757 } 758 EXPORT_SYMBOL(ath9k_hw_init); 759 760 static void ath9k_hw_init_qos(struct ath_hw *ah) 761 { 762 ENABLE_REGWRITE_BUFFER(ah); 763 764 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 765 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 766 767 REG_WRITE(ah, AR_QOS_NO_ACK, 768 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 769 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 770 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 771 772 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 773 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 774 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 775 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 776 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 777 778 REGWRITE_BUFFER_FLUSH(ah); 779 } 780 781 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 782 { 783 struct ath_common *common = ath9k_hw_common(ah); 784 int i = 0; 785 786 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 787 udelay(100); 788 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 789 790 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 791 792 udelay(100); 793 794 if (WARN_ON_ONCE(i >= 100)) { 795 ath_err(common, "PLL4 meaurement not done\n"); 796 break; 797 } 798 799 i++; 800 } 801 802 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 803 } 804 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 805 806 static void ath9k_hw_init_pll(struct ath_hw *ah, 807 struct ath9k_channel *chan) 808 { 809 u32 pll; 810 811 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 812 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 814 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 816 AR_CH0_DPLL2_KD, 0x40); 817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 818 AR_CH0_DPLL2_KI, 0x4); 819 820 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 821 AR_CH0_BB_DPLL1_REFDIV, 0x5); 822 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 823 AR_CH0_BB_DPLL1_NINI, 0x58); 824 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 825 AR_CH0_BB_DPLL1_NFRAC, 0x0); 826 827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 828 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 829 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 830 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 831 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 832 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 833 834 /* program BB PLL phase_shift to 0x6 */ 835 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 836 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 837 838 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 839 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 840 udelay(1000); 841 } else if (AR_SREV_9330(ah)) { 842 u32 ddr_dpll2, pll_control2, kd; 843 844 if (ah->is_clk_25mhz) { 845 ddr_dpll2 = 0x18e82f01; 846 pll_control2 = 0xe04a3d; 847 kd = 0x1d; 848 } else { 849 ddr_dpll2 = 0x19e82f01; 850 pll_control2 = 0x886666; 851 kd = 0x3d; 852 } 853 854 /* program DDR PLL ki and kd value */ 855 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 856 857 /* program DDR PLL phase_shift */ 858 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 859 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 860 861 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 862 udelay(1000); 863 864 /* program refdiv, nint, frac to RTC register */ 865 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 866 867 /* program BB PLL kd and ki value */ 868 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 869 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 870 871 /* program BB PLL phase_shift */ 872 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 873 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 874 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 875 u32 regval, pll2_divint, pll2_divfrac, refdiv; 876 877 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 878 udelay(1000); 879 880 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 881 udelay(100); 882 883 if (ah->is_clk_25mhz) { 884 pll2_divint = 0x54; 885 pll2_divfrac = 0x1eb85; 886 refdiv = 3; 887 } else { 888 if (AR_SREV_9340(ah)) { 889 pll2_divint = 88; 890 pll2_divfrac = 0; 891 refdiv = 5; 892 } else { 893 pll2_divint = 0x11; 894 pll2_divfrac = 0x26666; 895 refdiv = 1; 896 } 897 } 898 899 regval = REG_READ(ah, AR_PHY_PLL_MODE); 900 regval |= (0x1 << 16); 901 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 902 udelay(100); 903 904 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 905 (pll2_divint << 18) | pll2_divfrac); 906 udelay(100); 907 908 regval = REG_READ(ah, AR_PHY_PLL_MODE); 909 if (AR_SREV_9340(ah)) 910 regval = (regval & 0x80071fff) | (0x1 << 30) | 911 (0x1 << 13) | (0x4 << 26) | (0x18 << 19); 912 else 913 regval = (regval & 0x80071fff) | (0x3 << 30) | 914 (0x1 << 13) | (0x4 << 26) | (0x60 << 19); 915 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 916 REG_WRITE(ah, AR_PHY_PLL_MODE, 917 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 918 udelay(1000); 919 } 920 921 pll = ath9k_hw_compute_pll_control(ah, chan); 922 if (AR_SREV_9565(ah)) 923 pll |= 0x40000; 924 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 925 926 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 927 AR_SREV_9550(ah)) 928 udelay(1000); 929 930 /* Switch the core clock for ar9271 to 117Mhz */ 931 if (AR_SREV_9271(ah)) { 932 udelay(500); 933 REG_WRITE(ah, 0x50040, 0x304); 934 } 935 936 udelay(RTC_PLL_SETTLE_DELAY); 937 938 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 939 940 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 941 if (ah->is_clk_25mhz) { 942 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 943 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 944 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 945 } else { 946 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 947 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 948 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 949 } 950 udelay(100); 951 } 952 } 953 954 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 955 enum nl80211_iftype opmode) 956 { 957 u32 sync_default = AR_INTR_SYNC_DEFAULT; 958 u32 imr_reg = AR_IMR_TXERR | 959 AR_IMR_TXURN | 960 AR_IMR_RXERR | 961 AR_IMR_RXORN | 962 AR_IMR_BCNMISC; 963 964 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) 965 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 966 967 if (AR_SREV_9300_20_OR_LATER(ah)) { 968 imr_reg |= AR_IMR_RXOK_HP; 969 if (ah->config.rx_intr_mitigation) 970 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 971 else 972 imr_reg |= AR_IMR_RXOK_LP; 973 974 } else { 975 if (ah->config.rx_intr_mitigation) 976 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 977 else 978 imr_reg |= AR_IMR_RXOK; 979 } 980 981 if (ah->config.tx_intr_mitigation) 982 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 983 else 984 imr_reg |= AR_IMR_TXOK; 985 986 ENABLE_REGWRITE_BUFFER(ah); 987 988 REG_WRITE(ah, AR_IMR, imr_reg); 989 ah->imrs2_reg |= AR_IMR_S2_GTT; 990 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 991 992 if (!AR_SREV_9100(ah)) { 993 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 994 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 995 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 996 } 997 998 REGWRITE_BUFFER_FLUSH(ah); 999 1000 if (AR_SREV_9300_20_OR_LATER(ah)) { 1001 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 1002 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 1003 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 1004 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 1005 } 1006 } 1007 1008 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 1009 { 1010 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 1011 val = min(val, (u32) 0xFFFF); 1012 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 1013 } 1014 1015 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1016 { 1017 u32 val = ath9k_hw_mac_to_clks(ah, us); 1018 val = min(val, (u32) 0xFFFF); 1019 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1020 } 1021 1022 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1023 { 1024 u32 val = ath9k_hw_mac_to_clks(ah, us); 1025 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1026 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1027 } 1028 1029 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1030 { 1031 u32 val = ath9k_hw_mac_to_clks(ah, us); 1032 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1033 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1034 } 1035 1036 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1037 { 1038 if (tu > 0xFFFF) { 1039 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1040 tu); 1041 ah->globaltxtimeout = (u32) -1; 1042 return false; 1043 } else { 1044 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1045 ah->globaltxtimeout = tu; 1046 return true; 1047 } 1048 } 1049 1050 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1051 { 1052 struct ath_common *common = ath9k_hw_common(ah); 1053 struct ieee80211_conf *conf = &common->hw->conf; 1054 const struct ath9k_channel *chan = ah->curchan; 1055 int acktimeout, ctstimeout, ack_offset = 0; 1056 int slottime; 1057 int sifstime; 1058 int rx_lat = 0, tx_lat = 0, eifs = 0; 1059 u32 reg; 1060 1061 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1062 ah->misc_mode); 1063 1064 if (!chan) 1065 return; 1066 1067 if (ah->misc_mode != 0) 1068 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1069 1070 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1071 rx_lat = 41; 1072 else 1073 rx_lat = 37; 1074 tx_lat = 54; 1075 1076 if (IS_CHAN_5GHZ(chan)) 1077 sifstime = 16; 1078 else 1079 sifstime = 10; 1080 1081 if (IS_CHAN_HALF_RATE(chan)) { 1082 eifs = 175; 1083 rx_lat *= 2; 1084 tx_lat *= 2; 1085 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1086 tx_lat += 11; 1087 1088 sifstime *= 2; 1089 ack_offset = 16; 1090 slottime = 13; 1091 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1092 eifs = 340; 1093 rx_lat = (rx_lat * 4) - 1; 1094 tx_lat *= 4; 1095 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1096 tx_lat += 22; 1097 1098 sifstime *= 4; 1099 ack_offset = 32; 1100 slottime = 21; 1101 } else { 1102 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1103 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1104 reg = AR_USEC_ASYNC_FIFO; 1105 } else { 1106 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1107 common->clockrate; 1108 reg = REG_READ(ah, AR_USEC); 1109 } 1110 rx_lat = MS(reg, AR_USEC_RX_LAT); 1111 tx_lat = MS(reg, AR_USEC_TX_LAT); 1112 1113 slottime = ah->slottime; 1114 } 1115 1116 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1117 acktimeout = slottime + sifstime + 3 * ah->coverage_class + ack_offset; 1118 ctstimeout = acktimeout; 1119 1120 /* 1121 * Workaround for early ACK timeouts, add an offset to match the 1122 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1123 * This was initially only meant to work around an issue with delayed 1124 * BA frames in some implementations, but it has been found to fix ACK 1125 * timeout issues in other cases as well. 1126 */ 1127 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ && 1128 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1129 acktimeout += 64 - sifstime - ah->slottime; 1130 ctstimeout += 48 - sifstime - ah->slottime; 1131 } 1132 1133 1134 ath9k_hw_set_sifs_time(ah, sifstime); 1135 ath9k_hw_setslottime(ah, slottime); 1136 ath9k_hw_set_ack_timeout(ah, acktimeout); 1137 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1138 if (ah->globaltxtimeout != (u32) -1) 1139 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1140 1141 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1142 REG_RMW(ah, AR_USEC, 1143 (common->clockrate - 1) | 1144 SM(rx_lat, AR_USEC_RX_LAT) | 1145 SM(tx_lat, AR_USEC_TX_LAT), 1146 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1147 1148 } 1149 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1150 1151 void ath9k_hw_deinit(struct ath_hw *ah) 1152 { 1153 struct ath_common *common = ath9k_hw_common(ah); 1154 1155 if (common->state < ATH_HW_INITIALIZED) 1156 goto free_hw; 1157 1158 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1159 1160 free_hw: 1161 ath9k_hw_rf_free_ext_banks(ah); 1162 } 1163 EXPORT_SYMBOL(ath9k_hw_deinit); 1164 1165 /*******/ 1166 /* INI */ 1167 /*******/ 1168 1169 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1170 { 1171 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1172 1173 if (IS_CHAN_B(chan)) 1174 ctl |= CTL_11B; 1175 else if (IS_CHAN_G(chan)) 1176 ctl |= CTL_11G; 1177 else 1178 ctl |= CTL_11A; 1179 1180 return ctl; 1181 } 1182 1183 /****************************************/ 1184 /* Reset and Channel Switching Routines */ 1185 /****************************************/ 1186 1187 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1188 { 1189 struct ath_common *common = ath9k_hw_common(ah); 1190 1191 ENABLE_REGWRITE_BUFFER(ah); 1192 1193 /* 1194 * set AHB_MODE not to do cacheline prefetches 1195 */ 1196 if (!AR_SREV_9300_20_OR_LATER(ah)) 1197 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1198 1199 /* 1200 * let mac dma reads be in 128 byte chunks 1201 */ 1202 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1203 1204 REGWRITE_BUFFER_FLUSH(ah); 1205 1206 /* 1207 * Restore TX Trigger Level to its pre-reset value. 1208 * The initial value depends on whether aggregation is enabled, and is 1209 * adjusted whenever underruns are detected. 1210 */ 1211 if (!AR_SREV_9300_20_OR_LATER(ah)) 1212 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1213 1214 ENABLE_REGWRITE_BUFFER(ah); 1215 1216 /* 1217 * let mac dma writes be in 128 byte chunks 1218 */ 1219 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1220 1221 /* 1222 * Setup receive FIFO threshold to hold off TX activities 1223 */ 1224 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1225 1226 if (AR_SREV_9300_20_OR_LATER(ah)) { 1227 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1228 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1229 1230 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1231 ah->caps.rx_status_len); 1232 } 1233 1234 /* 1235 * reduce the number of usable entries in PCU TXBUF to avoid 1236 * wrap around issues. 1237 */ 1238 if (AR_SREV_9285(ah)) { 1239 /* For AR9285 the number of Fifos are reduced to half. 1240 * So set the usable tx buf size also to half to 1241 * avoid data/delimiter underruns 1242 */ 1243 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1244 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1245 } else if (!AR_SREV_9271(ah)) { 1246 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1247 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1248 } 1249 1250 REGWRITE_BUFFER_FLUSH(ah); 1251 1252 if (AR_SREV_9300_20_OR_LATER(ah)) 1253 ath9k_hw_reset_txstatus_ring(ah); 1254 } 1255 1256 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1257 { 1258 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1259 u32 set = AR_STA_ID1_KSRCH_MODE; 1260 1261 switch (opmode) { 1262 case NL80211_IFTYPE_ADHOC: 1263 case NL80211_IFTYPE_MESH_POINT: 1264 set |= AR_STA_ID1_ADHOC; 1265 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1266 break; 1267 case NL80211_IFTYPE_AP: 1268 set |= AR_STA_ID1_STA_AP; 1269 /* fall through */ 1270 case NL80211_IFTYPE_STATION: 1271 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1272 break; 1273 default: 1274 if (!ah->is_monitoring) 1275 set = 0; 1276 break; 1277 } 1278 REG_RMW(ah, AR_STA_ID1, set, mask); 1279 } 1280 1281 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1282 u32 *coef_mantissa, u32 *coef_exponent) 1283 { 1284 u32 coef_exp, coef_man; 1285 1286 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1287 if ((coef_scaled >> coef_exp) & 0x1) 1288 break; 1289 1290 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1291 1292 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1293 1294 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1295 *coef_exponent = coef_exp - 16; 1296 } 1297 1298 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1299 { 1300 u32 rst_flags; 1301 u32 tmpReg; 1302 1303 if (AR_SREV_9100(ah)) { 1304 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1305 AR_RTC_DERIVED_CLK_PERIOD, 1); 1306 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1307 } 1308 1309 ENABLE_REGWRITE_BUFFER(ah); 1310 1311 if (AR_SREV_9300_20_OR_LATER(ah)) { 1312 REG_WRITE(ah, AR_WA, ah->WARegVal); 1313 udelay(10); 1314 } 1315 1316 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1317 AR_RTC_FORCE_WAKE_ON_INT); 1318 1319 if (AR_SREV_9100(ah)) { 1320 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1321 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1322 } else { 1323 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1324 if (tmpReg & 1325 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1326 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1327 u32 val; 1328 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1329 1330 val = AR_RC_HOSTIF; 1331 if (!AR_SREV_9300_20_OR_LATER(ah)) 1332 val |= AR_RC_AHB; 1333 REG_WRITE(ah, AR_RC, val); 1334 1335 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1336 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1337 1338 rst_flags = AR_RTC_RC_MAC_WARM; 1339 if (type == ATH9K_RESET_COLD) 1340 rst_flags |= AR_RTC_RC_MAC_COLD; 1341 } 1342 1343 if (AR_SREV_9330(ah)) { 1344 int npend = 0; 1345 int i; 1346 1347 /* AR9330 WAR: 1348 * call external reset function to reset WMAC if: 1349 * - doing a cold reset 1350 * - we have pending frames in the TX queues 1351 */ 1352 1353 for (i = 0; i < AR_NUM_QCU; i++) { 1354 npend = ath9k_hw_numtxpending(ah, i); 1355 if (npend) 1356 break; 1357 } 1358 1359 if (ah->external_reset && 1360 (npend || type == ATH9K_RESET_COLD)) { 1361 int reset_err = 0; 1362 1363 ath_dbg(ath9k_hw_common(ah), RESET, 1364 "reset MAC via external reset\n"); 1365 1366 reset_err = ah->external_reset(); 1367 if (reset_err) { 1368 ath_err(ath9k_hw_common(ah), 1369 "External reset failed, err=%d\n", 1370 reset_err); 1371 return false; 1372 } 1373 1374 REG_WRITE(ah, AR_RTC_RESET, 1); 1375 } 1376 } 1377 1378 if (ath9k_hw_mci_is_enabled(ah)) 1379 ar9003_mci_check_gpm_offset(ah); 1380 1381 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1382 1383 REGWRITE_BUFFER_FLUSH(ah); 1384 1385 udelay(50); 1386 1387 REG_WRITE(ah, AR_RTC_RC, 0); 1388 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1389 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1390 return false; 1391 } 1392 1393 if (!AR_SREV_9100(ah)) 1394 REG_WRITE(ah, AR_RC, 0); 1395 1396 if (AR_SREV_9100(ah)) 1397 udelay(50); 1398 1399 return true; 1400 } 1401 1402 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1403 { 1404 ENABLE_REGWRITE_BUFFER(ah); 1405 1406 if (AR_SREV_9300_20_OR_LATER(ah)) { 1407 REG_WRITE(ah, AR_WA, ah->WARegVal); 1408 udelay(10); 1409 } 1410 1411 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1412 AR_RTC_FORCE_WAKE_ON_INT); 1413 1414 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1415 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1416 1417 REG_WRITE(ah, AR_RTC_RESET, 0); 1418 1419 REGWRITE_BUFFER_FLUSH(ah); 1420 1421 if (!AR_SREV_9300_20_OR_LATER(ah)) 1422 udelay(2); 1423 1424 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1425 REG_WRITE(ah, AR_RC, 0); 1426 1427 REG_WRITE(ah, AR_RTC_RESET, 1); 1428 1429 if (!ath9k_hw_wait(ah, 1430 AR_RTC_STATUS, 1431 AR_RTC_STATUS_M, 1432 AR_RTC_STATUS_ON, 1433 AH_WAIT_TIMEOUT)) { 1434 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1435 return false; 1436 } 1437 1438 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1439 } 1440 1441 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1442 { 1443 bool ret = false; 1444 1445 if (AR_SREV_9300_20_OR_LATER(ah)) { 1446 REG_WRITE(ah, AR_WA, ah->WARegVal); 1447 udelay(10); 1448 } 1449 1450 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1451 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1452 1453 if (!ah->reset_power_on) 1454 type = ATH9K_RESET_POWER_ON; 1455 1456 switch (type) { 1457 case ATH9K_RESET_POWER_ON: 1458 ret = ath9k_hw_set_reset_power_on(ah); 1459 if (ret) 1460 ah->reset_power_on = true; 1461 break; 1462 case ATH9K_RESET_WARM: 1463 case ATH9K_RESET_COLD: 1464 ret = ath9k_hw_set_reset(ah, type); 1465 break; 1466 default: 1467 break; 1468 } 1469 1470 return ret; 1471 } 1472 1473 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1474 struct ath9k_channel *chan) 1475 { 1476 int reset_type = ATH9K_RESET_WARM; 1477 1478 if (AR_SREV_9280(ah)) { 1479 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1480 reset_type = ATH9K_RESET_POWER_ON; 1481 else 1482 reset_type = ATH9K_RESET_COLD; 1483 } 1484 1485 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1486 return false; 1487 1488 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1489 return false; 1490 1491 ah->chip_fullsleep = false; 1492 1493 if (AR_SREV_9330(ah)) 1494 ar9003_hw_internal_regulator_apply(ah); 1495 ath9k_hw_init_pll(ah, chan); 1496 ath9k_hw_set_rfmode(ah, chan); 1497 1498 return true; 1499 } 1500 1501 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1502 struct ath9k_channel *chan) 1503 { 1504 struct ath_common *common = ath9k_hw_common(ah); 1505 u32 qnum; 1506 int r; 1507 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1508 bool band_switch, mode_diff; 1509 u8 ini_reloaded; 1510 1511 band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != 1512 (ah->curchan->channelFlags & (CHANNEL_2GHZ | 1513 CHANNEL_5GHZ)); 1514 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1515 1516 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1517 if (ath9k_hw_numtxpending(ah, qnum)) { 1518 ath_dbg(common, QUEUE, 1519 "Transmit frames pending on queue %d\n", qnum); 1520 return false; 1521 } 1522 } 1523 1524 if (!ath9k_hw_rfbus_req(ah)) { 1525 ath_err(common, "Could not kill baseband RX\n"); 1526 return false; 1527 } 1528 1529 if (edma && (band_switch || mode_diff)) { 1530 ath9k_hw_mark_phy_inactive(ah); 1531 udelay(5); 1532 1533 ath9k_hw_init_pll(ah, NULL); 1534 1535 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1536 ath_err(common, "Failed to do fast channel change\n"); 1537 return false; 1538 } 1539 } 1540 1541 ath9k_hw_set_channel_regs(ah, chan); 1542 1543 r = ath9k_hw_rf_set_freq(ah, chan); 1544 if (r) { 1545 ath_err(common, "Failed to set channel\n"); 1546 return false; 1547 } 1548 ath9k_hw_set_clockrate(ah); 1549 ath9k_hw_apply_txpower(ah, chan, false); 1550 ath9k_hw_rfbus_done(ah); 1551 1552 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1553 ath9k_hw_set_delta_slope(ah, chan); 1554 1555 ath9k_hw_spur_mitigate_freq(ah, chan); 1556 1557 if (edma && (band_switch || mode_diff)) { 1558 ah->ah_flags |= AH_FASTCC; 1559 if (band_switch || ini_reloaded) 1560 ah->eep_ops->set_board_values(ah, chan); 1561 1562 ath9k_hw_init_bb(ah, chan); 1563 1564 if (band_switch || ini_reloaded) 1565 ath9k_hw_init_cal(ah, chan); 1566 ah->ah_flags &= ~AH_FASTCC; 1567 } 1568 1569 return true; 1570 } 1571 1572 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1573 { 1574 u32 gpio_mask = ah->gpio_mask; 1575 int i; 1576 1577 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1578 if (!(gpio_mask & 1)) 1579 continue; 1580 1581 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1582 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1583 } 1584 } 1585 1586 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1587 int *hang_state, int *hang_pos) 1588 { 1589 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1590 u32 chain_state, dcs_pos, i; 1591 1592 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1593 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1594 for (i = 0; i < 3; i++) { 1595 if (chain_state == dcu_chain_state[i]) { 1596 *hang_state = chain_state; 1597 *hang_pos = dcs_pos; 1598 return true; 1599 } 1600 } 1601 } 1602 return false; 1603 } 1604 1605 #define DCU_COMPLETE_STATE 1 1606 #define DCU_COMPLETE_STATE_MASK 0x3 1607 #define NUM_STATUS_READS 50 1608 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1609 { 1610 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1611 u32 i, hang_pos, hang_state, num_state = 6; 1612 1613 comp_state = REG_READ(ah, AR_DMADBG_6); 1614 1615 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1616 ath_dbg(ath9k_hw_common(ah), RESET, 1617 "MAC Hang signature not found at DCU complete\n"); 1618 return false; 1619 } 1620 1621 chain_state = REG_READ(ah, dcs_reg); 1622 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1623 goto hang_check_iter; 1624 1625 dcs_reg = AR_DMADBG_5; 1626 num_state = 4; 1627 chain_state = REG_READ(ah, dcs_reg); 1628 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1629 goto hang_check_iter; 1630 1631 ath_dbg(ath9k_hw_common(ah), RESET, 1632 "MAC Hang signature 1 not found\n"); 1633 return false; 1634 1635 hang_check_iter: 1636 ath_dbg(ath9k_hw_common(ah), RESET, 1637 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1638 chain_state, comp_state, hang_state, hang_pos); 1639 1640 for (i = 0; i < NUM_STATUS_READS; i++) { 1641 chain_state = REG_READ(ah, dcs_reg); 1642 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1643 comp_state = REG_READ(ah, AR_DMADBG_6); 1644 1645 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1646 DCU_COMPLETE_STATE) || 1647 (chain_state != hang_state)) 1648 return false; 1649 } 1650 1651 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1652 1653 return true; 1654 } 1655 1656 bool ath9k_hw_check_alive(struct ath_hw *ah) 1657 { 1658 int count = 50; 1659 u32 reg; 1660 1661 if (AR_SREV_9300(ah)) 1662 return !ath9k_hw_detect_mac_hang(ah); 1663 1664 if (AR_SREV_9285_12_OR_LATER(ah)) 1665 return true; 1666 1667 do { 1668 reg = REG_READ(ah, AR_OBS_BUS_1); 1669 1670 if ((reg & 0x7E7FFFEF) == 0x00702400) 1671 continue; 1672 1673 switch (reg & 0x7E000B00) { 1674 case 0x1E000000: 1675 case 0x52000B00: 1676 case 0x18000B00: 1677 continue; 1678 default: 1679 return true; 1680 } 1681 } while (count-- > 0); 1682 1683 return false; 1684 } 1685 EXPORT_SYMBOL(ath9k_hw_check_alive); 1686 1687 /* 1688 * Fast channel change: 1689 * (Change synthesizer based on channel freq without resetting chip) 1690 * 1691 * Don't do FCC when 1692 * - Flag is not set 1693 * - Chip is just coming out of full sleep 1694 * - Channel to be set is same as current channel 1695 * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel) 1696 */ 1697 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1698 { 1699 struct ath_common *common = ath9k_hw_common(ah); 1700 int ret; 1701 1702 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1703 goto fail; 1704 1705 if (ah->chip_fullsleep) 1706 goto fail; 1707 1708 if (!ah->curchan) 1709 goto fail; 1710 1711 if (chan->channel == ah->curchan->channel) 1712 goto fail; 1713 1714 if ((ah->curchan->channelFlags | chan->channelFlags) & 1715 (CHANNEL_HALF | CHANNEL_QUARTER)) 1716 goto fail; 1717 1718 if ((chan->channelFlags & CHANNEL_ALL) != 1719 (ah->curchan->channelFlags & CHANNEL_ALL)) 1720 goto fail; 1721 1722 if (!ath9k_hw_check_alive(ah)) 1723 goto fail; 1724 1725 /* 1726 * For AR9462, make sure that calibration data for 1727 * re-using are present. 1728 */ 1729 if (AR_SREV_9462(ah) && (ah->caldata && 1730 (!ah->caldata->done_txiqcal_once || 1731 !ah->caldata->done_txclcal_once || 1732 !ah->caldata->rtt_done))) 1733 goto fail; 1734 1735 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1736 ah->curchan->channel, chan->channel); 1737 1738 ret = ath9k_hw_channel_change(ah, chan); 1739 if (!ret) 1740 goto fail; 1741 1742 if (ath9k_hw_mci_is_enabled(ah)) 1743 ar9003_mci_2g5g_switch(ah, false); 1744 1745 ath9k_hw_loadnf(ah, ah->curchan); 1746 ath9k_hw_start_nfcal(ah, true); 1747 1748 if (AR_SREV_9271(ah)) 1749 ar9002_hw_load_ani_reg(ah, chan); 1750 1751 return 0; 1752 fail: 1753 return -EINVAL; 1754 } 1755 1756 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1757 struct ath9k_hw_cal_data *caldata, bool fastcc) 1758 { 1759 struct ath_common *common = ath9k_hw_common(ah); 1760 u32 saveLedState; 1761 u32 saveDefAntenna; 1762 u32 macStaId1; 1763 u64 tsf = 0; 1764 int i, r; 1765 bool start_mci_reset = false; 1766 bool save_fullsleep = ah->chip_fullsleep; 1767 1768 if (ath9k_hw_mci_is_enabled(ah)) { 1769 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1770 if (start_mci_reset) 1771 return 0; 1772 } 1773 1774 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1775 return -EIO; 1776 1777 if (ah->curchan && !ah->chip_fullsleep) 1778 ath9k_hw_getnf(ah, ah->curchan); 1779 1780 ah->caldata = caldata; 1781 if (caldata && 1782 (chan->channel != caldata->channel || 1783 (chan->channelFlags & ~CHANNEL_CW_INT) != 1784 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1785 /* Operating channel changed, reset channel calibration data */ 1786 memset(caldata, 0, sizeof(*caldata)); 1787 ath9k_init_nfcal_hist_buffer(ah, chan); 1788 } else if (caldata) { 1789 caldata->paprd_packet_sent = false; 1790 } 1791 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1792 1793 if (fastcc) { 1794 r = ath9k_hw_do_fastcc(ah, chan); 1795 if (!r) 1796 return r; 1797 } 1798 1799 if (ath9k_hw_mci_is_enabled(ah)) 1800 ar9003_mci_stop_bt(ah, save_fullsleep); 1801 1802 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1803 if (saveDefAntenna == 0) 1804 saveDefAntenna = 1; 1805 1806 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1807 1808 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1809 if (AR_SREV_9100(ah) || 1810 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1811 tsf = ath9k_hw_gettsf64(ah); 1812 1813 saveLedState = REG_READ(ah, AR_CFG_LED) & 1814 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1815 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1816 1817 ath9k_hw_mark_phy_inactive(ah); 1818 1819 ah->paprd_table_write_done = false; 1820 1821 /* Only required on the first reset */ 1822 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1823 REG_WRITE(ah, 1824 AR9271_RESET_POWER_DOWN_CONTROL, 1825 AR9271_RADIO_RF_RST); 1826 udelay(50); 1827 } 1828 1829 if (!ath9k_hw_chip_reset(ah, chan)) { 1830 ath_err(common, "Chip reset failed\n"); 1831 return -EINVAL; 1832 } 1833 1834 /* Only required on the first reset */ 1835 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1836 ah->htc_reset_init = false; 1837 REG_WRITE(ah, 1838 AR9271_RESET_POWER_DOWN_CONTROL, 1839 AR9271_GATE_MAC_CTL); 1840 udelay(50); 1841 } 1842 1843 /* Restore TSF */ 1844 if (tsf) 1845 ath9k_hw_settsf64(ah, tsf); 1846 1847 if (AR_SREV_9280_20_OR_LATER(ah)) 1848 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1849 1850 if (!AR_SREV_9300_20_OR_LATER(ah)) 1851 ar9002_hw_enable_async_fifo(ah); 1852 1853 r = ath9k_hw_process_ini(ah, chan); 1854 if (r) 1855 return r; 1856 1857 if (ath9k_hw_mci_is_enabled(ah)) 1858 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1859 1860 /* 1861 * Some AR91xx SoC devices frequently fail to accept TSF writes 1862 * right after the chip reset. When that happens, write a new 1863 * value after the initvals have been applied, with an offset 1864 * based on measured time difference 1865 */ 1866 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1867 tsf += 1500; 1868 ath9k_hw_settsf64(ah, tsf); 1869 } 1870 1871 /* Setup MFP options for CCMP */ 1872 if (AR_SREV_9280_20_OR_LATER(ah)) { 1873 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1874 * frames when constructing CCMP AAD. */ 1875 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1876 0xc7ff); 1877 ah->sw_mgmt_crypto = false; 1878 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1879 /* Disable hardware crypto for management frames */ 1880 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1881 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1882 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1883 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1884 ah->sw_mgmt_crypto = true; 1885 } else 1886 ah->sw_mgmt_crypto = true; 1887 1888 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1889 ath9k_hw_set_delta_slope(ah, chan); 1890 1891 ath9k_hw_spur_mitigate_freq(ah, chan); 1892 ah->eep_ops->set_board_values(ah, chan); 1893 1894 ENABLE_REGWRITE_BUFFER(ah); 1895 1896 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1897 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1898 | macStaId1 1899 | AR_STA_ID1_RTS_USE_DEF 1900 | (ah->config. 1901 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1902 | ah->sta_id1_defaults); 1903 ath_hw_setbssidmask(common); 1904 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1905 ath9k_hw_write_associd(ah); 1906 REG_WRITE(ah, AR_ISR, ~0); 1907 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1908 1909 REGWRITE_BUFFER_FLUSH(ah); 1910 1911 ath9k_hw_set_operating_mode(ah, ah->opmode); 1912 1913 r = ath9k_hw_rf_set_freq(ah, chan); 1914 if (r) 1915 return r; 1916 1917 ath9k_hw_set_clockrate(ah); 1918 1919 ENABLE_REGWRITE_BUFFER(ah); 1920 1921 for (i = 0; i < AR_NUM_DCU; i++) 1922 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1923 1924 REGWRITE_BUFFER_FLUSH(ah); 1925 1926 ah->intr_txqs = 0; 1927 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1928 ath9k_hw_resettxqueue(ah, i); 1929 1930 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1931 ath9k_hw_ani_cache_ini_regs(ah); 1932 ath9k_hw_init_qos(ah); 1933 1934 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1935 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1936 1937 ath9k_hw_init_global_settings(ah); 1938 1939 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1940 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1941 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1942 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1943 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1944 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1945 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 1946 } 1947 1948 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1949 1950 ath9k_hw_set_dma(ah); 1951 1952 if (!ath9k_hw_mci_is_enabled(ah)) 1953 REG_WRITE(ah, AR_OBS, 8); 1954 1955 if (ah->config.rx_intr_mitigation) { 1956 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1957 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1958 } 1959 1960 if (ah->config.tx_intr_mitigation) { 1961 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1962 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1963 } 1964 1965 ath9k_hw_init_bb(ah, chan); 1966 1967 if (caldata) { 1968 caldata->done_txiqcal_once = false; 1969 caldata->done_txclcal_once = false; 1970 } 1971 if (!ath9k_hw_init_cal(ah, chan)) 1972 return -EIO; 1973 1974 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 1975 return -EIO; 1976 1977 ENABLE_REGWRITE_BUFFER(ah); 1978 1979 ath9k_hw_restore_chainmask(ah); 1980 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1981 1982 REGWRITE_BUFFER_FLUSH(ah); 1983 1984 /* 1985 * For big endian systems turn on swapping for descriptors 1986 */ 1987 if (AR_SREV_9100(ah)) { 1988 u32 mask; 1989 mask = REG_READ(ah, AR_CFG); 1990 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1991 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1992 mask); 1993 } else { 1994 mask = 1995 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1996 REG_WRITE(ah, AR_CFG, mask); 1997 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1998 REG_READ(ah, AR_CFG)); 1999 } 2000 } else { 2001 if (common->bus_ops->ath_bus_type == ATH_USB) { 2002 /* Configure AR9271 target WLAN */ 2003 if (AR_SREV_9271(ah)) 2004 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 2005 else 2006 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2007 } 2008 #ifdef __BIG_ENDIAN 2009 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 2010 AR_SREV_9550(ah)) 2011 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 2012 else 2013 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2014 #endif 2015 } 2016 2017 if (ath9k_hw_btcoex_is_enabled(ah)) 2018 ath9k_hw_btcoex_enable(ah); 2019 2020 if (ath9k_hw_mci_is_enabled(ah)) 2021 ar9003_mci_check_bt(ah); 2022 2023 ath9k_hw_loadnf(ah, chan); 2024 ath9k_hw_start_nfcal(ah, true); 2025 2026 if (AR_SREV_9300_20_OR_LATER(ah)) { 2027 ar9003_hw_bb_watchdog_config(ah); 2028 2029 ar9003_hw_disable_phy_restart(ah); 2030 } 2031 2032 ath9k_hw_apply_gpio_override(ah); 2033 2034 if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv) 2035 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2036 2037 return 0; 2038 } 2039 EXPORT_SYMBOL(ath9k_hw_reset); 2040 2041 /******************************/ 2042 /* Power Management (Chipset) */ 2043 /******************************/ 2044 2045 /* 2046 * Notify Power Mgt is disabled in self-generated frames. 2047 * If requested, force chip to sleep. 2048 */ 2049 static void ath9k_set_power_sleep(struct ath_hw *ah) 2050 { 2051 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2052 2053 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2054 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2055 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2056 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2057 /* xxx Required for WLAN only case ? */ 2058 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2059 udelay(100); 2060 } 2061 2062 /* 2063 * Clear the RTC force wake bit to allow the 2064 * mac to go to sleep. 2065 */ 2066 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2067 2068 if (ath9k_hw_mci_is_enabled(ah)) 2069 udelay(100); 2070 2071 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2072 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2073 2074 /* Shutdown chip. Active low */ 2075 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2076 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2077 udelay(2); 2078 } 2079 2080 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2081 if (AR_SREV_9300_20_OR_LATER(ah)) 2082 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2083 } 2084 2085 /* 2086 * Notify Power Management is enabled in self-generating 2087 * frames. If request, set power mode of chip to 2088 * auto/normal. Duration in units of 128us (1/8 TU). 2089 */ 2090 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2091 { 2092 struct ath9k_hw_capabilities *pCap = &ah->caps; 2093 2094 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2095 2096 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2097 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2098 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2099 AR_RTC_FORCE_WAKE_ON_INT); 2100 } else { 2101 2102 /* When chip goes into network sleep, it could be waken 2103 * up by MCI_INT interrupt caused by BT's HW messages 2104 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2105 * rate (~100us). This will cause chip to leave and 2106 * re-enter network sleep mode frequently, which in 2107 * consequence will have WLAN MCI HW to generate lots of 2108 * SYS_WAKING and SYS_SLEEPING messages which will make 2109 * BT CPU to busy to process. 2110 */ 2111 if (ath9k_hw_mci_is_enabled(ah)) 2112 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2113 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2114 /* 2115 * Clear the RTC force wake bit to allow the 2116 * mac to go to sleep. 2117 */ 2118 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2119 2120 if (ath9k_hw_mci_is_enabled(ah)) 2121 udelay(30); 2122 } 2123 2124 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2125 if (AR_SREV_9300_20_OR_LATER(ah)) 2126 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2127 } 2128 2129 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2130 { 2131 u32 val; 2132 int i; 2133 2134 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2135 if (AR_SREV_9300_20_OR_LATER(ah)) { 2136 REG_WRITE(ah, AR_WA, ah->WARegVal); 2137 udelay(10); 2138 } 2139 2140 if ((REG_READ(ah, AR_RTC_STATUS) & 2141 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2142 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2143 return false; 2144 } 2145 if (!AR_SREV_9300_20_OR_LATER(ah)) 2146 ath9k_hw_init_pll(ah, NULL); 2147 } 2148 if (AR_SREV_9100(ah)) 2149 REG_SET_BIT(ah, AR_RTC_RESET, 2150 AR_RTC_RESET_EN); 2151 2152 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2153 AR_RTC_FORCE_WAKE_EN); 2154 udelay(50); 2155 2156 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2157 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2158 if (val == AR_RTC_STATUS_ON) 2159 break; 2160 udelay(50); 2161 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2162 AR_RTC_FORCE_WAKE_EN); 2163 } 2164 if (i == 0) { 2165 ath_err(ath9k_hw_common(ah), 2166 "Failed to wakeup in %uus\n", 2167 POWER_UP_TIME / 20); 2168 return false; 2169 } 2170 2171 if (ath9k_hw_mci_is_enabled(ah)) 2172 ar9003_mci_set_power_awake(ah); 2173 2174 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2175 2176 return true; 2177 } 2178 2179 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2180 { 2181 struct ath_common *common = ath9k_hw_common(ah); 2182 int status = true; 2183 static const char *modes[] = { 2184 "AWAKE", 2185 "FULL-SLEEP", 2186 "NETWORK SLEEP", 2187 "UNDEFINED" 2188 }; 2189 2190 if (ah->power_mode == mode) 2191 return status; 2192 2193 ath_dbg(common, RESET, "%s -> %s\n", 2194 modes[ah->power_mode], modes[mode]); 2195 2196 switch (mode) { 2197 case ATH9K_PM_AWAKE: 2198 status = ath9k_hw_set_power_awake(ah); 2199 break; 2200 case ATH9K_PM_FULL_SLEEP: 2201 if (ath9k_hw_mci_is_enabled(ah)) 2202 ar9003_mci_set_full_sleep(ah); 2203 2204 ath9k_set_power_sleep(ah); 2205 ah->chip_fullsleep = true; 2206 break; 2207 case ATH9K_PM_NETWORK_SLEEP: 2208 ath9k_set_power_network_sleep(ah); 2209 break; 2210 default: 2211 ath_err(common, "Unknown power mode %u\n", mode); 2212 return false; 2213 } 2214 ah->power_mode = mode; 2215 2216 /* 2217 * XXX: If this warning never comes up after a while then 2218 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2219 * ath9k_hw_setpower() return type void. 2220 */ 2221 2222 if (!(ah->ah_flags & AH_UNPLUGGED)) 2223 ATH_DBG_WARN_ON_ONCE(!status); 2224 2225 return status; 2226 } 2227 EXPORT_SYMBOL(ath9k_hw_setpower); 2228 2229 /*******************/ 2230 /* Beacon Handling */ 2231 /*******************/ 2232 2233 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2234 { 2235 int flags = 0; 2236 2237 ENABLE_REGWRITE_BUFFER(ah); 2238 2239 switch (ah->opmode) { 2240 case NL80211_IFTYPE_ADHOC: 2241 case NL80211_IFTYPE_MESH_POINT: 2242 REG_SET_BIT(ah, AR_TXCFG, 2243 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2244 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2245 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2246 flags |= AR_NDP_TIMER_EN; 2247 case NL80211_IFTYPE_AP: 2248 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2249 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2250 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2251 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2252 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2253 flags |= 2254 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2255 break; 2256 default: 2257 ath_dbg(ath9k_hw_common(ah), BEACON, 2258 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2259 return; 2260 break; 2261 } 2262 2263 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2264 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2265 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2266 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2267 2268 REGWRITE_BUFFER_FLUSH(ah); 2269 2270 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2271 } 2272 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2273 2274 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2275 const struct ath9k_beacon_state *bs) 2276 { 2277 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2278 struct ath9k_hw_capabilities *pCap = &ah->caps; 2279 struct ath_common *common = ath9k_hw_common(ah); 2280 2281 ENABLE_REGWRITE_BUFFER(ah); 2282 2283 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2284 2285 REG_WRITE(ah, AR_BEACON_PERIOD, 2286 TU_TO_USEC(bs->bs_intval)); 2287 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2288 TU_TO_USEC(bs->bs_intval)); 2289 2290 REGWRITE_BUFFER_FLUSH(ah); 2291 2292 REG_RMW_FIELD(ah, AR_RSSI_THR, 2293 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2294 2295 beaconintval = bs->bs_intval; 2296 2297 if (bs->bs_sleepduration > beaconintval) 2298 beaconintval = bs->bs_sleepduration; 2299 2300 dtimperiod = bs->bs_dtimperiod; 2301 if (bs->bs_sleepduration > dtimperiod) 2302 dtimperiod = bs->bs_sleepduration; 2303 2304 if (beaconintval == dtimperiod) 2305 nextTbtt = bs->bs_nextdtim; 2306 else 2307 nextTbtt = bs->bs_nexttbtt; 2308 2309 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2310 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2311 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2312 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2313 2314 ENABLE_REGWRITE_BUFFER(ah); 2315 2316 REG_WRITE(ah, AR_NEXT_DTIM, 2317 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2318 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2319 2320 REG_WRITE(ah, AR_SLEEP1, 2321 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2322 | AR_SLEEP1_ASSUME_DTIM); 2323 2324 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2325 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2326 else 2327 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2328 2329 REG_WRITE(ah, AR_SLEEP2, 2330 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2331 2332 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2333 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2334 2335 REGWRITE_BUFFER_FLUSH(ah); 2336 2337 REG_SET_BIT(ah, AR_TIMER_MODE, 2338 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2339 AR_DTIM_TIMER_EN); 2340 2341 /* TSF Out of Range Threshold */ 2342 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2343 } 2344 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2345 2346 /*******************/ 2347 /* HW Capabilities */ 2348 /*******************/ 2349 2350 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2351 { 2352 eeprom_chainmask &= chip_chainmask; 2353 if (eeprom_chainmask) 2354 return eeprom_chainmask; 2355 else 2356 return chip_chainmask; 2357 } 2358 2359 /** 2360 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2361 * @ah: the atheros hardware data structure 2362 * 2363 * We enable DFS support upstream on chipsets which have passed a series 2364 * of tests. The testing requirements are going to be documented. Desired 2365 * test requirements are documented at: 2366 * 2367 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2368 * 2369 * Once a new chipset gets properly tested an individual commit can be used 2370 * to document the testing for DFS for that chipset. 2371 */ 2372 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2373 { 2374 2375 switch (ah->hw_version.macVersion) { 2376 /* AR9580 will likely be our first target to get testing on */ 2377 case AR_SREV_VERSION_9580: 2378 default: 2379 return false; 2380 } 2381 } 2382 2383 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2384 { 2385 struct ath9k_hw_capabilities *pCap = &ah->caps; 2386 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2387 struct ath_common *common = ath9k_hw_common(ah); 2388 unsigned int chip_chainmask; 2389 2390 u16 eeval; 2391 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2392 2393 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2394 regulatory->current_rd = eeval; 2395 2396 if (ah->opmode != NL80211_IFTYPE_AP && 2397 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2398 if (regulatory->current_rd == 0x64 || 2399 regulatory->current_rd == 0x65) 2400 regulatory->current_rd += 5; 2401 else if (regulatory->current_rd == 0x41) 2402 regulatory->current_rd = 0x43; 2403 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2404 regulatory->current_rd); 2405 } 2406 2407 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2408 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2409 ath_err(common, 2410 "no band has been marked as supported in EEPROM\n"); 2411 return -EINVAL; 2412 } 2413 2414 if (eeval & AR5416_OPFLAGS_11A) 2415 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2416 2417 if (eeval & AR5416_OPFLAGS_11G) 2418 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2419 2420 if (AR_SREV_9485(ah) || 2421 AR_SREV_9285(ah) || 2422 AR_SREV_9330(ah) || 2423 AR_SREV_9565(ah)) 2424 chip_chainmask = 1; 2425 else if (AR_SREV_9462(ah)) 2426 chip_chainmask = 3; 2427 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2428 chip_chainmask = 7; 2429 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2430 chip_chainmask = 3; 2431 else 2432 chip_chainmask = 7; 2433 2434 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2435 /* 2436 * For AR9271 we will temporarilly uses the rx chainmax as read from 2437 * the EEPROM. 2438 */ 2439 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2440 !(eeval & AR5416_OPFLAGS_11A) && 2441 !(AR_SREV_9271(ah))) 2442 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2443 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2444 else if (AR_SREV_9100(ah)) 2445 pCap->rx_chainmask = 0x7; 2446 else 2447 /* Use rx_chainmask from EEPROM. */ 2448 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2449 2450 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2451 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2452 ah->txchainmask = pCap->tx_chainmask; 2453 ah->rxchainmask = pCap->rx_chainmask; 2454 2455 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2456 2457 /* enable key search for every frame in an aggregate */ 2458 if (AR_SREV_9300_20_OR_LATER(ah)) 2459 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2460 2461 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2462 2463 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2464 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2465 else 2466 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2467 2468 if (AR_SREV_9271(ah)) 2469 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2470 else if (AR_DEVID_7010(ah)) 2471 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2472 else if (AR_SREV_9300_20_OR_LATER(ah)) 2473 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2474 else if (AR_SREV_9287_11_OR_LATER(ah)) 2475 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2476 else if (AR_SREV_9285_12_OR_LATER(ah)) 2477 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2478 else if (AR_SREV_9280_20_OR_LATER(ah)) 2479 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2480 else 2481 pCap->num_gpio_pins = AR_NUM_GPIO; 2482 2483 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2484 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2485 else 2486 pCap->rts_aggr_limit = (8 * 1024); 2487 2488 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2489 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2490 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2491 ah->rfkill_gpio = 2492 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2493 ah->rfkill_polarity = 2494 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2495 2496 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2497 } 2498 #endif 2499 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2500 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2501 else 2502 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2503 2504 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2505 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2506 else 2507 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2508 2509 if (AR_SREV_9300_20_OR_LATER(ah)) { 2510 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2511 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2512 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2513 2514 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2515 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2516 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2517 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2518 pCap->txs_len = sizeof(struct ar9003_txs); 2519 } else { 2520 pCap->tx_desc_len = sizeof(struct ath_desc); 2521 if (AR_SREV_9280_20(ah)) 2522 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2523 } 2524 2525 if (AR_SREV_9300_20_OR_LATER(ah)) 2526 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2527 2528 if (AR_SREV_9300_20_OR_LATER(ah)) 2529 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2530 2531 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2532 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2533 2534 if (AR_SREV_9285(ah)) 2535 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2536 ant_div_ctl1 = 2537 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2538 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2539 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2540 } 2541 if (AR_SREV_9300_20_OR_LATER(ah)) { 2542 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2543 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2544 } 2545 2546 2547 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2548 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2549 /* 2550 * enable the diversity-combining algorithm only when 2551 * both enable_lna_div and enable_fast_div are set 2552 * Table for Diversity 2553 * ant_div_alt_lnaconf bit 0-1 2554 * ant_div_main_lnaconf bit 2-3 2555 * ant_div_alt_gaintb bit 4 2556 * ant_div_main_gaintb bit 5 2557 * enable_ant_div_lnadiv bit 6 2558 * enable_ant_fast_div bit 7 2559 */ 2560 if ((ant_div_ctl1 >> 0x6) == 0x3) 2561 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2562 } 2563 2564 if (ath9k_hw_dfs_tested(ah)) 2565 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2566 2567 tx_chainmask = pCap->tx_chainmask; 2568 rx_chainmask = pCap->rx_chainmask; 2569 while (tx_chainmask || rx_chainmask) { 2570 if (tx_chainmask & BIT(0)) 2571 pCap->max_txchains++; 2572 if (rx_chainmask & BIT(0)) 2573 pCap->max_rxchains++; 2574 2575 tx_chainmask >>= 1; 2576 rx_chainmask >>= 1; 2577 } 2578 2579 if (AR_SREV_9300_20_OR_LATER(ah)) { 2580 ah->enabled_cals |= TX_IQ_CAL; 2581 if (AR_SREV_9485_OR_LATER(ah)) 2582 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2583 } 2584 2585 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2586 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2587 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2588 2589 if (AR_SREV_9462_20(ah)) 2590 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2591 } 2592 2593 2594 if (AR_SREV_9280_20_OR_LATER(ah)) { 2595 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE | 2596 ATH9K_HW_WOW_PATTERN_MATCH_EXACT; 2597 2598 if (AR_SREV_9280(ah)) 2599 pCap->hw_caps |= ATH9K_HW_WOW_PATTERN_MATCH_DWORD; 2600 } 2601 2602 if (AR_SREV_9300_20_OR_LATER(ah) && 2603 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2604 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2605 2606 return 0; 2607 } 2608 2609 /****************************/ 2610 /* GPIO / RFKILL / Antennae */ 2611 /****************************/ 2612 2613 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2614 u32 gpio, u32 type) 2615 { 2616 int addr; 2617 u32 gpio_shift, tmp; 2618 2619 if (gpio > 11) 2620 addr = AR_GPIO_OUTPUT_MUX3; 2621 else if (gpio > 5) 2622 addr = AR_GPIO_OUTPUT_MUX2; 2623 else 2624 addr = AR_GPIO_OUTPUT_MUX1; 2625 2626 gpio_shift = (gpio % 6) * 5; 2627 2628 if (AR_SREV_9280_20_OR_LATER(ah) 2629 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2630 REG_RMW(ah, addr, (type << gpio_shift), 2631 (0x1f << gpio_shift)); 2632 } else { 2633 tmp = REG_READ(ah, addr); 2634 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2635 tmp &= ~(0x1f << gpio_shift); 2636 tmp |= (type << gpio_shift); 2637 REG_WRITE(ah, addr, tmp); 2638 } 2639 } 2640 2641 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2642 { 2643 u32 gpio_shift; 2644 2645 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2646 2647 if (AR_DEVID_7010(ah)) { 2648 gpio_shift = gpio; 2649 REG_RMW(ah, AR7010_GPIO_OE, 2650 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2651 (AR7010_GPIO_OE_MASK << gpio_shift)); 2652 return; 2653 } 2654 2655 gpio_shift = gpio << 1; 2656 REG_RMW(ah, 2657 AR_GPIO_OE_OUT, 2658 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2659 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2660 } 2661 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2662 2663 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2664 { 2665 #define MS_REG_READ(x, y) \ 2666 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2667 2668 if (gpio >= ah->caps.num_gpio_pins) 2669 return 0xffffffff; 2670 2671 if (AR_DEVID_7010(ah)) { 2672 u32 val; 2673 val = REG_READ(ah, AR7010_GPIO_IN); 2674 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2675 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2676 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2677 AR_GPIO_BIT(gpio)) != 0; 2678 else if (AR_SREV_9271(ah)) 2679 return MS_REG_READ(AR9271, gpio) != 0; 2680 else if (AR_SREV_9287_11_OR_LATER(ah)) 2681 return MS_REG_READ(AR9287, gpio) != 0; 2682 else if (AR_SREV_9285_12_OR_LATER(ah)) 2683 return MS_REG_READ(AR9285, gpio) != 0; 2684 else if (AR_SREV_9280_20_OR_LATER(ah)) 2685 return MS_REG_READ(AR928X, gpio) != 0; 2686 else 2687 return MS_REG_READ(AR, gpio) != 0; 2688 } 2689 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2690 2691 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2692 u32 ah_signal_type) 2693 { 2694 u32 gpio_shift; 2695 2696 if (AR_DEVID_7010(ah)) { 2697 gpio_shift = gpio; 2698 REG_RMW(ah, AR7010_GPIO_OE, 2699 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2700 (AR7010_GPIO_OE_MASK << gpio_shift)); 2701 return; 2702 } 2703 2704 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2705 gpio_shift = 2 * gpio; 2706 REG_RMW(ah, 2707 AR_GPIO_OE_OUT, 2708 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2709 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2710 } 2711 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2712 2713 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2714 { 2715 if (AR_DEVID_7010(ah)) { 2716 val = val ? 0 : 1; 2717 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2718 AR_GPIO_BIT(gpio)); 2719 return; 2720 } 2721 2722 if (AR_SREV_9271(ah)) 2723 val = ~val; 2724 2725 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2726 AR_GPIO_BIT(gpio)); 2727 } 2728 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2729 2730 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2731 { 2732 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2733 } 2734 EXPORT_SYMBOL(ath9k_hw_setantenna); 2735 2736 /*********************/ 2737 /* General Operation */ 2738 /*********************/ 2739 2740 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2741 { 2742 u32 bits = REG_READ(ah, AR_RX_FILTER); 2743 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2744 2745 if (phybits & AR_PHY_ERR_RADAR) 2746 bits |= ATH9K_RX_FILTER_PHYRADAR; 2747 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2748 bits |= ATH9K_RX_FILTER_PHYERR; 2749 2750 return bits; 2751 } 2752 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2753 2754 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2755 { 2756 u32 phybits; 2757 2758 ENABLE_REGWRITE_BUFFER(ah); 2759 2760 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2761 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2762 2763 REG_WRITE(ah, AR_RX_FILTER, bits); 2764 2765 phybits = 0; 2766 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2767 phybits |= AR_PHY_ERR_RADAR; 2768 if (bits & ATH9K_RX_FILTER_PHYERR) 2769 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2770 REG_WRITE(ah, AR_PHY_ERR, phybits); 2771 2772 if (phybits) 2773 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2774 else 2775 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2776 2777 REGWRITE_BUFFER_FLUSH(ah); 2778 } 2779 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2780 2781 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2782 { 2783 if (ath9k_hw_mci_is_enabled(ah)) 2784 ar9003_mci_bt_gain_ctrl(ah); 2785 2786 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2787 return false; 2788 2789 ath9k_hw_init_pll(ah, NULL); 2790 ah->htc_reset_init = true; 2791 return true; 2792 } 2793 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2794 2795 bool ath9k_hw_disable(struct ath_hw *ah) 2796 { 2797 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2798 return false; 2799 2800 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2801 return false; 2802 2803 ath9k_hw_init_pll(ah, NULL); 2804 return true; 2805 } 2806 EXPORT_SYMBOL(ath9k_hw_disable); 2807 2808 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2809 { 2810 enum eeprom_param gain_param; 2811 2812 if (IS_CHAN_2GHZ(chan)) 2813 gain_param = EEP_ANTENNA_GAIN_2G; 2814 else 2815 gain_param = EEP_ANTENNA_GAIN_5G; 2816 2817 return ah->eep_ops->get_eeprom(ah, gain_param); 2818 } 2819 2820 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2821 bool test) 2822 { 2823 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2824 struct ieee80211_channel *channel; 2825 int chan_pwr, new_pwr, max_gain; 2826 int ant_gain, ant_reduction = 0; 2827 2828 if (!chan) 2829 return; 2830 2831 channel = chan->chan; 2832 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2833 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2834 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2835 2836 ant_gain = get_antenna_gain(ah, chan); 2837 if (ant_gain > max_gain) 2838 ant_reduction = ant_gain - max_gain; 2839 2840 ah->eep_ops->set_txpower(ah, chan, 2841 ath9k_regd_get_ctl(reg, chan), 2842 ant_reduction, new_pwr, test); 2843 } 2844 2845 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2846 { 2847 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2848 struct ath9k_channel *chan = ah->curchan; 2849 struct ieee80211_channel *channel = chan->chan; 2850 2851 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2852 if (test) 2853 channel->max_power = MAX_RATE_POWER / 2; 2854 2855 ath9k_hw_apply_txpower(ah, chan, test); 2856 2857 if (test) 2858 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2859 } 2860 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2861 2862 void ath9k_hw_setopmode(struct ath_hw *ah) 2863 { 2864 ath9k_hw_set_operating_mode(ah, ah->opmode); 2865 } 2866 EXPORT_SYMBOL(ath9k_hw_setopmode); 2867 2868 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2869 { 2870 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2871 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2872 } 2873 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2874 2875 void ath9k_hw_write_associd(struct ath_hw *ah) 2876 { 2877 struct ath_common *common = ath9k_hw_common(ah); 2878 2879 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2880 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2881 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2882 } 2883 EXPORT_SYMBOL(ath9k_hw_write_associd); 2884 2885 #define ATH9K_MAX_TSF_READ 10 2886 2887 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2888 { 2889 u32 tsf_lower, tsf_upper1, tsf_upper2; 2890 int i; 2891 2892 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2893 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2894 tsf_lower = REG_READ(ah, AR_TSF_L32); 2895 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2896 if (tsf_upper2 == tsf_upper1) 2897 break; 2898 tsf_upper1 = tsf_upper2; 2899 } 2900 2901 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2902 2903 return (((u64)tsf_upper1 << 32) | tsf_lower); 2904 } 2905 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2906 2907 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2908 { 2909 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2910 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2911 } 2912 EXPORT_SYMBOL(ath9k_hw_settsf64); 2913 2914 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2915 { 2916 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2917 AH_TSF_WRITE_TIMEOUT)) 2918 ath_dbg(ath9k_hw_common(ah), RESET, 2919 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2920 2921 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2922 } 2923 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2924 2925 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2926 { 2927 if (set) 2928 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2929 else 2930 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2931 } 2932 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2933 2934 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2935 { 2936 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2937 u32 macmode; 2938 2939 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2940 macmode = AR_2040_JOINED_RX_CLEAR; 2941 else 2942 macmode = 0; 2943 2944 REG_WRITE(ah, AR_2040_MODE, macmode); 2945 } 2946 2947 /* HW Generic timers configuration */ 2948 2949 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2950 { 2951 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2952 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2953 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2954 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2955 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2956 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2957 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2958 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2959 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2960 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2961 AR_NDP2_TIMER_MODE, 0x0002}, 2962 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2963 AR_NDP2_TIMER_MODE, 0x0004}, 2964 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2965 AR_NDP2_TIMER_MODE, 0x0008}, 2966 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2967 AR_NDP2_TIMER_MODE, 0x0010}, 2968 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2969 AR_NDP2_TIMER_MODE, 0x0020}, 2970 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2971 AR_NDP2_TIMER_MODE, 0x0040}, 2972 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2973 AR_NDP2_TIMER_MODE, 0x0080} 2974 }; 2975 2976 /* HW generic timer primitives */ 2977 2978 /* compute and clear index of rightmost 1 */ 2979 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2980 { 2981 u32 b; 2982 2983 b = *mask; 2984 b &= (0-b); 2985 *mask &= ~b; 2986 b *= debruijn32; 2987 b >>= 27; 2988 2989 return timer_table->gen_timer_index[b]; 2990 } 2991 2992 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2993 { 2994 return REG_READ(ah, AR_TSF_L32); 2995 } 2996 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2997 2998 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2999 void (*trigger)(void *), 3000 void (*overflow)(void *), 3001 void *arg, 3002 u8 timer_index) 3003 { 3004 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3005 struct ath_gen_timer *timer; 3006 3007 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3008 3009 if (timer == NULL) { 3010 ath_err(ath9k_hw_common(ah), 3011 "Failed to allocate memory for hw timer[%d]\n", 3012 timer_index); 3013 return NULL; 3014 } 3015 3016 /* allocate a hardware generic timer slot */ 3017 timer_table->timers[timer_index] = timer; 3018 timer->index = timer_index; 3019 timer->trigger = trigger; 3020 timer->overflow = overflow; 3021 timer->arg = arg; 3022 3023 return timer; 3024 } 3025 EXPORT_SYMBOL(ath_gen_timer_alloc); 3026 3027 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3028 struct ath_gen_timer *timer, 3029 u32 trig_timeout, 3030 u32 timer_period) 3031 { 3032 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3033 u32 tsf, timer_next; 3034 3035 BUG_ON(!timer_period); 3036 3037 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3038 3039 tsf = ath9k_hw_gettsf32(ah); 3040 3041 timer_next = tsf + trig_timeout; 3042 3043 ath_dbg(ath9k_hw_common(ah), HWTIMER, 3044 "current tsf %x period %x timer_next %x\n", 3045 tsf, timer_period, timer_next); 3046 3047 /* 3048 * Program generic timer registers 3049 */ 3050 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3051 timer_next); 3052 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3053 timer_period); 3054 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3055 gen_tmr_configuration[timer->index].mode_mask); 3056 3057 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3058 /* 3059 * Starting from AR9462, each generic timer can select which tsf 3060 * to use. But we still follow the old rule, 0 - 7 use tsf and 3061 * 8 - 15 use tsf2. 3062 */ 3063 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3064 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3065 (1 << timer->index)); 3066 else 3067 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3068 (1 << timer->index)); 3069 } 3070 3071 /* Enable both trigger and thresh interrupt masks */ 3072 REG_SET_BIT(ah, AR_IMR_S5, 3073 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3074 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3075 } 3076 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3077 3078 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3079 { 3080 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3081 3082 if ((timer->index < AR_FIRST_NDP_TIMER) || 3083 (timer->index >= ATH_MAX_GEN_TIMER)) { 3084 return; 3085 } 3086 3087 /* Clear generic timer enable bits. */ 3088 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3089 gen_tmr_configuration[timer->index].mode_mask); 3090 3091 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3092 /* 3093 * Need to switch back to TSF if it was using TSF2. 3094 */ 3095 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3096 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3097 (1 << timer->index)); 3098 } 3099 } 3100 3101 /* Disable both trigger and thresh interrupt masks */ 3102 REG_CLR_BIT(ah, AR_IMR_S5, 3103 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3104 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3105 3106 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3107 } 3108 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3109 3110 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3111 { 3112 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3113 3114 /* free the hardware generic timer slot */ 3115 timer_table->timers[timer->index] = NULL; 3116 kfree(timer); 3117 } 3118 EXPORT_SYMBOL(ath_gen_timer_free); 3119 3120 /* 3121 * Generic Timer Interrupts handling 3122 */ 3123 void ath_gen_timer_isr(struct ath_hw *ah) 3124 { 3125 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3126 struct ath_gen_timer *timer; 3127 struct ath_common *common = ath9k_hw_common(ah); 3128 u32 trigger_mask, thresh_mask, index; 3129 3130 /* get hardware generic timer interrupt status */ 3131 trigger_mask = ah->intr_gen_timer_trigger; 3132 thresh_mask = ah->intr_gen_timer_thresh; 3133 trigger_mask &= timer_table->timer_mask.val; 3134 thresh_mask &= timer_table->timer_mask.val; 3135 3136 trigger_mask &= ~thresh_mask; 3137 3138 while (thresh_mask) { 3139 index = rightmost_index(timer_table, &thresh_mask); 3140 timer = timer_table->timers[index]; 3141 BUG_ON(!timer); 3142 ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", 3143 index); 3144 timer->overflow(timer->arg); 3145 } 3146 3147 while (trigger_mask) { 3148 index = rightmost_index(timer_table, &trigger_mask); 3149 timer = timer_table->timers[index]; 3150 BUG_ON(!timer); 3151 ath_dbg(common, HWTIMER, 3152 "Gen timer[%d] trigger\n", index); 3153 timer->trigger(timer->arg); 3154 } 3155 } 3156 EXPORT_SYMBOL(ath_gen_timer_isr); 3157 3158 /********/ 3159 /* HTC */ 3160 /********/ 3161 3162 static struct { 3163 u32 version; 3164 const char * name; 3165 } ath_mac_bb_names[] = { 3166 /* Devices with external radios */ 3167 { AR_SREV_VERSION_5416_PCI, "5416" }, 3168 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3169 { AR_SREV_VERSION_9100, "9100" }, 3170 { AR_SREV_VERSION_9160, "9160" }, 3171 /* Single-chip solutions */ 3172 { AR_SREV_VERSION_9280, "9280" }, 3173 { AR_SREV_VERSION_9285, "9285" }, 3174 { AR_SREV_VERSION_9287, "9287" }, 3175 { AR_SREV_VERSION_9271, "9271" }, 3176 { AR_SREV_VERSION_9300, "9300" }, 3177 { AR_SREV_VERSION_9330, "9330" }, 3178 { AR_SREV_VERSION_9340, "9340" }, 3179 { AR_SREV_VERSION_9485, "9485" }, 3180 { AR_SREV_VERSION_9462, "9462" }, 3181 { AR_SREV_VERSION_9550, "9550" }, 3182 { AR_SREV_VERSION_9565, "9565" }, 3183 }; 3184 3185 /* For devices with external radios */ 3186 static struct { 3187 u16 version; 3188 const char * name; 3189 } ath_rf_names[] = { 3190 { 0, "5133" }, 3191 { AR_RAD5133_SREV_MAJOR, "5133" }, 3192 { AR_RAD5122_SREV_MAJOR, "5122" }, 3193 { AR_RAD2133_SREV_MAJOR, "2133" }, 3194 { AR_RAD2122_SREV_MAJOR, "2122" } 3195 }; 3196 3197 /* 3198 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3199 */ 3200 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3201 { 3202 int i; 3203 3204 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3205 if (ath_mac_bb_names[i].version == mac_bb_version) { 3206 return ath_mac_bb_names[i].name; 3207 } 3208 } 3209 3210 return "????"; 3211 } 3212 3213 /* 3214 * Return the RF name. "????" is returned if the RF is unknown. 3215 * Used for devices with external radios. 3216 */ 3217 static const char *ath9k_hw_rf_name(u16 rf_version) 3218 { 3219 int i; 3220 3221 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3222 if (ath_rf_names[i].version == rf_version) { 3223 return ath_rf_names[i].name; 3224 } 3225 } 3226 3227 return "????"; 3228 } 3229 3230 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3231 { 3232 int used; 3233 3234 /* chipsets >= AR9280 are single-chip */ 3235 if (AR_SREV_9280_20_OR_LATER(ah)) { 3236 used = snprintf(hw_name, len, 3237 "Atheros AR%s Rev:%x", 3238 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3239 ah->hw_version.macRev); 3240 } 3241 else { 3242 used = snprintf(hw_name, len, 3243 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3244 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3245 ah->hw_version.macRev, 3246 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 3247 AR_RADIO_SREV_MAJOR)), 3248 ah->hw_version.phyRev); 3249 } 3250 3251 hw_name[used] = '\0'; 3252 } 3253 EXPORT_SYMBOL(ath9k_hw_name); 3254