1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <asm/unaligned.h> 18 #include "hw.h" 19 #include "ar9002_phy.h" 20 21 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 22 { 23 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF); 24 } 25 26 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) 27 { 28 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF); 29 } 30 31 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 32 33 static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 34 { 35 struct ath_common *common = ath9k_hw_common(ah); 36 u16 *eep_data = (u16 *)&ah->eeprom.map4k; 37 int addr, eep_start_loc = 64; 38 39 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 40 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { 41 ath_dbg(common, ATH_DBG_EEPROM, 42 "Unable to read eeprom region\n"); 43 return false; 44 } 45 eep_data++; 46 } 47 48 return true; 49 } 50 51 static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah) 52 { 53 u16 *eep_data = (u16 *)&ah->eeprom.map4k; 54 55 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K); 56 57 return true; 58 } 59 60 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 61 { 62 struct ath_common *common = ath9k_hw_common(ah); 63 64 if (!ath9k_hw_use_flash(ah)) { 65 ath_dbg(common, ATH_DBG_EEPROM, 66 "Reading from EEPROM, not flash\n"); 67 } 68 69 if (common->bus_ops->ath_bus_type == ATH_USB) 70 return __ath9k_hw_usb_4k_fill_eeprom(ah); 71 else 72 return __ath9k_hw_4k_fill_eeprom(ah); 73 } 74 75 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) 76 static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size, 77 struct modal_eep_4k_header *modal_hdr) 78 { 79 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]); 80 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon); 81 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]); 82 PR_EEP("Switch Settle", modal_hdr->switchSettling); 83 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]); 84 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]); 85 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); 86 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize); 87 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]); 88 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); 89 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn); 90 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); 91 PR_EEP("CCA Threshold)", modal_hdr->thresh62); 92 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); 93 PR_EEP("xpdGain", modal_hdr->xpdGain); 94 PR_EEP("External PD", modal_hdr->xpd); 95 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]); 96 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]); 97 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap); 98 PR_EEP("O/D Bias Version", modal_hdr->version); 99 PR_EEP("CCK OutputBias", modal_hdr->ob_0); 100 PR_EEP("BPSK OutputBias", modal_hdr->ob_1); 101 PR_EEP("QPSK OutputBias", modal_hdr->ob_2); 102 PR_EEP("16QAM OutputBias", modal_hdr->ob_3); 103 PR_EEP("64QAM OutputBias", modal_hdr->ob_4); 104 PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0); 105 PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1); 106 PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2); 107 PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3); 108 PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4); 109 PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0); 110 PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1); 111 PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2); 112 PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3); 113 PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4); 114 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); 115 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); 116 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); 117 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc); 118 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]); 119 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]); 120 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40); 121 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]); 122 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]); 123 PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1); 124 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2); 125 PR_EEP("TX Diversity", modal_hdr->tx_diversity); 126 127 return len; 128 } 129 130 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 131 u8 *buf, u32 len, u32 size) 132 { 133 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 134 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 135 136 if (!dump_base_hdr) { 137 len += snprintf(buf + len, size - len, 138 "%20s :\n", "2GHz modal Header"); 139 len += ath9k_dump_4k_modal_eeprom(buf, len, size, 140 &eep->modalHeader); 141 goto out; 142 } 143 144 PR_EEP("Major Version", pBase->version >> 12); 145 PR_EEP("Minor Version", pBase->version & 0xFFF); 146 PR_EEP("Checksum", pBase->checksum); 147 PR_EEP("Length", pBase->length); 148 PR_EEP("RegDomain1", pBase->regDmn[0]); 149 PR_EEP("RegDomain2", pBase->regDmn[1]); 150 PR_EEP("TX Mask", pBase->txMask); 151 PR_EEP("RX Mask", pBase->rxMask); 152 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A)); 153 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G)); 154 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags & 155 AR5416_OPFLAGS_N_2G_HT20)); 156 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags & 157 AR5416_OPFLAGS_N_2G_HT40)); 158 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags & 159 AR5416_OPFLAGS_N_5G_HT20)); 160 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags & 161 AR5416_OPFLAGS_N_5G_HT40)); 162 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01)); 163 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF); 164 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF); 165 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF); 166 PR_EEP("TX Gain type", pBase->txGainType); 167 168 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", 169 pBase->macAddr); 170 171 out: 172 if (len > size) 173 len = size; 174 175 return len; 176 } 177 #else 178 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 179 u8 *buf, u32 len, u32 size) 180 { 181 return 0; 182 } 183 #endif 184 185 186 #undef SIZE_EEPROM_4K 187 188 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) 189 { 190 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 191 struct ath_common *common = ath9k_hw_common(ah); 192 struct ar5416_eeprom_4k *eep = 193 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; 194 u16 *eepdata, temp, magic, magic2; 195 u32 sum = 0, el; 196 bool need_swap = false; 197 int i, addr; 198 199 200 if (!ath9k_hw_use_flash(ah)) { 201 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, 202 &magic)) { 203 ath_err(common, "Reading Magic # failed\n"); 204 return false; 205 } 206 207 ath_dbg(common, ATH_DBG_EEPROM, 208 "Read Magic = 0x%04X\n", magic); 209 210 if (magic != AR5416_EEPROM_MAGIC) { 211 magic2 = swab16(magic); 212 213 if (magic2 == AR5416_EEPROM_MAGIC) { 214 need_swap = true; 215 eepdata = (u16 *) (&ah->eeprom); 216 217 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { 218 temp = swab16(*eepdata); 219 *eepdata = temp; 220 eepdata++; 221 } 222 } else { 223 ath_err(common, 224 "Invalid EEPROM Magic. Endianness mismatch.\n"); 225 return -EINVAL; 226 } 227 } 228 } 229 230 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", 231 need_swap ? "True" : "False"); 232 233 if (need_swap) 234 el = swab16(ah->eeprom.map4k.baseEepHeader.length); 235 else 236 el = ah->eeprom.map4k.baseEepHeader.length; 237 238 if (el > sizeof(struct ar5416_eeprom_4k)) 239 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); 240 else 241 el = el / sizeof(u16); 242 243 eepdata = (u16 *)(&ah->eeprom); 244 245 for (i = 0; i < el; i++) 246 sum ^= *eepdata++; 247 248 if (need_swap) { 249 u32 integer; 250 u16 word; 251 252 ath_dbg(common, ATH_DBG_EEPROM, 253 "EEPROM Endianness is not native.. Changing\n"); 254 255 word = swab16(eep->baseEepHeader.length); 256 eep->baseEepHeader.length = word; 257 258 word = swab16(eep->baseEepHeader.checksum); 259 eep->baseEepHeader.checksum = word; 260 261 word = swab16(eep->baseEepHeader.version); 262 eep->baseEepHeader.version = word; 263 264 word = swab16(eep->baseEepHeader.regDmn[0]); 265 eep->baseEepHeader.regDmn[0] = word; 266 267 word = swab16(eep->baseEepHeader.regDmn[1]); 268 eep->baseEepHeader.regDmn[1] = word; 269 270 word = swab16(eep->baseEepHeader.rfSilent); 271 eep->baseEepHeader.rfSilent = word; 272 273 word = swab16(eep->baseEepHeader.blueToothOptions); 274 eep->baseEepHeader.blueToothOptions = word; 275 276 word = swab16(eep->baseEepHeader.deviceCap); 277 eep->baseEepHeader.deviceCap = word; 278 279 integer = swab32(eep->modalHeader.antCtrlCommon); 280 eep->modalHeader.antCtrlCommon = integer; 281 282 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { 283 integer = swab32(eep->modalHeader.antCtrlChain[i]); 284 eep->modalHeader.antCtrlChain[i] = integer; 285 } 286 287 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 288 word = swab16(eep->modalHeader.spurChans[i].spurChan); 289 eep->modalHeader.spurChans[i].spurChan = word; 290 } 291 } 292 293 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 294 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 295 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 296 sum, ah->eep_ops->get_eeprom_ver(ah)); 297 return -EINVAL; 298 } 299 300 return 0; 301 #undef EEPROM_4K_SIZE 302 } 303 304 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, 305 enum eeprom_param param) 306 { 307 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 308 struct modal_eep_4k_header *pModal = &eep->modalHeader; 309 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 310 u16 ver_minor; 311 312 ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK; 313 314 switch (param) { 315 case EEP_NFTHRESH_2: 316 return pModal->noiseFloorThreshCh[0]; 317 case EEP_MAC_LSW: 318 return get_unaligned_be16(pBase->macAddr); 319 case EEP_MAC_MID: 320 return get_unaligned_be16(pBase->macAddr + 2); 321 case EEP_MAC_MSW: 322 return get_unaligned_be16(pBase->macAddr + 4); 323 case EEP_REG_0: 324 return pBase->regDmn[0]; 325 case EEP_OP_CAP: 326 return pBase->deviceCap; 327 case EEP_OP_MODE: 328 return pBase->opCapFlags; 329 case EEP_RF_SILENT: 330 return pBase->rfSilent; 331 case EEP_OB_2: 332 return pModal->ob_0; 333 case EEP_DB_2: 334 return pModal->db1_1; 335 case EEP_MINOR_REV: 336 return ver_minor; 337 case EEP_TX_MASK: 338 return pBase->txMask; 339 case EEP_RX_MASK: 340 return pBase->rxMask; 341 case EEP_FRAC_N_5G: 342 return 0; 343 case EEP_PWR_TABLE_OFFSET: 344 return AR5416_PWR_TABLE_OFFSET_DB; 345 case EEP_MODAL_VER: 346 return pModal->version; 347 case EEP_ANT_DIV_CTL1: 348 return pModal->antdiv_ctl1; 349 case EEP_TXGAIN_TYPE: 350 return pBase->txGainType; 351 case EEP_ANTENNA_GAIN_2G: 352 return pModal->antennaGainCh[0]; 353 default: 354 return 0; 355 } 356 } 357 358 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, 359 struct ath9k_channel *chan) 360 { 361 struct ath_common *common = ath9k_hw_common(ah); 362 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 363 struct cal_data_per_freq_4k *pRawDataset; 364 u8 *pCalBChans = NULL; 365 u16 pdGainOverlap_t2; 366 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 367 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 368 u16 numPiers, i, j; 369 u16 numXpdGain, xpdMask; 370 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; 371 u32 reg32, regOffset, regChainOffset; 372 373 xpdMask = pEepData->modalHeader.xpdGain; 374 375 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 376 AR5416_EEP_MINOR_VER_2) { 377 pdGainOverlap_t2 = 378 pEepData->modalHeader.pdGainOverlap; 379 } else { 380 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), 381 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 382 } 383 384 pCalBChans = pEepData->calFreqPier2G; 385 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS; 386 387 numXpdGain = 0; 388 389 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 390 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 391 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) 392 break; 393 xpdGainValues[numXpdGain] = 394 (u16)(AR5416_PD_GAINS_IN_MASK - i); 395 numXpdGain++; 396 } 397 } 398 399 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 400 (numXpdGain - 1) & 0x3); 401 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 402 xpdGainValues[0]); 403 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, 404 xpdGainValues[1]); 405 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0); 406 407 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { 408 regChainOffset = i * 0x1000; 409 410 if (pEepData->baseEepHeader.txMask & (1 << i)) { 411 pRawDataset = pEepData->calPierData2G[i]; 412 413 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, 414 pRawDataset, pCalBChans, 415 numPiers, pdGainOverlap_t2, 416 gainBoundaries, 417 pdadcValues, numXpdGain); 418 419 ENABLE_REGWRITE_BUFFER(ah); 420 421 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 422 SM(pdGainOverlap_t2, 423 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) 424 | SM(gainBoundaries[0], 425 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) 426 | SM(gainBoundaries[1], 427 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) 428 | SM(gainBoundaries[2], 429 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) 430 | SM(gainBoundaries[3], 431 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 432 433 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 434 for (j = 0; j < 32; j++) { 435 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); 436 REG_WRITE(ah, regOffset, reg32); 437 438 ath_dbg(common, ATH_DBG_EEPROM, 439 "PDADC (%d,%4x): %4.4x %8.8x\n", 440 i, regChainOffset, regOffset, 441 reg32); 442 ath_dbg(common, ATH_DBG_EEPROM, 443 "PDADC: Chain %d | " 444 "PDADC %3d Value %3d | " 445 "PDADC %3d Value %3d | " 446 "PDADC %3d Value %3d | " 447 "PDADC %3d Value %3d |\n", 448 i, 4 * j, pdadcValues[4 * j], 449 4 * j + 1, pdadcValues[4 * j + 1], 450 4 * j + 2, pdadcValues[4 * j + 2], 451 4 * j + 3, pdadcValues[4 * j + 3]); 452 453 regOffset += 4; 454 } 455 456 REGWRITE_BUFFER_FLUSH(ah); 457 } 458 } 459 } 460 461 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, 462 struct ath9k_channel *chan, 463 int16_t *ratesArray, 464 u16 cfgCtl, 465 u16 antenna_reduction, 466 u16 powerLimit) 467 { 468 #define CMP_TEST_GRP \ 469 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 470 pEepData->ctlIndex[i]) \ 471 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ 472 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) 473 474 int i; 475 u16 twiceMinEdgePower; 476 u16 twiceMaxEdgePower = MAX_RATE_POWER; 477 u16 scaledPower = 0, minCtlPower; 478 u16 numCtlModes; 479 const u16 *pCtlMode; 480 u16 ctlMode, freq; 481 struct chan_centers centers; 482 struct cal_ctl_data_4k *rep; 483 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 484 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 485 0, { 0, 0, 0, 0} 486 }; 487 struct cal_target_power_leg targetPowerOfdmExt = { 488 0, { 0, 0, 0, 0} }, targetPowerCckExt = { 489 0, { 0, 0, 0, 0 } 490 }; 491 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 492 0, {0, 0, 0, 0} 493 }; 494 static const u16 ctlModesFor11g[] = { 495 CTL_11B, CTL_11G, CTL_2GHT20, 496 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 497 }; 498 499 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 500 501 scaledPower = powerLimit - antenna_reduction; 502 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; 503 pCtlMode = ctlModesFor11g; 504 505 ath9k_hw_get_legacy_target_powers(ah, chan, 506 pEepData->calTargetPowerCck, 507 AR5416_NUM_2G_CCK_TARGET_POWERS, 508 &targetPowerCck, 4, false); 509 ath9k_hw_get_legacy_target_powers(ah, chan, 510 pEepData->calTargetPower2G, 511 AR5416_NUM_2G_20_TARGET_POWERS, 512 &targetPowerOfdm, 4, false); 513 ath9k_hw_get_target_powers(ah, chan, 514 pEepData->calTargetPower2GHT20, 515 AR5416_NUM_2G_20_TARGET_POWERS, 516 &targetPowerHt20, 8, false); 517 518 if (IS_CHAN_HT40(chan)) { 519 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 520 ath9k_hw_get_target_powers(ah, chan, 521 pEepData->calTargetPower2GHT40, 522 AR5416_NUM_2G_40_TARGET_POWERS, 523 &targetPowerHt40, 8, true); 524 ath9k_hw_get_legacy_target_powers(ah, chan, 525 pEepData->calTargetPowerCck, 526 AR5416_NUM_2G_CCK_TARGET_POWERS, 527 &targetPowerCckExt, 4, true); 528 ath9k_hw_get_legacy_target_powers(ah, chan, 529 pEepData->calTargetPower2G, 530 AR5416_NUM_2G_20_TARGET_POWERS, 531 &targetPowerOfdmExt, 4, true); 532 } 533 534 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 535 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 536 (pCtlMode[ctlMode] == CTL_2GHT40); 537 538 if (isHt40CtlMode) 539 freq = centers.synth_center; 540 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 541 freq = centers.ext_center; 542 else 543 freq = centers.ctl_center; 544 545 if (ah->eep_ops->get_eeprom_ver(ah) == 14 && 546 ah->eep_ops->get_eeprom_rev(ah) <= 2) 547 twiceMaxEdgePower = MAX_RATE_POWER; 548 549 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && 550 pEepData->ctlIndex[i]; i++) { 551 552 if (CMP_TEST_GRP) { 553 rep = &(pEepData->ctlData[i]); 554 555 twiceMinEdgePower = ath9k_hw_get_max_edge_power( 556 freq, 557 rep->ctlEdges[ 558 ar5416_get_ntxchains(ah->txchainmask) - 1], 559 IS_CHAN_2GHZ(chan), 560 AR5416_EEP4K_NUM_BAND_EDGES); 561 562 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 563 twiceMaxEdgePower = 564 min(twiceMaxEdgePower, 565 twiceMinEdgePower); 566 } else { 567 twiceMaxEdgePower = twiceMinEdgePower; 568 break; 569 } 570 } 571 } 572 573 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 574 575 switch (pCtlMode[ctlMode]) { 576 case CTL_11B: 577 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 578 targetPowerCck.tPow2x[i] = 579 min((u16)targetPowerCck.tPow2x[i], 580 minCtlPower); 581 } 582 break; 583 case CTL_11G: 584 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { 585 targetPowerOfdm.tPow2x[i] = 586 min((u16)targetPowerOfdm.tPow2x[i], 587 minCtlPower); 588 } 589 break; 590 case CTL_2GHT20: 591 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { 592 targetPowerHt20.tPow2x[i] = 593 min((u16)targetPowerHt20.tPow2x[i], 594 minCtlPower); 595 } 596 break; 597 case CTL_11B_EXT: 598 targetPowerCckExt.tPow2x[0] = 599 min((u16)targetPowerCckExt.tPow2x[0], 600 minCtlPower); 601 break; 602 case CTL_11G_EXT: 603 targetPowerOfdmExt.tPow2x[0] = 604 min((u16)targetPowerOfdmExt.tPow2x[0], 605 minCtlPower); 606 break; 607 case CTL_2GHT40: 608 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 609 targetPowerHt40.tPow2x[i] = 610 min((u16)targetPowerHt40.tPow2x[i], 611 minCtlPower); 612 } 613 break; 614 default: 615 break; 616 } 617 } 618 619 ratesArray[rate6mb] = 620 ratesArray[rate9mb] = 621 ratesArray[rate12mb] = 622 ratesArray[rate18mb] = 623 ratesArray[rate24mb] = 624 targetPowerOfdm.tPow2x[0]; 625 626 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 627 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 628 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 629 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 630 631 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) 632 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 633 634 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 635 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 636 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 637 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 638 639 if (IS_CHAN_HT40(chan)) { 640 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 641 ratesArray[rateHt40_0 + i] = 642 targetPowerHt40.tPow2x[i]; 643 } 644 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 645 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 646 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 647 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 648 } 649 650 #undef CMP_TEST_GRP 651 } 652 653 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, 654 struct ath9k_channel *chan, 655 u16 cfgCtl, 656 u8 twiceAntennaReduction, 657 u8 powerLimit, bool test) 658 { 659 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 660 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 661 struct modal_eep_4k_header *pModal = &pEepData->modalHeader; 662 int16_t ratesArray[Ar5416RateSize]; 663 u8 ht40PowerIncForPdadc = 2; 664 int i; 665 666 memset(ratesArray, 0, sizeof(ratesArray)); 667 668 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 669 AR5416_EEP_MINOR_VER_2) { 670 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 671 } 672 673 ath9k_hw_set_4k_power_per_rate_table(ah, chan, 674 &ratesArray[0], cfgCtl, 675 twiceAntennaReduction, 676 powerLimit); 677 678 ath9k_hw_set_4k_power_cal_table(ah, chan); 679 680 regulatory->max_power_level = 0; 681 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 682 if (ratesArray[i] > MAX_RATE_POWER) 683 ratesArray[i] = MAX_RATE_POWER; 684 685 if (ratesArray[i] > regulatory->max_power_level) 686 regulatory->max_power_level = ratesArray[i]; 687 } 688 689 if (test) 690 return; 691 692 for (i = 0; i < Ar5416RateSize; i++) 693 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 694 695 ENABLE_REGWRITE_BUFFER(ah); 696 697 /* OFDM power per rate */ 698 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 699 ATH9K_POW_SM(ratesArray[rate18mb], 24) 700 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 701 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 702 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); 703 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 704 ATH9K_POW_SM(ratesArray[rate54mb], 24) 705 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 706 | ATH9K_POW_SM(ratesArray[rate36mb], 8) 707 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); 708 709 /* CCK power per rate */ 710 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 711 ATH9K_POW_SM(ratesArray[rate2s], 24) 712 | ATH9K_POW_SM(ratesArray[rate2l], 16) 713 | ATH9K_POW_SM(ratesArray[rateXr], 8) 714 | ATH9K_POW_SM(ratesArray[rate1l], 0)); 715 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 716 ATH9K_POW_SM(ratesArray[rate11s], 24) 717 | ATH9K_POW_SM(ratesArray[rate11l], 16) 718 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) 719 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); 720 721 /* HT20 power per rate */ 722 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 723 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 724 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 725 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 726 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); 727 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 728 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) 729 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) 730 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) 731 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); 732 733 /* HT40 power per rate */ 734 if (IS_CHAN_HT40(chan)) { 735 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 736 ATH9K_POW_SM(ratesArray[rateHt40_3] + 737 ht40PowerIncForPdadc, 24) 738 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 739 ht40PowerIncForPdadc, 16) 740 | ATH9K_POW_SM(ratesArray[rateHt40_1] + 741 ht40PowerIncForPdadc, 8) 742 | ATH9K_POW_SM(ratesArray[rateHt40_0] + 743 ht40PowerIncForPdadc, 0)); 744 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 745 ATH9K_POW_SM(ratesArray[rateHt40_7] + 746 ht40PowerIncForPdadc, 24) 747 | ATH9K_POW_SM(ratesArray[rateHt40_6] + 748 ht40PowerIncForPdadc, 16) 749 | ATH9K_POW_SM(ratesArray[rateHt40_5] + 750 ht40PowerIncForPdadc, 8) 751 | ATH9K_POW_SM(ratesArray[rateHt40_4] + 752 ht40PowerIncForPdadc, 0)); 753 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 754 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 755 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 756 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 757 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 758 } 759 760 REGWRITE_BUFFER_FLUSH(ah); 761 } 762 763 static void ath9k_hw_4k_set_gain(struct ath_hw *ah, 764 struct modal_eep_4k_header *pModal, 765 struct ar5416_eeprom_4k *eep, 766 u8 txRxAttenLocal) 767 { 768 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, 769 pModal->antCtrlChain[0]); 770 771 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), 772 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & 773 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 774 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 775 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 776 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 777 778 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 779 AR5416_EEP_MINOR_VER_3) { 780 txRxAttenLocal = pModal->txRxAttenCh[0]; 781 782 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 783 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 784 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 785 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 786 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 787 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 788 pModal->xatten2Margin[0]); 789 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 790 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 791 792 /* Set the block 1 value to block 0 value */ 793 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 794 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 795 pModal->bswMargin[0]); 796 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 797 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 798 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 799 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 800 pModal->xatten2Margin[0]); 801 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, 802 AR_PHY_GAIN_2GHZ_XATTEN2_DB, 803 pModal->xatten2Db[0]); 804 } 805 806 REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 807 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 808 REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 809 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 810 811 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 812 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 813 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, 814 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 815 } 816 817 /* 818 * Read EEPROM header info and program the device for correct operation 819 * given the channel value. 820 */ 821 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, 822 struct ath9k_channel *chan) 823 { 824 struct modal_eep_4k_header *pModal; 825 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 826 struct base_eep_header_4k *pBase = &eep->baseEepHeader; 827 u8 txRxAttenLocal; 828 u8 ob[5], db1[5], db2[5]; 829 u8 ant_div_control1, ant_div_control2; 830 u8 bb_desired_scale; 831 u32 regVal; 832 833 pModal = &eep->modalHeader; 834 txRxAttenLocal = 23; 835 836 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 837 838 /* Single chain for 4K EEPROM*/ 839 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal); 840 841 /* Initialize Ant Diversity settings from EEPROM */ 842 if (pModal->version >= 3) { 843 ant_div_control1 = pModal->antdiv_ctl1; 844 ant_div_control2 = pModal->antdiv_ctl2; 845 846 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 847 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); 848 849 regVal |= SM(ant_div_control1, 850 AR_PHY_9285_ANT_DIV_CTL); 851 regVal |= SM(ant_div_control2, 852 AR_PHY_9285_ANT_DIV_ALT_LNACONF); 853 regVal |= SM((ant_div_control2 >> 2), 854 AR_PHY_9285_ANT_DIV_MAIN_LNACONF); 855 regVal |= SM((ant_div_control1 >> 1), 856 AR_PHY_9285_ANT_DIV_ALT_GAINTB); 857 regVal |= SM((ant_div_control1 >> 2), 858 AR_PHY_9285_ANT_DIV_MAIN_GAINTB); 859 860 861 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); 862 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); 863 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); 864 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 865 regVal |= SM((ant_div_control1 >> 3), 866 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 867 868 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); 869 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); 870 } 871 872 if (pModal->version >= 2) { 873 ob[0] = pModal->ob_0; 874 ob[1] = pModal->ob_1; 875 ob[2] = pModal->ob_2; 876 ob[3] = pModal->ob_3; 877 ob[4] = pModal->ob_4; 878 879 db1[0] = pModal->db1_0; 880 db1[1] = pModal->db1_1; 881 db1[2] = pModal->db1_2; 882 db1[3] = pModal->db1_3; 883 db1[4] = pModal->db1_4; 884 885 db2[0] = pModal->db2_0; 886 db2[1] = pModal->db2_1; 887 db2[2] = pModal->db2_2; 888 db2[3] = pModal->db2_3; 889 db2[4] = pModal->db2_4; 890 } else if (pModal->version == 1) { 891 ob[0] = pModal->ob_0; 892 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; 893 db1[0] = pModal->db1_0; 894 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; 895 db2[0] = pModal->db2_0; 896 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; 897 } else { 898 int i; 899 900 for (i = 0; i < 5; i++) { 901 ob[i] = pModal->ob_0; 902 db1[i] = pModal->db1_0; 903 db2[i] = pModal->db1_0; 904 } 905 } 906 907 if (AR_SREV_9271(ah)) { 908 ath9k_hw_analog_shift_rmw(ah, 909 AR9285_AN_RF2G3, 910 AR9271_AN_RF2G3_OB_cck, 911 AR9271_AN_RF2G3_OB_cck_S, 912 ob[0]); 913 ath9k_hw_analog_shift_rmw(ah, 914 AR9285_AN_RF2G3, 915 AR9271_AN_RF2G3_OB_psk, 916 AR9271_AN_RF2G3_OB_psk_S, 917 ob[1]); 918 ath9k_hw_analog_shift_rmw(ah, 919 AR9285_AN_RF2G3, 920 AR9271_AN_RF2G3_OB_qam, 921 AR9271_AN_RF2G3_OB_qam_S, 922 ob[2]); 923 ath9k_hw_analog_shift_rmw(ah, 924 AR9285_AN_RF2G3, 925 AR9271_AN_RF2G3_DB_1, 926 AR9271_AN_RF2G3_DB_1_S, 927 db1[0]); 928 ath9k_hw_analog_shift_rmw(ah, 929 AR9285_AN_RF2G4, 930 AR9271_AN_RF2G4_DB_2, 931 AR9271_AN_RF2G4_DB_2_S, 932 db2[0]); 933 } else { 934 ath9k_hw_analog_shift_rmw(ah, 935 AR9285_AN_RF2G3, 936 AR9285_AN_RF2G3_OB_0, 937 AR9285_AN_RF2G3_OB_0_S, 938 ob[0]); 939 ath9k_hw_analog_shift_rmw(ah, 940 AR9285_AN_RF2G3, 941 AR9285_AN_RF2G3_OB_1, 942 AR9285_AN_RF2G3_OB_1_S, 943 ob[1]); 944 ath9k_hw_analog_shift_rmw(ah, 945 AR9285_AN_RF2G3, 946 AR9285_AN_RF2G3_OB_2, 947 AR9285_AN_RF2G3_OB_2_S, 948 ob[2]); 949 ath9k_hw_analog_shift_rmw(ah, 950 AR9285_AN_RF2G3, 951 AR9285_AN_RF2G3_OB_3, 952 AR9285_AN_RF2G3_OB_3_S, 953 ob[3]); 954 ath9k_hw_analog_shift_rmw(ah, 955 AR9285_AN_RF2G3, 956 AR9285_AN_RF2G3_OB_4, 957 AR9285_AN_RF2G3_OB_4_S, 958 ob[4]); 959 960 ath9k_hw_analog_shift_rmw(ah, 961 AR9285_AN_RF2G3, 962 AR9285_AN_RF2G3_DB1_0, 963 AR9285_AN_RF2G3_DB1_0_S, 964 db1[0]); 965 ath9k_hw_analog_shift_rmw(ah, 966 AR9285_AN_RF2G3, 967 AR9285_AN_RF2G3_DB1_1, 968 AR9285_AN_RF2G3_DB1_1_S, 969 db1[1]); 970 ath9k_hw_analog_shift_rmw(ah, 971 AR9285_AN_RF2G3, 972 AR9285_AN_RF2G3_DB1_2, 973 AR9285_AN_RF2G3_DB1_2_S, 974 db1[2]); 975 ath9k_hw_analog_shift_rmw(ah, 976 AR9285_AN_RF2G4, 977 AR9285_AN_RF2G4_DB1_3, 978 AR9285_AN_RF2G4_DB1_3_S, 979 db1[3]); 980 ath9k_hw_analog_shift_rmw(ah, 981 AR9285_AN_RF2G4, 982 AR9285_AN_RF2G4_DB1_4, 983 AR9285_AN_RF2G4_DB1_4_S, db1[4]); 984 985 ath9k_hw_analog_shift_rmw(ah, 986 AR9285_AN_RF2G4, 987 AR9285_AN_RF2G4_DB2_0, 988 AR9285_AN_RF2G4_DB2_0_S, 989 db2[0]); 990 ath9k_hw_analog_shift_rmw(ah, 991 AR9285_AN_RF2G4, 992 AR9285_AN_RF2G4_DB2_1, 993 AR9285_AN_RF2G4_DB2_1_S, 994 db2[1]); 995 ath9k_hw_analog_shift_rmw(ah, 996 AR9285_AN_RF2G4, 997 AR9285_AN_RF2G4_DB2_2, 998 AR9285_AN_RF2G4_DB2_2_S, 999 db2[2]); 1000 ath9k_hw_analog_shift_rmw(ah, 1001 AR9285_AN_RF2G4, 1002 AR9285_AN_RF2G4_DB2_3, 1003 AR9285_AN_RF2G4_DB2_3_S, 1004 db2[3]); 1005 ath9k_hw_analog_shift_rmw(ah, 1006 AR9285_AN_RF2G4, 1007 AR9285_AN_RF2G4_DB2_4, 1008 AR9285_AN_RF2G4_DB2_4_S, 1009 db2[4]); 1010 } 1011 1012 1013 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 1014 pModal->switchSettling); 1015 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, 1016 pModal->adcDesiredSize); 1017 1018 REG_WRITE(ah, AR_PHY_RF_CTL4, 1019 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | 1020 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | 1021 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | 1022 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1023 1024 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1025 pModal->txEndToRxOn); 1026 1027 if (AR_SREV_9271_10(ah)) 1028 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1029 pModal->txEndToRxOn); 1030 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1031 pModal->thresh62); 1032 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1033 pModal->thresh62); 1034 1035 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1036 AR5416_EEP_MINOR_VER_2) { 1037 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, 1038 pModal->txFrameToDataStart); 1039 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, 1040 pModal->txFrameToPaOn); 1041 } 1042 1043 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1044 AR5416_EEP_MINOR_VER_3) { 1045 if (IS_CHAN_HT40(chan)) 1046 REG_RMW_FIELD(ah, AR_PHY_SETTLING, 1047 AR_PHY_SETTLING_SWITCH, 1048 pModal->swSettleHt40); 1049 } 1050 1051 bb_desired_scale = (pModal->bb_scale_smrt_antenna & 1052 EEP_4K_BB_DESIRED_SCALE_MASK); 1053 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) { 1054 u32 pwrctrl, mask, clr; 1055 1056 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25); 1057 pwrctrl = mask * bb_desired_scale; 1058 clr = mask * 0x1f; 1059 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); 1060 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); 1061 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); 1062 1063 mask = BIT(0)|BIT(5)|BIT(15); 1064 pwrctrl = mask * bb_desired_scale; 1065 clr = mask * 0x1f; 1066 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); 1067 1068 mask = BIT(0)|BIT(5); 1069 pwrctrl = mask * bb_desired_scale; 1070 clr = mask * 0x1f; 1071 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); 1072 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); 1073 } 1074 } 1075 1076 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 1077 { 1078 #define EEP_MAP4K_SPURCHAN \ 1079 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) 1080 struct ath_common *common = ath9k_hw_common(ah); 1081 1082 u16 spur_val = AR_NO_SPUR; 1083 1084 ath_dbg(common, ATH_DBG_ANI, 1085 "Getting spur idx:%d is2Ghz:%d val:%x\n", 1086 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1087 1088 switch (ah->config.spurmode) { 1089 case SPUR_DISABLE: 1090 break; 1091 case SPUR_ENABLE_IOCTL: 1092 spur_val = ah->config.spurchans[i][is2GHz]; 1093 ath_dbg(common, ATH_DBG_ANI, 1094 "Getting spur val from new loc. %d\n", spur_val); 1095 break; 1096 case SPUR_ENABLE_EEPROM: 1097 spur_val = EEP_MAP4K_SPURCHAN; 1098 break; 1099 } 1100 1101 return spur_val; 1102 1103 #undef EEP_MAP4K_SPURCHAN 1104 } 1105 1106 const struct eeprom_ops eep_4k_ops = { 1107 .check_eeprom = ath9k_hw_4k_check_eeprom, 1108 .get_eeprom = ath9k_hw_4k_get_eeprom, 1109 .fill_eeprom = ath9k_hw_4k_fill_eeprom, 1110 .dump_eeprom = ath9k_hw_4k_dump_eeprom, 1111 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, 1112 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, 1113 .set_board_values = ath9k_hw_4k_set_board_values, 1114 .set_txpower = ath9k_hw_4k_set_txpower, 1115 .get_spur_channel = ath9k_hw_4k_get_spur_channel 1116 }; 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