1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef DEBUG_H 18 #define DEBUG_H 19 20 #include "hw.h" 21 #include "rc.h" 22 23 struct ath_txq; 24 struct ath_buf; 25 26 #ifdef CONFIG_ATH9K_DEBUGFS 27 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 28 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++ 29 #else 30 #define TX_STAT_INC(q, c) do { } while (0) 31 #define RESET_STAT_INC(sc, type) do { } while (0) 32 #endif 33 34 #ifdef CONFIG_ATH9K_DEBUGFS 35 36 /** 37 * struct ath_interrupt_stats - Contains statistics about interrupts 38 * @total: Total no. of interrupts generated so far 39 * @rxok: RX with no errors 40 * @rxlp: RX with low priority RX 41 * @rxhp: RX with high priority, uapsd only 42 * @rxeol: RX with no more RXDESC available 43 * @rxorn: RX FIFO overrun 44 * @txok: TX completed at the requested rate 45 * @txurn: TX FIFO underrun 46 * @mib: MIB regs reaching its threshold 47 * @rxphyerr: RX with phy errors 48 * @rx_keycache_miss: RX with key cache misses 49 * @swba: Software Beacon Alert 50 * @bmiss: Beacon Miss 51 * @bnr: Beacon Not Ready 52 * @cst: Carrier Sense TImeout 53 * @gtt: Global TX Timeout 54 * @tim: RX beacon TIM occurrence 55 * @cabend: RX End of CAB traffic 56 * @dtimsync: DTIM sync lossage 57 * @dtim: RX Beacon with DTIM 58 * @bb_watchdog: Baseband watchdog 59 * @tsfoor: TSF out of range, indicates that the corrected TSF received 60 * from a beacon differs from the PCU's internal TSF by more than a 61 * (programmable) threshold 62 */ 63 struct ath_interrupt_stats { 64 u32 total; 65 u32 rxok; 66 u32 rxlp; 67 u32 rxhp; 68 u32 rxeol; 69 u32 rxorn; 70 u32 txok; 71 u32 txeol; 72 u32 txurn; 73 u32 mib; 74 u32 rxphyerr; 75 u32 rx_keycache_miss; 76 u32 swba; 77 u32 bmiss; 78 u32 bnr; 79 u32 cst; 80 u32 gtt; 81 u32 tim; 82 u32 cabend; 83 u32 dtimsync; 84 u32 dtim; 85 u32 bb_watchdog; 86 u32 tsfoor; 87 }; 88 89 /** 90 * struct ath_tx_stats - Statistics about TX 91 * @tx_pkts_all: No. of total frames transmitted, including ones that 92 may have had errors. 93 * @tx_bytes_all: No. of total bytes transmitted, including ones that 94 may have had errors. 95 * @queued: Total MPDUs (non-aggr) queued 96 * @completed: Total MPDUs (non-aggr) completed 97 * @a_aggr: Total no. of aggregates queued 98 * @a_queued_hw: Total AMPDUs queued to hardware 99 * @a_queued_sw: Total AMPDUs queued to software queues 100 * @a_completed: Total AMPDUs completed 101 * @a_retries: No. of AMPDUs retried (SW) 102 * @a_xretries: No. of AMPDUs dropped due to xretries 103 * @fifo_underrun: FIFO underrun occurrences 104 Valid only for: 105 - non-aggregate condition. 106 - first packet of aggregate. 107 * @xtxop: No. of frames filtered because of TXOP limit 108 * @timer_exp: Transmit timer expiry 109 * @desc_cfg_err: Descriptor configuration errors 110 * @data_urn: TX data underrun errors 111 * @delim_urn: TX delimiter underrun errors 112 * @puttxbuf: Number of times hardware was given txbuf to write. 113 * @txstart: Number of times hardware was told to start tx. 114 * @txprocdesc: Number of times tx descriptor was processed 115 */ 116 struct ath_tx_stats { 117 u32 tx_pkts_all; 118 u32 tx_bytes_all; 119 u32 queued; 120 u32 completed; 121 u32 xretries; 122 u32 a_aggr; 123 u32 a_queued_hw; 124 u32 a_queued_sw; 125 u32 a_completed; 126 u32 a_retries; 127 u32 a_xretries; 128 u32 fifo_underrun; 129 u32 xtxop; 130 u32 timer_exp; 131 u32 desc_cfg_err; 132 u32 data_underrun; 133 u32 delim_underrun; 134 u32 puttxbuf; 135 u32 txstart; 136 u32 txprocdesc; 137 }; 138 139 /** 140 * struct ath_rx_stats - RX Statistics 141 * @rx_pkts_all: No. of total frames received, including ones that 142 may have had errors. 143 * @rx_bytes_all: No. of total bytes received, including ones that 144 may have had errors. 145 * @crc_err: No. of frames with incorrect CRC value 146 * @decrypt_crc_err: No. of frames whose CRC check failed after 147 decryption process completed 148 * @phy_err: No. of frames whose reception failed because the PHY 149 encountered an error 150 * @mic_err: No. of frames with incorrect TKIP MIC verification failure 151 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections 152 * @post_delim_crc_err: Post-Frame delimiter CRC error detections 153 * @decrypt_busy_err: Decryption interruptions counter 154 * @phy_err_stats: Individual PHY error statistics 155 */ 156 struct ath_rx_stats { 157 u32 rx_pkts_all; 158 u32 rx_bytes_all; 159 u32 crc_err; 160 u32 decrypt_crc_err; 161 u32 phy_err; 162 u32 mic_err; 163 u32 pre_delim_crc_err; 164 u32 post_delim_crc_err; 165 u32 decrypt_busy_err; 166 u32 phy_err_stats[ATH9K_PHYERR_MAX]; 167 int8_t rs_rssi_ctl0; 168 int8_t rs_rssi_ctl1; 169 int8_t rs_rssi_ctl2; 170 int8_t rs_rssi_ext0; 171 int8_t rs_rssi_ext1; 172 int8_t rs_rssi_ext2; 173 u8 rs_antenna; 174 }; 175 176 enum ath_reset_type { 177 RESET_TYPE_BB_HANG, 178 RESET_TYPE_BB_WATCHDOG, 179 RESET_TYPE_FATAL_INT, 180 RESET_TYPE_TX_ERROR, 181 RESET_TYPE_TX_HANG, 182 RESET_TYPE_PLL_HANG, 183 __RESET_TYPE_MAX 184 }; 185 186 struct ath_stats { 187 struct ath_interrupt_stats istats; 188 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 189 struct ath_rx_stats rxstats; 190 u32 reset[__RESET_TYPE_MAX]; 191 }; 192 193 #define ATH_DBG_MAX_SAMPLES 10 194 struct ath_dbg_bb_mac_samp { 195 u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS]; 196 u32 pcu_obs, pcu_cr, noise; 197 struct { 198 u64 jiffies; 199 int8_t rssi_ctl0; 200 int8_t rssi_ctl1; 201 int8_t rssi_ctl2; 202 int8_t rssi_ext0; 203 int8_t rssi_ext1; 204 int8_t rssi_ext2; 205 int8_t rssi; 206 bool isok; 207 u8 rts_fail_cnt; 208 u8 data_fail_cnt; 209 u8 rateindex; 210 u8 qid; 211 u8 tid; 212 u32 ba_low; 213 u32 ba_high; 214 } ts[ATH_DBG_MAX_SAMPLES]; 215 struct { 216 u64 jiffies; 217 int8_t rssi_ctl0; 218 int8_t rssi_ctl1; 219 int8_t rssi_ctl2; 220 int8_t rssi_ext0; 221 int8_t rssi_ext1; 222 int8_t rssi_ext2; 223 int8_t rssi; 224 bool is_mybeacon; 225 u8 antenna; 226 u8 rate; 227 } rs[ATH_DBG_MAX_SAMPLES]; 228 struct ath_cycle_counters cc; 229 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 230 }; 231 232 struct ath9k_debug { 233 struct dentry *debugfs_phy; 234 u32 regidx; 235 struct ath_stats stats; 236 spinlock_t samp_lock; 237 struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES]; 238 u8 sampidx; 239 u8 tsidx; 240 u8 rsidx; 241 }; 242 243 int ath9k_init_debug(struct ath_hw *ah); 244 245 void ath9k_debug_samp_bb_mac(struct ath_softc *sc); 246 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 247 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, 248 struct ath_tx_status *ts, struct ath_txq *txq, 249 unsigned int flags); 250 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); 251 252 #else 253 254 static inline int ath9k_init_debug(struct ath_hw *ah) 255 { 256 return 0; 257 } 258 259 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc) 260 { 261 } 262 263 static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 264 enum ath9k_int status) 265 { 266 } 267 268 static inline void ath_debug_stat_tx(struct ath_softc *sc, 269 struct ath_buf *bf, 270 struct ath_tx_status *ts, 271 struct ath_txq *txq, 272 unsigned int flags) 273 { 274 } 275 276 static inline void ath_debug_stat_rx(struct ath_softc *sc, 277 struct ath_rx_status *rs) 278 { 279 } 280 281 #endif /* CONFIG_ATH9K_DEBUGFS */ 282 283 #endif /* DEBUG_H */ 284