1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef DEBUG_H 18 #define DEBUG_H 19 20 #include "hw.h" 21 #include "rc.h" 22 23 struct ath_txq; 24 struct ath_buf; 25 26 #ifdef CONFIG_ATH9K_DEBUGFS 27 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 28 #else 29 #define TX_STAT_INC(q, c) do { } while (0) 30 #endif 31 32 #ifdef CONFIG_ATH9K_DEBUGFS 33 34 /** 35 * struct ath_interrupt_stats - Contains statistics about interrupts 36 * @total: Total no. of interrupts generated so far 37 * @rxok: RX with no errors 38 * @rxlp: RX with low priority RX 39 * @rxhp: RX with high priority, uapsd only 40 * @rxeol: RX with no more RXDESC available 41 * @rxorn: RX FIFO overrun 42 * @txok: TX completed at the requested rate 43 * @txurn: TX FIFO underrun 44 * @mib: MIB regs reaching its threshold 45 * @rxphyerr: RX with phy errors 46 * @rx_keycache_miss: RX with key cache misses 47 * @swba: Software Beacon Alert 48 * @bmiss: Beacon Miss 49 * @bnr: Beacon Not Ready 50 * @cst: Carrier Sense TImeout 51 * @gtt: Global TX Timeout 52 * @tim: RX beacon TIM occurrence 53 * @cabend: RX End of CAB traffic 54 * @dtimsync: DTIM sync lossage 55 * @dtim: RX Beacon with DTIM 56 * @bb_watchdog: Baseband watchdog 57 */ 58 struct ath_interrupt_stats { 59 u32 total; 60 u32 rxok; 61 u32 rxlp; 62 u32 rxhp; 63 u32 rxeol; 64 u32 rxorn; 65 u32 txok; 66 u32 txeol; 67 u32 txurn; 68 u32 mib; 69 u32 rxphyerr; 70 u32 rx_keycache_miss; 71 u32 swba; 72 u32 bmiss; 73 u32 bnr; 74 u32 cst; 75 u32 gtt; 76 u32 tim; 77 u32 cabend; 78 u32 dtimsync; 79 u32 dtim; 80 u32 bb_watchdog; 81 }; 82 83 struct ath_rc_stats { 84 u32 success; 85 u32 retries; 86 u32 xretries; 87 u8 per; 88 }; 89 90 /** 91 * struct ath_tx_stats - Statistics about TX 92 * @queued: Total MPDUs (non-aggr) queued 93 * @completed: Total MPDUs (non-aggr) completed 94 * @a_aggr: Total no. of aggregates queued 95 * @a_queued: Total AMPDUs queued 96 * @a_completed: Total AMPDUs completed 97 * @a_retries: No. of AMPDUs retried (SW) 98 * @a_xretries: No. of AMPDUs dropped due to xretries 99 * @fifo_underrun: FIFO underrun occurrences 100 Valid only for: 101 - non-aggregate condition. 102 - first packet of aggregate. 103 * @xtxop: No. of frames filtered because of TXOP limit 104 * @timer_exp: Transmit timer expiry 105 * @desc_cfg_err: Descriptor configuration errors 106 * @data_urn: TX data underrun errors 107 * @delim_urn: TX delimiter underrun errors 108 */ 109 struct ath_tx_stats { 110 u32 queued; 111 u32 completed; 112 u32 a_aggr; 113 u32 a_queued; 114 u32 a_completed; 115 u32 a_retries; 116 u32 a_xretries; 117 u32 fifo_underrun; 118 u32 xtxop; 119 u32 timer_exp; 120 u32 desc_cfg_err; 121 u32 data_underrun; 122 u32 delim_underrun; 123 }; 124 125 /** 126 * struct ath_rx_stats - RX Statistics 127 * @crc_err: No. of frames with incorrect CRC value 128 * @decrypt_crc_err: No. of frames whose CRC check failed after 129 decryption process completed 130 * @phy_err: No. of frames whose reception failed because the PHY 131 encountered an error 132 * @mic_err: No. of frames with incorrect TKIP MIC verification failure 133 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections 134 * @post_delim_crc_err: Post-Frame delimiter CRC error detections 135 * @decrypt_busy_err: Decryption interruptions counter 136 * @phy_err_stats: Individual PHY error statistics 137 */ 138 struct ath_rx_stats { 139 u32 crc_err; 140 u32 decrypt_crc_err; 141 u32 phy_err; 142 u32 mic_err; 143 u32 pre_delim_crc_err; 144 u32 post_delim_crc_err; 145 u32 decrypt_busy_err; 146 u32 phy_err_stats[ATH9K_PHYERR_MAX]; 147 }; 148 149 struct ath_stats { 150 struct ath_interrupt_stats istats; 151 struct ath_rc_stats rcstats[RATE_TABLE_SIZE]; 152 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 153 struct ath_rx_stats rxstats; 154 }; 155 156 struct ath9k_debug { 157 struct dentry *debugfs_phy; 158 u32 regidx; 159 struct ath_stats stats; 160 }; 161 162 int ath9k_init_debug(struct ath_hw *ah); 163 void ath9k_exit_debug(struct ath_hw *ah); 164 165 int ath9k_debug_create_root(void); 166 void ath9k_debug_remove_root(void); 167 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 168 void ath_debug_stat_rc(struct ath_softc *sc, int final_rate); 169 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq, 170 struct ath_buf *bf, struct ath_tx_status *ts); 171 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); 172 void ath_debug_stat_retries(struct ath_softc *sc, int rix, 173 int xretries, int retries, u8 per); 174 175 #else 176 177 static inline int ath9k_init_debug(struct ath_hw *ah) 178 { 179 return 0; 180 } 181 182 static inline void ath9k_exit_debug(struct ath_hw *ah) 183 { 184 } 185 186 static inline int ath9k_debug_create_root(void) 187 { 188 return 0; 189 } 190 191 static inline void ath9k_debug_remove_root(void) 192 { 193 } 194 195 static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 196 enum ath9k_int status) 197 { 198 } 199 200 static inline void ath_debug_stat_rc(struct ath_softc *sc, 201 int final_rate) 202 { 203 } 204 205 static inline void ath_debug_stat_tx(struct ath_softc *sc, 206 struct ath_txq *txq, 207 struct ath_buf *bf, 208 struct ath_tx_status *ts) 209 { 210 } 211 212 static inline void ath_debug_stat_rx(struct ath_softc *sc, 213 struct ath_rx_status *rs) 214 { 215 } 216 217 static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix, 218 int xretries, int retries, u8 per) 219 { 220 } 221 222 #endif /* CONFIG_ATH9K_DEBUGFS */ 223 224 #endif /* DEBUG_H */ 225