1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef DEBUG_H 18 #define DEBUG_H 19 20 #include "hw.h" 21 #include "rc.h" 22 23 struct ath_txq; 24 struct ath_buf; 25 26 #ifdef CONFIG_ATH9K_DEBUGFS 27 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 28 #else 29 #define TX_STAT_INC(q, c) do { } while (0) 30 #endif 31 32 #ifdef CONFIG_ATH9K_DEBUGFS 33 34 /** 35 * struct ath_interrupt_stats - Contains statistics about interrupts 36 * @total: Total no. of interrupts generated so far 37 * @rxok: RX with no errors 38 * @rxlp: RX with low priority RX 39 * @rxhp: RX with high priority, uapsd only 40 * @rxeol: RX with no more RXDESC available 41 * @rxorn: RX FIFO overrun 42 * @txok: TX completed at the requested rate 43 * @txurn: TX FIFO underrun 44 * @mib: MIB regs reaching its threshold 45 * @rxphyerr: RX with phy errors 46 * @rx_keycache_miss: RX with key cache misses 47 * @swba: Software Beacon Alert 48 * @bmiss: Beacon Miss 49 * @bnr: Beacon Not Ready 50 * @cst: Carrier Sense TImeout 51 * @gtt: Global TX Timeout 52 * @tim: RX beacon TIM occurrence 53 * @cabend: RX End of CAB traffic 54 * @dtimsync: DTIM sync lossage 55 * @dtim: RX Beacon with DTIM 56 * @bb_watchdog: Baseband watchdog 57 * @tsfoor: TSF out of range, indicates that the corrected TSF received 58 * from a beacon differs from the PCU's internal TSF by more than a 59 * (programmable) threshold 60 */ 61 struct ath_interrupt_stats { 62 u32 total; 63 u32 rxok; 64 u32 rxlp; 65 u32 rxhp; 66 u32 rxeol; 67 u32 rxorn; 68 u32 txok; 69 u32 txeol; 70 u32 txurn; 71 u32 mib; 72 u32 rxphyerr; 73 u32 rx_keycache_miss; 74 u32 swba; 75 u32 bmiss; 76 u32 bnr; 77 u32 cst; 78 u32 gtt; 79 u32 tim; 80 u32 cabend; 81 u32 dtimsync; 82 u32 dtim; 83 u32 bb_watchdog; 84 u32 tsfoor; 85 }; 86 87 /** 88 * struct ath_tx_stats - Statistics about TX 89 * @tx_pkts_all: No. of total frames transmitted, including ones that 90 may have had errors. 91 * @tx_bytes_all: No. of total bytes transmitted, including ones that 92 may have had errors. 93 * @queued: Total MPDUs (non-aggr) queued 94 * @completed: Total MPDUs (non-aggr) completed 95 * @a_aggr: Total no. of aggregates queued 96 * @a_queued_hw: Total AMPDUs queued to hardware 97 * @a_queued_sw: Total AMPDUs queued to software queues 98 * @a_completed: Total AMPDUs completed 99 * @a_retries: No. of AMPDUs retried (SW) 100 * @a_xretries: No. of AMPDUs dropped due to xretries 101 * @fifo_underrun: FIFO underrun occurrences 102 Valid only for: 103 - non-aggregate condition. 104 - first packet of aggregate. 105 * @xtxop: No. of frames filtered because of TXOP limit 106 * @timer_exp: Transmit timer expiry 107 * @desc_cfg_err: Descriptor configuration errors 108 * @data_urn: TX data underrun errors 109 * @delim_urn: TX delimiter underrun errors 110 * @puttxbuf: Number of times hardware was given txbuf to write. 111 * @txstart: Number of times hardware was told to start tx. 112 * @txprocdesc: Number of times tx descriptor was processed 113 */ 114 struct ath_tx_stats { 115 u32 tx_pkts_all; 116 u32 tx_bytes_all; 117 u32 queued; 118 u32 completed; 119 u32 a_aggr; 120 u32 a_queued_hw; 121 u32 a_queued_sw; 122 u32 a_completed; 123 u32 a_retries; 124 u32 a_xretries; 125 u32 fifo_underrun; 126 u32 xtxop; 127 u32 timer_exp; 128 u32 desc_cfg_err; 129 u32 data_underrun; 130 u32 delim_underrun; 131 u32 puttxbuf; 132 u32 txstart; 133 u32 txprocdesc; 134 }; 135 136 /** 137 * struct ath_rx_stats - RX Statistics 138 * @rx_pkts_all: No. of total frames received, including ones that 139 may have had errors. 140 * @rx_bytes_all: No. of total bytes received, including ones that 141 may have had errors. 142 * @crc_err: No. of frames with incorrect CRC value 143 * @decrypt_crc_err: No. of frames whose CRC check failed after 144 decryption process completed 145 * @phy_err: No. of frames whose reception failed because the PHY 146 encountered an error 147 * @mic_err: No. of frames with incorrect TKIP MIC verification failure 148 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections 149 * @post_delim_crc_err: Post-Frame delimiter CRC error detections 150 * @decrypt_busy_err: Decryption interruptions counter 151 * @phy_err_stats: Individual PHY error statistics 152 */ 153 struct ath_rx_stats { 154 u32 rx_pkts_all; 155 u32 rx_bytes_all; 156 u32 crc_err; 157 u32 decrypt_crc_err; 158 u32 phy_err; 159 u32 mic_err; 160 u32 pre_delim_crc_err; 161 u32 post_delim_crc_err; 162 u32 decrypt_busy_err; 163 u32 phy_err_stats[ATH9K_PHYERR_MAX]; 164 int8_t rs_rssi_ctl0; 165 int8_t rs_rssi_ctl1; 166 int8_t rs_rssi_ctl2; 167 int8_t rs_rssi_ext0; 168 int8_t rs_rssi_ext1; 169 int8_t rs_rssi_ext2; 170 u8 rs_antenna; 171 }; 172 173 struct ath_stats { 174 struct ath_interrupt_stats istats; 175 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 176 struct ath_rx_stats rxstats; 177 }; 178 179 struct ath9k_debug { 180 struct dentry *debugfs_phy; 181 u32 regidx; 182 struct ath_stats stats; 183 }; 184 185 int ath9k_init_debug(struct ath_hw *ah); 186 187 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 188 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, 189 struct ath_tx_status *ts, struct ath_txq *txq); 190 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); 191 192 #else 193 194 static inline int ath9k_init_debug(struct ath_hw *ah) 195 { 196 return 0; 197 } 198 199 static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 200 enum ath9k_int status) 201 { 202 } 203 204 static inline void ath_debug_stat_tx(struct ath_softc *sc, 205 struct ath_buf *bf, 206 struct ath_tx_status *ts, 207 struct ath_txq *txq) 208 { 209 } 210 211 static inline void ath_debug_stat_rx(struct ath_softc *sc, 212 struct ath_rx_status *rs) 213 { 214 } 215 216 #endif /* CONFIG_ATH9K_DEBUGFS */ 217 218 #endif /* DEBUG_H */ 219