1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 31 /* 32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 33 * should rely on this file or its contents. 34 */ 35 36 struct ath_node; 37 38 /* Macro to expand scalars to 64-bit objects */ 39 40 #define ito64(x) (sizeof(x) == 1) ? \ 41 (((unsigned long long int)(x)) & (0xff)) : \ 42 (sizeof(x) == 2) ? \ 43 (((unsigned long long int)(x)) & 0xffff) : \ 44 ((sizeof(x) == 4) ? \ 45 (((unsigned long long int)(x)) & 0xffffffff) : \ 46 (unsigned long long int)(x)) 47 48 /* increment with wrap-around */ 49 #define INCR(_l, _sz) do { \ 50 (_l)++; \ 51 (_l) &= ((_sz) - 1); \ 52 } while (0) 53 54 /* decrement with wrap-around */ 55 #define DECR(_l, _sz) do { \ 56 (_l)--; \ 57 (_l) &= ((_sz) - 1); \ 58 } while (0) 59 60 #define TSF_TO_TU(_h,_l) \ 61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 62 63 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 64 65 struct ath_config { 66 u16 txpowlimit; 67 u8 cabqReadytime; 68 }; 69 70 /*************************/ 71 /* Descriptor Management */ 72 /*************************/ 73 74 #define ATH_TXBUF_RESET(_bf) do { \ 75 (_bf)->bf_stale = false; \ 76 (_bf)->bf_lastbf = NULL; \ 77 (_bf)->bf_next = NULL; \ 78 memset(&((_bf)->bf_state), 0, \ 79 sizeof(struct ath_buf_state)); \ 80 } while (0) 81 82 #define ATH_RXBUF_RESET(_bf) do { \ 83 (_bf)->bf_stale = false; \ 84 } while (0) 85 86 /** 87 * enum buffer_type - Buffer type flags 88 * 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 */ 93 enum buffer_type { 94 BUF_AMPDU = BIT(0), 95 BUF_AGGR = BIT(1), 96 }; 97 98 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 99 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 100 101 #define ATH_TXSTATUS_RING_SIZE 512 102 103 #define DS2PHYS(_dd, _ds) \ 104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 107 108 struct ath_descdma { 109 void *dd_desc; 110 dma_addr_t dd_desc_paddr; 111 u32 dd_desc_len; 112 struct ath_buf *dd_bufptr; 113 }; 114 115 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 116 struct list_head *head, const char *name, 117 int nbuf, int ndesc, bool is_tx); 118 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 119 struct list_head *head); 120 121 /***********/ 122 /* RX / TX */ 123 /***********/ 124 125 #define ATH_RXBUF 512 126 #define ATH_TXBUF 512 127 #define ATH_TXBUF_RESERVE 5 128 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 129 #define ATH_TXMAXTRY 13 130 131 #define TID_TO_WME_AC(_tid) \ 132 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 133 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 134 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 135 WME_AC_VO) 136 137 #define ATH_AGGR_DELIM_SZ 4 138 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 139 /* number of delimiters for encryption padding */ 140 #define ATH_AGGR_ENCRYPTDELIM 10 141 /* minimum h/w qdepth to be sustained to maximize aggregation */ 142 #define ATH_AGGR_MIN_QDEPTH 2 143 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 144 145 #define IEEE80211_SEQ_SEQ_SHIFT 4 146 #define IEEE80211_SEQ_MAX 4096 147 #define IEEE80211_WEP_IVLEN 3 148 #define IEEE80211_WEP_KIDLEN 1 149 #define IEEE80211_WEP_CRCLEN 4 150 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 151 (IEEE80211_WEP_IVLEN + \ 152 IEEE80211_WEP_KIDLEN + \ 153 IEEE80211_WEP_CRCLEN)) 154 155 /* return whether a bit at index _n in bitmap _bm is set 156 * _sz is the size of the bitmap */ 157 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 158 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 159 160 /* return block-ack bitmap index given sequence and starting sequence */ 161 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 162 163 /* return the seqno for _start + _offset */ 164 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 165 166 /* returns delimiter padding required given the packet length */ 167 #define ATH_AGGR_GET_NDELIM(_len) \ 168 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 169 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 170 171 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 172 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 173 174 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 175 176 #define ATH_TX_COMPLETE_POLL_INT 1000 177 178 enum ATH_AGGR_STATUS { 179 ATH_AGGR_DONE, 180 ATH_AGGR_BAW_CLOSED, 181 ATH_AGGR_LIMITED, 182 }; 183 184 #define ATH_TXFIFO_DEPTH 8 185 struct ath_txq { 186 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 187 u32 axq_qnum; /* ath9k hardware queue number */ 188 void *axq_link; 189 struct list_head axq_q; 190 spinlock_t axq_lock; 191 u32 axq_depth; 192 u32 axq_ampdu_depth; 193 bool stopped; 194 bool axq_tx_inprogress; 195 struct list_head axq_acq; 196 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 197 u8 txq_headidx; 198 u8 txq_tailidx; 199 int pending_frames; 200 struct sk_buff_head complete_q; 201 }; 202 203 struct ath_atx_ac { 204 struct ath_txq *txq; 205 int sched; 206 struct list_head list; 207 struct list_head tid_q; 208 bool clear_ps_filter; 209 }; 210 211 struct ath_frame_info { 212 struct ath_buf *bf; 213 int framelen; 214 enum ath9k_key_type keytype; 215 u8 keyix; 216 u8 retries; 217 }; 218 219 struct ath_buf_state { 220 u8 bf_type; 221 u8 bfs_paprd; 222 u8 ndelim; 223 u16 seqno; 224 unsigned long bfs_paprd_timestamp; 225 }; 226 227 struct ath_buf { 228 struct list_head list; 229 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 230 an aggregate) */ 231 struct ath_buf *bf_next; /* next subframe in the aggregate */ 232 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 233 void *bf_desc; /* virtual addr of desc */ 234 dma_addr_t bf_daddr; /* physical addr of desc */ 235 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 236 bool bf_stale; 237 struct ath_buf_state bf_state; 238 }; 239 240 struct ath_atx_tid { 241 struct list_head list; 242 struct sk_buff_head buf_q; 243 struct ath_node *an; 244 struct ath_atx_ac *ac; 245 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 246 int bar_index; 247 u16 seq_start; 248 u16 seq_next; 249 u16 baw_size; 250 int tidno; 251 int baw_head; /* first un-acked tx buffer */ 252 int baw_tail; /* next unused tx buffer slot */ 253 int sched; 254 int paused; 255 u8 state; 256 }; 257 258 struct ath_node { 259 #ifdef CONFIG_ATH9K_DEBUGFS 260 struct list_head list; /* for sc->nodes */ 261 #endif 262 struct ieee80211_sta *sta; /* station struct we're part of */ 263 struct ieee80211_vif *vif; /* interface with which we're associated */ 264 struct ath_atx_tid tid[WME_NUM_TID]; 265 struct ath_atx_ac ac[WME_NUM_AC]; 266 int ps_key; 267 268 u16 maxampdu; 269 u8 mpdudensity; 270 271 bool sleeping; 272 }; 273 274 #define AGGR_CLEANUP BIT(1) 275 #define AGGR_ADDBA_COMPLETE BIT(2) 276 #define AGGR_ADDBA_PROGRESS BIT(3) 277 278 struct ath_tx_control { 279 struct ath_txq *txq; 280 struct ath_node *an; 281 u8 paprd; 282 }; 283 284 #define ATH_TX_ERROR 0x01 285 286 /** 287 * @txq_map: Index is mac80211 queue number. This is 288 * not necessarily the same as the hardware queue number 289 * (axq_qnum). 290 */ 291 struct ath_tx { 292 u16 seq_no; 293 u32 txqsetup; 294 spinlock_t txbuflock; 295 struct list_head txbuf; 296 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 297 struct ath_descdma txdma; 298 struct ath_txq *txq_map[WME_NUM_AC]; 299 }; 300 301 struct ath_rx_edma { 302 struct sk_buff_head rx_fifo; 303 u32 rx_fifo_hwsize; 304 }; 305 306 struct ath_rx { 307 u8 defant; 308 u8 rxotherant; 309 u32 *rxlink; 310 unsigned int rxfilter; 311 spinlock_t rxbuflock; 312 struct list_head rxbuf; 313 struct ath_descdma rxdma; 314 struct ath_buf *rx_bufptr; 315 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 316 317 struct sk_buff *frag; 318 }; 319 320 int ath_startrecv(struct ath_softc *sc); 321 bool ath_stoprecv(struct ath_softc *sc); 322 void ath_flushrecv(struct ath_softc *sc); 323 u32 ath_calcrxfilter(struct ath_softc *sc); 324 int ath_rx_init(struct ath_softc *sc, int nbufs); 325 void ath_rx_cleanup(struct ath_softc *sc); 326 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 327 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 328 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 329 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 330 void ath_draintxq(struct ath_softc *sc, 331 struct ath_txq *txq, bool retry_tx); 332 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 333 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 334 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 335 int ath_tx_init(struct ath_softc *sc, int nbufs); 336 void ath_tx_cleanup(struct ath_softc *sc); 337 int ath_txq_update(struct ath_softc *sc, int qnum, 338 struct ath9k_tx_queue_info *q); 339 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 340 struct ath_tx_control *txctl); 341 void ath_tx_tasklet(struct ath_softc *sc); 342 void ath_tx_edma_tasklet(struct ath_softc *sc); 343 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 344 u16 tid, u16 *ssn); 345 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 346 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 347 348 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 349 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 350 struct ath_node *an); 351 352 /********/ 353 /* VIFs */ 354 /********/ 355 356 struct ath_vif { 357 int av_bslot; 358 bool is_bslot_active, primary_sta_vif; 359 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 360 struct ath_buf *av_bcbuf; 361 }; 362 363 /*******************/ 364 /* Beacon Handling */ 365 /*******************/ 366 367 /* 368 * Regardless of the number of beacons we stagger, (i.e. regardless of the 369 * number of BSSIDs) if a given beacon does not go out even after waiting this 370 * number of beacon intervals, the game's up. 371 */ 372 #define BSTUCK_THRESH 9 373 #define ATH_BCBUF 8 374 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 375 #define ATH_DEFAULT_BMISS_LIMIT 10 376 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 377 378 struct ath_beacon_config { 379 int beacon_interval; 380 u16 listen_interval; 381 u16 dtim_period; 382 u16 bmiss_timeout; 383 u8 dtim_count; 384 }; 385 386 struct ath_beacon { 387 enum { 388 OK, /* no change needed */ 389 UPDATE, /* update pending */ 390 COMMIT /* beacon sent, commit change */ 391 } updateslot; /* slot time update fsm */ 392 393 u32 beaconq; 394 u32 bmisscnt; 395 u32 ast_be_xmit; 396 u32 bc_tstamp; 397 struct ieee80211_vif *bslot[ATH_BCBUF]; 398 int slottime; 399 int slotupdate; 400 struct ath9k_tx_queue_info beacon_qi; 401 struct ath_descdma bdma; 402 struct ath_txq *cabq; 403 struct list_head bbuf; 404 405 bool tx_processed; 406 bool tx_last; 407 }; 408 409 void ath_beacon_tasklet(unsigned long data); 410 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 411 int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif); 412 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 413 int ath_beaconq_config(struct ath_softc *sc); 414 void ath_set_beacon(struct ath_softc *sc); 415 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); 416 417 /*******/ 418 /* ANI */ 419 /*******/ 420 421 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 422 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 423 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 424 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 425 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 426 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 427 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 428 429 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 430 431 void ath_reset_work(struct work_struct *work); 432 void ath_hw_check(struct work_struct *work); 433 void ath_hw_pll_work(struct work_struct *work); 434 void ath_rx_poll(unsigned long data); 435 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); 436 void ath_paprd_calibrate(struct work_struct *work); 437 void ath_ani_calibrate(unsigned long data); 438 void ath_start_ani(struct ath_common *common); 439 440 /**********/ 441 /* BTCOEX */ 442 /**********/ 443 444 struct ath_btcoex { 445 bool hw_timer_enabled; 446 spinlock_t btcoex_lock; 447 struct timer_list period_timer; /* Timer for BT period */ 448 u32 bt_priority_cnt; 449 unsigned long bt_priority_time; 450 int bt_stomp_type; /* Types of BT stomping */ 451 u32 btcoex_no_stomp; /* in usec */ 452 u32 btcoex_period; /* in usec */ 453 u32 btscan_no_stomp; /* in usec */ 454 u32 duty_cycle; 455 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 456 struct ath_mci_profile mci; 457 }; 458 459 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 460 int ath9k_init_btcoex(struct ath_softc *sc); 461 void ath9k_deinit_btcoex(struct ath_softc *sc); 462 void ath9k_start_btcoex(struct ath_softc *sc); 463 void ath9k_stop_btcoex(struct ath_softc *sc); 464 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 465 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 466 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 467 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 468 #else 469 static inline int ath9k_init_btcoex(struct ath_softc *sc) 470 { 471 return 0; 472 } 473 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 474 { 475 } 476 static inline void ath9k_start_btcoex(struct ath_softc *sc) 477 { 478 } 479 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 480 { 481 } 482 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 483 u32 status) 484 { 485 } 486 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 487 u32 max_4ms_framelen) 488 { 489 return 0; 490 } 491 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 492 493 /********************/ 494 /* LED Control */ 495 /********************/ 496 497 #define ATH_LED_PIN_DEF 1 498 #define ATH_LED_PIN_9287 8 499 #define ATH_LED_PIN_9300 10 500 #define ATH_LED_PIN_9485 6 501 #define ATH_LED_PIN_9462 4 502 503 #ifdef CONFIG_MAC80211_LEDS 504 void ath_init_leds(struct ath_softc *sc); 505 void ath_deinit_leds(struct ath_softc *sc); 506 #else 507 static inline void ath_init_leds(struct ath_softc *sc) 508 { 509 } 510 511 static inline void ath_deinit_leds(struct ath_softc *sc) 512 { 513 } 514 #endif 515 516 517 /* Antenna diversity/combining */ 518 #define ATH_ANT_RX_CURRENT_SHIFT 4 519 #define ATH_ANT_RX_MAIN_SHIFT 2 520 #define ATH_ANT_RX_MASK 0x3 521 522 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 523 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 524 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 525 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 526 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 527 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 528 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 529 530 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 531 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 532 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 533 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 534 535 enum ath9k_ant_div_comb_lna_conf { 536 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, 537 ATH_ANT_DIV_COMB_LNA2, 538 ATH_ANT_DIV_COMB_LNA1, 539 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, 540 }; 541 542 struct ath_ant_comb { 543 u16 count; 544 u16 total_pkt_count; 545 bool scan; 546 bool scan_not_start; 547 int main_total_rssi; 548 int alt_total_rssi; 549 int alt_recv_cnt; 550 int main_recv_cnt; 551 int rssi_lna1; 552 int rssi_lna2; 553 int rssi_add; 554 int rssi_sub; 555 int rssi_first; 556 int rssi_second; 557 int rssi_third; 558 bool alt_good; 559 int quick_scan_cnt; 560 int main_conf; 561 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 562 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 563 int first_bias; 564 int second_bias; 565 bool first_ratio; 566 bool second_ratio; 567 unsigned long scan_start_time; 568 }; 569 570 /********************/ 571 /* Main driver core */ 572 /********************/ 573 574 /* 575 * Default cache line size, in bytes. 576 * Used when PCI device not fully initialized by bootrom/BIOS 577 */ 578 #define DEFAULT_CACHELINE 32 579 #define ATH_REGCLASSIDS_MAX 10 580 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 581 #define ATH_MAX_SW_RETRIES 30 582 #define ATH_CHAN_MAX 255 583 584 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 585 #define ATH_RATE_DUMMY_MARKER 0 586 587 #define SC_OP_INVALID BIT(0) 588 #define SC_OP_BEACONS BIT(1) 589 #define SC_OP_OFFCHANNEL BIT(2) 590 #define SC_OP_RXFLUSH BIT(3) 591 #define SC_OP_TSF_RESET BIT(4) 592 #define SC_OP_BT_PRIORITY_DETECTED BIT(5) 593 #define SC_OP_BT_SCAN BIT(6) 594 #define SC_OP_ANI_RUN BIT(7) 595 #define SC_OP_PRIM_STA_VIF BIT(8) 596 597 /* Powersave flags */ 598 #define PS_WAIT_FOR_BEACON BIT(0) 599 #define PS_WAIT_FOR_CAB BIT(1) 600 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 601 #define PS_WAIT_FOR_TX_ACK BIT(3) 602 #define PS_BEACON_SYNC BIT(4) 603 604 struct ath_rate_table; 605 606 struct ath9k_vif_iter_data { 607 const u8 *hw_macaddr; /* phy's hardware address, set 608 * before starting iteration for 609 * valid bssid mask. 610 */ 611 u8 mask[ETH_ALEN]; /* bssid mask */ 612 int naps; /* number of AP vifs */ 613 int nmeshes; /* number of mesh vifs */ 614 int nstations; /* number of station vifs */ 615 int nwds; /* number of WDS vifs */ 616 int nadhocs; /* number of adhoc vifs */ 617 }; 618 619 struct ath_softc { 620 struct ieee80211_hw *hw; 621 struct device *dev; 622 623 struct survey_info *cur_survey; 624 struct survey_info survey[ATH9K_NUM_CHANNELS]; 625 626 struct tasklet_struct intr_tq; 627 struct tasklet_struct bcon_tasklet; 628 struct ath_hw *sc_ah; 629 void __iomem *mem; 630 int irq; 631 spinlock_t sc_serial_rw; 632 spinlock_t sc_pm_lock; 633 spinlock_t sc_pcu_lock; 634 struct mutex mutex; 635 struct work_struct paprd_work; 636 struct work_struct hw_check_work; 637 struct work_struct hw_reset_work; 638 struct completion paprd_complete; 639 640 unsigned int hw_busy_count; 641 642 u32 intrstatus; 643 u32 sc_flags; /* SC_OP_* */ 644 u16 ps_flags; /* PS_* */ 645 u16 curtxpow; 646 bool ps_enabled; 647 bool ps_idle; 648 short nbcnvifs; 649 short nvifs; 650 unsigned long ps_usecount; 651 652 struct ath_config config; 653 struct ath_rx rx; 654 struct ath_tx tx; 655 struct ath_beacon beacon; 656 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 657 658 #ifdef CONFIG_MAC80211_LEDS 659 bool led_registered; 660 char led_name[32]; 661 struct led_classdev led_cdev; 662 #endif 663 664 struct ath9k_hw_cal_data caldata; 665 int last_rssi; 666 667 #ifdef CONFIG_ATH9K_DEBUGFS 668 struct ath9k_debug debug; 669 spinlock_t nodes_lock; 670 struct list_head nodes; /* basically, stations */ 671 unsigned int tx_complete_poll_work_seen; 672 #endif 673 struct ath_beacon_config cur_beacon_conf; 674 struct delayed_work tx_complete_work; 675 struct delayed_work hw_pll_work; 676 struct timer_list rx_poll_timer; 677 678 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 679 struct ath_btcoex btcoex; 680 struct ath_mci_coex mci_coex; 681 #endif 682 683 struct ath_descdma txsdma; 684 685 struct ath_ant_comb ant_comb; 686 u8 ant_tx, ant_rx; 687 struct dfs_pattern_detector *dfs_detector; 688 }; 689 690 void ath9k_tasklet(unsigned long data); 691 int ath_cabq_update(struct ath_softc *); 692 693 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 694 { 695 common->bus_ops->read_cachesize(common, csz); 696 } 697 698 extern struct ieee80211_ops ath9k_ops; 699 extern int ath9k_modparam_nohwcrypt; 700 extern int led_blink; 701 extern bool is_ath9k_unloaded; 702 703 irqreturn_t ath_isr(int irq, void *dev); 704 int ath9k_init_device(u16 devid, struct ath_softc *sc, 705 const struct ath_bus_ops *bus_ops); 706 void ath9k_deinit_device(struct ath_softc *sc); 707 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 708 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 709 710 bool ath9k_uses_beacons(int type); 711 712 #ifdef CONFIG_ATH9K_PCI 713 int ath_pci_init(void); 714 void ath_pci_exit(void); 715 #else 716 static inline int ath_pci_init(void) { return 0; }; 717 static inline void ath_pci_exit(void) {}; 718 #endif 719 720 #ifdef CONFIG_ATH9K_AHB 721 int ath_ahb_init(void); 722 void ath_ahb_exit(void); 723 #else 724 static inline int ath_ahb_init(void) { return 0; }; 725 static inline void ath_ahb_exit(void) {}; 726 #endif 727 728 void ath9k_ps_wakeup(struct ath_softc *sc); 729 void ath9k_ps_restore(struct ath_softc *sc); 730 731 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 732 733 void ath_start_rfkill_poll(struct ath_softc *sc); 734 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 735 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 736 struct ieee80211_vif *vif, 737 struct ath9k_vif_iter_data *iter_data); 738 739 740 #endif /* ATH9K_H */ 741