1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/leds.h> 23 24 #include "debug.h" 25 #include "common.h" 26 27 /* 28 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 29 * should rely on this file or its contents. 30 */ 31 32 struct ath_node; 33 34 /* Macro to expand scalars to 64-bit objects */ 35 36 #define ito64(x) (sizeof(x) == 8) ? \ 37 (((unsigned long long int)(x)) & (0xff)) : \ 38 (sizeof(x) == 16) ? \ 39 (((unsigned long long int)(x)) & 0xffff) : \ 40 ((sizeof(x) == 32) ? \ 41 (((unsigned long long int)(x)) & 0xffffffff) : \ 42 (unsigned long long int)(x)) 43 44 /* increment with wrap-around */ 45 #define INCR(_l, _sz) do { \ 46 (_l)++; \ 47 (_l) &= ((_sz) - 1); \ 48 } while (0) 49 50 /* decrement with wrap-around */ 51 #define DECR(_l, _sz) do { \ 52 (_l)--; \ 53 (_l) &= ((_sz) - 1); \ 54 } while (0) 55 56 #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 57 58 #define TSF_TO_TU(_h,_l) \ 59 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 60 61 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 62 63 struct ath_config { 64 u32 ath_aggr_prot; 65 u16 txpowlimit; 66 u8 cabqReadytime; 67 }; 68 69 /*************************/ 70 /* Descriptor Management */ 71 /*************************/ 72 73 #define ATH_TXBUF_RESET(_bf) do { \ 74 (_bf)->bf_stale = false; \ 75 (_bf)->bf_lastbf = NULL; \ 76 (_bf)->bf_next = NULL; \ 77 memset(&((_bf)->bf_state), 0, \ 78 sizeof(struct ath_buf_state)); \ 79 } while (0) 80 81 #define ATH_RXBUF_RESET(_bf) do { \ 82 (_bf)->bf_stale = false; \ 83 } while (0) 84 85 /** 86 * enum buffer_type - Buffer type flags 87 * 88 * @BUF_HT: Send this buffer using HT capabilities 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 * @BUF_RETRY: Indicates whether the buffer is retried 93 * @BUF_XRETRY: To denote excessive retries of the buffer 94 */ 95 enum buffer_type { 96 BUF_HT = BIT(1), 97 BUF_AMPDU = BIT(2), 98 BUF_AGGR = BIT(3), 99 BUF_RETRY = BIT(4), 100 BUF_XRETRY = BIT(5), 101 }; 102 103 #define bf_nframes bf_state.bfs_nframes 104 #define bf_al bf_state.bfs_al 105 #define bf_frmlen bf_state.bfs_frmlen 106 #define bf_retries bf_state.bfs_retries 107 #define bf_seqno bf_state.bfs_seqno 108 #define bf_tidno bf_state.bfs_tidno 109 #define bf_keyix bf_state.bfs_keyix 110 #define bf_keytype bf_state.bfs_keytype 111 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) 112 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 113 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 114 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 115 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 116 117 struct ath_descdma { 118 struct ath_desc *dd_desc; 119 dma_addr_t dd_desc_paddr; 120 u32 dd_desc_len; 121 struct ath_buf *dd_bufptr; 122 }; 123 124 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 125 struct list_head *head, const char *name, 126 int nbuf, int ndesc); 127 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 128 struct list_head *head); 129 130 /***********/ 131 /* RX / TX */ 132 /***********/ 133 134 #define ATH_MAX_ANTENNA 3 135 #define ATH_RXBUF 512 136 #define ATH_TXBUF 512 137 #define ATH_TXMAXTRY 13 138 #define ATH_MGT_TXMAXTRY 4 139 140 #define TID_TO_WME_AC(_tid) \ 141 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 142 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 143 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 144 WME_AC_VO) 145 146 #define ADDBA_EXCHANGE_ATTEMPTS 10 147 #define ATH_AGGR_DELIM_SZ 4 148 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 149 /* number of delimiters for encryption padding */ 150 #define ATH_AGGR_ENCRYPTDELIM 10 151 /* minimum h/w qdepth to be sustained to maximize aggregation */ 152 #define ATH_AGGR_MIN_QDEPTH 2 153 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 154 155 #define IEEE80211_SEQ_SEQ_SHIFT 4 156 #define IEEE80211_SEQ_MAX 4096 157 #define IEEE80211_WEP_IVLEN 3 158 #define IEEE80211_WEP_KIDLEN 1 159 #define IEEE80211_WEP_CRCLEN 4 160 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 161 (IEEE80211_WEP_IVLEN + \ 162 IEEE80211_WEP_KIDLEN + \ 163 IEEE80211_WEP_CRCLEN)) 164 165 /* return whether a bit at index _n in bitmap _bm is set 166 * _sz is the size of the bitmap */ 167 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 168 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 169 170 /* return block-ack bitmap index given sequence and starting sequence */ 171 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 172 173 /* returns delimiter padding required given the packet length */ 174 #define ATH_AGGR_GET_NDELIM(_len) \ 175 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ 176 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) 177 178 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 179 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 180 181 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) 182 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) 183 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) 184 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 185 186 #define ATH_TX_COMPLETE_POLL_INT 1000 187 188 enum ATH_AGGR_STATUS { 189 ATH_AGGR_DONE, 190 ATH_AGGR_BAW_CLOSED, 191 ATH_AGGR_LIMITED, 192 }; 193 194 struct ath_txq { 195 u32 axq_qnum; 196 u32 *axq_link; 197 struct list_head axq_q; 198 spinlock_t axq_lock; 199 u32 axq_depth; 200 bool stopped; 201 bool axq_tx_inprogress; 202 struct list_head axq_acq; 203 }; 204 205 #define AGGR_CLEANUP BIT(1) 206 #define AGGR_ADDBA_COMPLETE BIT(2) 207 #define AGGR_ADDBA_PROGRESS BIT(3) 208 209 struct ath_tx_control { 210 struct ath_txq *txq; 211 int if_id; 212 enum ath9k_internal_frame_type frame_type; 213 }; 214 215 #define ATH_TX_ERROR 0x01 216 #define ATH_TX_XRETRY 0x02 217 #define ATH_TX_BAR 0x04 218 219 struct ath_tx { 220 u16 seq_no; 221 u32 txqsetup; 222 int hwq_map[ATH9K_WME_AC_VO+1]; 223 spinlock_t txbuflock; 224 struct list_head txbuf; 225 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 226 struct ath_descdma txdma; 227 }; 228 229 struct ath_rx { 230 u8 defant; 231 u8 rxotherant; 232 u32 *rxlink; 233 unsigned int rxfilter; 234 spinlock_t rxflushlock; 235 spinlock_t rxbuflock; 236 struct list_head rxbuf; 237 struct ath_descdma rxdma; 238 }; 239 240 int ath_startrecv(struct ath_softc *sc); 241 bool ath_stoprecv(struct ath_softc *sc); 242 void ath_flushrecv(struct ath_softc *sc); 243 u32 ath_calcrxfilter(struct ath_softc *sc); 244 int ath_rx_init(struct ath_softc *sc, int nbufs); 245 void ath_rx_cleanup(struct ath_softc *sc); 246 int ath_rx_tasklet(struct ath_softc *sc, int flush); 247 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 248 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 249 int ath_tx_setup(struct ath_softc *sc, int haltype); 250 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 251 void ath_draintxq(struct ath_softc *sc, 252 struct ath_txq *txq, bool retry_tx); 253 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 254 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 255 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 256 int ath_tx_init(struct ath_softc *sc, int nbufs); 257 void ath_tx_cleanup(struct ath_softc *sc); 258 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); 259 int ath_txq_update(struct ath_softc *sc, int qnum, 260 struct ath9k_tx_queue_info *q); 261 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 262 struct ath_tx_control *txctl); 263 void ath_tx_tasklet(struct ath_softc *sc); 264 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); 265 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); 266 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 267 u16 tid, u16 *ssn); 268 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 269 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 270 271 /********/ 272 /* VIFs */ 273 /********/ 274 275 struct ath_vif { 276 int av_bslot; 277 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 278 enum nl80211_iftype av_opmode; 279 struct ath_buf *av_bcbuf; 280 struct ath_tx_control av_btxctl; 281 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ 282 }; 283 284 /*******************/ 285 /* Beacon Handling */ 286 /*******************/ 287 288 /* 289 * Regardless of the number of beacons we stagger, (i.e. regardless of the 290 * number of BSSIDs) if a given beacon does not go out even after waiting this 291 * number of beacon intervals, the game's up. 292 */ 293 #define BSTUCK_THRESH (9 * ATH_BCBUF) 294 #define ATH_BCBUF 4 295 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 296 #define ATH_DEFAULT_BMISS_LIMIT 10 297 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 298 299 struct ath_beacon_config { 300 u16 beacon_interval; 301 u16 listen_interval; 302 u16 dtim_period; 303 u16 bmiss_timeout; 304 u8 dtim_count; 305 }; 306 307 struct ath_beacon { 308 enum { 309 OK, /* no change needed */ 310 UPDATE, /* update pending */ 311 COMMIT /* beacon sent, commit change */ 312 } updateslot; /* slot time update fsm */ 313 314 u32 beaconq; 315 u32 bmisscnt; 316 u32 ast_be_xmit; 317 u64 bc_tstamp; 318 struct ieee80211_vif *bslot[ATH_BCBUF]; 319 struct ath_wiphy *bslot_aphy[ATH_BCBUF]; 320 int slottime; 321 int slotupdate; 322 struct ath9k_tx_queue_info beacon_qi; 323 struct ath_descdma bdma; 324 struct ath_txq *cabq; 325 struct list_head bbuf; 326 }; 327 328 void ath_beacon_tasklet(unsigned long data); 329 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 330 int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); 331 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 332 int ath_beaconq_config(struct ath_softc *sc); 333 334 /*******/ 335 /* ANI */ 336 /*******/ 337 338 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 339 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 340 #define ATH_ANI_POLLINTERVAL 100 /* 100 ms */ 341 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 342 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 343 344 /* Defines the BT AR_BT_COEX_WGHT used */ 345 enum ath_stomp_type { 346 ATH_BTCOEX_NO_STOMP, 347 ATH_BTCOEX_STOMP_ALL, 348 ATH_BTCOEX_STOMP_LOW, 349 ATH_BTCOEX_STOMP_NONE 350 }; 351 352 struct ath_btcoex { 353 bool hw_timer_enabled; 354 spinlock_t btcoex_lock; 355 struct timer_list period_timer; /* Timer for BT period */ 356 u32 bt_priority_cnt; 357 unsigned long bt_priority_time; 358 int bt_stomp_type; /* Types of BT stomping */ 359 u32 btcoex_no_stomp; /* in usec */ 360 u32 btcoex_period; /* in usec */ 361 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 362 }; 363 364 /********************/ 365 /* LED Control */ 366 /********************/ 367 368 #define ATH_LED_PIN_DEF 1 369 #define ATH_LED_PIN_9287 8 370 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ 371 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ 372 373 enum ath_led_type { 374 ATH_LED_RADIO, 375 ATH_LED_ASSOC, 376 ATH_LED_TX, 377 ATH_LED_RX 378 }; 379 380 struct ath_led { 381 struct ath_softc *sc; 382 struct led_classdev led_cdev; 383 enum ath_led_type led_type; 384 char name[32]; 385 bool registered; 386 }; 387 388 /********************/ 389 /* Main driver core */ 390 /********************/ 391 392 /* 393 * Default cache line size, in bytes. 394 * Used when PCI device not fully initialized by bootrom/BIOS 395 */ 396 #define DEFAULT_CACHELINE 32 397 #define ATH_REGCLASSIDS_MAX 10 398 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 399 #define ATH_MAX_SW_RETRIES 10 400 #define ATH_CHAN_MAX 255 401 #define IEEE80211_WEP_NKID 4 /* number of key ids */ 402 403 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 404 #define ATH_RATE_DUMMY_MARKER 0 405 406 #define SC_OP_INVALID BIT(0) 407 #define SC_OP_BEACONS BIT(1) 408 #define SC_OP_RXAGGR BIT(2) 409 #define SC_OP_TXAGGR BIT(3) 410 #define SC_OP_FULL_RESET BIT(4) 411 #define SC_OP_PREAMBLE_SHORT BIT(5) 412 #define SC_OP_PROTECT_ENABLE BIT(6) 413 #define SC_OP_RXFLUSH BIT(7) 414 #define SC_OP_LED_ASSOCIATED BIT(8) 415 #define SC_OP_WAIT_FOR_BEACON BIT(12) 416 #define SC_OP_LED_ON BIT(13) 417 #define SC_OP_SCANNING BIT(14) 418 #define SC_OP_TSF_RESET BIT(15) 419 #define SC_OP_WAIT_FOR_CAB BIT(16) 420 #define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17) 421 #define SC_OP_WAIT_FOR_TX_ACK BIT(18) 422 #define SC_OP_BEACON_SYNC BIT(19) 423 #define SC_OP_BT_PRIORITY_DETECTED BIT(21) 424 #define SC_OP_NULLFUNC_COMPLETED BIT(22) 425 #define SC_OP_PS_ENABLED BIT(23) 426 427 struct ath_wiphy; 428 struct ath_rate_table; 429 430 struct ath_softc { 431 struct ieee80211_hw *hw; 432 struct device *dev; 433 434 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ 435 struct ath_wiphy *pri_wiphy; 436 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may 437 * have NULL entries */ 438 int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ 439 int chan_idx; 440 int chan_is_ht; 441 struct ath_wiphy *next_wiphy; 442 struct work_struct chan_work; 443 int wiphy_select_failures; 444 unsigned long wiphy_select_first_fail; 445 struct delayed_work wiphy_work; 446 unsigned long wiphy_scheduler_int; 447 int wiphy_scheduler_index; 448 449 struct tasklet_struct intr_tq; 450 struct tasklet_struct bcon_tasklet; 451 struct ath_hw *sc_ah; 452 void __iomem *mem; 453 int irq; 454 spinlock_t sc_resetlock; 455 spinlock_t sc_serial_rw; 456 spinlock_t ani_lock; 457 spinlock_t sc_pm_lock; 458 struct mutex mutex; 459 460 u32 intrstatus; 461 u32 sc_flags; /* SC_OP_* */ 462 u16 curtxpow; 463 u8 nbcnvifs; 464 u16 nvifs; 465 bool ps_enabled; 466 unsigned long ps_usecount; 467 enum ath9k_int imask; 468 469 struct ath_config config; 470 struct ath_rx rx; 471 struct ath_tx tx; 472 struct ath_beacon beacon; 473 const struct ath_rate_table *cur_rate_table; 474 enum wireless_mode cur_rate_mode; 475 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 476 477 struct ath_led radio_led; 478 struct ath_led assoc_led; 479 struct ath_led tx_led; 480 struct ath_led rx_led; 481 struct delayed_work ath_led_blink_work; 482 int led_on_duration; 483 int led_off_duration; 484 int led_on_cnt; 485 int led_off_cnt; 486 487 int beacon_interval; 488 489 #ifdef CONFIG_ATH9K_DEBUG 490 struct ath9k_debug debug; 491 #endif 492 struct ath_beacon_config cur_beacon_conf; 493 struct delayed_work tx_complete_work; 494 struct ath_btcoex btcoex; 495 }; 496 497 struct ath_wiphy { 498 struct ath_softc *sc; /* shared for all virtual wiphys */ 499 struct ieee80211_hw *hw; 500 enum ath_wiphy_state { 501 ATH_WIPHY_INACTIVE, 502 ATH_WIPHY_ACTIVE, 503 ATH_WIPHY_PAUSING, 504 ATH_WIPHY_PAUSED, 505 ATH_WIPHY_SCAN, 506 } state; 507 bool idle; 508 int chan_idx; 509 int chan_is_ht; 510 }; 511 512 int ath_reset(struct ath_softc *sc, bool retry_tx); 513 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); 514 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); 515 int ath_cabq_update(struct ath_softc *); 516 517 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 518 { 519 common->bus_ops->read_cachesize(common, csz); 520 } 521 522 static inline void ath_bus_cleanup(struct ath_common *common) 523 { 524 common->bus_ops->cleanup(common); 525 } 526 527 extern struct ieee80211_ops ath9k_ops; 528 529 irqreturn_t ath_isr(int irq, void *dev); 530 void ath_cleanup(struct ath_softc *sc); 531 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, 532 const struct ath_bus_ops *bus_ops); 533 void ath_detach(struct ath_softc *sc); 534 const char *ath_mac_bb_name(u32 mac_bb_version); 535 const char *ath_rf_name(u16 rf_version); 536 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 537 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, 538 struct ath9k_channel *ichan); 539 void ath_update_chainmask(struct ath_softc *sc, int is_ht); 540 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 541 struct ath9k_channel *hchan); 542 543 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); 544 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); 545 546 #ifdef CONFIG_PCI 547 int ath_pci_init(void); 548 void ath_pci_exit(void); 549 #else 550 static inline int ath_pci_init(void) { return 0; }; 551 static inline void ath_pci_exit(void) {}; 552 #endif 553 554 #ifdef CONFIG_ATHEROS_AR71XX 555 int ath_ahb_init(void); 556 void ath_ahb_exit(void); 557 #else 558 static inline int ath_ahb_init(void) { return 0; }; 559 static inline void ath_ahb_exit(void) {}; 560 #endif 561 562 void ath9k_ps_wakeup(struct ath_softc *sc); 563 void ath9k_ps_restore(struct ath_softc *sc); 564 565 void ath9k_set_bssid_mask(struct ieee80211_hw *hw); 566 int ath9k_wiphy_add(struct ath_softc *sc); 567 int ath9k_wiphy_del(struct ath_wiphy *aphy); 568 void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); 569 int ath9k_wiphy_pause(struct ath_wiphy *aphy); 570 int ath9k_wiphy_unpause(struct ath_wiphy *aphy); 571 int ath9k_wiphy_select(struct ath_wiphy *aphy); 572 void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); 573 void ath9k_wiphy_chan_work(struct work_struct *work); 574 bool ath9k_wiphy_started(struct ath_softc *sc); 575 void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, 576 struct ath_wiphy *selected); 577 bool ath9k_wiphy_scanning(struct ath_softc *sc); 578 void ath9k_wiphy_work(struct work_struct *work); 579 bool ath9k_all_wiphys_idle(struct ath_softc *sc); 580 void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); 581 582 void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); 583 void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); 584 585 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype); 586 #endif /* ATH9K_H */ 587