1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 31 /* 32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 33 * should rely on this file or its contents. 34 */ 35 36 struct ath_node; 37 38 /* Macro to expand scalars to 64-bit objects */ 39 40 #define ito64(x) (sizeof(x) == 1) ? \ 41 (((unsigned long long int)(x)) & (0xff)) : \ 42 (sizeof(x) == 2) ? \ 43 (((unsigned long long int)(x)) & 0xffff) : \ 44 ((sizeof(x) == 4) ? \ 45 (((unsigned long long int)(x)) & 0xffffffff) : \ 46 (unsigned long long int)(x)) 47 48 /* increment with wrap-around */ 49 #define INCR(_l, _sz) do { \ 50 (_l)++; \ 51 (_l) &= ((_sz) - 1); \ 52 } while (0) 53 54 /* decrement with wrap-around */ 55 #define DECR(_l, _sz) do { \ 56 (_l)--; \ 57 (_l) &= ((_sz) - 1); \ 58 } while (0) 59 60 #define TSF_TO_TU(_h,_l) \ 61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 62 63 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 64 65 struct ath_config { 66 u16 txpowlimit; 67 u8 cabqReadytime; 68 }; 69 70 /*************************/ 71 /* Descriptor Management */ 72 /*************************/ 73 74 #define ATH_TXBUF_RESET(_bf) do { \ 75 (_bf)->bf_stale = false; \ 76 (_bf)->bf_lastbf = NULL; \ 77 (_bf)->bf_next = NULL; \ 78 memset(&((_bf)->bf_state), 0, \ 79 sizeof(struct ath_buf_state)); \ 80 } while (0) 81 82 #define ATH_RXBUF_RESET(_bf) do { \ 83 (_bf)->bf_stale = false; \ 84 } while (0) 85 86 /** 87 * enum buffer_type - Buffer type flags 88 * 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 */ 93 enum buffer_type { 94 BUF_AMPDU = BIT(0), 95 BUF_AGGR = BIT(1), 96 }; 97 98 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 99 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 100 101 #define ATH_TXSTATUS_RING_SIZE 512 102 103 #define DS2PHYS(_dd, _ds) \ 104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 107 108 struct ath_descdma { 109 void *dd_desc; 110 dma_addr_t dd_desc_paddr; 111 u32 dd_desc_len; 112 struct ath_buf *dd_bufptr; 113 }; 114 115 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 116 struct list_head *head, const char *name, 117 int nbuf, int ndesc, bool is_tx); 118 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 119 struct list_head *head); 120 121 /***********/ 122 /* RX / TX */ 123 /***********/ 124 125 #define ATH_RXBUF 512 126 #define ATH_TXBUF 512 127 #define ATH_TXBUF_RESERVE 5 128 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 129 #define ATH_TXMAXTRY 13 130 131 #define TID_TO_WME_AC(_tid) \ 132 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ 133 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ 134 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ 135 IEEE80211_AC_VO) 136 137 #define ATH_AGGR_DELIM_SZ 4 138 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 139 /* number of delimiters for encryption padding */ 140 #define ATH_AGGR_ENCRYPTDELIM 10 141 /* minimum h/w qdepth to be sustained to maximize aggregation */ 142 #define ATH_AGGR_MIN_QDEPTH 2 143 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 144 145 #define IEEE80211_SEQ_SEQ_SHIFT 4 146 #define IEEE80211_SEQ_MAX 4096 147 #define IEEE80211_WEP_IVLEN 3 148 #define IEEE80211_WEP_KIDLEN 1 149 #define IEEE80211_WEP_CRCLEN 4 150 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 151 (IEEE80211_WEP_IVLEN + \ 152 IEEE80211_WEP_KIDLEN + \ 153 IEEE80211_WEP_CRCLEN)) 154 155 /* return whether a bit at index _n in bitmap _bm is set 156 * _sz is the size of the bitmap */ 157 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 158 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 159 160 /* return block-ack bitmap index given sequence and starting sequence */ 161 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 162 163 /* return the seqno for _start + _offset */ 164 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 165 166 /* returns delimiter padding required given the packet length */ 167 #define ATH_AGGR_GET_NDELIM(_len) \ 168 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 169 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 170 171 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 172 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 173 174 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 175 176 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) 177 178 #define ATH_TX_COMPLETE_POLL_INT 1000 179 180 enum ATH_AGGR_STATUS { 181 ATH_AGGR_DONE, 182 ATH_AGGR_BAW_CLOSED, 183 ATH_AGGR_LIMITED, 184 }; 185 186 #define ATH_TXFIFO_DEPTH 8 187 struct ath_txq { 188 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 189 u32 axq_qnum; /* ath9k hardware queue number */ 190 void *axq_link; 191 struct list_head axq_q; 192 spinlock_t axq_lock; 193 u32 axq_depth; 194 u32 axq_ampdu_depth; 195 bool stopped; 196 bool axq_tx_inprogress; 197 struct list_head axq_acq; 198 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 199 u8 txq_headidx; 200 u8 txq_tailidx; 201 int pending_frames; 202 struct sk_buff_head complete_q; 203 }; 204 205 struct ath_atx_ac { 206 struct ath_txq *txq; 207 int sched; 208 struct list_head list; 209 struct list_head tid_q; 210 bool clear_ps_filter; 211 }; 212 213 struct ath_frame_info { 214 struct ath_buf *bf; 215 int framelen; 216 enum ath9k_key_type keytype; 217 u8 keyix; 218 u8 retries; 219 u8 rtscts_rate; 220 }; 221 222 struct ath_buf_state { 223 u8 bf_type; 224 u8 bfs_paprd; 225 u8 ndelim; 226 u16 seqno; 227 unsigned long bfs_paprd_timestamp; 228 }; 229 230 struct ath_buf { 231 struct list_head list; 232 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 233 an aggregate) */ 234 struct ath_buf *bf_next; /* next subframe in the aggregate */ 235 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 236 void *bf_desc; /* virtual addr of desc */ 237 dma_addr_t bf_daddr; /* physical addr of desc */ 238 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 239 bool bf_stale; 240 struct ath_buf_state bf_state; 241 }; 242 243 struct ath_atx_tid { 244 struct list_head list; 245 struct sk_buff_head buf_q; 246 struct ath_node *an; 247 struct ath_atx_ac *ac; 248 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 249 int bar_index; 250 u16 seq_start; 251 u16 seq_next; 252 u16 baw_size; 253 int tidno; 254 int baw_head; /* first un-acked tx buffer */ 255 int baw_tail; /* next unused tx buffer slot */ 256 int sched; 257 int paused; 258 u8 state; 259 }; 260 261 struct ath_node { 262 struct ath_softc *sc; 263 struct ieee80211_sta *sta; /* station struct we're part of */ 264 struct ieee80211_vif *vif; /* interface with which we're associated */ 265 struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; 266 struct ath_atx_ac ac[IEEE80211_NUM_ACS]; 267 int ps_key; 268 269 u16 maxampdu; 270 u8 mpdudensity; 271 272 bool sleeping; 273 274 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS) 275 struct dentry *node_stat; 276 #endif 277 }; 278 279 #define AGGR_CLEANUP BIT(1) 280 #define AGGR_ADDBA_COMPLETE BIT(2) 281 #define AGGR_ADDBA_PROGRESS BIT(3) 282 283 struct ath_tx_control { 284 struct ath_txq *txq; 285 struct ath_node *an; 286 u8 paprd; 287 struct ieee80211_sta *sta; 288 }; 289 290 #define ATH_TX_ERROR 0x01 291 292 /** 293 * @txq_map: Index is mac80211 queue number. This is 294 * not necessarily the same as the hardware queue number 295 * (axq_qnum). 296 */ 297 struct ath_tx { 298 u16 seq_no; 299 u32 txqsetup; 300 spinlock_t txbuflock; 301 struct list_head txbuf; 302 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 303 struct ath_descdma txdma; 304 struct ath_txq *txq_map[IEEE80211_NUM_ACS]; 305 u32 txq_max_pending[IEEE80211_NUM_ACS]; 306 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; 307 }; 308 309 struct ath_rx_edma { 310 struct sk_buff_head rx_fifo; 311 u32 rx_fifo_hwsize; 312 }; 313 314 struct ath_rx { 315 u8 defant; 316 u8 rxotherant; 317 u32 *rxlink; 318 u32 num_pkts; 319 unsigned int rxfilter; 320 spinlock_t rxbuflock; 321 struct list_head rxbuf; 322 struct ath_descdma rxdma; 323 struct ath_buf *rx_bufptr; 324 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 325 326 struct sk_buff *frag; 327 }; 328 329 int ath_startrecv(struct ath_softc *sc); 330 bool ath_stoprecv(struct ath_softc *sc); 331 void ath_flushrecv(struct ath_softc *sc); 332 u32 ath_calcrxfilter(struct ath_softc *sc); 333 int ath_rx_init(struct ath_softc *sc, int nbufs); 334 void ath_rx_cleanup(struct ath_softc *sc); 335 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 336 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 337 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); 338 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); 339 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); 340 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 341 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 342 void ath_draintxq(struct ath_softc *sc, 343 struct ath_txq *txq, bool retry_tx); 344 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 345 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 346 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 347 int ath_tx_init(struct ath_softc *sc, int nbufs); 348 void ath_tx_cleanup(struct ath_softc *sc); 349 int ath_txq_update(struct ath_softc *sc, int qnum, 350 struct ath9k_tx_queue_info *q); 351 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); 352 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 353 struct ath_tx_control *txctl); 354 void ath_tx_tasklet(struct ath_softc *sc); 355 void ath_tx_edma_tasklet(struct ath_softc *sc); 356 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 357 u16 tid, u16 *ssn); 358 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 359 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 360 361 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 362 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 363 struct ath_node *an); 364 365 /********/ 366 /* VIFs */ 367 /********/ 368 369 struct ath_vif { 370 int av_bslot; 371 bool primary_sta_vif; 372 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 373 struct ath_buf *av_bcbuf; 374 }; 375 376 /*******************/ 377 /* Beacon Handling */ 378 /*******************/ 379 380 /* 381 * Regardless of the number of beacons we stagger, (i.e. regardless of the 382 * number of BSSIDs) if a given beacon does not go out even after waiting this 383 * number of beacon intervals, the game's up. 384 */ 385 #define BSTUCK_THRESH 9 386 #define ATH_BCBUF 8 387 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 388 #define ATH_DEFAULT_BMISS_LIMIT 10 389 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 390 391 struct ath_beacon_config { 392 int beacon_interval; 393 u16 listen_interval; 394 u16 dtim_period; 395 u16 bmiss_timeout; 396 u8 dtim_count; 397 bool enable_beacon; 398 }; 399 400 struct ath_beacon { 401 enum { 402 OK, /* no change needed */ 403 UPDATE, /* update pending */ 404 COMMIT /* beacon sent, commit change */ 405 } updateslot; /* slot time update fsm */ 406 407 u32 beaconq; 408 u32 bmisscnt; 409 u32 bc_tstamp; 410 struct ieee80211_vif *bslot[ATH_BCBUF]; 411 int slottime; 412 int slotupdate; 413 struct ath9k_tx_queue_info beacon_qi; 414 struct ath_descdma bdma; 415 struct ath_txq *cabq; 416 struct list_head bbuf; 417 418 bool tx_processed; 419 bool tx_last; 420 }; 421 422 void ath9k_beacon_tasklet(unsigned long data); 423 bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 424 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, 425 u32 changed); 426 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 427 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 428 void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif); 429 void ath9k_set_beacon(struct ath_softc *sc); 430 431 /*******************/ 432 /* Link Monitoring */ 433 /*******************/ 434 435 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 436 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 437 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 438 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 439 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 440 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 441 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 442 #define ATH_ANI_MAX_SKIP_COUNT 10 443 444 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 445 #define ATH_PLL_WORK_INTERVAL 100 446 447 void ath_tx_complete_poll_work(struct work_struct *work); 448 void ath_reset_work(struct work_struct *work); 449 void ath_hw_check(struct work_struct *work); 450 void ath_hw_pll_work(struct work_struct *work); 451 void ath_rx_poll(unsigned long data); 452 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); 453 void ath_paprd_calibrate(struct work_struct *work); 454 void ath_ani_calibrate(unsigned long data); 455 void ath_start_ani(struct ath_softc *sc); 456 void ath_stop_ani(struct ath_softc *sc); 457 void ath_check_ani(struct ath_softc *sc); 458 int ath_update_survey_stats(struct ath_softc *sc); 459 void ath_update_survey_nf(struct ath_softc *sc, int channel); 460 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); 461 462 /**********/ 463 /* BTCOEX */ 464 /**********/ 465 466 #define ATH_DUMP_BTCOEX(_s, _val) \ 467 do { \ 468 len += snprintf(buf + len, size - len, \ 469 "%20s : %10d\n", _s, (_val)); \ 470 } while (0) 471 472 enum bt_op_flags { 473 BT_OP_PRIORITY_DETECTED, 474 BT_OP_SCAN, 475 }; 476 477 struct ath_btcoex { 478 bool hw_timer_enabled; 479 spinlock_t btcoex_lock; 480 struct timer_list period_timer; /* Timer for BT period */ 481 u32 bt_priority_cnt; 482 unsigned long bt_priority_time; 483 unsigned long op_flags; 484 int bt_stomp_type; /* Types of BT stomping */ 485 u32 btcoex_no_stomp; /* in usec */ 486 u32 btcoex_period; /* in msec */ 487 u32 btscan_no_stomp; /* in usec */ 488 u32 duty_cycle; 489 u32 bt_wait_time; 490 int rssi_count; 491 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 492 struct ath_mci_profile mci; 493 u8 stomp_audio; 494 }; 495 496 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 497 int ath9k_init_btcoex(struct ath_softc *sc); 498 void ath9k_deinit_btcoex(struct ath_softc *sc); 499 void ath9k_start_btcoex(struct ath_softc *sc); 500 void ath9k_stop_btcoex(struct ath_softc *sc); 501 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 502 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 503 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 504 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 505 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); 506 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); 507 #else 508 static inline int ath9k_init_btcoex(struct ath_softc *sc) 509 { 510 return 0; 511 } 512 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 513 { 514 } 515 static inline void ath9k_start_btcoex(struct ath_softc *sc) 516 { 517 } 518 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 519 { 520 } 521 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 522 u32 status) 523 { 524 } 525 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 526 u32 max_4ms_framelen) 527 { 528 return 0; 529 } 530 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 531 { 532 } 533 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) 534 { 535 return 0; 536 } 537 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 538 539 struct ath9k_wow_pattern { 540 u8 pattern_bytes[MAX_PATTERN_SIZE]; 541 u8 mask_bytes[MAX_PATTERN_SIZE]; 542 u32 pattern_len; 543 }; 544 545 /********************/ 546 /* LED Control */ 547 /********************/ 548 549 #define ATH_LED_PIN_DEF 1 550 #define ATH_LED_PIN_9287 8 551 #define ATH_LED_PIN_9300 10 552 #define ATH_LED_PIN_9485 6 553 #define ATH_LED_PIN_9462 4 554 555 #ifdef CONFIG_MAC80211_LEDS 556 void ath_init_leds(struct ath_softc *sc); 557 void ath_deinit_leds(struct ath_softc *sc); 558 void ath_fill_led_pin(struct ath_softc *sc); 559 #else 560 static inline void ath_init_leds(struct ath_softc *sc) 561 { 562 } 563 564 static inline void ath_deinit_leds(struct ath_softc *sc) 565 { 566 } 567 static inline void ath_fill_led_pin(struct ath_softc *sc) 568 { 569 } 570 #endif 571 572 /*******************************/ 573 /* Antenna diversity/combining */ 574 /*******************************/ 575 576 #define ATH_ANT_RX_CURRENT_SHIFT 4 577 #define ATH_ANT_RX_MAIN_SHIFT 2 578 #define ATH_ANT_RX_MASK 0x3 579 580 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 581 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 582 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 583 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 584 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 585 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 586 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 587 588 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 589 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 590 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 591 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 592 593 enum ath9k_ant_div_comb_lna_conf { 594 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, 595 ATH_ANT_DIV_COMB_LNA2, 596 ATH_ANT_DIV_COMB_LNA1, 597 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, 598 }; 599 600 struct ath_ant_comb { 601 u16 count; 602 u16 total_pkt_count; 603 bool scan; 604 bool scan_not_start; 605 int main_total_rssi; 606 int alt_total_rssi; 607 int alt_recv_cnt; 608 int main_recv_cnt; 609 int rssi_lna1; 610 int rssi_lna2; 611 int rssi_add; 612 int rssi_sub; 613 int rssi_first; 614 int rssi_second; 615 int rssi_third; 616 bool alt_good; 617 int quick_scan_cnt; 618 int main_conf; 619 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 620 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 621 bool first_ratio; 622 bool second_ratio; 623 unsigned long scan_start_time; 624 }; 625 626 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 627 void ath_ant_comb_update(struct ath_softc *sc); 628 629 /********************/ 630 /* Main driver core */ 631 /********************/ 632 633 /* 634 * Default cache line size, in bytes. 635 * Used when PCI device not fully initialized by bootrom/BIOS 636 */ 637 #define DEFAULT_CACHELINE 32 638 #define ATH_REGCLASSIDS_MAX 10 639 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 640 #define ATH_MAX_SW_RETRIES 30 641 #define ATH_CHAN_MAX 255 642 643 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 644 #define ATH_RATE_DUMMY_MARKER 0 645 646 enum sc_op_flags { 647 SC_OP_INVALID, 648 SC_OP_BEACONS, 649 SC_OP_RXFLUSH, 650 SC_OP_ANI_RUN, 651 SC_OP_PRIM_STA_VIF, 652 SC_OP_HW_RESET, 653 }; 654 655 /* Powersave flags */ 656 #define PS_WAIT_FOR_BEACON BIT(0) 657 #define PS_WAIT_FOR_CAB BIT(1) 658 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 659 #define PS_WAIT_FOR_TX_ACK BIT(3) 660 #define PS_BEACON_SYNC BIT(4) 661 #define PS_WAIT_FOR_ANI BIT(5) 662 663 struct ath_rate_table; 664 665 struct ath9k_vif_iter_data { 666 const u8 *hw_macaddr; /* phy's hardware address, set 667 * before starting iteration for 668 * valid bssid mask. 669 */ 670 u8 mask[ETH_ALEN]; /* bssid mask */ 671 int naps; /* number of AP vifs */ 672 int nmeshes; /* number of mesh vifs */ 673 int nstations; /* number of station vifs */ 674 int nwds; /* number of WDS vifs */ 675 int nadhocs; /* number of adhoc vifs */ 676 }; 677 678 struct ath_softc { 679 struct ieee80211_hw *hw; 680 struct device *dev; 681 682 struct survey_info *cur_survey; 683 struct survey_info survey[ATH9K_NUM_CHANNELS]; 684 685 struct tasklet_struct intr_tq; 686 struct tasklet_struct bcon_tasklet; 687 struct ath_hw *sc_ah; 688 void __iomem *mem; 689 int irq; 690 spinlock_t sc_serial_rw; 691 spinlock_t sc_pm_lock; 692 spinlock_t sc_pcu_lock; 693 struct mutex mutex; 694 struct work_struct paprd_work; 695 struct work_struct hw_check_work; 696 struct work_struct hw_reset_work; 697 struct completion paprd_complete; 698 699 unsigned int hw_busy_count; 700 unsigned long sc_flags; 701 702 u32 intrstatus; 703 u16 ps_flags; /* PS_* */ 704 u16 curtxpow; 705 bool ps_enabled; 706 bool ps_idle; 707 short nbcnvifs; 708 short nvifs; 709 unsigned long ps_usecount; 710 711 struct ath_config config; 712 struct ath_rx rx; 713 struct ath_tx tx; 714 struct ath_beacon beacon; 715 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 716 717 #ifdef CONFIG_MAC80211_LEDS 718 bool led_registered; 719 char led_name[32]; 720 struct led_classdev led_cdev; 721 #endif 722 723 struct ath9k_hw_cal_data caldata; 724 int last_rssi; 725 726 #ifdef CONFIG_ATH9K_DEBUGFS 727 struct ath9k_debug debug; 728 #endif 729 struct ath_beacon_config cur_beacon_conf; 730 struct delayed_work tx_complete_work; 731 struct delayed_work hw_pll_work; 732 struct timer_list rx_poll_timer; 733 734 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 735 struct ath_btcoex btcoex; 736 struct ath_mci_coex mci_coex; 737 struct work_struct mci_work; 738 #endif 739 740 struct ath_descdma txsdma; 741 742 struct ath_ant_comb ant_comb; 743 u8 ant_tx, ant_rx; 744 struct dfs_pattern_detector *dfs_detector; 745 u32 wow_enabled; 746 747 #ifdef CONFIG_PM_SLEEP 748 atomic_t wow_got_bmiss_intr; 749 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ 750 u32 wow_intr_before_sleep; 751 #endif 752 }; 753 754 void ath9k_tasklet(unsigned long data); 755 int ath_cabq_update(struct ath_softc *); 756 757 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 758 { 759 common->bus_ops->read_cachesize(common, csz); 760 } 761 762 extern struct ieee80211_ops ath9k_ops; 763 extern int ath9k_modparam_nohwcrypt; 764 extern int led_blink; 765 extern bool is_ath9k_unloaded; 766 767 u8 ath9k_parse_mpdudensity(u8 mpdudensity); 768 irqreturn_t ath_isr(int irq, void *dev); 769 int ath9k_init_device(u16 devid, struct ath_softc *sc, 770 const struct ath_bus_ops *bus_ops); 771 void ath9k_deinit_device(struct ath_softc *sc); 772 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 773 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 774 775 bool ath9k_uses_beacons(int type); 776 777 #ifdef CONFIG_ATH9K_PCI 778 int ath_pci_init(void); 779 void ath_pci_exit(void); 780 #else 781 static inline int ath_pci_init(void) { return 0; }; 782 static inline void ath_pci_exit(void) {}; 783 #endif 784 785 #ifdef CONFIG_ATH9K_AHB 786 int ath_ahb_init(void); 787 void ath_ahb_exit(void); 788 #else 789 static inline int ath_ahb_init(void) { return 0; }; 790 static inline void ath_ahb_exit(void) {}; 791 #endif 792 793 void ath9k_ps_wakeup(struct ath_softc *sc); 794 void ath9k_ps_restore(struct ath_softc *sc); 795 796 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 797 798 void ath_start_rfkill_poll(struct ath_softc *sc); 799 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 800 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 801 struct ieee80211_vif *vif, 802 struct ath9k_vif_iter_data *iter_data); 803 804 #endif /* ATH9K_H */ 805