1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 31 /* 32 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver 33 * should rely on this file or its contents. 34 */ 35 36 struct ath_node; 37 38 /* Macro to expand scalars to 64-bit objects */ 39 40 #define ito64(x) (sizeof(x) == 1) ? \ 41 (((unsigned long long int)(x)) & (0xff)) : \ 42 (sizeof(x) == 2) ? \ 43 (((unsigned long long int)(x)) & 0xffff) : \ 44 ((sizeof(x) == 4) ? \ 45 (((unsigned long long int)(x)) & 0xffffffff) : \ 46 (unsigned long long int)(x)) 47 48 /* increment with wrap-around */ 49 #define INCR(_l, _sz) do { \ 50 (_l)++; \ 51 (_l) &= ((_sz) - 1); \ 52 } while (0) 53 54 /* decrement with wrap-around */ 55 #define DECR(_l, _sz) do { \ 56 (_l)--; \ 57 (_l) &= ((_sz) - 1); \ 58 } while (0) 59 60 #define TSF_TO_TU(_h,_l) \ 61 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 62 63 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 64 65 struct ath_config { 66 u16 txpowlimit; 67 u8 cabqReadytime; 68 }; 69 70 /*************************/ 71 /* Descriptor Management */ 72 /*************************/ 73 74 #define ATH_TXBUF_RESET(_bf) do { \ 75 (_bf)->bf_stale = false; \ 76 (_bf)->bf_lastbf = NULL; \ 77 (_bf)->bf_next = NULL; \ 78 memset(&((_bf)->bf_state), 0, \ 79 sizeof(struct ath_buf_state)); \ 80 } while (0) 81 82 #define ATH_RXBUF_RESET(_bf) do { \ 83 (_bf)->bf_stale = false; \ 84 } while (0) 85 86 /** 87 * enum buffer_type - Buffer type flags 88 * 89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 90 * @BUF_AGGR: Indicates whether the buffer can be aggregated 91 * (used in aggregation scheduling) 92 */ 93 enum buffer_type { 94 BUF_AMPDU = BIT(0), 95 BUF_AGGR = BIT(1), 96 }; 97 98 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 99 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 100 101 #define ATH_TXSTATUS_RING_SIZE 512 102 103 #define DS2PHYS(_dd, _ds) \ 104 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 105 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 106 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 107 108 struct ath_descdma { 109 void *dd_desc; 110 dma_addr_t dd_desc_paddr; 111 u32 dd_desc_len; 112 struct ath_buf *dd_bufptr; 113 }; 114 115 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 116 struct list_head *head, const char *name, 117 int nbuf, int ndesc, bool is_tx); 118 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 119 struct list_head *head); 120 121 /***********/ 122 /* RX / TX */ 123 /***********/ 124 125 #define ATH_RXBUF 512 126 #define ATH_TXBUF 512 127 #define ATH_TXBUF_RESERVE 5 128 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 129 #define ATH_TXMAXTRY 13 130 131 #define TID_TO_WME_AC(_tid) \ 132 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 133 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 134 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 135 WME_AC_VO) 136 137 #define ATH_AGGR_DELIM_SZ 4 138 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 139 /* number of delimiters for encryption padding */ 140 #define ATH_AGGR_ENCRYPTDELIM 10 141 /* minimum h/w qdepth to be sustained to maximize aggregation */ 142 #define ATH_AGGR_MIN_QDEPTH 2 143 #define ATH_AMPDU_SUBFRAME_DEFAULT 32 144 145 #define IEEE80211_SEQ_SEQ_SHIFT 4 146 #define IEEE80211_SEQ_MAX 4096 147 #define IEEE80211_WEP_IVLEN 3 148 #define IEEE80211_WEP_KIDLEN 1 149 #define IEEE80211_WEP_CRCLEN 4 150 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 151 (IEEE80211_WEP_IVLEN + \ 152 IEEE80211_WEP_KIDLEN + \ 153 IEEE80211_WEP_CRCLEN)) 154 155 /* return whether a bit at index _n in bitmap _bm is set 156 * _sz is the size of the bitmap */ 157 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 158 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 159 160 /* return block-ack bitmap index given sequence and starting sequence */ 161 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 162 163 /* return the seqno for _start + _offset */ 164 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 165 166 /* returns delimiter padding required given the packet length */ 167 #define ATH_AGGR_GET_NDELIM(_len) \ 168 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 169 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 170 171 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 172 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 173 174 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 175 176 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) 177 178 #define ATH_TX_COMPLETE_POLL_INT 1000 179 180 enum ATH_AGGR_STATUS { 181 ATH_AGGR_DONE, 182 ATH_AGGR_BAW_CLOSED, 183 ATH_AGGR_LIMITED, 184 }; 185 186 #define ATH_TXFIFO_DEPTH 8 187 struct ath_txq { 188 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 189 u32 axq_qnum; /* ath9k hardware queue number */ 190 void *axq_link; 191 struct list_head axq_q; 192 spinlock_t axq_lock; 193 u32 axq_depth; 194 u32 axq_ampdu_depth; 195 bool stopped; 196 bool axq_tx_inprogress; 197 struct list_head axq_acq; 198 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 199 u8 txq_headidx; 200 u8 txq_tailidx; 201 int pending_frames; 202 struct sk_buff_head complete_q; 203 }; 204 205 struct ath_atx_ac { 206 struct ath_txq *txq; 207 int sched; 208 struct list_head list; 209 struct list_head tid_q; 210 bool clear_ps_filter; 211 }; 212 213 struct ath_frame_info { 214 struct ath_buf *bf; 215 int framelen; 216 enum ath9k_key_type keytype; 217 u8 keyix; 218 u8 retries; 219 u8 rtscts_rate; 220 }; 221 222 struct ath_buf_state { 223 u8 bf_type; 224 u8 bfs_paprd; 225 u8 ndelim; 226 u16 seqno; 227 unsigned long bfs_paprd_timestamp; 228 }; 229 230 struct ath_buf { 231 struct list_head list; 232 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 233 an aggregate) */ 234 struct ath_buf *bf_next; /* next subframe in the aggregate */ 235 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 236 void *bf_desc; /* virtual addr of desc */ 237 dma_addr_t bf_daddr; /* physical addr of desc */ 238 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 239 bool bf_stale; 240 struct ath_buf_state bf_state; 241 }; 242 243 struct ath_atx_tid { 244 struct list_head list; 245 struct sk_buff_head buf_q; 246 struct ath_node *an; 247 struct ath_atx_ac *ac; 248 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 249 int bar_index; 250 u16 seq_start; 251 u16 seq_next; 252 u16 baw_size; 253 int tidno; 254 int baw_head; /* first un-acked tx buffer */ 255 int baw_tail; /* next unused tx buffer slot */ 256 int sched; 257 int paused; 258 u8 state; 259 }; 260 261 struct ath_node { 262 #ifdef CONFIG_ATH9K_DEBUGFS 263 struct list_head list; /* for sc->nodes */ 264 #endif 265 struct ieee80211_sta *sta; /* station struct we're part of */ 266 struct ieee80211_vif *vif; /* interface with which we're associated */ 267 struct ath_atx_tid tid[WME_NUM_TID]; 268 struct ath_atx_ac ac[WME_NUM_AC]; 269 int ps_key; 270 271 u16 maxampdu; 272 u8 mpdudensity; 273 274 bool sleeping; 275 }; 276 277 #define AGGR_CLEANUP BIT(1) 278 #define AGGR_ADDBA_COMPLETE BIT(2) 279 #define AGGR_ADDBA_PROGRESS BIT(3) 280 281 struct ath_tx_control { 282 struct ath_txq *txq; 283 struct ath_node *an; 284 u8 paprd; 285 struct ieee80211_sta *sta; 286 }; 287 288 #define ATH_TX_ERROR 0x01 289 290 /** 291 * @txq_map: Index is mac80211 queue number. This is 292 * not necessarily the same as the hardware queue number 293 * (axq_qnum). 294 */ 295 struct ath_tx { 296 u16 seq_no; 297 u32 txqsetup; 298 spinlock_t txbuflock; 299 struct list_head txbuf; 300 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 301 struct ath_descdma txdma; 302 struct ath_txq *txq_map[WME_NUM_AC]; 303 u32 txq_max_pending[WME_NUM_AC]; 304 u16 max_aggr_framelen[WME_NUM_AC][4][32]; 305 }; 306 307 struct ath_rx_edma { 308 struct sk_buff_head rx_fifo; 309 u32 rx_fifo_hwsize; 310 }; 311 312 struct ath_rx { 313 u8 defant; 314 u8 rxotherant; 315 u32 *rxlink; 316 u32 num_pkts; 317 unsigned int rxfilter; 318 spinlock_t rxbuflock; 319 struct list_head rxbuf; 320 struct ath_descdma rxdma; 321 struct ath_buf *rx_bufptr; 322 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 323 324 struct sk_buff *frag; 325 }; 326 327 int ath_startrecv(struct ath_softc *sc); 328 bool ath_stoprecv(struct ath_softc *sc); 329 void ath_flushrecv(struct ath_softc *sc); 330 u32 ath_calcrxfilter(struct ath_softc *sc); 331 int ath_rx_init(struct ath_softc *sc, int nbufs); 332 void ath_rx_cleanup(struct ath_softc *sc); 333 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 334 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 335 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); 336 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); 337 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); 338 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 339 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 340 void ath_draintxq(struct ath_softc *sc, 341 struct ath_txq *txq, bool retry_tx); 342 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 343 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 344 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 345 int ath_tx_init(struct ath_softc *sc, int nbufs); 346 void ath_tx_cleanup(struct ath_softc *sc); 347 int ath_txq_update(struct ath_softc *sc, int qnum, 348 struct ath9k_tx_queue_info *q); 349 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); 350 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 351 struct ath_tx_control *txctl); 352 void ath_tx_tasklet(struct ath_softc *sc); 353 void ath_tx_edma_tasklet(struct ath_softc *sc); 354 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 355 u16 tid, u16 *ssn); 356 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 357 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 358 359 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 360 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 361 struct ath_node *an); 362 363 /********/ 364 /* VIFs */ 365 /********/ 366 367 struct ath_vif { 368 int av_bslot; 369 bool primary_sta_vif; 370 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 371 struct ath_buf *av_bcbuf; 372 }; 373 374 /*******************/ 375 /* Beacon Handling */ 376 /*******************/ 377 378 /* 379 * Regardless of the number of beacons we stagger, (i.e. regardless of the 380 * number of BSSIDs) if a given beacon does not go out even after waiting this 381 * number of beacon intervals, the game's up. 382 */ 383 #define BSTUCK_THRESH 9 384 #define ATH_BCBUF 8 385 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 386 #define ATH_DEFAULT_BMISS_LIMIT 10 387 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 388 389 struct ath_beacon_config { 390 int beacon_interval; 391 u16 listen_interval; 392 u16 dtim_period; 393 u16 bmiss_timeout; 394 u8 dtim_count; 395 bool enable_beacon; 396 }; 397 398 struct ath_beacon { 399 enum { 400 OK, /* no change needed */ 401 UPDATE, /* update pending */ 402 COMMIT /* beacon sent, commit change */ 403 } updateslot; /* slot time update fsm */ 404 405 u32 beaconq; 406 u32 bmisscnt; 407 u32 bc_tstamp; 408 struct ieee80211_vif *bslot[ATH_BCBUF]; 409 int slottime; 410 int slotupdate; 411 struct ath9k_tx_queue_info beacon_qi; 412 struct ath_descdma bdma; 413 struct ath_txq *cabq; 414 struct list_head bbuf; 415 416 bool tx_processed; 417 bool tx_last; 418 }; 419 420 void ath9k_beacon_tasklet(unsigned long data); 421 bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 422 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, 423 u32 changed); 424 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 425 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 426 void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif); 427 void ath9k_set_beacon(struct ath_softc *sc); 428 429 /*******************/ 430 /* Link Monitoring */ 431 /*******************/ 432 433 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 434 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 435 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 436 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 437 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 438 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 439 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 440 441 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 442 #define ATH_PLL_WORK_INTERVAL 100 443 444 void ath_tx_complete_poll_work(struct work_struct *work); 445 void ath_reset_work(struct work_struct *work); 446 void ath_hw_check(struct work_struct *work); 447 void ath_hw_pll_work(struct work_struct *work); 448 void ath_rx_poll(unsigned long data); 449 void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); 450 void ath_paprd_calibrate(struct work_struct *work); 451 void ath_ani_calibrate(unsigned long data); 452 void ath_start_ani(struct ath_softc *sc); 453 void ath_stop_ani(struct ath_softc *sc); 454 void ath_check_ani(struct ath_softc *sc); 455 int ath_update_survey_stats(struct ath_softc *sc); 456 void ath_update_survey_nf(struct ath_softc *sc, int channel); 457 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); 458 459 /**********/ 460 /* BTCOEX */ 461 /**********/ 462 463 enum bt_op_flags { 464 BT_OP_PRIORITY_DETECTED, 465 BT_OP_SCAN, 466 }; 467 468 struct ath_btcoex { 469 bool hw_timer_enabled; 470 spinlock_t btcoex_lock; 471 struct timer_list period_timer; /* Timer for BT period */ 472 u32 bt_priority_cnt; 473 unsigned long bt_priority_time; 474 unsigned long op_flags; 475 int bt_stomp_type; /* Types of BT stomping */ 476 u32 btcoex_no_stomp; /* in usec */ 477 u32 btcoex_period; /* in msec */ 478 u32 btscan_no_stomp; /* in usec */ 479 u32 duty_cycle; 480 u32 bt_wait_time; 481 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 482 struct ath_mci_profile mci; 483 }; 484 485 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 486 int ath9k_init_btcoex(struct ath_softc *sc); 487 void ath9k_deinit_btcoex(struct ath_softc *sc); 488 void ath9k_start_btcoex(struct ath_softc *sc); 489 void ath9k_stop_btcoex(struct ath_softc *sc); 490 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 491 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 492 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 493 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 494 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); 495 #else 496 static inline int ath9k_init_btcoex(struct ath_softc *sc) 497 { 498 return 0; 499 } 500 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 501 { 502 } 503 static inline void ath9k_start_btcoex(struct ath_softc *sc) 504 { 505 } 506 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 507 { 508 } 509 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 510 u32 status) 511 { 512 } 513 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 514 u32 max_4ms_framelen) 515 { 516 return 0; 517 } 518 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 519 { 520 } 521 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 522 523 struct ath9k_wow_pattern { 524 u8 pattern_bytes[MAX_PATTERN_SIZE]; 525 u8 mask_bytes[MAX_PATTERN_SIZE]; 526 u32 pattern_len; 527 }; 528 529 /********************/ 530 /* LED Control */ 531 /********************/ 532 533 #define ATH_LED_PIN_DEF 1 534 #define ATH_LED_PIN_9287 8 535 #define ATH_LED_PIN_9300 10 536 #define ATH_LED_PIN_9485 6 537 #define ATH_LED_PIN_9462 4 538 539 #ifdef CONFIG_MAC80211_LEDS 540 void ath_init_leds(struct ath_softc *sc); 541 void ath_deinit_leds(struct ath_softc *sc); 542 void ath_fill_led_pin(struct ath_softc *sc); 543 #else 544 static inline void ath_init_leds(struct ath_softc *sc) 545 { 546 } 547 548 static inline void ath_deinit_leds(struct ath_softc *sc) 549 { 550 } 551 static inline void ath_fill_led_pin(struct ath_softc *sc) 552 { 553 } 554 #endif 555 556 /*******************************/ 557 /* Antenna diversity/combining */ 558 /*******************************/ 559 560 #define ATH_ANT_RX_CURRENT_SHIFT 4 561 #define ATH_ANT_RX_MAIN_SHIFT 2 562 #define ATH_ANT_RX_MASK 0x3 563 564 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 565 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 566 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 567 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 568 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 569 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 570 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 571 572 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 573 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 574 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 575 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 576 577 enum ath9k_ant_div_comb_lna_conf { 578 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, 579 ATH_ANT_DIV_COMB_LNA2, 580 ATH_ANT_DIV_COMB_LNA1, 581 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, 582 }; 583 584 struct ath_ant_comb { 585 u16 count; 586 u16 total_pkt_count; 587 bool scan; 588 bool scan_not_start; 589 int main_total_rssi; 590 int alt_total_rssi; 591 int alt_recv_cnt; 592 int main_recv_cnt; 593 int rssi_lna1; 594 int rssi_lna2; 595 int rssi_add; 596 int rssi_sub; 597 int rssi_first; 598 int rssi_second; 599 int rssi_third; 600 bool alt_good; 601 int quick_scan_cnt; 602 int main_conf; 603 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 604 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 605 bool first_ratio; 606 bool second_ratio; 607 unsigned long scan_start_time; 608 }; 609 610 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 611 void ath_ant_comb_update(struct ath_softc *sc); 612 613 /********************/ 614 /* Main driver core */ 615 /********************/ 616 617 /* 618 * Default cache line size, in bytes. 619 * Used when PCI device not fully initialized by bootrom/BIOS 620 */ 621 #define DEFAULT_CACHELINE 32 622 #define ATH_REGCLASSIDS_MAX 10 623 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 624 #define ATH_MAX_SW_RETRIES 30 625 #define ATH_CHAN_MAX 255 626 627 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 628 #define ATH_RATE_DUMMY_MARKER 0 629 630 enum sc_op_flags { 631 SC_OP_INVALID, 632 SC_OP_BEACONS, 633 SC_OP_RXFLUSH, 634 SC_OP_ANI_RUN, 635 SC_OP_PRIM_STA_VIF, 636 SC_OP_HW_RESET, 637 }; 638 639 /* Powersave flags */ 640 #define PS_WAIT_FOR_BEACON BIT(0) 641 #define PS_WAIT_FOR_CAB BIT(1) 642 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 643 #define PS_WAIT_FOR_TX_ACK BIT(3) 644 #define PS_BEACON_SYNC BIT(4) 645 646 struct ath_rate_table; 647 648 struct ath9k_vif_iter_data { 649 const u8 *hw_macaddr; /* phy's hardware address, set 650 * before starting iteration for 651 * valid bssid mask. 652 */ 653 u8 mask[ETH_ALEN]; /* bssid mask */ 654 int naps; /* number of AP vifs */ 655 int nmeshes; /* number of mesh vifs */ 656 int nstations; /* number of station vifs */ 657 int nwds; /* number of WDS vifs */ 658 int nadhocs; /* number of adhoc vifs */ 659 }; 660 661 struct ath_softc { 662 struct ieee80211_hw *hw; 663 struct device *dev; 664 665 struct survey_info *cur_survey; 666 struct survey_info survey[ATH9K_NUM_CHANNELS]; 667 668 struct tasklet_struct intr_tq; 669 struct tasklet_struct bcon_tasklet; 670 struct ath_hw *sc_ah; 671 void __iomem *mem; 672 int irq; 673 spinlock_t sc_serial_rw; 674 spinlock_t sc_pm_lock; 675 spinlock_t sc_pcu_lock; 676 struct mutex mutex; 677 struct work_struct paprd_work; 678 struct work_struct hw_check_work; 679 struct work_struct hw_reset_work; 680 struct completion paprd_complete; 681 682 unsigned int hw_busy_count; 683 unsigned long sc_flags; 684 685 u32 intrstatus; 686 u16 ps_flags; /* PS_* */ 687 u16 curtxpow; 688 bool ps_enabled; 689 bool ps_idle; 690 short nbcnvifs; 691 short nvifs; 692 unsigned long ps_usecount; 693 694 struct ath_config config; 695 struct ath_rx rx; 696 struct ath_tx tx; 697 struct ath_beacon beacon; 698 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 699 700 #ifdef CONFIG_MAC80211_LEDS 701 bool led_registered; 702 char led_name[32]; 703 struct led_classdev led_cdev; 704 #endif 705 706 struct ath9k_hw_cal_data caldata; 707 int last_rssi; 708 709 #ifdef CONFIG_ATH9K_DEBUGFS 710 struct ath9k_debug debug; 711 spinlock_t nodes_lock; 712 struct list_head nodes; /* basically, stations */ 713 unsigned int tx_complete_poll_work_seen; 714 #endif 715 struct ath_beacon_config cur_beacon_conf; 716 struct delayed_work tx_complete_work; 717 struct delayed_work hw_pll_work; 718 struct timer_list rx_poll_timer; 719 720 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 721 struct ath_btcoex btcoex; 722 struct ath_mci_coex mci_coex; 723 struct work_struct mci_work; 724 #endif 725 726 struct ath_descdma txsdma; 727 728 struct ath_ant_comb ant_comb; 729 u8 ant_tx, ant_rx; 730 struct dfs_pattern_detector *dfs_detector; 731 u32 wow_enabled; 732 733 #ifdef CONFIG_PM_SLEEP 734 atomic_t wow_got_bmiss_intr; 735 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ 736 u32 wow_intr_before_sleep; 737 #endif 738 }; 739 740 void ath9k_tasklet(unsigned long data); 741 int ath_cabq_update(struct ath_softc *); 742 743 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 744 { 745 common->bus_ops->read_cachesize(common, csz); 746 } 747 748 extern struct ieee80211_ops ath9k_ops; 749 extern int ath9k_modparam_nohwcrypt; 750 extern int led_blink; 751 extern bool is_ath9k_unloaded; 752 753 u8 ath9k_parse_mpdudensity(u8 mpdudensity); 754 irqreturn_t ath_isr(int irq, void *dev); 755 int ath9k_init_device(u16 devid, struct ath_softc *sc, 756 const struct ath_bus_ops *bus_ops); 757 void ath9k_deinit_device(struct ath_softc *sc); 758 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 759 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 760 761 bool ath9k_uses_beacons(int type); 762 763 #ifdef CONFIG_ATH9K_PCI 764 int ath_pci_init(void); 765 void ath_pci_exit(void); 766 #else 767 static inline int ath_pci_init(void) { return 0; }; 768 static inline void ath_pci_exit(void) {}; 769 #endif 770 771 #ifdef CONFIG_ATH9K_AHB 772 int ath_ahb_init(void); 773 void ath_ahb_exit(void); 774 #else 775 static inline int ath_ahb_init(void) { return 0; }; 776 static inline void ath_ahb_exit(void) {}; 777 #endif 778 779 void ath9k_ps_wakeup(struct ath_softc *sc); 780 void ath9k_ps_restore(struct ath_softc *sc); 781 782 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 783 784 void ath_start_rfkill_poll(struct ath_softc *sc); 785 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 786 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 787 struct ieee80211_vif *vif, 788 struct ath9k_vif_iter_data *iter_data); 789 790 #endif /* ATH9K_H */ 791