1 /* 2 * Copyright (c) 2002-2010 Atheros Communications, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef AR9003_PHY_H 18 #define AR9003_PHY_H 19 20 /* 21 * Channel Register Map 22 */ 23 #define AR_CHAN_BASE 0x9800 24 25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0) 26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4) 27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8) 28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc) 29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10) 30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14) 31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18) 32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c) 33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc) 34 #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0) 35 36 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 37 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 38 39 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 40 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 41 42 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000 43 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30 44 45 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000 46 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31 47 48 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000 49 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26 50 51 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */ 52 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17 53 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF 54 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 55 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100 56 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8 57 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000 58 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 59 60 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000 61 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29 62 63 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000 64 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31 65 66 #define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20) 67 68 #define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24) 69 #define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28) 70 #define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c) 71 72 #define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30) 73 #define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34) 74 #define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38) 75 #define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c) 76 #define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80) 77 #define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84) 78 79 #define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0) 80 #define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4) 81 #define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0) 82 #define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4) 83 #define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8) 84 #define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc) 85 86 /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */ 87 #define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10) 88 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10) 89 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8) 90 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8) 91 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8) 92 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8) 93 94 #define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0) 95 #define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4) 96 #define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8) 97 #define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300) 98 99 /* 100 * Channel Field Definitions 101 */ 102 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000 103 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff 104 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 105 #define AR_PHY_TIMING3_DSC_MAN_S 17 106 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 107 #define AR_PHY_TIMING3_DSC_EXP_S 13 108 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000 109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12 110 #define AR_PHY_TIMING4_DO_CAL 0x10000 111 112 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000 113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28 114 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000 115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29 116 117 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000 118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30 119 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000 120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31 121 122 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 123 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 124 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 125 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 127 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 129 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 131 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 132 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 133 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 134 #define AR_PHY_SFCORR_M1_THRESH_S 17 135 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 136 #define AR_PHY_SFCORR_M2_THRESH_S 24 137 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 138 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 139 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 140 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 141 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 143 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 145 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000 146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28 147 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 148 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 149 #define AR_PHY_EXT_CCA_THRESH62_S 16 150 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000 151 #define AR_PHY_EXT_MINCCA_PWR_S 16 152 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L 153 #define AR_PHY_EXT_CYCPWR_THR1_S 9 154 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 155 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 156 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 157 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0 158 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000 159 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16 160 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16) 161 #define AR_PHY_TIMING5_RSSI_THR1A_S 16 162 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15) 163 #define AR_PHY_RADAR_0_ENA 0x00000001 164 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 165 #define AR_PHY_RADAR_0_INBAND 0x0000003e 166 #define AR_PHY_RADAR_0_INBAND_S 1 167 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 168 #define AR_PHY_RADAR_0_PRSSI_S 6 169 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 170 #define AR_PHY_RADAR_0_HEIGHT_S 12 171 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 172 #define AR_PHY_RADAR_0_RRSSI_S 18 173 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 174 #define AR_PHY_RADAR_0_FIRPWR_S 24 175 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 176 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 177 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 178 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 179 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 180 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 181 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 182 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 183 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 184 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF 185 #define AR_PHY_RADAR_1_MAXLEN_S 0 186 #define AR_PHY_RADAR_EXT_ENA 0x00004000 187 #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000 188 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15 189 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000 190 #define AR_PHY_RADAR_LB_DC_CAP_S 23 191 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6) 192 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6 193 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12) 194 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12 195 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19 196 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f 197 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0 198 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5 199 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008 200 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3 201 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F 202 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0 203 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80 204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7 205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000 206 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000 207 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15 208 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000 209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22 210 211 /* 212 * MRC Register Map 213 */ 214 #define AR_MRC_BASE 0x9c00 215 216 #define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0) 217 #define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4) 218 #define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8) 219 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc) 220 #define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10) 221 #define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14) 222 #define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18) 223 #define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c) 224 #define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20) 225 226 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0 227 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5 228 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F 229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0 230 231 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0 232 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5 233 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F 234 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0 235 236 /* 237 * MRC Feild Definitions 238 */ 239 #define AR_PHY_SGI_DSC_MAN 0x0007FFF0 240 #define AR_PHY_SGI_DSC_MAN_S 4 241 #define AR_PHY_SGI_DSC_EXP 0x0000000F 242 #define AR_PHY_SGI_DSC_EXP_S 0 243 /* 244 * BBB Register Map 245 */ 246 #define AR_BBB_BASE 0x9d00 247 248 /* 249 * AGC Register Map 250 */ 251 #define AR_AGC_BASE 0x9e00 252 253 #define AR_PHY_SETTLING (AR_AGC_BASE + 0x0) 254 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4) 255 #define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8) 256 #define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc) 257 #define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10) 258 #define AR_PHY_AGC (AR_AGC_BASE + 0x14) 259 #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18) 260 #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c) 261 #define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20) 262 #define AR_PHY_RESTART (AR_AGC_BASE + 0x24) 263 #define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28) 264 #define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c) 265 #define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30) 266 #define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34) 267 #define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38) 268 #define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c) 269 #define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40) 270 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44) 271 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48) 272 #define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180) 273 #define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184) 274 #define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0) 275 #define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4) 276 #define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8) 277 278 #define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc) 279 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe 280 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1 281 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000 282 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29 283 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001 284 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0 285 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00 286 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9 287 288 #define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0) 289 #define AR_PHY_MRC_CCK_ENABLE 0x00000001 290 #define AR_PHY_MRC_CCK_ENABLE_S 0 291 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002 292 #define AR_PHY_MRC_CCK_MUX_REG_S 1 293 294 #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200) 295 296 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110 297 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115 298 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125 299 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125 300 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 301 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 302 303 /* 304 * AGC Field Definitions 305 */ 306 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000 307 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18 308 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00 309 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10 310 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F 311 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0 312 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000 313 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17 314 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000 315 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12 316 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0 317 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6 318 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F 319 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0 320 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 321 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 322 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 323 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 324 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 325 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 326 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 327 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 328 #define AR_PHY_SETTLING_SWITCH 0x00003F80 329 #define AR_PHY_SETTLING_SWITCH_S 7 330 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF 331 #define AR_PHY_DESIRED_SZ_ADC_S 0 332 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 333 #define AR_PHY_DESIRED_SZ_PGA_S 8 334 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 335 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 336 #define AR_PHY_MINCCA_PWR 0x1FF00000 337 #define AR_PHY_MINCCA_PWR_S 20 338 #define AR_PHY_CCA_THRESH62 0x0007F000 339 #define AR_PHY_CCA_THRESH62_S 12 340 #define AR9280_PHY_MINCCA_PWR 0x1FF00000 341 #define AR9280_PHY_MINCCA_PWR_S 20 342 #define AR9280_PHY_CCA_THRESH62 0x000FF000 343 #define AR9280_PHY_CCA_THRESH62_S 12 344 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 345 #define AR_PHY_EXT_CCA0_THRESH62_S 0 346 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 347 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 348 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 349 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 350 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 351 352 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 353 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9 354 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 355 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 356 357 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000 358 #define AR_PHY_AGC_COARSE_LOW 0x00007F80 359 #define AR_PHY_AGC_COARSE_LOW_S 7 360 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000 361 #define AR_PHY_AGC_COARSE_HIGH_S 15 362 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F 363 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0 364 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 365 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 366 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 367 #define AR_PHY_FIND_SIG_FIRPWR_S 18 368 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25 369 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6) 370 #define AR_PHY_FIND_SIG_RELPWR_S 6 371 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11 372 #define AR_PHY_FIND_SIG_RELSTEP 0x1f 373 #define AR_PHY_FIND_SIG_RELSTEP_S 0 374 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5 375 #define AR_PHY_RESTART_DIV_GC 0x001C0000 376 #define AR_PHY_RESTART_DIV_GC_S 18 377 #define AR_PHY_RESTART_ENA 0x01 378 #define AR_PHY_DC_RESTART_DIS 0x40000000 379 380 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000 381 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24 382 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000 383 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16 384 385 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000 386 #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24 387 388 /* 389 * SM Register Map 390 */ 391 #define AR_SM_BASE 0xa200 392 393 #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0) 394 #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4) 395 #define AR_PHY_MODE (AR_SM_BASE + 0x8) 396 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc) 397 #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20) 398 #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24) 399 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28) 400 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c) 401 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30) 402 #define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34) 403 #define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38) 404 #define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c) 405 #define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40) 406 #define AR_PHY_RIFS (AR_SM_BASE + 0x44) 407 #define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50) 408 #define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54) 409 410 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64) 411 #define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80) 412 #define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84) 413 #define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88) 414 #define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c) 415 #define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0) 416 #define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0) 417 #define AR_PHY_CALMODE (AR_SM_BASE + 0xc8) 418 #define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc) 419 #define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0) 420 #define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4) 421 #define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8) 422 #define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100) 423 #define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140) 424 #define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144) 425 #define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148) 426 #define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c) 427 #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150) 428 #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158) 429 430 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00 431 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10 432 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF 433 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 434 435 #define AR_PHY_TEST (AR_SM_BASE + 0x160) 436 437 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000 438 #define AR_PHY_TEST_BBB_OBS_SEL_S 19 439 440 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23 441 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S) 442 443 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000 444 #define AR_PHY_TEST_CHAIN_SEL_S 30 445 446 #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164) 447 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 448 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 449 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C 450 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2 451 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60 452 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5 453 #define AR_PHY_TEST_CTL_TSTADC_EN 0x100 454 #define AR_PHY_TEST_CTL_TSTADC_EN_S 8 455 #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 456 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 457 458 459 #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168) 460 461 #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c) 462 463 #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170) 464 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008 465 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3 466 467 #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174) 468 #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178) 469 #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c) 470 #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180) 471 #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190) 472 #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194) 473 474 #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4) 475 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8) 476 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac) 477 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0) 478 479 #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0) 480 #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4) 481 482 #define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8) 483 #define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e 484 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1 485 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001 486 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0 487 488 #define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204) 489 #define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208) 490 #define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c) 491 492 #define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220) 493 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) 494 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220) 495 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000 496 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16 497 498 #define AR_PHY_TPC_12 (AR_SM_BASE + 0x224) 499 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000 500 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25 501 502 #define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c) 503 #define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff 504 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0 505 #define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00 506 #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S 8 507 508 #define AR_PHY_TPC_19 (AR_SM_BASE + 0x240) 509 #define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000 510 #define AR_PHY_TPC_19_ALPHA_VOLT_S 16 511 #define AR_PHY_TPC_19_ALPHA_THERM 0xff 512 #define AR_PHY_TPC_19_ALPHA_THERM_S 0 513 514 #define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258) 515 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001 516 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0 517 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e 518 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1 519 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030 520 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4 521 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0 522 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6 523 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00 524 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10 525 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000 526 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14 527 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000 528 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18 529 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000 530 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22 531 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000 532 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24 533 534 535 #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280) 536 537 #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300) 538 539 #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448) 540 #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440) 541 #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c) 542 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450) 543 544 #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0) 545 #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4) 546 #define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8) 547 #define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc) 548 #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0) 549 #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4) 550 #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc) 551 552 #define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248) 553 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff 554 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0 555 556 #define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254) 557 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff 558 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0 559 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00 560 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8 561 562 563 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c 564 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002 565 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1 566 #define AR_PHY_65NM_CH0_SYNTH7 0x16098 567 #define AR_PHY_65NM_CH0_BIAS1 0x160c0 568 #define AR_PHY_65NM_CH0_BIAS2 0x160c4 569 #define AR_PHY_65NM_CH0_BIAS4 0x160cc 570 #define AR_PHY_65NM_CH0_RXTX4 0x1610c 571 #define AR_PHY_65NM_CH0_THERM 0x16290 572 573 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 574 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 575 #define AR_PHY_65NM_CH0_THERM_START 0x20000000 576 #define AR_PHY_65NM_CH0_THERM_START_S 29 577 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00 578 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8 579 580 #define AR_PHY_65NM_CH0_RXTX1 0x16100 581 #define AR_PHY_65NM_CH0_RXTX2 0x16104 582 #define AR_PHY_65NM_CH1_RXTX1 0x16500 583 #define AR_PHY_65NM_CH1_RXTX2 0x16504 584 #define AR_PHY_65NM_CH2_RXTX1 0x16900 585 #define AR_PHY_65NM_CH2_RXTX2 0x16904 586 587 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000 588 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19 589 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000 590 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22 591 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000 592 #define AR_PHY_LNAGAIN_LONG_SHIFT_S 29 593 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000 594 #define AR_PHY_MXRGAIN_LONG_SHIFT_S 24 595 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000 596 #define AR_PHY_VGAGAIN_LONG_SHIFT_S 26 597 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001 598 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0 599 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002 600 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1 601 602 /* 603 * SM Field Definitions 604 */ 605 #define AR_PHY_CL_CAL_ENABLE 0x00000002 606 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 607 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 608 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 609 610 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000 611 612 #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000 613 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20 614 615 #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */ 616 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */ 617 #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */ 618 #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */ 619 #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */ 620 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ 621 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ 622 #define AR_PHY_GC_DYN2040_PRI_CH_S 4 623 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ 624 #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */ 625 #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ 626 #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ 627 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ 628 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */ 629 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */ 630 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ 631 632 #define AR_PHY_CALMODE_IQ 0x00000000 633 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 634 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 635 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 636 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 637 #define AR_PHY_MODE_OFDM 0x00000000 638 #define AR_PHY_MODE_CCK 0x00000001 639 #define AR_PHY_MODE_DYNAMIC 0x00000004 640 #define AR_PHY_MODE_DYNAMIC_S 2 641 #define AR_PHY_MODE_HALF 0x00000020 642 #define AR_PHY_MODE_QUARTER 0x00000040 643 #define AR_PHY_MAC_CLK_MODE 0x00000080 644 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100 645 #define AR_PHY_MODE_SVD_HALF 0x00000200 646 #define AR_PHY_ACTIVE_EN 0x00000001 647 #define AR_PHY_ACTIVE_DIS 0x00000000 648 #define AR_PHY_FORCE_XPA_CFG 0x000000001 649 #define AR_PHY_FORCE_XPA_CFG_S 0 650 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000 651 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24 652 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000 653 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16 654 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00 655 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8 656 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF 657 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0 658 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 659 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 660 #define AR_PHY_TX_END_DATA_START 0x000000FF 661 #define AR_PHY_TX_END_DATA_START_S 0 662 #define AR_PHY_TX_END_PA_ON 0x0000FF00 663 #define AR_PHY_TX_END_PA_ON_S 8 664 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 665 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 666 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 667 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 668 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 669 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 670 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 671 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 672 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 673 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 674 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 675 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 676 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 677 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 678 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 679 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 680 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 681 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 682 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e 683 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1 684 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001 685 #define AR_PHY_TXGAIN_FORCE 0x00000001 686 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00 687 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10 688 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000 689 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14 690 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000 691 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22 692 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0 693 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6 694 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e 695 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1 696 697 #define AR_PHY_POWER_TX_RATE1 0x9934 698 #define AR_PHY_POWER_TX_RATE2 0x9938 699 #define AR_PHY_POWER_TX_RATE_MAX 0x993c 700 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 701 #define PHY_AGC_CLR 0x10000000 702 #define RFSILENT_BB 0x00002000 703 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF 704 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800 705 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 706 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 707 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF 708 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 709 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 710 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0 711 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 712 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 713 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 714 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 715 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 716 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 717 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 718 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 719 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 720 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 721 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 722 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000 723 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18 724 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001 725 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0 726 727 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001 728 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff 729 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0 730 731 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 732 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 733 734 /* 735 * Channel 1 Register Map 736 */ 737 #define AR_CHAN1_BASE 0xa800 738 739 #define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30) 740 #define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0) 741 #define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4) 742 743 #define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8) 744 #define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300) 745 #define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc) 746 747 /* 748 * Channel 1 Field Definitions 749 */ 750 #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 751 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16 752 753 /* 754 * AGC 1 Register Map 755 */ 756 #define AR_AGC1_BASE 0xae00 757 758 #define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4) 759 #define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18) 760 #define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c) 761 #define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20) 762 #define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180) 763 #define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184) 764 #define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200) 765 766 /* 767 * AGC 1 Field Definitions 768 */ 769 #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000 770 #define AR_PHY_CH1_MINCCA_PWR_S 20 771 772 /* 773 * SM 1 Register Map 774 */ 775 #define AR_SM1_BASE 0xb200 776 777 #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84) 778 #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0) 779 #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4) 780 #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100) 781 #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180) 782 #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204) 783 #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208) 784 #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c) 785 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) 786 #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240) 787 #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c) 788 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 (AR_SM1_BASE + 0x450) 789 790 /* 791 * Channel 2 Register Map 792 */ 793 #define AR_CHAN2_BASE 0xb800 794 795 #define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30) 796 #define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0) 797 #define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4) 798 799 #define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8) 800 #define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300) 801 #define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc) 802 803 /* 804 * Channel 2 Field Definitions 805 */ 806 #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000 807 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16 808 /* 809 * AGC 2 Register Map 810 */ 811 #define AR_AGC2_BASE 0xbe00 812 813 #define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4) 814 #define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18) 815 #define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c) 816 #define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20) 817 #define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180) 818 819 /* 820 * AGC 2 Field Definitions 821 */ 822 #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000 823 #define AR_PHY_CH2_MINCCA_PWR_S 20 824 825 /* 826 * SM 2 Register Map 827 */ 828 #define AR_SM2_BASE 0xc200 829 830 #define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84) 831 #define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0) 832 #define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4) 833 #define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100) 834 #define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180) 835 #define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204) 836 #define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208) 837 #define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c) 838 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220) 839 #define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240) 840 #define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c) 841 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 (AR_SM2_BASE + 0x450) 842 843 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001 844 845 /* 846 * AGC 3 Register Map 847 */ 848 #define AR_AGC3_BASE 0xce00 849 850 #define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180) 851 852 /* 853 * Misc helper defines 854 */ 855 #define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE) 856 857 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 858 #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) 859 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 860 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 861 862 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 863 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 864 #define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i))) 865 866 #define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 867 #define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 868 #define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 869 #define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i))) 870 #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) 871 #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) 872 #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) 873 #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i))) 874 875 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE 0x00000001 876 #define AR_PHY_WATCHDOG_IDLE_ENABLE 0x00000002 877 #define AR_PHY_WATCHDOG_IDLE_MASK 0xFFFF0000 878 #define AR_PHY_WATCHDOG_NON_IDLE_MASK 0x0000FFFC 879 880 #define AR_PHY_WATCHDOG_RST_ENABLE 0x00000002 881 #define AR_PHY_WATCHDOG_IRQ_ENABLE 0x00000004 882 #define AR_PHY_WATCHDOG_CNTL2_MASK 0xFFFFFFF9 883 884 #define AR_PHY_WATCHDOG_INFO 0x00000007 885 #define AR_PHY_WATCHDOG_INFO_S 0 886 #define AR_PHY_WATCHDOG_DET_HANG 0x00000008 887 #define AR_PHY_WATCHDOG_DET_HANG_S 3 888 #define AR_PHY_WATCHDOG_RADAR_SM 0x000000F0 889 #define AR_PHY_WATCHDOG_RADAR_SM_S 4 890 #define AR_PHY_WATCHDOG_RX_OFDM_SM 0x00000F00 891 #define AR_PHY_WATCHDOG_RX_OFDM_SM_S 8 892 #define AR_PHY_WATCHDOG_RX_CCK_SM 0x0000F000 893 #define AR_PHY_WATCHDOG_RX_CCK_SM_S 12 894 #define AR_PHY_WATCHDOG_TX_OFDM_SM 0x000F0000 895 #define AR_PHY_WATCHDOG_TX_OFDM_SM_S 16 896 #define AR_PHY_WATCHDOG_TX_CCK_SM 0x00F00000 897 #define AR_PHY_WATCHDOG_TX_CCK_SM_S 20 898 #define AR_PHY_WATCHDOG_AGC_SM 0x0F000000 899 #define AR_PHY_WATCHDOG_AGC_SM_S 24 900 #define AR_PHY_WATCHDOG_SRCH_SM 0xF0000000 901 #define AR_PHY_WATCHDOG_SRCH_SM_S 28 902 903 #define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008 904 905 /* 906 * PAPRD registers 907 */ 908 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64) 909 910 #define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4) 911 #define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff 912 #define AR_PHY_PAPRD_AM2AM_MASK_S 0 913 914 #define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8) 915 #define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff 916 #define AR_PHY_PAPRD_AM2PM_MASK_S 0 917 918 #define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec) 919 #define AR_PHY_PAPRD_HT40_MASK 0x01ffffff 920 #define AR_PHY_PAPRD_HT40_MASK_S 0 921 922 #define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0) 923 #define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0) 924 #define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0) 925 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001 926 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 0 927 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x00000002 928 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S 1 929 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf8000000 930 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27 931 932 #define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4) 933 #define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4) 934 #define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4) 935 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001 936 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 0 937 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x00000002 938 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S 1 939 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x00000004 940 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S 2 941 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f8 942 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S 3 943 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe00 944 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S 9 945 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000 946 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17 947 948 #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + 0x490) 949 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001 950 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0 951 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e 952 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1 953 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x00000100 954 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8 955 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x00000200 956 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9 957 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x00000400 958 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10 959 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x00000800 960 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11 961 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000 962 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12 963 964 #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + 0x494) 965 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF 966 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0 967 968 #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + 0x498) 969 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f 970 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0 971 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0 972 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6 973 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f000 974 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12 975 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e0000 976 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17 977 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f00000 978 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20 979 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f000000 980 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24 981 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000 982 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29 983 984 #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + 0x49c) 985 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000 986 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16 987 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000 988 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12 989 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff 990 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0 991 992 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100) 993 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104) 994 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108) 995 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c) 996 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110) 997 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114) 998 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118) 999 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c) 1000 #define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF 1001 #define AR_PHY_PAPRD_PRE_POST_SCALING_S 0 1002 1003 #define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + 0x4a0) 1004 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x00000001 1005 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0 1006 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x00000002 1007 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1 1008 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x00000004 1009 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2 1010 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x00000008 1011 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3 1012 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f0 1013 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4 1014 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe00 1015 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9 1016 1017 #define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + 0x4a4) 1018 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff 1019 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0 1020 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f0000 1021 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16 1022 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x00600000 1023 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21 1024 1025 #define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + 0x4a8) 1026 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff 1027 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0 1028 1029 #define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120) 1030 #define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120) 1031 #define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120) 1032 1033 #define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8) 1034 #define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8) 1035 #define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8) 1036 #define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF 1037 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0 1038 1039 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0) 1040 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F 1041 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0 1042 1043 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1044 1045 #endif /* AR9003_PHY_H */ 1046