1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/export.h> 18 #include "hw.h" 19 #include "ar9003_phy.h" 20 21 static const int firstep_table[] = 22 /* level: 0 1 2 3 4 5 6 7 8 */ 23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 24 25 static const int cycpwrThr1_table[] = 26 /* level: 0 1 2 3 4 5 6 7 8 */ 27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 28 29 /* 30 * register values to turn OFDM weak signal detection OFF 31 */ 32 static const int m1ThreshLow_off = 127; 33 static const int m2ThreshLow_off = 127; 34 static const int m1Thresh_off = 127; 35 static const int m2Thresh_off = 127; 36 static const int m2CountThr_off = 31; 37 static const int m2CountThrLow_off = 63; 38 static const int m1ThreshLowExt_off = 127; 39 static const int m2ThreshLowExt_off = 127; 40 static const int m1ThreshExt_off = 127; 41 static const int m2ThreshExt_off = 127; 42 43 /** 44 * ar9003_hw_set_channel - set channel on single-chip device 45 * @ah: atheros hardware structure 46 * @chan: 47 * 48 * This is the function to change channel on single-chip devices, that is 49 * all devices after ar9280. 50 * 51 * This function takes the channel value in MHz and sets 52 * hardware channel value. Assumes writes have been enabled to analog bus. 53 * 54 * Actual Expression, 55 * 56 * For 2GHz channel, 57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 58 * (freq_ref = 40MHz) 59 * 60 * For 5GHz channel, 61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 62 * (freq_ref = 40MHz/(24>>amodeRefSel)) 63 * 64 * For 5GHz channels which are 5MHz spaced, 65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 66 * (freq_ref = 40MHz) 67 */ 68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 69 { 70 u16 bMode, fracMode = 0, aModeRefSel = 0; 71 u32 freq, channelSel = 0, reg32 = 0; 72 struct chan_centers centers; 73 int loadSynthChannel; 74 75 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 76 freq = centers.synth_center; 77 78 if (freq < 4800) { /* 2 GHz, fractional mode */ 79 if (AR_SREV_9330(ah)) { 80 u32 chan_frac; 81 u32 div; 82 83 if (ah->is_clk_25mhz) 84 div = 75; 85 else 86 div = 120; 87 88 channelSel = (freq * 4) / div; 89 chan_frac = (((freq * 4) % div) * 0x20000) / div; 90 channelSel = (channelSel << 17) | chan_frac; 91 } else if (AR_SREV_9485(ah)) { 92 u32 chan_frac; 93 94 /* 95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0 96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 98 */ 99 channelSel = (freq * 4) / 120; 100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120; 101 channelSel = (channelSel << 17) | chan_frac; 102 } else if (AR_SREV_9340(ah)) { 103 if (ah->is_clk_25mhz) { 104 u32 chan_frac; 105 106 channelSel = (freq * 2) / 75; 107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 108 channelSel = (channelSel << 17) | chan_frac; 109 } else 110 channelSel = CHANSEL_2G(freq) >> 1; 111 } else 112 channelSel = CHANSEL_2G(freq); 113 /* Set to 2G mode */ 114 bMode = 1; 115 } else { 116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) { 117 u32 chan_frac; 118 119 channelSel = (freq * 2) / 75; 120 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 121 channelSel = (channelSel << 17) | chan_frac; 122 } else { 123 channelSel = CHANSEL_5G(freq); 124 /* Doubler is ON, so, divide channelSel by 2. */ 125 channelSel >>= 1; 126 } 127 /* Set to 5G mode */ 128 bMode = 0; 129 } 130 131 /* Enable fractional mode for all channels */ 132 fracMode = 1; 133 aModeRefSel = 0; 134 loadSynthChannel = 0; 135 136 reg32 = (bMode << 29); 137 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 138 139 /* Enable Long shift Select for Synthesizer */ 140 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, 141 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); 142 143 /* Program Synth. setting */ 144 reg32 = (channelSel << 2) | (fracMode << 30) | 145 (aModeRefSel << 28) | (loadSynthChannel << 31); 146 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 147 148 /* Toggle Load Synth channel bit */ 149 loadSynthChannel = 1; 150 reg32 = (channelSel << 2) | (fracMode << 30) | 151 (aModeRefSel << 28) | (loadSynthChannel << 31); 152 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 153 154 ah->curchan = chan; 155 ah->curchan_rad_index = -1; 156 157 return 0; 158 } 159 160 /** 161 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency 162 * @ah: atheros hardware structure 163 * @chan: 164 * 165 * For single-chip solutions. Converts to baseband spur frequency given the 166 * input channel frequency and compute register settings below. 167 * 168 * Spur mitigation for MRC CCK 169 */ 170 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, 171 struct ath9k_channel *chan) 172 { 173 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 174 int cur_bb_spur, negative = 0, cck_spur_freq; 175 int i; 176 int range, max_spur_cnts, synth_freq; 177 u8 *spur_fbin_ptr = NULL; 178 179 /* 180 * Need to verify range +/- 10 MHz in control channel, otherwise spur 181 * is out-of-band and can be ignored. 182 */ 183 184 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) { 185 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, 186 IS_CHAN_2GHZ(chan)); 187 if (spur_fbin_ptr[0] == 0) /* No spur */ 188 return; 189 max_spur_cnts = 5; 190 if (IS_CHAN_HT40(chan)) { 191 range = 19; 192 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 193 AR_PHY_GC_DYN2040_PRI_CH) == 0) 194 synth_freq = chan->channel + 10; 195 else 196 synth_freq = chan->channel - 10; 197 } else { 198 range = 10; 199 synth_freq = chan->channel; 200 } 201 } else { 202 range = 10; 203 max_spur_cnts = 4; 204 synth_freq = chan->channel; 205 } 206 207 for (i = 0; i < max_spur_cnts; i++) { 208 negative = 0; 209 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 210 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i], 211 IS_CHAN_2GHZ(chan)) - synth_freq; 212 else 213 cur_bb_spur = spur_freq[i] - synth_freq; 214 215 if (cur_bb_spur < 0) { 216 negative = 1; 217 cur_bb_spur = -cur_bb_spur; 218 } 219 if (cur_bb_spur < range) { 220 cck_spur_freq = (int)((cur_bb_spur << 19) / 11); 221 222 if (negative == 1) 223 cck_spur_freq = -cck_spur_freq; 224 225 cck_spur_freq = cck_spur_freq & 0xfffff; 226 227 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 228 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); 229 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 230 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); 231 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 232 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 233 0x2); 234 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 235 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 236 0x1); 237 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 238 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 239 cck_spur_freq); 240 241 return; 242 } 243 } 244 245 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 246 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); 247 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 248 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); 249 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 250 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); 251 } 252 253 /* Clean all spur register fields */ 254 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) 255 { 256 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 257 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); 258 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 259 AR_PHY_TIMING11_SPUR_FREQ_SD, 0); 260 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 261 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); 262 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 263 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); 264 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 265 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); 266 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 267 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); 268 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 269 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); 270 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 271 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); 272 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 273 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); 274 275 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 276 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); 277 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 278 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); 279 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 280 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); 281 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 282 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); 283 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 284 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); 285 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 286 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); 287 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 288 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); 289 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 290 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); 291 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 292 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); 293 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 294 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); 295 } 296 297 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, 298 int freq_offset, 299 int spur_freq_sd, 300 int spur_delta_phase, 301 int spur_subchannel_sd) 302 { 303 int mask_index = 0; 304 305 /* OFDM Spur mitigation */ 306 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 307 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); 308 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 309 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); 310 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 311 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); 312 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 313 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); 314 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 315 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); 316 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 317 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); 318 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 319 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); 320 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 321 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); 322 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 323 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); 324 325 if (REG_READ_FIELD(ah, AR_PHY_MODE, 326 AR_PHY_MODE_DYNAMIC) == 0x1) 327 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 328 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); 329 330 mask_index = (freq_offset << 4) / 5; 331 if (mask_index < 0) 332 mask_index = mask_index - 1; 333 334 mask_index = mask_index & 0x7f; 335 336 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 337 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); 338 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 339 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); 340 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 341 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); 342 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 343 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); 344 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 345 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); 346 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 347 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); 348 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 349 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); 350 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 351 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); 352 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 353 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 354 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 355 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 356 } 357 358 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, 359 struct ath9k_channel *chan, 360 int freq_offset) 361 { 362 int spur_freq_sd = 0; 363 int spur_subchannel_sd = 0; 364 int spur_delta_phase = 0; 365 366 if (IS_CHAN_HT40(chan)) { 367 if (freq_offset < 0) { 368 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 369 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 370 spur_subchannel_sd = 1; 371 else 372 spur_subchannel_sd = 0; 373 374 spur_freq_sd = (freq_offset << 9) / 11; 375 376 } else { 377 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 378 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 379 spur_subchannel_sd = 0; 380 else 381 spur_subchannel_sd = 1; 382 383 spur_freq_sd = (freq_offset << 9) / 11; 384 385 } 386 387 spur_delta_phase = (freq_offset << 17) / 5; 388 389 } else { 390 spur_subchannel_sd = 0; 391 spur_freq_sd = (freq_offset << 9) /11; 392 spur_delta_phase = (freq_offset << 18) / 5; 393 } 394 395 spur_freq_sd = spur_freq_sd & 0x3ff; 396 spur_delta_phase = spur_delta_phase & 0xfffff; 397 398 ar9003_hw_spur_ofdm(ah, 399 freq_offset, 400 spur_freq_sd, 401 spur_delta_phase, 402 spur_subchannel_sd); 403 } 404 405 /* Spur mitigation for OFDM */ 406 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, 407 struct ath9k_channel *chan) 408 { 409 int synth_freq; 410 int range = 10; 411 int freq_offset = 0; 412 int mode; 413 u8* spurChansPtr; 414 unsigned int i; 415 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 416 417 if (IS_CHAN_5GHZ(chan)) { 418 spurChansPtr = &(eep->modalHeader5G.spurChans[0]); 419 mode = 0; 420 } 421 else { 422 spurChansPtr = &(eep->modalHeader2G.spurChans[0]); 423 mode = 1; 424 } 425 426 if (spurChansPtr[0] == 0) 427 return; /* No spur in the mode */ 428 429 if (IS_CHAN_HT40(chan)) { 430 range = 19; 431 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 432 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 433 synth_freq = chan->channel - 10; 434 else 435 synth_freq = chan->channel + 10; 436 } else { 437 range = 10; 438 synth_freq = chan->channel; 439 } 440 441 ar9003_hw_spur_ofdm_clear(ah); 442 443 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) { 444 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq; 445 if (abs(freq_offset) < range) { 446 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset); 447 break; 448 } 449 } 450 } 451 452 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, 453 struct ath9k_channel *chan) 454 { 455 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); 456 ar9003_hw_spur_mitigate_ofdm(ah, chan); 457 } 458 459 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, 460 struct ath9k_channel *chan) 461 { 462 u32 pll; 463 464 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); 465 466 if (chan && IS_CHAN_HALF_RATE(chan)) 467 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); 468 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 469 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); 470 471 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); 472 473 return pll; 474 } 475 476 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, 477 struct ath9k_channel *chan) 478 { 479 u32 phymode; 480 u32 enableDacFifo = 0; 481 482 enableDacFifo = 483 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); 484 485 /* Enable 11n HT, 20 MHz */ 486 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | 487 AR_PHY_GC_SHORT_GI_40 | enableDacFifo; 488 489 /* Configure baseband for dynamic 20/40 operation */ 490 if (IS_CHAN_HT40(chan)) { 491 phymode |= AR_PHY_GC_DYN2040_EN; 492 /* Configure control (primary) channel at +-10MHz */ 493 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 494 (chan->chanmode == CHANNEL_G_HT40PLUS)) 495 phymode |= AR_PHY_GC_DYN2040_PRI_CH; 496 497 } 498 499 /* make sure we preserve INI settings */ 500 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); 501 /* turn off Green Field detection for STA for now */ 502 phymode &= ~AR_PHY_GC_GF_DETECT_EN; 503 504 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); 505 506 /* Configure MAC for 20/40 operation */ 507 ath9k_hw_set11nmac2040(ah); 508 509 /* global transmit timeout (25 TUs default)*/ 510 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 511 /* carrier sense timeout */ 512 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 513 } 514 515 static void ar9003_hw_init_bb(struct ath_hw *ah, 516 struct ath9k_channel *chan) 517 { 518 u32 synthDelay; 519 520 /* 521 * Wait for the frequency synth to settle (synth goes on 522 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 523 * Value is in 100ns increments. 524 */ 525 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 526 if (IS_CHAN_B(chan)) 527 synthDelay = (4 * synthDelay) / 22; 528 else 529 synthDelay /= 10; 530 531 /* Activate the PHY (includes baseband activate + synthesizer on) */ 532 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 533 534 /* 535 * There is an issue if the AP starts the calibration before 536 * the base band timeout completes. This could result in the 537 * rx_clear false triggering. As a workaround we add delay an 538 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 539 * does not happen. 540 */ 541 udelay(synthDelay + BASE_ACTIVATE_DELAY); 542 } 543 544 static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) 545 { 546 switch (rx) { 547 case 0x5: 548 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 549 AR_PHY_SWAP_ALT_CHAIN); 550 case 0x3: 551 case 0x1: 552 case 0x2: 553 case 0x7: 554 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); 555 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); 556 break; 557 default: 558 break; 559 } 560 561 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 562 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 563 else if (AR_SREV_9462(ah)) 564 /* xxx only when MCI support is enabled */ 565 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 566 else 567 REG_WRITE(ah, AR_SELFGEN_MASK, tx); 568 569 if (tx == 0x5) { 570 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 571 AR_PHY_SWAP_ALT_CHAIN); 572 } 573 } 574 575 /* 576 * Override INI values with chip specific configuration. 577 */ 578 static void ar9003_hw_override_ini(struct ath_hw *ah) 579 { 580 u32 val; 581 582 /* 583 * Set the RX_ABORT and RX_DIS and clear it only after 584 * RXE is set for MAC. This prevents frames with 585 * corrupted descriptor status. 586 */ 587 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 588 589 /* 590 * For AR9280 and above, there is a new feature that allows 591 * Multicast search based on both MAC Address and Key ID. By default, 592 * this feature is enabled. But since the driver is not using this 593 * feature, we switch it off; otherwise multicast search based on 594 * MAC addr only will fail. 595 */ 596 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); 597 REG_WRITE(ah, AR_PCU_MISC_MODE2, 598 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); 599 600 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 601 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 602 } 603 604 static void ar9003_hw_prog_ini(struct ath_hw *ah, 605 struct ar5416IniArray *iniArr, 606 int column) 607 { 608 unsigned int i, regWrites = 0; 609 610 /* New INI format: Array may be undefined (pre, core, post arrays) */ 611 if (!iniArr->ia_array) 612 return; 613 614 /* 615 * New INI format: Pre, core, and post arrays for a given subsystem 616 * may be modal (> 2 columns) or non-modal (2 columns). Determine if 617 * the array is non-modal and force the column to 1. 618 */ 619 if (column >= iniArr->ia_columns) 620 column = 1; 621 622 for (i = 0; i < iniArr->ia_rows; i++) { 623 u32 reg = INI_RA(iniArr, i, 0); 624 u32 val = INI_RA(iniArr, i, column); 625 626 REG_WRITE(ah, reg, val); 627 628 DO_DELAY(regWrites); 629 } 630 } 631 632 static int ar9003_hw_process_ini(struct ath_hw *ah, 633 struct ath9k_channel *chan) 634 { 635 unsigned int regWrites = 0, i; 636 u32 modesIndex; 637 638 switch (chan->chanmode) { 639 case CHANNEL_A: 640 case CHANNEL_A_HT20: 641 modesIndex = 1; 642 break; 643 case CHANNEL_A_HT40PLUS: 644 case CHANNEL_A_HT40MINUS: 645 modesIndex = 2; 646 break; 647 case CHANNEL_G: 648 case CHANNEL_G_HT20: 649 case CHANNEL_B: 650 modesIndex = 4; 651 break; 652 case CHANNEL_G_HT40PLUS: 653 case CHANNEL_G_HT40MINUS: 654 modesIndex = 3; 655 break; 656 657 default: 658 return -EINVAL; 659 } 660 661 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { 662 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); 663 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 664 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 665 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 666 if (i == ATH_INI_POST && AR_SREV_9462_20(ah)) 667 ar9003_hw_prog_ini(ah, 668 &ah->ini_radio_post_sys2ant, 669 modesIndex); 670 } 671 672 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); 673 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 674 675 /* 676 * For 5GHz channels requiring Fast Clock, apply 677 * different modal values. 678 */ 679 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 680 REG_WRITE_ARRAY(&ah->iniModesAdditional, 681 modesIndex, regWrites); 682 683 if (AR_SREV_9330(ah)) 684 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); 685 686 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 687 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 688 689 if (AR_SREV_9462(ah)) 690 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1); 691 692 ah->modes_index = modesIndex; 693 ar9003_hw_override_ini(ah); 694 ar9003_hw_set_channel_regs(ah, chan); 695 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 696 ath9k_hw_apply_txpower(ah, chan); 697 698 if (AR_SREV_9462(ah)) { 699 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 700 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 701 ah->enabled_cals |= TX_IQ_CAL; 702 else 703 ah->enabled_cals &= ~TX_IQ_CAL; 704 705 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) 706 ah->enabled_cals |= TX_CL_CAL; 707 else 708 ah->enabled_cals &= ~TX_CL_CAL; 709 } 710 711 return 0; 712 } 713 714 static void ar9003_hw_set_rfmode(struct ath_hw *ah, 715 struct ath9k_channel *chan) 716 { 717 u32 rfMode = 0; 718 719 if (chan == NULL) 720 return; 721 722 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 723 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 724 725 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 726 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 727 728 REG_WRITE(ah, AR_PHY_MODE, rfMode); 729 } 730 731 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) 732 { 733 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 734 } 735 736 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, 737 struct ath9k_channel *chan) 738 { 739 u32 coef_scaled, ds_coef_exp, ds_coef_man; 740 u32 clockMhzScaled = 0x64000000; 741 struct chan_centers centers; 742 743 /* 744 * half and quarter rate can divide the scaled clock by 2 or 4 745 * scale for selected channel bandwidth 746 */ 747 if (IS_CHAN_HALF_RATE(chan)) 748 clockMhzScaled = clockMhzScaled >> 1; 749 else if (IS_CHAN_QUARTER_RATE(chan)) 750 clockMhzScaled = clockMhzScaled >> 2; 751 752 /* 753 * ALGO -> coef = 1e8/fcarrier*fclock/40; 754 * scaled coef to provide precision for this floating calculation 755 */ 756 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 757 coef_scaled = clockMhzScaled / centers.synth_center; 758 759 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 760 &ds_coef_exp); 761 762 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 763 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 764 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 765 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 766 767 /* 768 * For Short GI, 769 * scaled coeff is 9/10 that of normal coeff 770 */ 771 coef_scaled = (9 * coef_scaled) / 10; 772 773 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 774 &ds_coef_exp); 775 776 /* for short gi */ 777 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 778 AR_PHY_SGI_DSC_MAN, ds_coef_man); 779 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 780 AR_PHY_SGI_DSC_EXP, ds_coef_exp); 781 } 782 783 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) 784 { 785 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 786 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 787 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 788 } 789 790 /* 791 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 792 * Read the phy active delay register. Value is in 100ns increments. 793 */ 794 static void ar9003_hw_rfbus_done(struct ath_hw *ah) 795 { 796 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 797 if (IS_CHAN_B(ah->curchan)) 798 synthDelay = (4 * synthDelay) / 22; 799 else 800 synthDelay /= 10; 801 802 udelay(synthDelay + BASE_ACTIVATE_DELAY); 803 804 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 805 } 806 807 static bool ar9003_hw_ani_control(struct ath_hw *ah, 808 enum ath9k_ani_cmd cmd, int param) 809 { 810 struct ath_common *common = ath9k_hw_common(ah); 811 struct ath9k_channel *chan = ah->curchan; 812 struct ar5416AniState *aniState = &chan->ani; 813 s32 value, value2; 814 815 switch (cmd & ah->ani_function) { 816 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 817 /* 818 * on == 1 means ofdm weak signal detection is ON 819 * on == 1 is the default, for less noise immunity 820 * 821 * on == 0 means ofdm weak signal detection is OFF 822 * on == 0 means more noise imm 823 */ 824 u32 on = param ? 1 : 0; 825 /* 826 * make register setting for default 827 * (weak sig detect ON) come from INI file 828 */ 829 int m1ThreshLow = on ? 830 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 831 int m2ThreshLow = on ? 832 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 833 int m1Thresh = on ? 834 aniState->iniDef.m1Thresh : m1Thresh_off; 835 int m2Thresh = on ? 836 aniState->iniDef.m2Thresh : m2Thresh_off; 837 int m2CountThr = on ? 838 aniState->iniDef.m2CountThr : m2CountThr_off; 839 int m2CountThrLow = on ? 840 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 841 int m1ThreshLowExt = on ? 842 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 843 int m2ThreshLowExt = on ? 844 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 845 int m1ThreshExt = on ? 846 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 847 int m2ThreshExt = on ? 848 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 849 850 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 851 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 852 m1ThreshLow); 853 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 854 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 855 m2ThreshLow); 856 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 857 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 858 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 859 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 860 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 861 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 862 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 863 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 864 m2CountThrLow); 865 866 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 867 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 868 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 869 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 870 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 871 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 872 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 873 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 874 875 if (on) 876 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 877 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 878 else 879 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 880 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 881 882 if (!on != aniState->ofdmWeakSigDetectOff) { 883 ath_dbg(common, ATH_DBG_ANI, 884 "** ch %d: ofdm weak signal: %s=>%s\n", 885 chan->channel, 886 !aniState->ofdmWeakSigDetectOff ? 887 "on" : "off", 888 on ? "on" : "off"); 889 if (on) 890 ah->stats.ast_ani_ofdmon++; 891 else 892 ah->stats.ast_ani_ofdmoff++; 893 aniState->ofdmWeakSigDetectOff = !on; 894 } 895 break; 896 } 897 case ATH9K_ANI_FIRSTEP_LEVEL:{ 898 u32 level = param; 899 900 if (level >= ARRAY_SIZE(firstep_table)) { 901 ath_dbg(common, ATH_DBG_ANI, 902 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 903 level, ARRAY_SIZE(firstep_table)); 904 return false; 905 } 906 907 /* 908 * make register setting relative to default 909 * from INI file & cap value 910 */ 911 value = firstep_table[level] - 912 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 913 aniState->iniDef.firstep; 914 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 915 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 916 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 917 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 918 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 919 AR_PHY_FIND_SIG_FIRSTEP, 920 value); 921 /* 922 * we need to set first step low register too 923 * make register setting relative to default 924 * from INI file & cap value 925 */ 926 value2 = firstep_table[level] - 927 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 928 aniState->iniDef.firstepLow; 929 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 930 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 931 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 932 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 933 934 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 935 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); 936 937 if (level != aniState->firstepLevel) { 938 ath_dbg(common, ATH_DBG_ANI, 939 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 940 chan->channel, 941 aniState->firstepLevel, 942 level, 943 ATH9K_ANI_FIRSTEP_LVL_NEW, 944 value, 945 aniState->iniDef.firstep); 946 ath_dbg(common, ATH_DBG_ANI, 947 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 948 chan->channel, 949 aniState->firstepLevel, 950 level, 951 ATH9K_ANI_FIRSTEP_LVL_NEW, 952 value2, 953 aniState->iniDef.firstepLow); 954 if (level > aniState->firstepLevel) 955 ah->stats.ast_ani_stepup++; 956 else if (level < aniState->firstepLevel) 957 ah->stats.ast_ani_stepdown++; 958 aniState->firstepLevel = level; 959 } 960 break; 961 } 962 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 963 u32 level = param; 964 965 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 966 ath_dbg(common, ATH_DBG_ANI, 967 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 968 level, ARRAY_SIZE(cycpwrThr1_table)); 969 return false; 970 } 971 /* 972 * make register setting relative to default 973 * from INI file & cap value 974 */ 975 value = cycpwrThr1_table[level] - 976 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 977 aniState->iniDef.cycpwrThr1; 978 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 979 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 980 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 981 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 982 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 983 AR_PHY_TIMING5_CYCPWR_THR1, 984 value); 985 986 /* 987 * set AR_PHY_EXT_CCA for extension channel 988 * make register setting relative to default 989 * from INI file & cap value 990 */ 991 value2 = cycpwrThr1_table[level] - 992 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 993 aniState->iniDef.cycpwrThr1Ext; 994 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 995 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 996 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 997 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 998 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 999 AR_PHY_EXT_CYCPWR_THR1, value2); 1000 1001 if (level != aniState->spurImmunityLevel) { 1002 ath_dbg(common, ATH_DBG_ANI, 1003 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1004 chan->channel, 1005 aniState->spurImmunityLevel, 1006 level, 1007 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1008 value, 1009 aniState->iniDef.cycpwrThr1); 1010 ath_dbg(common, ATH_DBG_ANI, 1011 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1012 chan->channel, 1013 aniState->spurImmunityLevel, 1014 level, 1015 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1016 value2, 1017 aniState->iniDef.cycpwrThr1Ext); 1018 if (level > aniState->spurImmunityLevel) 1019 ah->stats.ast_ani_spurup++; 1020 else if (level < aniState->spurImmunityLevel) 1021 ah->stats.ast_ani_spurdown++; 1022 aniState->spurImmunityLevel = level; 1023 } 1024 break; 1025 } 1026 case ATH9K_ANI_MRC_CCK:{ 1027 /* 1028 * is_on == 1 means MRC CCK ON (default, less noise imm) 1029 * is_on == 0 means MRC CCK is OFF (more noise imm) 1030 */ 1031 bool is_on = param ? 1 : 0; 1032 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1033 AR_PHY_MRC_CCK_ENABLE, is_on); 1034 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1035 AR_PHY_MRC_CCK_MUX_REG, is_on); 1036 if (!is_on != aniState->mrcCCKOff) { 1037 ath_dbg(common, ATH_DBG_ANI, 1038 "** ch %d: MRC CCK: %s=>%s\n", 1039 chan->channel, 1040 !aniState->mrcCCKOff ? "on" : "off", 1041 is_on ? "on" : "off"); 1042 if (is_on) 1043 ah->stats.ast_ani_ccklow++; 1044 else 1045 ah->stats.ast_ani_cckhigh++; 1046 aniState->mrcCCKOff = !is_on; 1047 } 1048 break; 1049 } 1050 case ATH9K_ANI_PRESENT: 1051 break; 1052 default: 1053 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); 1054 return false; 1055 } 1056 1057 ath_dbg(common, ATH_DBG_ANI, 1058 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1059 aniState->spurImmunityLevel, 1060 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1061 aniState->firstepLevel, 1062 !aniState->mrcCCKOff ? "on" : "off", 1063 aniState->listenTime, 1064 aniState->ofdmPhyErrCount, 1065 aniState->cckPhyErrCount); 1066 return true; 1067 } 1068 1069 static void ar9003_hw_do_getnf(struct ath_hw *ah, 1070 int16_t nfarray[NUM_NF_READINGS]) 1071 { 1072 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 1073 #define AR_PHY_CH_MINCCA_PWR_S 20 1074 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 1075 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16 1076 1077 int16_t nf; 1078 int i; 1079 1080 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 1081 if (ah->rxchainmask & BIT(i)) { 1082 nf = MS(REG_READ(ah, ah->nf_regs[i]), 1083 AR_PHY_CH_MINCCA_PWR); 1084 nfarray[i] = sign_extend32(nf, 8); 1085 1086 if (IS_CHAN_HT40(ah->curchan)) { 1087 u8 ext_idx = AR9300_MAX_CHAINS + i; 1088 1089 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), 1090 AR_PHY_CH_EXT_MINCCA_PWR); 1091 nfarray[ext_idx] = sign_extend32(nf, 8); 1092 } 1093 } 1094 } 1095 } 1096 1097 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) 1098 { 1099 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; 1100 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; 1101 if (AR_SREV_9330(ah)) 1102 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; 1103 else 1104 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; 1105 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; 1106 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; 1107 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; 1108 } 1109 1110 /* 1111 * Initialize the ANI register values with default (ini) values. 1112 * This routine is called during a (full) hardware reset after 1113 * all the registers are initialised from the INI. 1114 */ 1115 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) 1116 { 1117 struct ar5416AniState *aniState; 1118 struct ath_common *common = ath9k_hw_common(ah); 1119 struct ath9k_channel *chan = ah->curchan; 1120 struct ath9k_ani_default *iniDef; 1121 u32 val; 1122 1123 aniState = &ah->curchan->ani; 1124 iniDef = &aniState->iniDef; 1125 1126 ath_dbg(common, ATH_DBG_ANI, 1127 "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1128 ah->hw_version.macVersion, 1129 ah->hw_version.macRev, 1130 ah->opmode, 1131 chan->channel, 1132 chan->channelFlags); 1133 1134 val = REG_READ(ah, AR_PHY_SFCORR); 1135 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1136 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1137 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1138 1139 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1140 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1141 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1142 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1143 1144 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1145 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1146 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1147 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1148 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1149 iniDef->firstep = REG_READ_FIELD(ah, 1150 AR_PHY_FIND_SIG, 1151 AR_PHY_FIND_SIG_FIRSTEP); 1152 iniDef->firstepLow = REG_READ_FIELD(ah, 1153 AR_PHY_FIND_SIG_LOW, 1154 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); 1155 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1156 AR_PHY_TIMING5, 1157 AR_PHY_TIMING5_CYCPWR_THR1); 1158 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1159 AR_PHY_EXT_CCA, 1160 AR_PHY_EXT_CYCPWR_THR1); 1161 1162 /* these levels just got reset to defaults by the INI */ 1163 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1164 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1165 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1166 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; 1167 } 1168 1169 static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1170 struct ath_hw_radar_conf *conf) 1171 { 1172 u32 radar_0 = 0, radar_1 = 0; 1173 1174 if (!conf) { 1175 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1176 return; 1177 } 1178 1179 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1180 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1181 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1182 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1183 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1184 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1185 1186 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1187 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1188 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1189 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1190 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1191 1192 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1193 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1194 if (conf->ext_channel) 1195 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1196 else 1197 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1198 } 1199 1200 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) 1201 { 1202 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1203 1204 conf->fir_power = -28; 1205 conf->radar_rssi = 0; 1206 conf->pulse_height = 10; 1207 conf->pulse_rssi = 24; 1208 conf->pulse_inband = 8; 1209 conf->pulse_maxlen = 255; 1210 conf->pulse_inband_step = 12; 1211 conf->radar_inband = 8; 1212 } 1213 1214 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 1215 struct ath_hw_antcomb_conf *antconf) 1216 { 1217 u32 regval; 1218 1219 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1220 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >> 1221 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S; 1222 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >> 1223 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S; 1224 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >> 1225 AR_PHY_9485_ANT_FAST_DIV_BIAS_S; 1226 1227 if (AR_SREV_9330_11(ah)) { 1228 antconf->lna1_lna2_delta = -9; 1229 antconf->div_group = 1; 1230 } else if (AR_SREV_9485(ah)) { 1231 antconf->lna1_lna2_delta = -9; 1232 antconf->div_group = 2; 1233 } else { 1234 antconf->lna1_lna2_delta = -3; 1235 antconf->div_group = 0; 1236 } 1237 } 1238 1239 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 1240 struct ath_hw_antcomb_conf *antconf) 1241 { 1242 u32 regval; 1243 1244 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1245 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF | 1246 AR_PHY_9485_ANT_DIV_ALT_LNACONF | 1247 AR_PHY_9485_ANT_FAST_DIV_BIAS | 1248 AR_PHY_9485_ANT_DIV_MAIN_GAINTB | 1249 AR_PHY_9485_ANT_DIV_ALT_GAINTB); 1250 regval |= ((antconf->main_lna_conf << 1251 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S) 1252 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF); 1253 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S) 1254 & AR_PHY_9485_ANT_DIV_ALT_LNACONF); 1255 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S) 1256 & AR_PHY_9485_ANT_FAST_DIV_BIAS); 1257 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S) 1258 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB); 1259 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S) 1260 & AR_PHY_9485_ANT_DIV_ALT_GAINTB); 1261 1262 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1263 } 1264 1265 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 1266 struct ath9k_channel *chan, 1267 u8 *ini_reloaded) 1268 { 1269 unsigned int regWrites = 0; 1270 u32 modesIndex; 1271 1272 switch (chan->chanmode) { 1273 case CHANNEL_A: 1274 case CHANNEL_A_HT20: 1275 modesIndex = 1; 1276 break; 1277 case CHANNEL_A_HT40PLUS: 1278 case CHANNEL_A_HT40MINUS: 1279 modesIndex = 2; 1280 break; 1281 case CHANNEL_G: 1282 case CHANNEL_G_HT20: 1283 case CHANNEL_B: 1284 modesIndex = 4; 1285 break; 1286 case CHANNEL_G_HT40PLUS: 1287 case CHANNEL_G_HT40MINUS: 1288 modesIndex = 3; 1289 break; 1290 1291 default: 1292 return -EINVAL; 1293 } 1294 1295 if (modesIndex == ah->modes_index) { 1296 *ini_reloaded = false; 1297 goto set_rfmode; 1298 } 1299 1300 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); 1301 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1302 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1303 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1304 if (AR_SREV_9462_20(ah)) 1305 ar9003_hw_prog_ini(ah, 1306 &ah->ini_radio_post_sys2ant, 1307 modesIndex); 1308 1309 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1310 1311 /* 1312 * For 5GHz channels requiring Fast Clock, apply 1313 * different modal values. 1314 */ 1315 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1316 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites); 1317 1318 if (AR_SREV_9330(ah)) 1319 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); 1320 1321 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 1322 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 1323 1324 ah->modes_index = modesIndex; 1325 *ini_reloaded = true; 1326 1327 set_rfmode: 1328 ar9003_hw_set_rfmode(ah, chan); 1329 return 0; 1330 } 1331 1332 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1333 { 1334 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1335 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 1336 static const u32 ar9300_cca_regs[6] = { 1337 AR_PHY_CCA_0, 1338 AR_PHY_CCA_1, 1339 AR_PHY_CCA_2, 1340 AR_PHY_EXT_CCA, 1341 AR_PHY_EXT_CCA_1, 1342 AR_PHY_EXT_CCA_2, 1343 }; 1344 1345 priv_ops->rf_set_freq = ar9003_hw_set_channel; 1346 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; 1347 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 1348 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; 1349 priv_ops->init_bb = ar9003_hw_init_bb; 1350 priv_ops->process_ini = ar9003_hw_process_ini; 1351 priv_ops->set_rfmode = ar9003_hw_set_rfmode; 1352 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; 1353 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; 1354 priv_ops->rfbus_req = ar9003_hw_rfbus_req; 1355 priv_ops->rfbus_done = ar9003_hw_rfbus_done; 1356 priv_ops->ani_control = ar9003_hw_ani_control; 1357 priv_ops->do_getnf = ar9003_hw_do_getnf; 1358 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 1359 priv_ops->set_radar_params = ar9003_hw_set_radar_params; 1360 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; 1361 1362 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 1363 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 1364 1365 ar9003_hw_set_nf_limits(ah); 1366 ar9003_hw_set_radar_conf(ah); 1367 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); 1368 } 1369 1370 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) 1371 { 1372 struct ath_common *common = ath9k_hw_common(ah); 1373 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; 1374 u32 val, idle_count; 1375 1376 if (!idle_tmo_ms) { 1377 /* disable IRQ, disable chip-reset for BB panic */ 1378 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1379 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & 1380 ~(AR_PHY_WATCHDOG_RST_ENABLE | 1381 AR_PHY_WATCHDOG_IRQ_ENABLE)); 1382 1383 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ 1384 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1385 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & 1386 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1387 AR_PHY_WATCHDOG_IDLE_ENABLE)); 1388 1389 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n"); 1390 return; 1391 } 1392 1393 /* enable IRQ, disable chip-reset for BB watchdog */ 1394 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; 1395 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1396 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & 1397 ~AR_PHY_WATCHDOG_RST_ENABLE); 1398 1399 /* bound limit to 10 secs */ 1400 if (idle_tmo_ms > 10000) 1401 idle_tmo_ms = 10000; 1402 1403 /* 1404 * The time unit for watchdog event is 2^15 44/88MHz cycles. 1405 * 1406 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick 1407 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick 1408 * 1409 * Given we use fast clock now in 5 GHz, these time units should 1410 * be common for both 2 GHz and 5 GHz. 1411 */ 1412 idle_count = (100 * idle_tmo_ms) / 74; 1413 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) 1414 idle_count = (100 * idle_tmo_ms) / 37; 1415 1416 /* 1417 * enable watchdog in non-IDLE mode, disable in IDLE mode, 1418 * set idle time-out. 1419 */ 1420 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1421 AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1422 AR_PHY_WATCHDOG_IDLE_MASK | 1423 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); 1424 1425 ath_dbg(common, ATH_DBG_RESET, 1426 "Enabled BB Watchdog timeout (%u ms)\n", 1427 idle_tmo_ms); 1428 } 1429 1430 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) 1431 { 1432 /* 1433 * we want to avoid printing in ISR context so we save the 1434 * watchdog status to be printed later in bottom half context. 1435 */ 1436 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); 1437 1438 /* 1439 * the watchdog timer should reset on status read but to be sure 1440 * sure we write 0 to the watchdog status bit. 1441 */ 1442 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, 1443 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); 1444 } 1445 1446 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) 1447 { 1448 struct ath_common *common = ath9k_hw_common(ah); 1449 u32 status; 1450 1451 if (likely(!(common->debug_mask & ATH_DBG_RESET))) 1452 return; 1453 1454 status = ah->bb_watchdog_last_status; 1455 ath_dbg(common, ATH_DBG_RESET, 1456 "\n==== BB update: BB status=0x%08x ====\n", status); 1457 ath_dbg(common, ATH_DBG_RESET, 1458 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1459 MS(status, AR_PHY_WATCHDOG_INFO), 1460 MS(status, AR_PHY_WATCHDOG_DET_HANG), 1461 MS(status, AR_PHY_WATCHDOG_RADAR_SM), 1462 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), 1463 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), 1464 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), 1465 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), 1466 MS(status, AR_PHY_WATCHDOG_AGC_SM), 1467 MS(status, AR_PHY_WATCHDOG_SRCH_SM)); 1468 1469 ath_dbg(common, ATH_DBG_RESET, 1470 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1471 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), 1472 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); 1473 ath_dbg(common, ATH_DBG_RESET, 1474 "** BB mode: BB_gen_controls=0x%08x **\n", 1475 REG_READ(ah, AR_PHY_GEN_CTRL)); 1476 1477 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) 1478 if (common->cc_survey.cycles) 1479 ath_dbg(common, ATH_DBG_RESET, 1480 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", 1481 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); 1482 1483 ath_dbg(common, ATH_DBG_RESET, 1484 "==== BB update: done ====\n\n"); 1485 } 1486 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); 1487 1488 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) 1489 { 1490 u32 val; 1491 1492 /* While receiving unsupported rate frame rx state machine 1493 * gets into a state 0xb and if phy_restart happens in that 1494 * state, BB would go hang. If RXSM is in 0xb state after 1495 * first bb panic, ensure to disable the phy_restart. 1496 */ 1497 if (!((MS(ah->bb_watchdog_last_status, 1498 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) || 1499 ah->bb_hang_rx_ofdm)) 1500 return; 1501 1502 ah->bb_hang_rx_ofdm = true; 1503 val = REG_READ(ah, AR_PHY_RESTART); 1504 val &= ~AR_PHY_RESTART_ENA; 1505 1506 REG_WRITE(ah, AR_PHY_RESTART, val); 1507 } 1508 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart); 1509