1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/export.h> 18 #include "hw.h" 19 #include "ar9003_phy.h" 20 21 static const int firstep_table[] = 22 /* level: 0 1 2 3 4 5 6 7 8 */ 23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 24 25 static const int cycpwrThr1_table[] = 26 /* level: 0 1 2 3 4 5 6 7 8 */ 27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 28 29 /* 30 * register values to turn OFDM weak signal detection OFF 31 */ 32 static const int m1ThreshLow_off = 127; 33 static const int m2ThreshLow_off = 127; 34 static const int m1Thresh_off = 127; 35 static const int m2Thresh_off = 127; 36 static const int m2CountThr_off = 31; 37 static const int m2CountThrLow_off = 63; 38 static const int m1ThreshLowExt_off = 127; 39 static const int m2ThreshLowExt_off = 127; 40 static const int m1ThreshExt_off = 127; 41 static const int m2ThreshExt_off = 127; 42 43 /** 44 * ar9003_hw_set_channel - set channel on single-chip device 45 * @ah: atheros hardware structure 46 * @chan: 47 * 48 * This is the function to change channel on single-chip devices, that is 49 * for AR9300 family of chipsets. 50 * 51 * This function takes the channel value in MHz and sets 52 * hardware channel value. Assumes writes have been enabled to analog bus. 53 * 54 * Actual Expression, 55 * 56 * For 2GHz channel, 57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 58 * (freq_ref = 40MHz) 59 * 60 * For 5GHz channel, 61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 62 * (freq_ref = 40MHz/(24>>amodeRefSel)) 63 * 64 * For 5GHz channels which are 5MHz spaced, 65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 66 * (freq_ref = 40MHz) 67 */ 68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 69 { 70 u16 bMode, fracMode = 0, aModeRefSel = 0; 71 u32 freq, channelSel = 0, reg32 = 0; 72 struct chan_centers centers; 73 int loadSynthChannel; 74 75 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 76 freq = centers.synth_center; 77 78 if (freq < 4800) { /* 2 GHz, fractional mode */ 79 if (AR_SREV_9330(ah)) { 80 u32 chan_frac; 81 u32 div; 82 83 if (ah->is_clk_25mhz) 84 div = 75; 85 else 86 div = 120; 87 88 channelSel = (freq * 4) / div; 89 chan_frac = (((freq * 4) % div) * 0x20000) / div; 90 channelSel = (channelSel << 17) | chan_frac; 91 } else if (AR_SREV_9485(ah)) { 92 u32 chan_frac; 93 94 /* 95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0 96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 98 */ 99 channelSel = (freq * 4) / 120; 100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120; 101 channelSel = (channelSel << 17) | chan_frac; 102 } else if (AR_SREV_9340(ah)) { 103 if (ah->is_clk_25mhz) { 104 u32 chan_frac; 105 106 channelSel = (freq * 2) / 75; 107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 108 channelSel = (channelSel << 17) | chan_frac; 109 } else 110 channelSel = CHANSEL_2G(freq) >> 1; 111 } else 112 channelSel = CHANSEL_2G(freq); 113 /* Set to 2G mode */ 114 bMode = 1; 115 } else { 116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) { 117 u32 chan_frac; 118 119 channelSel = (freq * 2) / 75; 120 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; 121 channelSel = (channelSel << 17) | chan_frac; 122 } else { 123 channelSel = CHANSEL_5G(freq); 124 /* Doubler is ON, so, divide channelSel by 2. */ 125 channelSel >>= 1; 126 } 127 /* Set to 5G mode */ 128 bMode = 0; 129 } 130 131 /* Enable fractional mode for all channels */ 132 fracMode = 1; 133 aModeRefSel = 0; 134 loadSynthChannel = 0; 135 136 reg32 = (bMode << 29); 137 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 138 139 /* Enable Long shift Select for Synthesizer */ 140 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, 141 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); 142 143 /* Program Synth. setting */ 144 reg32 = (channelSel << 2) | (fracMode << 30) | 145 (aModeRefSel << 28) | (loadSynthChannel << 31); 146 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 147 148 /* Toggle Load Synth channel bit */ 149 loadSynthChannel = 1; 150 reg32 = (channelSel << 2) | (fracMode << 30) | 151 (aModeRefSel << 28) | (loadSynthChannel << 31); 152 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 153 154 ah->curchan = chan; 155 ah->curchan_rad_index = -1; 156 157 return 0; 158 } 159 160 /** 161 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency 162 * @ah: atheros hardware structure 163 * @chan: 164 * 165 * For single-chip solutions. Converts to baseband spur frequency given the 166 * input channel frequency and compute register settings below. 167 * 168 * Spur mitigation for MRC CCK 169 */ 170 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, 171 struct ath9k_channel *chan) 172 { 173 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; 174 int cur_bb_spur, negative = 0, cck_spur_freq; 175 int i; 176 int range, max_spur_cnts, synth_freq; 177 u8 *spur_fbin_ptr = NULL; 178 179 /* 180 * Need to verify range +/- 10 MHz in control channel, otherwise spur 181 * is out-of-band and can be ignored. 182 */ 183 184 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) { 185 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, 186 IS_CHAN_2GHZ(chan)); 187 if (spur_fbin_ptr[0] == 0) /* No spur */ 188 return; 189 max_spur_cnts = 5; 190 if (IS_CHAN_HT40(chan)) { 191 range = 19; 192 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 193 AR_PHY_GC_DYN2040_PRI_CH) == 0) 194 synth_freq = chan->channel + 10; 195 else 196 synth_freq = chan->channel - 10; 197 } else { 198 range = 10; 199 synth_freq = chan->channel; 200 } 201 } else { 202 range = AR_SREV_9462(ah) ? 5 : 10; 203 max_spur_cnts = 4; 204 synth_freq = chan->channel; 205 } 206 207 for (i = 0; i < max_spur_cnts; i++) { 208 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) 209 continue; 210 negative = 0; 211 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 212 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i], 213 IS_CHAN_2GHZ(chan)) - synth_freq; 214 else 215 cur_bb_spur = spur_freq[i] - synth_freq; 216 217 if (cur_bb_spur < 0) { 218 negative = 1; 219 cur_bb_spur = -cur_bb_spur; 220 } 221 if (cur_bb_spur < range) { 222 cck_spur_freq = (int)((cur_bb_spur << 19) / 11); 223 224 if (negative == 1) 225 cck_spur_freq = -cck_spur_freq; 226 227 cck_spur_freq = cck_spur_freq & 0xfffff; 228 229 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 230 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); 231 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 232 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); 233 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 234 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 235 0x2); 236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 237 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 238 0x1); 239 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 240 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 241 cck_spur_freq); 242 243 return; 244 } 245 } 246 247 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, 248 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); 249 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 250 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); 251 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, 252 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); 253 } 254 255 /* Clean all spur register fields */ 256 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) 257 { 258 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 259 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); 260 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 261 AR_PHY_TIMING11_SPUR_FREQ_SD, 0); 262 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 263 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); 264 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 265 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); 266 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 267 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); 268 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 269 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); 270 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 271 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); 272 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 273 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); 274 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 275 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); 276 277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 278 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); 279 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 280 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); 281 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 282 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); 283 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 284 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); 285 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 286 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); 287 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 288 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); 289 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 290 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); 291 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 292 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); 293 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 294 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); 295 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 296 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); 297 } 298 299 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, 300 int freq_offset, 301 int spur_freq_sd, 302 int spur_delta_phase, 303 int spur_subchannel_sd) 304 { 305 int mask_index = 0; 306 307 /* OFDM Spur mitigation */ 308 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 309 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); 310 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 311 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); 312 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 313 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); 314 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 315 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); 316 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 317 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); 318 REG_RMW_FIELD(ah, AR_PHY_TIMING11, 319 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); 320 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 321 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); 322 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 323 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); 324 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 325 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); 326 327 if (REG_READ_FIELD(ah, AR_PHY_MODE, 328 AR_PHY_MODE_DYNAMIC) == 0x1) 329 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 330 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); 331 332 mask_index = (freq_offset << 4) / 5; 333 if (mask_index < 0) 334 mask_index = mask_index - 1; 335 336 mask_index = mask_index & 0x7f; 337 338 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 339 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); 340 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 341 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); 342 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 343 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); 344 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 345 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); 346 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 347 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); 348 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 349 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); 350 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, 351 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); 352 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, 353 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); 354 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, 355 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); 356 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, 357 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); 358 } 359 360 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, 361 struct ath9k_channel *chan, 362 int freq_offset) 363 { 364 int spur_freq_sd = 0; 365 int spur_subchannel_sd = 0; 366 int spur_delta_phase = 0; 367 368 if (IS_CHAN_HT40(chan)) { 369 if (freq_offset < 0) { 370 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 371 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 372 spur_subchannel_sd = 1; 373 else 374 spur_subchannel_sd = 0; 375 376 spur_freq_sd = (freq_offset << 9) / 11; 377 378 } else { 379 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 380 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 381 spur_subchannel_sd = 0; 382 else 383 spur_subchannel_sd = 1; 384 385 spur_freq_sd = (freq_offset << 9) / 11; 386 387 } 388 389 spur_delta_phase = (freq_offset << 17) / 5; 390 391 } else { 392 spur_subchannel_sd = 0; 393 spur_freq_sd = (freq_offset << 9) /11; 394 spur_delta_phase = (freq_offset << 18) / 5; 395 } 396 397 spur_freq_sd = spur_freq_sd & 0x3ff; 398 spur_delta_phase = spur_delta_phase & 0xfffff; 399 400 ar9003_hw_spur_ofdm(ah, 401 freq_offset, 402 spur_freq_sd, 403 spur_delta_phase, 404 spur_subchannel_sd); 405 } 406 407 /* Spur mitigation for OFDM */ 408 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, 409 struct ath9k_channel *chan) 410 { 411 int synth_freq; 412 int range = 10; 413 int freq_offset = 0; 414 int mode; 415 u8* spurChansPtr; 416 unsigned int i; 417 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 418 419 if (IS_CHAN_5GHZ(chan)) { 420 spurChansPtr = &(eep->modalHeader5G.spurChans[0]); 421 mode = 0; 422 } 423 else { 424 spurChansPtr = &(eep->modalHeader2G.spurChans[0]); 425 mode = 1; 426 } 427 428 if (spurChansPtr[0] == 0) 429 return; /* No spur in the mode */ 430 431 if (IS_CHAN_HT40(chan)) { 432 range = 19; 433 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, 434 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) 435 synth_freq = chan->channel - 10; 436 else 437 synth_freq = chan->channel + 10; 438 } else { 439 range = 10; 440 synth_freq = chan->channel; 441 } 442 443 ar9003_hw_spur_ofdm_clear(ah); 444 445 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) { 446 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq; 447 if (abs(freq_offset) < range) { 448 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset); 449 break; 450 } 451 } 452 } 453 454 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, 455 struct ath9k_channel *chan) 456 { 457 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); 458 ar9003_hw_spur_mitigate_ofdm(ah, chan); 459 } 460 461 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, 462 struct ath9k_channel *chan) 463 { 464 u32 pll; 465 466 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); 467 468 if (chan && IS_CHAN_HALF_RATE(chan)) 469 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); 470 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 471 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); 472 473 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); 474 475 return pll; 476 } 477 478 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, 479 struct ath9k_channel *chan) 480 { 481 u32 phymode; 482 u32 enableDacFifo = 0; 483 484 enableDacFifo = 485 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); 486 487 /* Enable 11n HT, 20 MHz */ 488 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | 489 AR_PHY_GC_SHORT_GI_40 | enableDacFifo; 490 491 /* Configure baseband for dynamic 20/40 operation */ 492 if (IS_CHAN_HT40(chan)) { 493 phymode |= AR_PHY_GC_DYN2040_EN; 494 /* Configure control (primary) channel at +-10MHz */ 495 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 496 (chan->chanmode == CHANNEL_G_HT40PLUS)) 497 phymode |= AR_PHY_GC_DYN2040_PRI_CH; 498 499 } 500 501 /* make sure we preserve INI settings */ 502 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); 503 /* turn off Green Field detection for STA for now */ 504 phymode &= ~AR_PHY_GC_GF_DETECT_EN; 505 506 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); 507 508 /* Configure MAC for 20/40 operation */ 509 ath9k_hw_set11nmac2040(ah); 510 511 /* global transmit timeout (25 TUs default)*/ 512 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 513 /* carrier sense timeout */ 514 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 515 } 516 517 static void ar9003_hw_init_bb(struct ath_hw *ah, 518 struct ath9k_channel *chan) 519 { 520 u32 synthDelay; 521 522 /* 523 * Wait for the frequency synth to settle (synth goes on 524 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 525 * Value is in 100ns increments. 526 */ 527 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 528 if (IS_CHAN_B(chan)) 529 synthDelay = (4 * synthDelay) / 22; 530 else 531 synthDelay /= 10; 532 533 /* Activate the PHY (includes baseband activate + synthesizer on) */ 534 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 535 536 /* 537 * There is an issue if the AP starts the calibration before 538 * the base band timeout completes. This could result in the 539 * rx_clear false triggering. As a workaround we add delay an 540 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 541 * does not happen. 542 */ 543 udelay(synthDelay + BASE_ACTIVATE_DELAY); 544 } 545 546 static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) 547 { 548 switch (rx) { 549 case 0x5: 550 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 551 AR_PHY_SWAP_ALT_CHAIN); 552 case 0x3: 553 case 0x1: 554 case 0x2: 555 case 0x7: 556 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); 557 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); 558 break; 559 default: 560 break; 561 } 562 563 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 565 else if (AR_SREV_9462(ah)) 566 /* xxx only when MCI support is enabled */ 567 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 568 else 569 REG_WRITE(ah, AR_SELFGEN_MASK, tx); 570 571 if (tx == 0x5) { 572 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 573 AR_PHY_SWAP_ALT_CHAIN); 574 } 575 } 576 577 /* 578 * Override INI values with chip specific configuration. 579 */ 580 static void ar9003_hw_override_ini(struct ath_hw *ah) 581 { 582 u32 val; 583 584 /* 585 * Set the RX_ABORT and RX_DIS and clear it only after 586 * RXE is set for MAC. This prevents frames with 587 * corrupted descriptor status. 588 */ 589 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 590 591 /* 592 * For AR9280 and above, there is a new feature that allows 593 * Multicast search based on both MAC Address and Key ID. By default, 594 * this feature is enabled. But since the driver is not using this 595 * feature, we switch it off; otherwise multicast search based on 596 * MAC addr only will fail. 597 */ 598 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); 599 REG_WRITE(ah, AR_PCU_MISC_MODE2, 600 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); 601 602 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 603 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 604 } 605 606 static void ar9003_hw_prog_ini(struct ath_hw *ah, 607 struct ar5416IniArray *iniArr, 608 int column) 609 { 610 unsigned int i, regWrites = 0; 611 612 /* New INI format: Array may be undefined (pre, core, post arrays) */ 613 if (!iniArr->ia_array) 614 return; 615 616 /* 617 * New INI format: Pre, core, and post arrays for a given subsystem 618 * may be modal (> 2 columns) or non-modal (2 columns). Determine if 619 * the array is non-modal and force the column to 1. 620 */ 621 if (column >= iniArr->ia_columns) 622 column = 1; 623 624 for (i = 0; i < iniArr->ia_rows; i++) { 625 u32 reg = INI_RA(iniArr, i, 0); 626 u32 val = INI_RA(iniArr, i, column); 627 628 REG_WRITE(ah, reg, val); 629 630 DO_DELAY(regWrites); 631 } 632 } 633 634 static int ar9003_hw_process_ini(struct ath_hw *ah, 635 struct ath9k_channel *chan) 636 { 637 unsigned int regWrites = 0, i; 638 u32 modesIndex; 639 640 switch (chan->chanmode) { 641 case CHANNEL_A: 642 case CHANNEL_A_HT20: 643 modesIndex = 1; 644 break; 645 case CHANNEL_A_HT40PLUS: 646 case CHANNEL_A_HT40MINUS: 647 modesIndex = 2; 648 break; 649 case CHANNEL_G: 650 case CHANNEL_G_HT20: 651 case CHANNEL_B: 652 modesIndex = 4; 653 break; 654 case CHANNEL_G_HT40PLUS: 655 case CHANNEL_G_HT40MINUS: 656 modesIndex = 3; 657 break; 658 659 default: 660 return -EINVAL; 661 } 662 663 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { 664 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); 665 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 666 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 667 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 668 if (i == ATH_INI_POST && AR_SREV_9462_20(ah)) 669 ar9003_hw_prog_ini(ah, 670 &ah->ini_radio_post_sys2ant, 671 modesIndex); 672 } 673 674 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); 675 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 676 677 /* 678 * For 5GHz channels requiring Fast Clock, apply 679 * different modal values. 680 */ 681 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 682 REG_WRITE_ARRAY(&ah->iniModesAdditional, 683 modesIndex, regWrites); 684 685 if (AR_SREV_9330(ah)) 686 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); 687 688 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 689 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 690 691 if (AR_SREV_9462(ah)) 692 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1); 693 694 ah->modes_index = modesIndex; 695 ar9003_hw_override_ini(ah); 696 ar9003_hw_set_channel_regs(ah, chan); 697 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 698 ath9k_hw_apply_txpower(ah, chan); 699 700 if (AR_SREV_9462(ah)) { 701 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 702 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 703 ah->enabled_cals |= TX_IQ_CAL; 704 else 705 ah->enabled_cals &= ~TX_IQ_CAL; 706 707 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) 708 ah->enabled_cals |= TX_CL_CAL; 709 else 710 ah->enabled_cals &= ~TX_CL_CAL; 711 } 712 713 return 0; 714 } 715 716 static void ar9003_hw_set_rfmode(struct ath_hw *ah, 717 struct ath9k_channel *chan) 718 { 719 u32 rfMode = 0; 720 721 if (chan == NULL) 722 return; 723 724 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 725 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 726 727 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 728 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 729 730 REG_WRITE(ah, AR_PHY_MODE, rfMode); 731 } 732 733 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) 734 { 735 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 736 } 737 738 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, 739 struct ath9k_channel *chan) 740 { 741 u32 coef_scaled, ds_coef_exp, ds_coef_man; 742 u32 clockMhzScaled = 0x64000000; 743 struct chan_centers centers; 744 745 /* 746 * half and quarter rate can divide the scaled clock by 2 or 4 747 * scale for selected channel bandwidth 748 */ 749 if (IS_CHAN_HALF_RATE(chan)) 750 clockMhzScaled = clockMhzScaled >> 1; 751 else if (IS_CHAN_QUARTER_RATE(chan)) 752 clockMhzScaled = clockMhzScaled >> 2; 753 754 /* 755 * ALGO -> coef = 1e8/fcarrier*fclock/40; 756 * scaled coef to provide precision for this floating calculation 757 */ 758 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 759 coef_scaled = clockMhzScaled / centers.synth_center; 760 761 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 762 &ds_coef_exp); 763 764 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 765 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 766 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 767 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 768 769 /* 770 * For Short GI, 771 * scaled coeff is 9/10 that of normal coeff 772 */ 773 coef_scaled = (9 * coef_scaled) / 10; 774 775 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 776 &ds_coef_exp); 777 778 /* for short gi */ 779 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 780 AR_PHY_SGI_DSC_MAN, ds_coef_man); 781 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, 782 AR_PHY_SGI_DSC_EXP, ds_coef_exp); 783 } 784 785 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) 786 { 787 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 788 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 789 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 790 } 791 792 /* 793 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 794 * Read the phy active delay register. Value is in 100ns increments. 795 */ 796 static void ar9003_hw_rfbus_done(struct ath_hw *ah) 797 { 798 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 799 if (IS_CHAN_B(ah->curchan)) 800 synthDelay = (4 * synthDelay) / 22; 801 else 802 synthDelay /= 10; 803 804 udelay(synthDelay + BASE_ACTIVATE_DELAY); 805 806 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 807 } 808 809 static bool ar9003_hw_ani_control(struct ath_hw *ah, 810 enum ath9k_ani_cmd cmd, int param) 811 { 812 struct ath_common *common = ath9k_hw_common(ah); 813 struct ath9k_channel *chan = ah->curchan; 814 struct ar5416AniState *aniState = &chan->ani; 815 s32 value, value2; 816 817 switch (cmd & ah->ani_function) { 818 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 819 /* 820 * on == 1 means ofdm weak signal detection is ON 821 * on == 1 is the default, for less noise immunity 822 * 823 * on == 0 means ofdm weak signal detection is OFF 824 * on == 0 means more noise imm 825 */ 826 u32 on = param ? 1 : 0; 827 /* 828 * make register setting for default 829 * (weak sig detect ON) come from INI file 830 */ 831 int m1ThreshLow = on ? 832 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 833 int m2ThreshLow = on ? 834 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 835 int m1Thresh = on ? 836 aniState->iniDef.m1Thresh : m1Thresh_off; 837 int m2Thresh = on ? 838 aniState->iniDef.m2Thresh : m2Thresh_off; 839 int m2CountThr = on ? 840 aniState->iniDef.m2CountThr : m2CountThr_off; 841 int m2CountThrLow = on ? 842 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 843 int m1ThreshLowExt = on ? 844 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 845 int m2ThreshLowExt = on ? 846 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 847 int m1ThreshExt = on ? 848 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 849 int m2ThreshExt = on ? 850 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 851 852 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 853 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 854 m1ThreshLow); 855 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 856 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 857 m2ThreshLow); 858 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 859 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 860 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 861 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 862 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 863 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 864 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 865 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 866 m2CountThrLow); 867 868 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 869 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 870 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 871 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 872 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 873 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 874 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 875 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 876 877 if (on) 878 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 879 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 880 else 881 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 882 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 883 884 if (!on != aniState->ofdmWeakSigDetectOff) { 885 ath_dbg(common, ANI, 886 "** ch %d: ofdm weak signal: %s=>%s\n", 887 chan->channel, 888 !aniState->ofdmWeakSigDetectOff ? 889 "on" : "off", 890 on ? "on" : "off"); 891 if (on) 892 ah->stats.ast_ani_ofdmon++; 893 else 894 ah->stats.ast_ani_ofdmoff++; 895 aniState->ofdmWeakSigDetectOff = !on; 896 } 897 break; 898 } 899 case ATH9K_ANI_FIRSTEP_LEVEL:{ 900 u32 level = param; 901 902 if (level >= ARRAY_SIZE(firstep_table)) { 903 ath_dbg(common, ANI, 904 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 905 level, ARRAY_SIZE(firstep_table)); 906 return false; 907 } 908 909 /* 910 * make register setting relative to default 911 * from INI file & cap value 912 */ 913 value = firstep_table[level] - 914 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 915 aniState->iniDef.firstep; 916 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 917 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 918 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 919 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 920 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 921 AR_PHY_FIND_SIG_FIRSTEP, 922 value); 923 /* 924 * we need to set first step low register too 925 * make register setting relative to default 926 * from INI file & cap value 927 */ 928 value2 = firstep_table[level] - 929 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 930 aniState->iniDef.firstepLow; 931 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 932 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 933 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 934 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 935 936 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 937 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); 938 939 if (level != aniState->firstepLevel) { 940 ath_dbg(common, ANI, 941 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 942 chan->channel, 943 aniState->firstepLevel, 944 level, 945 ATH9K_ANI_FIRSTEP_LVL_NEW, 946 value, 947 aniState->iniDef.firstep); 948 ath_dbg(common, ANI, 949 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 950 chan->channel, 951 aniState->firstepLevel, 952 level, 953 ATH9K_ANI_FIRSTEP_LVL_NEW, 954 value2, 955 aniState->iniDef.firstepLow); 956 if (level > aniState->firstepLevel) 957 ah->stats.ast_ani_stepup++; 958 else if (level < aniState->firstepLevel) 959 ah->stats.ast_ani_stepdown++; 960 aniState->firstepLevel = level; 961 } 962 break; 963 } 964 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 965 u32 level = param; 966 967 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 968 ath_dbg(common, ANI, 969 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 970 level, ARRAY_SIZE(cycpwrThr1_table)); 971 return false; 972 } 973 /* 974 * make register setting relative to default 975 * from INI file & cap value 976 */ 977 value = cycpwrThr1_table[level] - 978 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 979 aniState->iniDef.cycpwrThr1; 980 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 981 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 982 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 983 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 984 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 985 AR_PHY_TIMING5_CYCPWR_THR1, 986 value); 987 988 /* 989 * set AR_PHY_EXT_CCA for extension channel 990 * make register setting relative to default 991 * from INI file & cap value 992 */ 993 value2 = cycpwrThr1_table[level] - 994 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 995 aniState->iniDef.cycpwrThr1Ext; 996 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 997 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 998 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 999 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1000 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1001 AR_PHY_EXT_CYCPWR_THR1, value2); 1002 1003 if (level != aniState->spurImmunityLevel) { 1004 ath_dbg(common, ANI, 1005 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1006 chan->channel, 1007 aniState->spurImmunityLevel, 1008 level, 1009 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1010 value, 1011 aniState->iniDef.cycpwrThr1); 1012 ath_dbg(common, ANI, 1013 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1014 chan->channel, 1015 aniState->spurImmunityLevel, 1016 level, 1017 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1018 value2, 1019 aniState->iniDef.cycpwrThr1Ext); 1020 if (level > aniState->spurImmunityLevel) 1021 ah->stats.ast_ani_spurup++; 1022 else if (level < aniState->spurImmunityLevel) 1023 ah->stats.ast_ani_spurdown++; 1024 aniState->spurImmunityLevel = level; 1025 } 1026 break; 1027 } 1028 case ATH9K_ANI_MRC_CCK:{ 1029 /* 1030 * is_on == 1 means MRC CCK ON (default, less noise imm) 1031 * is_on == 0 means MRC CCK is OFF (more noise imm) 1032 */ 1033 bool is_on = param ? 1 : 0; 1034 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1035 AR_PHY_MRC_CCK_ENABLE, is_on); 1036 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1037 AR_PHY_MRC_CCK_MUX_REG, is_on); 1038 if (!is_on != aniState->mrcCCKOff) { 1039 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", 1040 chan->channel, 1041 !aniState->mrcCCKOff ? "on" : "off", 1042 is_on ? "on" : "off"); 1043 if (is_on) 1044 ah->stats.ast_ani_ccklow++; 1045 else 1046 ah->stats.ast_ani_cckhigh++; 1047 aniState->mrcCCKOff = !is_on; 1048 } 1049 break; 1050 } 1051 case ATH9K_ANI_PRESENT: 1052 break; 1053 default: 1054 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1055 return false; 1056 } 1057 1058 ath_dbg(common, ANI, 1059 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1060 aniState->spurImmunityLevel, 1061 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1062 aniState->firstepLevel, 1063 !aniState->mrcCCKOff ? "on" : "off", 1064 aniState->listenTime, 1065 aniState->ofdmPhyErrCount, 1066 aniState->cckPhyErrCount); 1067 return true; 1068 } 1069 1070 static void ar9003_hw_do_getnf(struct ath_hw *ah, 1071 int16_t nfarray[NUM_NF_READINGS]) 1072 { 1073 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 1074 #define AR_PHY_CH_MINCCA_PWR_S 20 1075 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 1076 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16 1077 1078 int16_t nf; 1079 int i; 1080 1081 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 1082 if (ah->rxchainmask & BIT(i)) { 1083 nf = MS(REG_READ(ah, ah->nf_regs[i]), 1084 AR_PHY_CH_MINCCA_PWR); 1085 nfarray[i] = sign_extend32(nf, 8); 1086 1087 if (IS_CHAN_HT40(ah->curchan)) { 1088 u8 ext_idx = AR9300_MAX_CHAINS + i; 1089 1090 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), 1091 AR_PHY_CH_EXT_MINCCA_PWR); 1092 nfarray[ext_idx] = sign_extend32(nf, 8); 1093 } 1094 } 1095 } 1096 } 1097 1098 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) 1099 { 1100 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; 1101 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; 1102 if (AR_SREV_9330(ah)) 1103 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; 1104 else 1105 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; 1106 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; 1107 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; 1108 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; 1109 } 1110 1111 /* 1112 * Initialize the ANI register values with default (ini) values. 1113 * This routine is called during a (full) hardware reset after 1114 * all the registers are initialised from the INI. 1115 */ 1116 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) 1117 { 1118 struct ar5416AniState *aniState; 1119 struct ath_common *common = ath9k_hw_common(ah); 1120 struct ath9k_channel *chan = ah->curchan; 1121 struct ath9k_ani_default *iniDef; 1122 u32 val; 1123 1124 aniState = &ah->curchan->ani; 1125 iniDef = &aniState->iniDef; 1126 1127 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1128 ah->hw_version.macVersion, 1129 ah->hw_version.macRev, 1130 ah->opmode, 1131 chan->channel, 1132 chan->channelFlags); 1133 1134 val = REG_READ(ah, AR_PHY_SFCORR); 1135 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1136 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1137 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1138 1139 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1140 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1141 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1142 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1143 1144 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1145 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1146 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1147 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1148 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1149 iniDef->firstep = REG_READ_FIELD(ah, 1150 AR_PHY_FIND_SIG, 1151 AR_PHY_FIND_SIG_FIRSTEP); 1152 iniDef->firstepLow = REG_READ_FIELD(ah, 1153 AR_PHY_FIND_SIG_LOW, 1154 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); 1155 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1156 AR_PHY_TIMING5, 1157 AR_PHY_TIMING5_CYCPWR_THR1); 1158 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1159 AR_PHY_EXT_CCA, 1160 AR_PHY_EXT_CYCPWR_THR1); 1161 1162 /* these levels just got reset to defaults by the INI */ 1163 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1164 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1165 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1166 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; 1167 } 1168 1169 static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1170 struct ath_hw_radar_conf *conf) 1171 { 1172 u32 radar_0 = 0, radar_1 = 0; 1173 1174 if (!conf) { 1175 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1176 return; 1177 } 1178 1179 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1180 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1181 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1182 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1183 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1184 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1185 1186 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1187 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1188 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1189 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1190 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1191 1192 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1193 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1194 if (conf->ext_channel) 1195 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1196 else 1197 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1198 } 1199 1200 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) 1201 { 1202 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1203 1204 conf->fir_power = -28; 1205 conf->radar_rssi = 0; 1206 conf->pulse_height = 10; 1207 conf->pulse_rssi = 24; 1208 conf->pulse_inband = 8; 1209 conf->pulse_maxlen = 255; 1210 conf->pulse_inband_step = 12; 1211 conf->radar_inband = 8; 1212 } 1213 1214 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, 1215 struct ath_hw_antcomb_conf *antconf) 1216 { 1217 u32 regval; 1218 1219 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1220 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >> 1221 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S; 1222 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >> 1223 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S; 1224 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >> 1225 AR_PHY_9485_ANT_FAST_DIV_BIAS_S; 1226 1227 if (AR_SREV_9330_11(ah)) { 1228 antconf->lna1_lna2_delta = -9; 1229 antconf->div_group = 1; 1230 } else if (AR_SREV_9485(ah)) { 1231 antconf->lna1_lna2_delta = -9; 1232 antconf->div_group = 2; 1233 } else { 1234 antconf->lna1_lna2_delta = -3; 1235 antconf->div_group = 0; 1236 } 1237 } 1238 1239 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 1240 struct ath_hw_antcomb_conf *antconf) 1241 { 1242 u32 regval; 1243 1244 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 1245 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF | 1246 AR_PHY_9485_ANT_DIV_ALT_LNACONF | 1247 AR_PHY_9485_ANT_FAST_DIV_BIAS | 1248 AR_PHY_9485_ANT_DIV_MAIN_GAINTB | 1249 AR_PHY_9485_ANT_DIV_ALT_GAINTB); 1250 regval |= ((antconf->main_lna_conf << 1251 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S) 1252 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF); 1253 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S) 1254 & AR_PHY_9485_ANT_DIV_ALT_LNACONF); 1255 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S) 1256 & AR_PHY_9485_ANT_FAST_DIV_BIAS); 1257 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S) 1258 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB); 1259 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S) 1260 & AR_PHY_9485_ANT_DIV_ALT_GAINTB); 1261 1262 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 1263 } 1264 1265 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 1266 struct ath9k_channel *chan, 1267 u8 *ini_reloaded) 1268 { 1269 unsigned int regWrites = 0; 1270 u32 modesIndex; 1271 1272 switch (chan->chanmode) { 1273 case CHANNEL_A: 1274 case CHANNEL_A_HT20: 1275 modesIndex = 1; 1276 break; 1277 case CHANNEL_A_HT40PLUS: 1278 case CHANNEL_A_HT40MINUS: 1279 modesIndex = 2; 1280 break; 1281 case CHANNEL_G: 1282 case CHANNEL_G_HT20: 1283 case CHANNEL_B: 1284 modesIndex = 4; 1285 break; 1286 case CHANNEL_G_HT40PLUS: 1287 case CHANNEL_G_HT40MINUS: 1288 modesIndex = 3; 1289 break; 1290 1291 default: 1292 return -EINVAL; 1293 } 1294 1295 if (modesIndex == ah->modes_index) { 1296 *ini_reloaded = false; 1297 goto set_rfmode; 1298 } 1299 1300 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); 1301 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1302 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1303 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1304 if (AR_SREV_9462_20(ah)) 1305 ar9003_hw_prog_ini(ah, 1306 &ah->ini_radio_post_sys2ant, 1307 modesIndex); 1308 1309 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 1310 1311 /* 1312 * For 5GHz channels requiring Fast Clock, apply 1313 * different modal values. 1314 */ 1315 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1316 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites); 1317 1318 if (AR_SREV_9330(ah)) 1319 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); 1320 1321 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 1322 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 1323 1324 ah->modes_index = modesIndex; 1325 *ini_reloaded = true; 1326 1327 set_rfmode: 1328 ar9003_hw_set_rfmode(ah, chan); 1329 return 0; 1330 } 1331 1332 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 1333 { 1334 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1335 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 1336 static const u32 ar9300_cca_regs[6] = { 1337 AR_PHY_CCA_0, 1338 AR_PHY_CCA_1, 1339 AR_PHY_CCA_2, 1340 AR_PHY_EXT_CCA, 1341 AR_PHY_EXT_CCA_1, 1342 AR_PHY_EXT_CCA_2, 1343 }; 1344 1345 priv_ops->rf_set_freq = ar9003_hw_set_channel; 1346 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; 1347 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; 1348 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; 1349 priv_ops->init_bb = ar9003_hw_init_bb; 1350 priv_ops->process_ini = ar9003_hw_process_ini; 1351 priv_ops->set_rfmode = ar9003_hw_set_rfmode; 1352 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; 1353 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; 1354 priv_ops->rfbus_req = ar9003_hw_rfbus_req; 1355 priv_ops->rfbus_done = ar9003_hw_rfbus_done; 1356 priv_ops->ani_control = ar9003_hw_ani_control; 1357 priv_ops->do_getnf = ar9003_hw_do_getnf; 1358 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; 1359 priv_ops->set_radar_params = ar9003_hw_set_radar_params; 1360 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; 1361 1362 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; 1363 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; 1364 1365 ar9003_hw_set_nf_limits(ah); 1366 ar9003_hw_set_radar_conf(ah); 1367 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); 1368 } 1369 1370 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) 1371 { 1372 struct ath_common *common = ath9k_hw_common(ah); 1373 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; 1374 u32 val, idle_count; 1375 1376 if (!idle_tmo_ms) { 1377 /* disable IRQ, disable chip-reset for BB panic */ 1378 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1379 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & 1380 ~(AR_PHY_WATCHDOG_RST_ENABLE | 1381 AR_PHY_WATCHDOG_IRQ_ENABLE)); 1382 1383 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ 1384 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1385 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & 1386 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1387 AR_PHY_WATCHDOG_IDLE_ENABLE)); 1388 1389 ath_dbg(common, RESET, "Disabled BB Watchdog\n"); 1390 return; 1391 } 1392 1393 /* enable IRQ, disable chip-reset for BB watchdog */ 1394 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; 1395 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, 1396 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & 1397 ~AR_PHY_WATCHDOG_RST_ENABLE); 1398 1399 /* bound limit to 10 secs */ 1400 if (idle_tmo_ms > 10000) 1401 idle_tmo_ms = 10000; 1402 1403 /* 1404 * The time unit for watchdog event is 2^15 44/88MHz cycles. 1405 * 1406 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick 1407 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick 1408 * 1409 * Given we use fast clock now in 5 GHz, these time units should 1410 * be common for both 2 GHz and 5 GHz. 1411 */ 1412 idle_count = (100 * idle_tmo_ms) / 74; 1413 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) 1414 idle_count = (100 * idle_tmo_ms) / 37; 1415 1416 /* 1417 * enable watchdog in non-IDLE mode, disable in IDLE mode, 1418 * set idle time-out. 1419 */ 1420 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, 1421 AR_PHY_WATCHDOG_NON_IDLE_ENABLE | 1422 AR_PHY_WATCHDOG_IDLE_MASK | 1423 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); 1424 1425 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", 1426 idle_tmo_ms); 1427 } 1428 1429 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) 1430 { 1431 /* 1432 * we want to avoid printing in ISR context so we save the 1433 * watchdog status to be printed later in bottom half context. 1434 */ 1435 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); 1436 1437 /* 1438 * the watchdog timer should reset on status read but to be sure 1439 * sure we write 0 to the watchdog status bit. 1440 */ 1441 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, 1442 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); 1443 } 1444 1445 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) 1446 { 1447 struct ath_common *common = ath9k_hw_common(ah); 1448 u32 status; 1449 1450 if (likely(!(common->debug_mask & ATH_DBG_RESET))) 1451 return; 1452 1453 status = ah->bb_watchdog_last_status; 1454 ath_dbg(common, RESET, 1455 "\n==== BB update: BB status=0x%08x ====\n", status); 1456 ath_dbg(common, RESET, 1457 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1458 MS(status, AR_PHY_WATCHDOG_INFO), 1459 MS(status, AR_PHY_WATCHDOG_DET_HANG), 1460 MS(status, AR_PHY_WATCHDOG_RADAR_SM), 1461 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), 1462 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), 1463 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), 1464 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), 1465 MS(status, AR_PHY_WATCHDOG_AGC_SM), 1466 MS(status, AR_PHY_WATCHDOG_SRCH_SM)); 1467 1468 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1469 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), 1470 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); 1471 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", 1472 REG_READ(ah, AR_PHY_GEN_CTRL)); 1473 1474 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) 1475 if (common->cc_survey.cycles) 1476 ath_dbg(common, RESET, 1477 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", 1478 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); 1479 1480 ath_dbg(common, RESET, "==== BB update: done ====\n\n"); 1481 } 1482 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); 1483 1484 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) 1485 { 1486 u32 val; 1487 1488 /* While receiving unsupported rate frame rx state machine 1489 * gets into a state 0xb and if phy_restart happens in that 1490 * state, BB would go hang. If RXSM is in 0xb state after 1491 * first bb panic, ensure to disable the phy_restart. 1492 */ 1493 if (!((MS(ah->bb_watchdog_last_status, 1494 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) || 1495 ah->bb_hang_rx_ofdm)) 1496 return; 1497 1498 ah->bb_hang_rx_ofdm = true; 1499 val = REG_READ(ah, AR_PHY_RESTART); 1500 val &= ~AR_PHY_RESTART_ENA; 1501 1502 REG_WRITE(ah, AR_PHY_RESTART, val); 1503 } 1504 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart); 1505