1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #include <linux/export.h> 17 #include "hw.h" 18 #include "ar9003_mac.h" 19 20 static void ar9003_hw_rx_enable(struct ath_hw *hw) 21 { 22 REG_WRITE(hw, AR_CR, 0); 23 } 24 25 static void 26 ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) 27 { 28 struct ar9003_txc *ads = ds; 29 int checksum = 0; 30 u32 val, ctl12, ctl17; 31 32 val = (ATHEROS_VENDOR_ID << AR_DescId_S) | 33 (1 << AR_TxRxDesc_S) | 34 (1 << AR_CtrlStat_S) | 35 (i->qcu << AR_TxQcuNum_S) | 0x17; 36 37 checksum += val; 38 ACCESS_ONCE(ads->info) = val; 39 40 checksum += i->link; 41 ACCESS_ONCE(ads->link) = i->link; 42 43 checksum += i->buf_addr[0]; 44 ACCESS_ONCE(ads->data0) = i->buf_addr[0]; 45 checksum += i->buf_addr[1]; 46 ACCESS_ONCE(ads->data1) = i->buf_addr[1]; 47 checksum += i->buf_addr[2]; 48 ACCESS_ONCE(ads->data2) = i->buf_addr[2]; 49 checksum += i->buf_addr[3]; 50 ACCESS_ONCE(ads->data3) = i->buf_addr[3]; 51 52 checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen); 53 ACCESS_ONCE(ads->ctl3) = val; 54 checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen); 55 ACCESS_ONCE(ads->ctl5) = val; 56 checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen); 57 ACCESS_ONCE(ads->ctl7) = val; 58 checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen); 59 ACCESS_ONCE(ads->ctl9) = val; 60 61 checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff); 62 ACCESS_ONCE(ads->ctl10) = checksum; 63 64 if (i->is_first || i->is_last) { 65 ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0) 66 | set11nTries(i->rates, 1) 67 | set11nTries(i->rates, 2) 68 | set11nTries(i->rates, 3) 69 | (i->dur_update ? AR_DurUpdateEna : 0) 70 | SM(0, AR_BurstDur); 71 72 ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0) 73 | set11nRate(i->rates, 1) 74 | set11nRate(i->rates, 2) 75 | set11nRate(i->rates, 3); 76 } else { 77 ACCESS_ONCE(ads->ctl13) = 0; 78 ACCESS_ONCE(ads->ctl14) = 0; 79 } 80 81 ads->ctl20 = 0; 82 ads->ctl21 = 0; 83 ads->ctl22 = 0; 84 85 ctl17 = SM(i->keytype, AR_EncrType); 86 if (!i->is_first) { 87 ACCESS_ONCE(ads->ctl11) = 0; 88 ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore; 89 ACCESS_ONCE(ads->ctl15) = 0; 90 ACCESS_ONCE(ads->ctl16) = 0; 91 ACCESS_ONCE(ads->ctl17) = ctl17; 92 ACCESS_ONCE(ads->ctl18) = 0; 93 ACCESS_ONCE(ads->ctl19) = 0; 94 return; 95 } 96 97 ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen) 98 | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) 99 | SM(i->txpower, AR_XmitPower) 100 | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) 101 | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) 102 | (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0) 103 | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) 104 | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : 105 (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0)); 106 107 ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ? 108 SM(i->keyix, AR_DestIdx) : 0) 109 | SM(i->type, AR_FrameType) 110 | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) 111 | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) 112 | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); 113 114 ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); 115 switch (i->aggr) { 116 case AGGR_BUF_FIRST: 117 ctl17 |= SM(i->aggr_len, AR_AggrLen); 118 /* fall through */ 119 case AGGR_BUF_MIDDLE: 120 ctl12 |= AR_IsAggr | AR_MoreAggr; 121 ctl17 |= SM(i->ndelim, AR_PadDelim); 122 break; 123 case AGGR_BUF_LAST: 124 ctl12 |= AR_IsAggr; 125 break; 126 case AGGR_BUF_NONE: 127 break; 128 } 129 130 val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S; 131 ctl12 |= SM(val, AR_PAPRDChainMask); 132 133 ACCESS_ONCE(ads->ctl12) = ctl12; 134 ACCESS_ONCE(ads->ctl17) = ctl17; 135 136 ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0) 137 | set11nPktDurRTSCTS(i->rates, 1); 138 139 ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2) 140 | set11nPktDurRTSCTS(i->rates, 3); 141 142 ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0) 143 | set11nRateFlags(i->rates, 1) 144 | set11nRateFlags(i->rates, 2) 145 | set11nRateFlags(i->rates, 3) 146 | SM(i->rtscts_rate, AR_RTSCTSRate); 147 148 ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding; 149 } 150 151 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) 152 { 153 int checksum; 154 155 checksum = ads->info + ads->link 156 + ads->data0 + ads->ctl3 157 + ads->data1 + ads->ctl5 158 + ads->data2 + ads->ctl7 159 + ads->data3 + ads->ctl9; 160 161 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum; 162 } 163 164 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link) 165 { 166 struct ar9003_txc *ads = ds; 167 168 ads->link = ds_link; 169 ads->ctl10 &= ~AR_TxPtrChkSum; 170 ads->ctl10 |= ar9003_calc_ptr_chksum(ads); 171 } 172 173 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 174 { 175 u32 isr = 0; 176 u32 mask2 = 0; 177 struct ath9k_hw_capabilities *pCap = &ah->caps; 178 u32 sync_cause = 0; 179 struct ath_common *common = ath9k_hw_common(ah); 180 181 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 182 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 183 == AR_RTC_STATUS_ON) 184 isr = REG_READ(ah, AR_ISR); 185 } 186 187 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; 188 189 *masked = 0; 190 191 if (!isr && !sync_cause) 192 return false; 193 194 if (isr) { 195 if (isr & AR_ISR_BCNMISC) { 196 u32 isr2; 197 isr2 = REG_READ(ah, AR_ISR_S2); 198 199 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> 200 MAP_ISR_S2_TIM); 201 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> 202 MAP_ISR_S2_DTIM); 203 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> 204 MAP_ISR_S2_DTIMSYNC); 205 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> 206 MAP_ISR_S2_CABEND); 207 mask2 |= ((isr2 & AR_ISR_S2_GTT) << 208 MAP_ISR_S2_GTT); 209 mask2 |= ((isr2 & AR_ISR_S2_CST) << 210 MAP_ISR_S2_CST); 211 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> 212 MAP_ISR_S2_TSFOOR); 213 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> 214 MAP_ISR_S2_BB_WATCHDOG); 215 216 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 217 REG_WRITE(ah, AR_ISR_S2, isr2); 218 isr &= ~AR_ISR_BCNMISC; 219 } 220 } 221 222 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) 223 isr = REG_READ(ah, AR_ISR_RAC); 224 225 if (isr == 0xffffffff) { 226 *masked = 0; 227 return false; 228 } 229 230 *masked = isr & ATH9K_INT_COMMON; 231 232 if (ah->config.rx_intr_mitigation) 233 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 234 *masked |= ATH9K_INT_RXLP; 235 236 if (ah->config.tx_intr_mitigation) 237 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 238 *masked |= ATH9K_INT_TX; 239 240 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 241 *masked |= ATH9K_INT_RXLP; 242 243 if (isr & AR_ISR_HP_RXOK) 244 *masked |= ATH9K_INT_RXHP; 245 246 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) { 247 *masked |= ATH9K_INT_TX; 248 249 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 250 u32 s0, s1; 251 s0 = REG_READ(ah, AR_ISR_S0); 252 REG_WRITE(ah, AR_ISR_S0, s0); 253 s1 = REG_READ(ah, AR_ISR_S1); 254 REG_WRITE(ah, AR_ISR_S1, s1); 255 256 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR | 257 AR_ISR_TXEOL); 258 } 259 } 260 261 if (isr & AR_ISR_GENTMR) { 262 u32 s5; 263 264 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) 265 s5 = REG_READ(ah, AR_ISR_S5_S); 266 else 267 s5 = REG_READ(ah, AR_ISR_S5); 268 269 ah->intr_gen_timer_trigger = 270 MS(s5, AR_ISR_S5_GENTIMER_TRIG); 271 272 ah->intr_gen_timer_thresh = 273 MS(s5, AR_ISR_S5_GENTIMER_THRESH); 274 275 if (ah->intr_gen_timer_trigger) 276 *masked |= ATH9K_INT_GENTIMER; 277 278 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 279 REG_WRITE(ah, AR_ISR_S5, s5); 280 isr &= ~AR_ISR_GENTMR; 281 } 282 283 } 284 285 *masked |= mask2; 286 287 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 288 REG_WRITE(ah, AR_ISR, isr); 289 290 (void) REG_READ(ah, AR_ISR); 291 } 292 293 if (*masked & ATH9K_INT_BB_WATCHDOG) 294 ar9003_hw_bb_watchdog_read(ah); 295 } 296 297 if (sync_cause) { 298 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 299 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 300 REG_WRITE(ah, AR_RC, 0); 301 *masked |= ATH9K_INT_FATAL; 302 } 303 304 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 305 ath_dbg(common, ATH_DBG_INTERRUPT, 306 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 307 308 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 309 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 310 311 } 312 return true; 313 } 314 315 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, 316 struct ath_tx_status *ts) 317 { 318 struct ar9003_txc *txc = (struct ar9003_txc *) ds; 319 struct ar9003_txs *ads; 320 u32 status; 321 322 ads = &ah->ts_ring[ah->ts_tail]; 323 324 status = ACCESS_ONCE(ads->status8); 325 if ((status & AR_TxDone) == 0) 326 return -EINPROGRESS; 327 328 ts->qid = MS(ads->ds_info, AR_TxQcuNum); 329 if (!txc || (MS(txc->info, AR_TxQcuNum) == ts->qid)) 330 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; 331 else 332 return -ENOENT; 333 334 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || 335 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { 336 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 337 "Tx Descriptor error %x\n", ads->ds_info); 338 memset(ads, 0, sizeof(*ads)); 339 return -EIO; 340 } 341 342 ts->ts_rateindex = MS(status, AR_FinalTxIdx); 343 ts->ts_seqnum = MS(status, AR_SeqNum); 344 ts->tid = MS(status, AR_TxTid); 345 346 ts->desc_id = MS(ads->status1, AR_TxDescId); 347 ts->ts_tstamp = ads->status4; 348 ts->ts_status = 0; 349 ts->ts_flags = 0; 350 351 if (status & AR_TxOpExceeded) 352 ts->ts_status |= ATH9K_TXERR_XTXOP; 353 status = ACCESS_ONCE(ads->status2); 354 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); 355 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); 356 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); 357 if (status & AR_TxBaStatus) { 358 ts->ts_flags |= ATH9K_TX_BA; 359 ts->ba_low = ads->status5; 360 ts->ba_high = ads->status6; 361 } 362 363 status = ACCESS_ONCE(ads->status3); 364 if (status & AR_ExcessiveRetries) 365 ts->ts_status |= ATH9K_TXERR_XRETRY; 366 if (status & AR_Filtered) 367 ts->ts_status |= ATH9K_TXERR_FILT; 368 if (status & AR_FIFOUnderrun) { 369 ts->ts_status |= ATH9K_TXERR_FIFO; 370 ath9k_hw_updatetxtriglevel(ah, true); 371 } 372 if (status & AR_TxTimerExpired) 373 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; 374 if (status & AR_DescCfgErr) 375 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; 376 if (status & AR_TxDataUnderrun) { 377 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; 378 ath9k_hw_updatetxtriglevel(ah, true); 379 } 380 if (status & AR_TxDelimUnderrun) { 381 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; 382 ath9k_hw_updatetxtriglevel(ah, true); 383 } 384 ts->ts_shortretry = MS(status, AR_RTSFailCnt); 385 ts->ts_longretry = MS(status, AR_DataFailCnt); 386 ts->ts_virtcol = MS(status, AR_VirtRetryCnt); 387 388 status = ACCESS_ONCE(ads->status7); 389 ts->ts_rssi = MS(status, AR_TxRSSICombined); 390 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); 391 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); 392 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); 393 394 memset(ads, 0, sizeof(*ads)); 395 396 return 0; 397 } 398 399 void ar9003_hw_attach_mac_ops(struct ath_hw *hw) 400 { 401 struct ath_hw_ops *ops = ath9k_hw_ops(hw); 402 403 ops->rx_enable = ar9003_hw_rx_enable; 404 ops->set_desc_link = ar9003_hw_set_desc_link; 405 ops->get_isr = ar9003_hw_get_isr; 406 ops->set_txdesc = ar9003_set_txdesc; 407 ops->proc_txdesc = ar9003_hw_proc_txdesc; 408 } 409 410 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) 411 { 412 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); 413 } 414 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize); 415 416 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, 417 enum ath9k_rx_qtype qtype) 418 { 419 if (qtype == ATH9K_RX_QUEUE_HP) 420 REG_WRITE(ah, AR_HP_RXDP, rxdp); 421 else 422 REG_WRITE(ah, AR_LP_RXDP, rxdp); 423 } 424 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma); 425 426 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, 427 void *buf_addr) 428 { 429 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr; 430 unsigned int phyerr; 431 432 /* TODO: byte swap on big endian for ar9300_10 */ 433 434 if (!rxs) { 435 if ((rxsp->status11 & AR_RxDone) == 0) 436 return -EINPROGRESS; 437 438 if (MS(rxsp->ds_info, AR_DescId) != 0x168c) 439 return -EINVAL; 440 441 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0) 442 return -EINPROGRESS; 443 444 return 0; 445 } 446 447 rxs->rs_status = 0; 448 rxs->rs_flags = 0; 449 450 rxs->rs_datalen = rxsp->status2 & AR_DataLen; 451 rxs->rs_tstamp = rxsp->status3; 452 453 /* XXX: Keycache */ 454 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); 455 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00); 456 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01); 457 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02); 458 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10); 459 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11); 460 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12); 461 462 if (rxsp->status11 & AR_RxKeyIdxValid) 463 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); 464 else 465 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; 466 467 rxs->rs_rate = MS(rxsp->status1, AR_RxRate); 468 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; 469 470 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; 471 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; 472 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); 473 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0; 474 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0; 475 476 rxs->evm0 = rxsp->status6; 477 rxs->evm1 = rxsp->status7; 478 rxs->evm2 = rxsp->status8; 479 rxs->evm3 = rxsp->status9; 480 rxs->evm4 = (rxsp->status10 & 0xffff); 481 482 if (rxsp->status11 & AR_PreDelimCRCErr) 483 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 484 485 if (rxsp->status11 & AR_PostDelimCRCErr) 486 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; 487 488 if (rxsp->status11 & AR_DecryptBusyErr) 489 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; 490 491 if ((rxsp->status11 & AR_RxFrameOK) == 0) { 492 /* 493 * AR_CRCErr will bet set to true if we're on the last 494 * subframe and the AR_PostDelimCRCErr is caught. 495 * In a way this also gives us a guarantee that when 496 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot 497 * possibly be reviewing the last subframe. AR_CRCErr 498 * is the CRC of the actual data. 499 */ 500 if (rxsp->status11 & AR_CRCErr) 501 rxs->rs_status |= ATH9K_RXERR_CRC; 502 else if (rxsp->status11 & AR_PHYErr) { 503 phyerr = MS(rxsp->status11, AR_PHYErrCode); 504 /* 505 * If we reach a point here where AR_PostDelimCRCErr is 506 * true it implies we're *not* on the last subframe. In 507 * in that case that we know already that the CRC of 508 * the frame was OK, and MAC would send an ACK for that 509 * subframe, even if we did get a phy error of type 510 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable 511 * to frame that are prior to the last subframe. 512 * The AR_PostDelimCRCErr is the CRC for the MPDU 513 * delimiter, which contains the 4 reserved bits, 514 * the MPDU length (12 bits), and follows the MPDU 515 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII). 516 */ 517 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) && 518 (rxsp->status11 & AR_PostDelimCRCErr)) { 519 rxs->rs_phyerr = 0; 520 } else { 521 rxs->rs_status |= ATH9K_RXERR_PHY; 522 rxs->rs_phyerr = phyerr; 523 } 524 525 } else if (rxsp->status11 & AR_DecryptCRCErr) 526 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 527 else if (rxsp->status11 & AR_MichaelErr) 528 rxs->rs_status |= ATH9K_RXERR_MIC; 529 if (rxsp->status11 & AR_KeyMiss) 530 rxs->rs_status |= ATH9K_RXERR_KEYMISS; 531 } 532 533 return 0; 534 } 535 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma); 536 537 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) 538 { 539 ah->ts_tail = 0; 540 541 memset((void *) ah->ts_ring, 0, 542 ah->ts_size * sizeof(struct ar9003_txs)); 543 544 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, 545 "TS Start 0x%x End 0x%x Virt %p, Size %d\n", 546 ah->ts_paddr_start, ah->ts_paddr_end, 547 ah->ts_ring, ah->ts_size); 548 549 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); 550 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); 551 } 552 553 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, 554 u32 ts_paddr_start, 555 u8 size) 556 { 557 558 ah->ts_paddr_start = ts_paddr_start; 559 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs)); 560 ah->ts_size = size; 561 ah->ts_ring = (struct ar9003_txs *) ts_start; 562 563 ath9k_hw_reset_txstatus_ring(ah); 564 } 565 EXPORT_SYMBOL(ath9k_hw_setup_statusring); 566