1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #include <linux/export.h> 17 #include "hw.h" 18 #include "ar9003_mac.h" 19 #include "ar9003_mci.h" 20 21 static void ar9003_hw_rx_enable(struct ath_hw *hw) 22 { 23 REG_WRITE(hw, AR_CR, 0); 24 } 25 26 static void 27 ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) 28 { 29 struct ar9003_txc *ads = ds; 30 int checksum = 0; 31 u32 val, ctl12, ctl17; 32 u8 desc_len; 33 34 desc_len = ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x18 : 0x17); 35 36 val = (ATHEROS_VENDOR_ID << AR_DescId_S) | 37 (1 << AR_TxRxDesc_S) | 38 (1 << AR_CtrlStat_S) | 39 (i->qcu << AR_TxQcuNum_S) | desc_len; 40 41 checksum += val; 42 ACCESS_ONCE(ads->info) = val; 43 44 checksum += i->link; 45 ACCESS_ONCE(ads->link) = i->link; 46 47 checksum += i->buf_addr[0]; 48 ACCESS_ONCE(ads->data0) = i->buf_addr[0]; 49 checksum += i->buf_addr[1]; 50 ACCESS_ONCE(ads->data1) = i->buf_addr[1]; 51 checksum += i->buf_addr[2]; 52 ACCESS_ONCE(ads->data2) = i->buf_addr[2]; 53 checksum += i->buf_addr[3]; 54 ACCESS_ONCE(ads->data3) = i->buf_addr[3]; 55 56 checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen); 57 ACCESS_ONCE(ads->ctl3) = val; 58 checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen); 59 ACCESS_ONCE(ads->ctl5) = val; 60 checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen); 61 ACCESS_ONCE(ads->ctl7) = val; 62 checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen); 63 ACCESS_ONCE(ads->ctl9) = val; 64 65 checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff); 66 ACCESS_ONCE(ads->ctl10) = checksum; 67 68 if (i->is_first || i->is_last) { 69 ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0) 70 | set11nTries(i->rates, 1) 71 | set11nTries(i->rates, 2) 72 | set11nTries(i->rates, 3) 73 | (i->dur_update ? AR_DurUpdateEna : 0) 74 | SM(0, AR_BurstDur); 75 76 ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0) 77 | set11nRate(i->rates, 1) 78 | set11nRate(i->rates, 2) 79 | set11nRate(i->rates, 3); 80 } else { 81 ACCESS_ONCE(ads->ctl13) = 0; 82 ACCESS_ONCE(ads->ctl14) = 0; 83 } 84 85 ads->ctl20 = 0; 86 ads->ctl21 = 0; 87 ads->ctl22 = 0; 88 ads->ctl23 = 0; 89 90 ctl17 = SM(i->keytype, AR_EncrType); 91 if (!i->is_first) { 92 ACCESS_ONCE(ads->ctl11) = 0; 93 ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore; 94 ACCESS_ONCE(ads->ctl15) = 0; 95 ACCESS_ONCE(ads->ctl16) = 0; 96 ACCESS_ONCE(ads->ctl17) = ctl17; 97 ACCESS_ONCE(ads->ctl18) = 0; 98 ACCESS_ONCE(ads->ctl19) = 0; 99 return; 100 } 101 102 ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen) 103 | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) 104 | SM(i->txpower, AR_XmitPower) 105 | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) 106 | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) 107 | (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0) 108 | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) 109 | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : 110 (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0)); 111 112 ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ? 113 SM(i->keyix, AR_DestIdx) : 0) 114 | SM(i->type, AR_FrameType) 115 | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) 116 | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) 117 | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); 118 119 ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); 120 switch (i->aggr) { 121 case AGGR_BUF_FIRST: 122 ctl17 |= SM(i->aggr_len, AR_AggrLen); 123 /* fall through */ 124 case AGGR_BUF_MIDDLE: 125 ctl12 |= AR_IsAggr | AR_MoreAggr; 126 ctl17 |= SM(i->ndelim, AR_PadDelim); 127 break; 128 case AGGR_BUF_LAST: 129 ctl12 |= AR_IsAggr; 130 break; 131 case AGGR_BUF_NONE: 132 break; 133 } 134 135 val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S; 136 ctl12 |= SM(val, AR_PAPRDChainMask); 137 138 ACCESS_ONCE(ads->ctl12) = ctl12; 139 ACCESS_ONCE(ads->ctl17) = ctl17; 140 141 ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0) 142 | set11nPktDurRTSCTS(i->rates, 1); 143 144 ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2) 145 | set11nPktDurRTSCTS(i->rates, 3); 146 147 ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0) 148 | set11nRateFlags(i->rates, 1) 149 | set11nRateFlags(i->rates, 2) 150 | set11nRateFlags(i->rates, 3) 151 | SM(i->rtscts_rate, AR_RTSCTSRate); 152 153 ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding; 154 } 155 156 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) 157 { 158 int checksum; 159 160 checksum = ads->info + ads->link 161 + ads->data0 + ads->ctl3 162 + ads->data1 + ads->ctl5 163 + ads->data2 + ads->ctl7 164 + ads->data3 + ads->ctl9; 165 166 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum; 167 } 168 169 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link) 170 { 171 struct ar9003_txc *ads = ds; 172 173 ads->link = ds_link; 174 ads->ctl10 &= ~AR_TxPtrChkSum; 175 ads->ctl10 |= ar9003_calc_ptr_chksum(ads); 176 } 177 178 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 179 { 180 u32 isr = 0; 181 u32 mask2 = 0; 182 struct ath9k_hw_capabilities *pCap = &ah->caps; 183 struct ath_common *common = ath9k_hw_common(ah); 184 u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ; 185 bool fatal_int; 186 187 if (ath9k_hw_mci_is_enabled(ah)) 188 async_mask |= AR_INTR_ASYNC_MASK_MCI; 189 190 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 191 192 if (async_cause & async_mask) { 193 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 194 == AR_RTC_STATUS_ON) 195 isr = REG_READ(ah, AR_ISR); 196 } 197 198 199 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; 200 201 *masked = 0; 202 203 if (!isr && !sync_cause && !async_cause) 204 return false; 205 206 if (isr) { 207 if (isr & AR_ISR_BCNMISC) { 208 u32 isr2; 209 isr2 = REG_READ(ah, AR_ISR_S2); 210 211 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> 212 MAP_ISR_S2_TIM); 213 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> 214 MAP_ISR_S2_DTIM); 215 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> 216 MAP_ISR_S2_DTIMSYNC); 217 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> 218 MAP_ISR_S2_CABEND); 219 mask2 |= ((isr2 & AR_ISR_S2_GTT) << 220 MAP_ISR_S2_GTT); 221 mask2 |= ((isr2 & AR_ISR_S2_CST) << 222 MAP_ISR_S2_CST); 223 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> 224 MAP_ISR_S2_TSFOOR); 225 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> 226 MAP_ISR_S2_BB_WATCHDOG); 227 228 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 229 REG_WRITE(ah, AR_ISR_S2, isr2); 230 isr &= ~AR_ISR_BCNMISC; 231 } 232 } 233 234 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) 235 isr = REG_READ(ah, AR_ISR_RAC); 236 237 if (isr == 0xffffffff) { 238 *masked = 0; 239 return false; 240 } 241 242 *masked = isr & ATH9K_INT_COMMON; 243 244 if (ah->config.rx_intr_mitigation) 245 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 246 *masked |= ATH9K_INT_RXLP; 247 248 if (ah->config.tx_intr_mitigation) 249 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 250 *masked |= ATH9K_INT_TX; 251 252 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) 253 *masked |= ATH9K_INT_RXLP; 254 255 if (isr & AR_ISR_HP_RXOK) 256 *masked |= ATH9K_INT_RXHP; 257 258 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) { 259 *masked |= ATH9K_INT_TX; 260 261 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 262 u32 s0, s1; 263 s0 = REG_READ(ah, AR_ISR_S0); 264 REG_WRITE(ah, AR_ISR_S0, s0); 265 s1 = REG_READ(ah, AR_ISR_S1); 266 REG_WRITE(ah, AR_ISR_S1, s1); 267 268 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR | 269 AR_ISR_TXEOL); 270 } 271 } 272 273 if (isr & AR_ISR_GENTMR) { 274 u32 s5; 275 276 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) 277 s5 = REG_READ(ah, AR_ISR_S5_S); 278 else 279 s5 = REG_READ(ah, AR_ISR_S5); 280 281 ah->intr_gen_timer_trigger = 282 MS(s5, AR_ISR_S5_GENTIMER_TRIG); 283 284 ah->intr_gen_timer_thresh = 285 MS(s5, AR_ISR_S5_GENTIMER_THRESH); 286 287 if (ah->intr_gen_timer_trigger) 288 *masked |= ATH9K_INT_GENTIMER; 289 290 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 291 REG_WRITE(ah, AR_ISR_S5, s5); 292 isr &= ~AR_ISR_GENTMR; 293 } 294 295 } 296 297 *masked |= mask2; 298 299 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { 300 REG_WRITE(ah, AR_ISR, isr); 301 302 (void) REG_READ(ah, AR_ISR); 303 } 304 305 if (*masked & ATH9K_INT_BB_WATCHDOG) 306 ar9003_hw_bb_watchdog_read(ah); 307 } 308 309 if (async_cause & AR_INTR_ASYNC_MASK_MCI) 310 ar9003_mci_get_isr(ah, masked); 311 312 if (sync_cause) { 313 ath9k_debug_sync_cause(common, sync_cause); 314 fatal_int = 315 (sync_cause & 316 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) 317 ? true : false; 318 319 if (fatal_int) { 320 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 321 ath_dbg(common, ANY, 322 "received PCI FATAL interrupt\n"); 323 } 324 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 325 ath_dbg(common, ANY, 326 "received PCI PERR interrupt\n"); 327 } 328 *masked |= ATH9K_INT_FATAL; 329 } 330 331 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 332 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 333 REG_WRITE(ah, AR_RC, 0); 334 *masked |= ATH9K_INT_FATAL; 335 } 336 337 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 338 ath_dbg(common, INTERRUPT, 339 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 340 341 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 342 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 343 344 } 345 return true; 346 } 347 348 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, 349 struct ath_tx_status *ts) 350 { 351 struct ar9003_txs *ads; 352 u32 status; 353 354 ads = &ah->ts_ring[ah->ts_tail]; 355 356 status = ACCESS_ONCE(ads->status8); 357 if ((status & AR_TxDone) == 0) 358 return -EINPROGRESS; 359 360 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; 361 362 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || 363 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { 364 ath_dbg(ath9k_hw_common(ah), XMIT, 365 "Tx Descriptor error %x\n", ads->ds_info); 366 memset(ads, 0, sizeof(*ads)); 367 return -EIO; 368 } 369 370 ts->ts_rateindex = MS(status, AR_FinalTxIdx); 371 ts->ts_seqnum = MS(status, AR_SeqNum); 372 ts->tid = MS(status, AR_TxTid); 373 374 ts->qid = MS(ads->ds_info, AR_TxQcuNum); 375 ts->desc_id = MS(ads->status1, AR_TxDescId); 376 ts->ts_tstamp = ads->status4; 377 ts->ts_status = 0; 378 ts->ts_flags = 0; 379 380 if (status & AR_TxOpExceeded) 381 ts->ts_status |= ATH9K_TXERR_XTXOP; 382 status = ACCESS_ONCE(ads->status2); 383 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); 384 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); 385 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); 386 if (status & AR_TxBaStatus) { 387 ts->ts_flags |= ATH9K_TX_BA; 388 ts->ba_low = ads->status5; 389 ts->ba_high = ads->status6; 390 } 391 392 status = ACCESS_ONCE(ads->status3); 393 if (status & AR_ExcessiveRetries) 394 ts->ts_status |= ATH9K_TXERR_XRETRY; 395 if (status & AR_Filtered) 396 ts->ts_status |= ATH9K_TXERR_FILT; 397 if (status & AR_FIFOUnderrun) { 398 ts->ts_status |= ATH9K_TXERR_FIFO; 399 ath9k_hw_updatetxtriglevel(ah, true); 400 } 401 if (status & AR_TxTimerExpired) 402 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; 403 if (status & AR_DescCfgErr) 404 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; 405 if (status & AR_TxDataUnderrun) { 406 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; 407 ath9k_hw_updatetxtriglevel(ah, true); 408 } 409 if (status & AR_TxDelimUnderrun) { 410 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; 411 ath9k_hw_updatetxtriglevel(ah, true); 412 } 413 ts->ts_shortretry = MS(status, AR_RTSFailCnt); 414 ts->ts_longretry = MS(status, AR_DataFailCnt); 415 ts->ts_virtcol = MS(status, AR_VirtRetryCnt); 416 417 status = ACCESS_ONCE(ads->status7); 418 ts->ts_rssi = MS(status, AR_TxRSSICombined); 419 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); 420 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); 421 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); 422 423 memset(ads, 0, sizeof(*ads)); 424 425 return 0; 426 } 427 428 void ar9003_hw_attach_mac_ops(struct ath_hw *hw) 429 { 430 struct ath_hw_ops *ops = ath9k_hw_ops(hw); 431 432 ops->rx_enable = ar9003_hw_rx_enable; 433 ops->set_desc_link = ar9003_hw_set_desc_link; 434 ops->get_isr = ar9003_hw_get_isr; 435 ops->set_txdesc = ar9003_set_txdesc; 436 ops->proc_txdesc = ar9003_hw_proc_txdesc; 437 } 438 439 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) 440 { 441 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); 442 } 443 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize); 444 445 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, 446 enum ath9k_rx_qtype qtype) 447 { 448 if (qtype == ATH9K_RX_QUEUE_HP) 449 REG_WRITE(ah, AR_HP_RXDP, rxdp); 450 else 451 REG_WRITE(ah, AR_LP_RXDP, rxdp); 452 } 453 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma); 454 455 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, 456 void *buf_addr) 457 { 458 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr; 459 unsigned int phyerr; 460 461 if ((rxsp->status11 & AR_RxDone) == 0) 462 return -EINPROGRESS; 463 464 if (MS(rxsp->ds_info, AR_DescId) != 0x168c) 465 return -EINVAL; 466 467 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0) 468 return -EINPROGRESS; 469 470 rxs->rs_status = 0; 471 rxs->rs_flags = 0; 472 rxs->flag = 0; 473 474 rxs->rs_datalen = rxsp->status2 & AR_DataLen; 475 rxs->rs_tstamp = rxsp->status3; 476 477 /* XXX: Keycache */ 478 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); 479 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00); 480 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01); 481 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02); 482 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10); 483 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11); 484 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12); 485 486 if (rxsp->status11 & AR_RxKeyIdxValid) 487 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); 488 else 489 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; 490 491 rxs->rs_rate = MS(rxsp->status1, AR_RxRate); 492 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; 493 494 rxs->rs_firstaggr = (rxsp->status11 & AR_RxFirstAggr) ? 1 : 0; 495 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; 496 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; 497 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); 498 rxs->flag |= (rxsp->status4 & AR_GI) ? RX_FLAG_SHORT_GI : 0; 499 rxs->flag |= (rxsp->status4 & AR_2040) ? RX_FLAG_40MHZ : 0; 500 501 rxs->evm0 = rxsp->status6; 502 rxs->evm1 = rxsp->status7; 503 rxs->evm2 = rxsp->status8; 504 rxs->evm3 = rxsp->status9; 505 rxs->evm4 = (rxsp->status10 & 0xffff); 506 507 if (rxsp->status11 & AR_PreDelimCRCErr) 508 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 509 510 if (rxsp->status11 & AR_PostDelimCRCErr) 511 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; 512 513 if (rxsp->status11 & AR_DecryptBusyErr) 514 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; 515 516 if ((rxsp->status11 & AR_RxFrameOK) == 0) { 517 /* 518 * AR_CRCErr will bet set to true if we're on the last 519 * subframe and the AR_PostDelimCRCErr is caught. 520 * In a way this also gives us a guarantee that when 521 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot 522 * possibly be reviewing the last subframe. AR_CRCErr 523 * is the CRC of the actual data. 524 */ 525 if (rxsp->status11 & AR_CRCErr) 526 rxs->rs_status |= ATH9K_RXERR_CRC; 527 else if (rxsp->status11 & AR_DecryptCRCErr) 528 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 529 else if (rxsp->status11 & AR_MichaelErr) 530 rxs->rs_status |= ATH9K_RXERR_MIC; 531 if (rxsp->status11 & AR_PHYErr) { 532 phyerr = MS(rxsp->status11, AR_PHYErrCode); 533 /* 534 * If we reach a point here where AR_PostDelimCRCErr is 535 * true it implies we're *not* on the last subframe. In 536 * in that case that we know already that the CRC of 537 * the frame was OK, and MAC would send an ACK for that 538 * subframe, even if we did get a phy error of type 539 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable 540 * to frame that are prior to the last subframe. 541 * The AR_PostDelimCRCErr is the CRC for the MPDU 542 * delimiter, which contains the 4 reserved bits, 543 * the MPDU length (12 bits), and follows the MPDU 544 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII). 545 */ 546 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) && 547 (rxsp->status11 & AR_PostDelimCRCErr)) { 548 rxs->rs_phyerr = 0; 549 } else { 550 rxs->rs_status |= ATH9K_RXERR_PHY; 551 rxs->rs_phyerr = phyerr; 552 } 553 } 554 } 555 556 if (rxsp->status11 & AR_KeyMiss) 557 rxs->rs_status |= ATH9K_RXERR_KEYMISS; 558 559 return 0; 560 } 561 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma); 562 563 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) 564 { 565 ah->ts_tail = 0; 566 567 memset((void *) ah->ts_ring, 0, 568 ah->ts_size * sizeof(struct ar9003_txs)); 569 570 ath_dbg(ath9k_hw_common(ah), XMIT, 571 "TS Start 0x%x End 0x%x Virt %p, Size %d\n", 572 ah->ts_paddr_start, ah->ts_paddr_end, 573 ah->ts_ring, ah->ts_size); 574 575 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); 576 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); 577 } 578 579 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, 580 u32 ts_paddr_start, 581 u16 size) 582 { 583 584 ah->ts_paddr_start = ts_paddr_start; 585 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs)); 586 ah->ts_size = size; 587 ah->ts_ring = (struct ar9003_txs *) ts_start; 588 589 ath9k_hw_reset_txstatus_ring(ah); 590 } 591 EXPORT_SYMBOL(ath9k_hw_setup_statusring); 592