1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9003_mac.h" 19 #include "ar9003_2p2_initvals.h" 20 #include "ar9485_initvals.h" 21 #include "ar9340_initvals.h" 22 #include "ar9330_1p1_initvals.h" 23 #include "ar9330_1p2_initvals.h" 24 #include "ar955x_1p0_initvals.h" 25 #include "ar9580_1p0_initvals.h" 26 #include "ar9462_2p0_initvals.h" 27 #include "ar9565_1p0_initvals.h" 28 29 /* General hardware code for the AR9003 hadware family */ 30 31 /* 32 * The AR9003 family uses a new INI format (pre, core, post 33 * arrays per subsystem). This provides support for the 34 * AR9003 2.2 chipsets. 35 */ 36 static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 37 { 38 #define AR9462_BB_CTX_COEFJ(x) \ 39 ar9462_##x##_baseband_core_txfir_coeff_japan_2484 40 41 #define AR9462_BBC_TXIFR_COEFFJ \ 42 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 43 44 if (AR_SREV_9330_11(ah)) { 45 /* mac */ 46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 47 ar9331_1p1_mac_core); 48 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 49 ar9331_1p1_mac_postamble); 50 51 /* bb */ 52 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 53 ar9331_1p1_baseband_core); 54 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 55 ar9331_1p1_baseband_postamble); 56 57 /* radio */ 58 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 59 ar9331_1p1_radio_core); 60 61 /* soc */ 62 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 63 ar9331_1p1_soc_preamble); 64 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 65 ar9331_1p1_soc_postamble); 66 67 /* rx/tx gain */ 68 INIT_INI_ARRAY(&ah->iniModesRxGain, 69 ar9331_common_rx_gain_1p1); 70 INIT_INI_ARRAY(&ah->iniModesTxGain, 71 ar9331_modes_lowest_ob_db_tx_gain_1p1); 72 73 /* additional clock settings */ 74 if (ah->is_clk_25mhz) 75 INIT_INI_ARRAY(&ah->iniAdditional, 76 ar9331_1p1_xtal_25M); 77 else 78 INIT_INI_ARRAY(&ah->iniAdditional, 79 ar9331_1p1_xtal_40M); 80 } else if (AR_SREV_9330_12(ah)) { 81 /* mac */ 82 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 83 ar9331_1p2_mac_core); 84 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 85 ar9331_1p2_mac_postamble); 86 87 /* bb */ 88 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 89 ar9331_1p2_baseband_core); 90 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 91 ar9331_1p2_baseband_postamble); 92 93 /* radio */ 94 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 95 ar9331_1p2_radio_core); 96 97 /* soc */ 98 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 99 ar9331_1p2_soc_preamble); 100 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 101 ar9331_1p2_soc_postamble); 102 103 /* rx/tx gain */ 104 INIT_INI_ARRAY(&ah->iniModesRxGain, 105 ar9331_common_rx_gain_1p2); 106 INIT_INI_ARRAY(&ah->iniModesTxGain, 107 ar9331_modes_lowest_ob_db_tx_gain_1p2); 108 109 /* additional clock settings */ 110 if (ah->is_clk_25mhz) 111 INIT_INI_ARRAY(&ah->iniAdditional, 112 ar9331_1p2_xtal_25M); 113 else 114 INIT_INI_ARRAY(&ah->iniAdditional, 115 ar9331_1p2_xtal_40M); 116 } else if (AR_SREV_9340(ah)) { 117 /* mac */ 118 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 119 ar9340_1p0_mac_core); 120 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 121 ar9340_1p0_mac_postamble); 122 123 /* bb */ 124 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 125 ar9340_1p0_baseband_core); 126 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 127 ar9340_1p0_baseband_postamble); 128 129 /* radio */ 130 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 131 ar9340_1p0_radio_core); 132 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 133 ar9340_1p0_radio_postamble); 134 135 /* soc */ 136 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 137 ar9340_1p0_soc_preamble); 138 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 139 ar9340_1p0_soc_postamble); 140 141 /* rx/tx gain */ 142 INIT_INI_ARRAY(&ah->iniModesRxGain, 143 ar9340Common_wo_xlna_rx_gain_table_1p0); 144 INIT_INI_ARRAY(&ah->iniModesTxGain, 145 ar9340Modes_high_ob_db_tx_gain_table_1p0); 146 147 INIT_INI_ARRAY(&ah->iniModesFastClock, 148 ar9340Modes_fast_clock_1p0); 149 150 if (!ah->is_clk_25mhz) 151 INIT_INI_ARRAY(&ah->iniAdditional, 152 ar9340_1p0_radio_core_40M); 153 } else if (AR_SREV_9485_11(ah)) { 154 /* mac */ 155 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 156 ar9485_1_1_mac_core); 157 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 158 ar9485_1_1_mac_postamble); 159 160 /* bb */ 161 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1); 162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 163 ar9485_1_1_baseband_core); 164 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 165 ar9485_1_1_baseband_postamble); 166 167 /* radio */ 168 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 169 ar9485_1_1_radio_core); 170 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 171 ar9485_1_1_radio_postamble); 172 173 /* soc */ 174 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 175 ar9485_1_1_soc_preamble); 176 177 /* rx/tx gain */ 178 INIT_INI_ARRAY(&ah->iniModesRxGain, 179 ar9485Common_wo_xlna_rx_gain_1_1); 180 INIT_INI_ARRAY(&ah->iniModesTxGain, 181 ar9485_modes_lowest_ob_db_tx_gain_1_1); 182 183 /* Load PCIE SERDES settings from INI */ 184 185 /* Awake Setting */ 186 187 INIT_INI_ARRAY(&ah->iniPcieSerdes, 188 ar9485_1_1_pcie_phy_clkreq_disable_L1); 189 190 /* Sleep Setting */ 191 192 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 193 ar9485_1_1_pcie_phy_clkreq_disable_L1); 194 } else if (AR_SREV_9462_20(ah)) { 195 196 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); 197 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 198 ar9462_2p0_mac_postamble); 199 200 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 201 ar9462_2p0_baseband_core); 202 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 203 ar9462_2p0_baseband_postamble); 204 205 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 206 ar9462_2p0_radio_core); 207 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 208 ar9462_2p0_radio_postamble); 209 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 210 ar9462_2p0_radio_postamble_sys2ant); 211 212 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 213 ar9462_2p0_soc_preamble); 214 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 215 ar9462_2p0_soc_postamble); 216 217 INIT_INI_ARRAY(&ah->iniModesRxGain, 218 ar9462_common_rx_gain_table_2p0); 219 220 /* Awake -> Sleep Setting */ 221 INIT_INI_ARRAY(&ah->iniPcieSerdes, 222 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0); 223 /* Sleep -> Awake Setting */ 224 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 225 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0); 226 227 /* Fast clock modal settings */ 228 INIT_INI_ARRAY(&ah->iniModesFastClock, 229 ar9462_modes_fast_clock_2p0); 230 231 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 232 AR9462_BB_CTX_COEFJ(2p0)); 233 234 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ); 235 } else if (AR_SREV_9550(ah)) { 236 /* mac */ 237 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 238 ar955x_1p0_mac_core); 239 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 240 ar955x_1p0_mac_postamble); 241 242 /* bb */ 243 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 244 ar955x_1p0_baseband_core); 245 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 246 ar955x_1p0_baseband_postamble); 247 248 /* radio */ 249 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 250 ar955x_1p0_radio_core); 251 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 252 ar955x_1p0_radio_postamble); 253 254 /* soc */ 255 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 256 ar955x_1p0_soc_preamble); 257 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 258 ar955x_1p0_soc_postamble); 259 260 /* rx/tx gain */ 261 INIT_INI_ARRAY(&ah->iniModesRxGain, 262 ar955x_1p0_common_wo_xlna_rx_gain_table); 263 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 264 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 265 INIT_INI_ARRAY(&ah->iniModesTxGain, 266 ar955x_1p0_modes_xpa_tx_gain_table); 267 268 /* Fast clock modal settings */ 269 INIT_INI_ARRAY(&ah->iniModesFastClock, 270 ar955x_1p0_modes_fast_clock); 271 } else if (AR_SREV_9580(ah)) { 272 /* mac */ 273 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 274 ar9580_1p0_mac_core); 275 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 276 ar9580_1p0_mac_postamble); 277 278 /* bb */ 279 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 280 ar9580_1p0_baseband_core); 281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 282 ar9580_1p0_baseband_postamble); 283 284 /* radio */ 285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 286 ar9580_1p0_radio_core); 287 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 288 ar9580_1p0_radio_postamble); 289 290 /* soc */ 291 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 292 ar9580_1p0_soc_preamble); 293 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 294 ar9580_1p0_soc_postamble); 295 296 /* rx/tx gain */ 297 INIT_INI_ARRAY(&ah->iniModesRxGain, 298 ar9580_1p0_rx_gain_table); 299 INIT_INI_ARRAY(&ah->iniModesTxGain, 300 ar9580_1p0_low_ob_db_tx_gain_table); 301 302 INIT_INI_ARRAY(&ah->iniModesFastClock, 303 ar9580_1p0_modes_fast_clock); 304 } else if (AR_SREV_9565(ah)) { 305 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 306 ar9565_1p0_mac_core); 307 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 308 ar9565_1p0_mac_postamble); 309 310 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 311 ar9565_1p0_baseband_core); 312 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 313 ar9565_1p0_baseband_postamble); 314 315 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 316 ar9565_1p0_radio_core); 317 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 318 ar9565_1p0_radio_postamble); 319 320 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 321 ar9565_1p0_soc_preamble); 322 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 323 ar9565_1p0_soc_postamble); 324 325 INIT_INI_ARRAY(&ah->iniModesRxGain, 326 ar9565_1p0_Common_rx_gain_table); 327 INIT_INI_ARRAY(&ah->iniModesTxGain, 328 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table); 329 330 INIT_INI_ARRAY(&ah->iniPcieSerdes, 331 ar9565_1p0_pciephy_pll_on_clkreq_disable_L1); 332 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 333 ar9565_1p0_pciephy_pll_on_clkreq_disable_L1); 334 335 INIT_INI_ARRAY(&ah->iniModesFastClock, 336 ar9565_1p0_modes_fast_clock); 337 } else { 338 /* mac */ 339 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 340 ar9300_2p2_mac_core); 341 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 342 ar9300_2p2_mac_postamble); 343 344 /* bb */ 345 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 346 ar9300_2p2_baseband_core); 347 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 348 ar9300_2p2_baseband_postamble); 349 350 /* radio */ 351 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 352 ar9300_2p2_radio_core); 353 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 354 ar9300_2p2_radio_postamble); 355 356 /* soc */ 357 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 358 ar9300_2p2_soc_preamble); 359 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 360 ar9300_2p2_soc_postamble); 361 362 /* rx/tx gain */ 363 INIT_INI_ARRAY(&ah->iniModesRxGain, 364 ar9300Common_rx_gain_table_2p2); 365 INIT_INI_ARRAY(&ah->iniModesTxGain, 366 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 367 368 /* Load PCIE SERDES settings from INI */ 369 370 /* Awake Setting */ 371 372 INIT_INI_ARRAY(&ah->iniPcieSerdes, 373 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 374 375 /* Sleep Setting */ 376 377 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 378 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 379 380 /* Fast clock modal settings */ 381 INIT_INI_ARRAY(&ah->iniModesFastClock, 382 ar9300Modes_fast_clock_2p2); 383 } 384 } 385 386 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 387 { 388 if (AR_SREV_9330_12(ah)) 389 INIT_INI_ARRAY(&ah->iniModesTxGain, 390 ar9331_modes_lowest_ob_db_tx_gain_1p2); 391 else if (AR_SREV_9330_11(ah)) 392 INIT_INI_ARRAY(&ah->iniModesTxGain, 393 ar9331_modes_lowest_ob_db_tx_gain_1p1); 394 else if (AR_SREV_9340(ah)) 395 INIT_INI_ARRAY(&ah->iniModesTxGain, 396 ar9340Modes_lowest_ob_db_tx_gain_table_1p0); 397 else if (AR_SREV_9485_11(ah)) 398 INIT_INI_ARRAY(&ah->iniModesTxGain, 399 ar9485_modes_lowest_ob_db_tx_gain_1_1); 400 else if (AR_SREV_9550(ah)) 401 INIT_INI_ARRAY(&ah->iniModesTxGain, 402 ar955x_1p0_modes_xpa_tx_gain_table); 403 else if (AR_SREV_9580(ah)) 404 INIT_INI_ARRAY(&ah->iniModesTxGain, 405 ar9580_1p0_lowest_ob_db_tx_gain_table); 406 else if (AR_SREV_9462_20(ah)) 407 INIT_INI_ARRAY(&ah->iniModesTxGain, 408 ar9462_modes_low_ob_db_tx_gain_table_2p0); 409 else if (AR_SREV_9565(ah)) 410 INIT_INI_ARRAY(&ah->iniModesTxGain, 411 ar9565_1p0_modes_low_ob_db_tx_gain_table); 412 else 413 INIT_INI_ARRAY(&ah->iniModesTxGain, 414 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 415 } 416 417 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 418 { 419 if (AR_SREV_9330_12(ah)) 420 INIT_INI_ARRAY(&ah->iniModesTxGain, 421 ar9331_modes_high_ob_db_tx_gain_1p2); 422 else if (AR_SREV_9330_11(ah)) 423 INIT_INI_ARRAY(&ah->iniModesTxGain, 424 ar9331_modes_high_ob_db_tx_gain_1p1); 425 else if (AR_SREV_9340(ah)) 426 INIT_INI_ARRAY(&ah->iniModesTxGain, 427 ar9340Modes_high_ob_db_tx_gain_table_1p0); 428 else if (AR_SREV_9485_11(ah)) 429 INIT_INI_ARRAY(&ah->iniModesTxGain, 430 ar9485Modes_high_ob_db_tx_gain_1_1); 431 else if (AR_SREV_9580(ah)) 432 INIT_INI_ARRAY(&ah->iniModesTxGain, 433 ar9580_1p0_high_ob_db_tx_gain_table); 434 else if (AR_SREV_9550(ah)) 435 INIT_INI_ARRAY(&ah->iniModesTxGain, 436 ar955x_1p0_modes_no_xpa_tx_gain_table); 437 else if (AR_SREV_9462_20(ah)) 438 INIT_INI_ARRAY(&ah->iniModesTxGain, 439 ar9462_modes_high_ob_db_tx_gain_table_2p0); 440 else if (AR_SREV_9565(ah)) 441 INIT_INI_ARRAY(&ah->iniModesTxGain, 442 ar9565_1p0_modes_high_ob_db_tx_gain_table); 443 else 444 INIT_INI_ARRAY(&ah->iniModesTxGain, 445 ar9300Modes_high_ob_db_tx_gain_table_2p2); 446 } 447 448 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) 449 { 450 if (AR_SREV_9330_12(ah)) 451 INIT_INI_ARRAY(&ah->iniModesTxGain, 452 ar9331_modes_low_ob_db_tx_gain_1p2); 453 else if (AR_SREV_9330_11(ah)) 454 INIT_INI_ARRAY(&ah->iniModesTxGain, 455 ar9331_modes_low_ob_db_tx_gain_1p1); 456 else if (AR_SREV_9340(ah)) 457 INIT_INI_ARRAY(&ah->iniModesTxGain, 458 ar9340Modes_low_ob_db_tx_gain_table_1p0); 459 else if (AR_SREV_9485_11(ah)) 460 INIT_INI_ARRAY(&ah->iniModesTxGain, 461 ar9485Modes_low_ob_db_tx_gain_1_1); 462 else if (AR_SREV_9580(ah)) 463 INIT_INI_ARRAY(&ah->iniModesTxGain, 464 ar9580_1p0_low_ob_db_tx_gain_table); 465 else if (AR_SREV_9565(ah)) 466 INIT_INI_ARRAY(&ah->iniModesTxGain, 467 ar9565_1p0_modes_low_ob_db_tx_gain_table); 468 else 469 INIT_INI_ARRAY(&ah->iniModesTxGain, 470 ar9300Modes_low_ob_db_tx_gain_table_2p2); 471 } 472 473 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) 474 { 475 if (AR_SREV_9330_12(ah)) 476 INIT_INI_ARRAY(&ah->iniModesTxGain, 477 ar9331_modes_high_power_tx_gain_1p2); 478 else if (AR_SREV_9330_11(ah)) 479 INIT_INI_ARRAY(&ah->iniModesTxGain, 480 ar9331_modes_high_power_tx_gain_1p1); 481 else if (AR_SREV_9340(ah)) 482 INIT_INI_ARRAY(&ah->iniModesTxGain, 483 ar9340Modes_high_power_tx_gain_table_1p0); 484 else if (AR_SREV_9485_11(ah)) 485 INIT_INI_ARRAY(&ah->iniModesTxGain, 486 ar9485Modes_high_power_tx_gain_1_1); 487 else if (AR_SREV_9580(ah)) 488 INIT_INI_ARRAY(&ah->iniModesTxGain, 489 ar9580_1p0_high_power_tx_gain_table); 490 else if (AR_SREV_9565(ah)) 491 INIT_INI_ARRAY(&ah->iniModesTxGain, 492 ar9565_1p0_modes_high_power_tx_gain_table); 493 else 494 INIT_INI_ARRAY(&ah->iniModesTxGain, 495 ar9300Modes_high_power_tx_gain_table_2p2); 496 } 497 498 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) 499 { 500 if (AR_SREV_9340(ah)) 501 INIT_INI_ARRAY(&ah->iniModesTxGain, 502 ar9340Modes_mixed_ob_db_tx_gain_table_1p0); 503 else if (AR_SREV_9580(ah)) 504 INIT_INI_ARRAY(&ah->iniModesTxGain, 505 ar9580_1p0_mixed_ob_db_tx_gain_table); 506 } 507 508 static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 509 { 510 switch (ar9003_hw_get_tx_gain_idx(ah)) { 511 case 0: 512 default: 513 ar9003_tx_gain_table_mode0(ah); 514 break; 515 case 1: 516 ar9003_tx_gain_table_mode1(ah); 517 break; 518 case 2: 519 ar9003_tx_gain_table_mode2(ah); 520 break; 521 case 3: 522 ar9003_tx_gain_table_mode3(ah); 523 break; 524 case 4: 525 ar9003_tx_gain_table_mode4(ah); 526 break; 527 } 528 } 529 530 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 531 { 532 if (AR_SREV_9330_12(ah)) 533 INIT_INI_ARRAY(&ah->iniModesRxGain, 534 ar9331_common_rx_gain_1p2); 535 else if (AR_SREV_9330_11(ah)) 536 INIT_INI_ARRAY(&ah->iniModesRxGain, 537 ar9331_common_rx_gain_1p1); 538 else if (AR_SREV_9340(ah)) 539 INIT_INI_ARRAY(&ah->iniModesRxGain, 540 ar9340Common_rx_gain_table_1p0); 541 else if (AR_SREV_9485_11(ah)) 542 INIT_INI_ARRAY(&ah->iniModesRxGain, 543 ar9485Common_wo_xlna_rx_gain_1_1); 544 else if (AR_SREV_9550(ah)) { 545 INIT_INI_ARRAY(&ah->iniModesRxGain, 546 ar955x_1p0_common_rx_gain_table); 547 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 548 ar955x_1p0_common_rx_gain_bounds); 549 } else if (AR_SREV_9580(ah)) 550 INIT_INI_ARRAY(&ah->iniModesRxGain, 551 ar9580_1p0_rx_gain_table); 552 else if (AR_SREV_9462_20(ah)) 553 INIT_INI_ARRAY(&ah->iniModesRxGain, 554 ar9462_common_rx_gain_table_2p0); 555 else 556 INIT_INI_ARRAY(&ah->iniModesRxGain, 557 ar9300Common_rx_gain_table_2p2); 558 } 559 560 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 561 { 562 if (AR_SREV_9330_12(ah)) 563 INIT_INI_ARRAY(&ah->iniModesRxGain, 564 ar9331_common_wo_xlna_rx_gain_1p2); 565 else if (AR_SREV_9330_11(ah)) 566 INIT_INI_ARRAY(&ah->iniModesRxGain, 567 ar9331_common_wo_xlna_rx_gain_1p1); 568 else if (AR_SREV_9340(ah)) 569 INIT_INI_ARRAY(&ah->iniModesRxGain, 570 ar9340Common_wo_xlna_rx_gain_table_1p0); 571 else if (AR_SREV_9485_11(ah)) 572 INIT_INI_ARRAY(&ah->iniModesRxGain, 573 ar9485Common_wo_xlna_rx_gain_1_1); 574 else if (AR_SREV_9462_20(ah)) 575 INIT_INI_ARRAY(&ah->iniModesRxGain, 576 ar9462_common_wo_xlna_rx_gain_table_2p0); 577 else if (AR_SREV_9550(ah)) { 578 INIT_INI_ARRAY(&ah->iniModesRxGain, 579 ar955x_1p0_common_wo_xlna_rx_gain_table); 580 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 581 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 582 } else if (AR_SREV_9580(ah)) 583 INIT_INI_ARRAY(&ah->iniModesRxGain, 584 ar9580_1p0_wo_xlna_rx_gain_table); 585 else if (AR_SREV_9565(ah)) 586 INIT_INI_ARRAY(&ah->iniModesRxGain, 587 ar9565_1p0_common_wo_xlna_rx_gain_table); 588 else 589 INIT_INI_ARRAY(&ah->iniModesRxGain, 590 ar9300Common_wo_xlna_rx_gain_table_2p2); 591 } 592 593 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 594 { 595 if (AR_SREV_9462_20(ah)) 596 INIT_INI_ARRAY(&ah->iniModesRxGain, 597 ar9462_common_mixed_rx_gain_table_2p0); 598 } 599 600 static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 601 { 602 switch (ar9003_hw_get_rx_gain_idx(ah)) { 603 case 0: 604 default: 605 ar9003_rx_gain_table_mode0(ah); 606 break; 607 case 1: 608 ar9003_rx_gain_table_mode1(ah); 609 break; 610 case 2: 611 ar9003_rx_gain_table_mode2(ah); 612 break; 613 } 614 } 615 616 /* set gain table pointers according to values read from the eeprom */ 617 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) 618 { 619 ar9003_tx_gain_table_apply(ah); 620 ar9003_rx_gain_table_apply(ah); 621 } 622 623 /* 624 * Helper for ASPM support. 625 * 626 * Disable PLL when in L0s as well as receiver clock when in L1. 627 * This power saving option must be enabled through the SerDes. 628 * 629 * Programming the SerDes must go through the same 288 bit serial shift 630 * register as the other analog registers. Hence the 9 writes. 631 */ 632 static void ar9003_hw_configpcipowersave(struct ath_hw *ah, 633 bool power_off) 634 { 635 /* Nothing to do on restore for 11N */ 636 if (!power_off /* !restore */) { 637 /* set bit 19 to allow forcing of pcie core into L1 state */ 638 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 639 640 /* Several PCIe massages to ensure proper behaviour */ 641 if (ah->config.pcie_waen) 642 REG_WRITE(ah, AR_WA, ah->config.pcie_waen); 643 else 644 REG_WRITE(ah, AR_WA, ah->WARegVal); 645 } 646 647 /* 648 * Configire PCIE after Ini init. SERDES values now come from ini file 649 * This enables PCIe low power mode. 650 */ 651 if (ah->config.pcieSerDesWrite) { 652 unsigned int i; 653 struct ar5416IniArray *array; 654 655 array = power_off ? &ah->iniPcieSerdes : 656 &ah->iniPcieSerdesLowPower; 657 658 for (i = 0; i < array->ia_rows; i++) { 659 REG_WRITE(ah, 660 INI_RA(array, i, 0), 661 INI_RA(array, i, 1)); 662 } 663 } 664 } 665 666 /* Sets up the AR9003 hardware familiy callbacks */ 667 void ar9003_hw_attach_ops(struct ath_hw *ah) 668 { 669 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 670 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 671 672 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs; 673 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; 674 675 ops->config_pci_powersave = ar9003_hw_configpcipowersave; 676 677 ar9003_hw_attach_phy_ops(ah); 678 ar9003_hw_attach_calib_ops(ah); 679 ar9003_hw_attach_mac_ops(ah); 680 } 681