1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9003_mac.h" 19 #include "ar9003_2p2_initvals.h" 20 #include "ar9485_initvals.h" 21 #include "ar9340_initvals.h" 22 #include "ar9330_1p1_initvals.h" 23 #include "ar9330_1p2_initvals.h" 24 #include "ar9580_1p0_initvals.h" 25 #include "ar9462_1p0_initvals.h" 26 #include "ar9462_2p0_initvals.h" 27 28 /* General hardware code for the AR9003 hadware family */ 29 30 /* 31 * The AR9003 family uses a new INI format (pre, core, post 32 * arrays per subsystem). This provides support for the 33 * AR9003 2.2 chipsets. 34 */ 35 static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 36 { 37 #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \ 38 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0 39 40 #define AR9462_BB_CTX_COEFJ(x) \ 41 ar9462_##x##_baseband_core_txfir_coeff_japan_2484 42 43 #define AR9462_BBC_TXIFR_COEFFJ \ 44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 45 if (AR_SREV_9330_11(ah)) { 46 /* mac */ 47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 48 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 49 ar9331_1p1_mac_core, 50 ARRAY_SIZE(ar9331_1p1_mac_core), 2); 51 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 52 ar9331_1p1_mac_postamble, 53 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5); 54 55 /* bb */ 56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 57 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 58 ar9331_1p1_baseband_core, 59 ARRAY_SIZE(ar9331_1p1_baseband_core), 2); 60 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 61 ar9331_1p1_baseband_postamble, 62 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5); 63 64 /* radio */ 65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 66 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 67 ar9331_1p1_radio_core, 68 ARRAY_SIZE(ar9331_1p1_radio_core), 2); 69 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0); 70 71 /* soc */ 72 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 73 ar9331_1p1_soc_preamble, 74 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2); 75 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 76 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 77 ar9331_1p1_soc_postamble, 78 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2); 79 80 /* rx/tx gain */ 81 INIT_INI_ARRAY(&ah->iniModesRxGain, 82 ar9331_common_rx_gain_1p1, 83 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2); 84 INIT_INI_ARRAY(&ah->iniModesTxGain, 85 ar9331_modes_lowest_ob_db_tx_gain_1p1, 86 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1), 87 5); 88 89 /* additional clock settings */ 90 if (ah->is_clk_25mhz) 91 INIT_INI_ARRAY(&ah->iniModesAdditional, 92 ar9331_1p1_xtal_25M, 93 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2); 94 else 95 INIT_INI_ARRAY(&ah->iniModesAdditional, 96 ar9331_1p1_xtal_40M, 97 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2); 98 } else if (AR_SREV_9330_12(ah)) { 99 /* mac */ 100 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 101 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 102 ar9331_1p2_mac_core, 103 ARRAY_SIZE(ar9331_1p2_mac_core), 2); 104 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 105 ar9331_1p2_mac_postamble, 106 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5); 107 108 /* bb */ 109 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 110 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 111 ar9331_1p2_baseband_core, 112 ARRAY_SIZE(ar9331_1p2_baseband_core), 2); 113 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 114 ar9331_1p2_baseband_postamble, 115 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5); 116 117 /* radio */ 118 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 119 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 120 ar9331_1p2_radio_core, 121 ARRAY_SIZE(ar9331_1p2_radio_core), 2); 122 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0); 123 124 /* soc */ 125 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 126 ar9331_1p2_soc_preamble, 127 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2); 128 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 129 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 130 ar9331_1p2_soc_postamble, 131 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2); 132 133 /* rx/tx gain */ 134 INIT_INI_ARRAY(&ah->iniModesRxGain, 135 ar9331_common_rx_gain_1p2, 136 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2); 137 INIT_INI_ARRAY(&ah->iniModesTxGain, 138 ar9331_modes_lowest_ob_db_tx_gain_1p2, 139 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2), 140 5); 141 142 /* additional clock settings */ 143 if (ah->is_clk_25mhz) 144 INIT_INI_ARRAY(&ah->iniModesAdditional, 145 ar9331_1p2_xtal_25M, 146 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2); 147 else 148 INIT_INI_ARRAY(&ah->iniModesAdditional, 149 ar9331_1p2_xtal_40M, 150 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2); 151 } else if (AR_SREV_9340(ah)) { 152 /* mac */ 153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 154 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 155 ar9340_1p0_mac_core, 156 ARRAY_SIZE(ar9340_1p0_mac_core), 2); 157 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 158 ar9340_1p0_mac_postamble, 159 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5); 160 161 /* bb */ 162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 163 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 164 ar9340_1p0_baseband_core, 165 ARRAY_SIZE(ar9340_1p0_baseband_core), 2); 166 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 167 ar9340_1p0_baseband_postamble, 168 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5); 169 170 /* radio */ 171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 172 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 173 ar9340_1p0_radio_core, 174 ARRAY_SIZE(ar9340_1p0_radio_core), 2); 175 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 176 ar9340_1p0_radio_postamble, 177 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5); 178 179 /* soc */ 180 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 181 ar9340_1p0_soc_preamble, 182 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2); 183 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 184 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 185 ar9340_1p0_soc_postamble, 186 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5); 187 188 /* rx/tx gain */ 189 INIT_INI_ARRAY(&ah->iniModesRxGain, 190 ar9340Common_wo_xlna_rx_gain_table_1p0, 191 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0), 192 5); 193 INIT_INI_ARRAY(&ah->iniModesTxGain, 194 ar9340Modes_high_ob_db_tx_gain_table_1p0, 195 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0), 196 5); 197 198 INIT_INI_ARRAY(&ah->iniModesAdditional, 199 ar9340Modes_fast_clock_1p0, 200 ARRAY_SIZE(ar9340Modes_fast_clock_1p0), 201 3); 202 203 INIT_INI_ARRAY(&ah->iniModesAdditional_40M, 204 ar9340_1p0_radio_core_40M, 205 ARRAY_SIZE(ar9340_1p0_radio_core_40M), 206 2); 207 } else if (AR_SREV_9485_11(ah)) { 208 /* mac */ 209 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 211 ar9485_1_1_mac_core, 212 ARRAY_SIZE(ar9485_1_1_mac_core), 2); 213 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 214 ar9485_1_1_mac_postamble, 215 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5); 216 217 /* bb */ 218 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1, 219 ARRAY_SIZE(ar9485_1_1), 2); 220 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 221 ar9485_1_1_baseband_core, 222 ARRAY_SIZE(ar9485_1_1_baseband_core), 2); 223 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 224 ar9485_1_1_baseband_postamble, 225 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5); 226 227 /* radio */ 228 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 229 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 230 ar9485_1_1_radio_core, 231 ARRAY_SIZE(ar9485_1_1_radio_core), 2); 232 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 233 ar9485_1_1_radio_postamble, 234 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2); 235 236 /* soc */ 237 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 238 ar9485_1_1_soc_preamble, 239 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2); 240 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 241 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0); 242 243 /* rx/tx gain */ 244 INIT_INI_ARRAY(&ah->iniModesRxGain, 245 ar9485Common_wo_xlna_rx_gain_1_1, 246 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2); 247 INIT_INI_ARRAY(&ah->iniModesTxGain, 248 ar9485_modes_lowest_ob_db_tx_gain_1_1, 249 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), 250 5); 251 252 /* Load PCIE SERDES settings from INI */ 253 254 /* Awake Setting */ 255 256 INIT_INI_ARRAY(&ah->iniPcieSerdes, 257 ar9485_1_1_pcie_phy_clkreq_disable_L1, 258 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 259 2); 260 261 /* Sleep Setting */ 262 263 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 264 ar9485_1_1_pcie_phy_clkreq_disable_L1, 265 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 266 2); 267 } else if (AR_SREV_9462_10(ah)) { 268 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core, 270 ARRAY_SIZE(ar9462_1p0_mac_core), 2); 271 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 272 ar9462_1p0_mac_postamble, 273 ARRAY_SIZE(ar9462_1p0_mac_postamble), 274 5); 275 276 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 278 ar9462_1p0_baseband_core, 279 ARRAY_SIZE(ar9462_1p0_baseband_core), 280 2); 281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 282 ar9462_1p0_baseband_postamble, 283 ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5); 284 285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 287 ar9462_1p0_radio_core, 288 ARRAY_SIZE(ar9462_1p0_radio_core), 2); 289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 290 ar9462_1p0_radio_postamble, 291 ARRAY_SIZE(ar9462_1p0_radio_postamble), 5); 292 293 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 294 ar9462_1p0_soc_preamble, 295 ARRAY_SIZE(ar9462_1p0_soc_preamble), 2); 296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 298 ar9462_1p0_soc_postamble, 299 ARRAY_SIZE(ar9462_1p0_soc_postamble), 5); 300 301 INIT_INI_ARRAY(&ah->iniModesRxGain, 302 ar9462_common_rx_gain_table_1p0, 303 ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2); 304 305 /* Awake -> Sleep Setting */ 306 INIT_INI_ARRAY(&ah->iniPcieSerdes, 307 ar9462_pcie_phy_clkreq_disable_L1_1p0, 308 ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0), 309 2); 310 311 /* Sleep -> Awake Setting */ 312 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 313 ar9462_pcie_phy_clkreq_disable_L1_1p0, 314 ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0), 315 2); 316 317 INIT_INI_ARRAY(&ah->iniModesAdditional, 318 ar9462_modes_fast_clock_1p0, 319 ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3); 320 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 321 AR9462_BB_CTX_COEFJ(1p0), 322 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2); 323 324 } else if (AR_SREV_9462_20(ah)) { 325 326 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 327 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core, 328 ARRAY_SIZE(ar9462_2p0_mac_core), 2); 329 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 330 ar9462_2p0_mac_postamble, 331 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5); 332 333 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 334 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 335 ar9462_2p0_baseband_core, 336 ARRAY_SIZE(ar9462_2p0_baseband_core), 2); 337 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 338 ar9462_2p0_baseband_postamble, 339 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5); 340 341 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 342 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 343 ar9462_2p0_radio_core, 344 ARRAY_SIZE(ar9462_2p0_radio_core), 2); 345 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 346 ar9462_2p0_radio_postamble, 347 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5); 348 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 349 ar9462_2p0_radio_postamble_sys2ant, 350 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant), 351 5); 352 353 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 354 ar9462_2p0_soc_preamble, 355 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2); 356 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 357 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 358 ar9462_2p0_soc_postamble, 359 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5); 360 361 INIT_INI_ARRAY(&ah->iniModesRxGain, 362 ar9462_common_rx_gain_table_2p0, 363 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2); 364 365 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR, 366 ar9462_2p0_BTCOEX_MAX_TXPWR_table, 367 ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table), 368 2); 369 370 /* Awake -> Sleep Setting */ 371 INIT_INI_ARRAY(&ah->iniPcieSerdes, 372 PCIE_PLL_ON_CREQ_DIS_L1_2P0, 373 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), 374 2); 375 /* Sleep -> Awake Setting */ 376 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 377 PCIE_PLL_ON_CREQ_DIS_L1_2P0, 378 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0), 379 2); 380 381 /* Fast clock modal settings */ 382 INIT_INI_ARRAY(&ah->iniModesAdditional, 383 ar9462_modes_fast_clock_2p0, 384 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3); 385 386 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 387 AR9462_BB_CTX_COEFJ(2p0), 388 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2); 389 390 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ, 391 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2); 392 393 } else if (AR_SREV_9580(ah)) { 394 /* mac */ 395 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 396 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 397 ar9580_1p0_mac_core, 398 ARRAY_SIZE(ar9580_1p0_mac_core), 2); 399 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 400 ar9580_1p0_mac_postamble, 401 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5); 402 403 /* bb */ 404 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 405 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 406 ar9580_1p0_baseband_core, 407 ARRAY_SIZE(ar9580_1p0_baseband_core), 2); 408 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 409 ar9580_1p0_baseband_postamble, 410 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5); 411 412 /* radio */ 413 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 414 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 415 ar9580_1p0_radio_core, 416 ARRAY_SIZE(ar9580_1p0_radio_core), 2); 417 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 418 ar9580_1p0_radio_postamble, 419 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5); 420 421 /* soc */ 422 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 423 ar9580_1p0_soc_preamble, 424 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2); 425 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 426 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 427 ar9580_1p0_soc_postamble, 428 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5); 429 430 /* rx/tx gain */ 431 INIT_INI_ARRAY(&ah->iniModesRxGain, 432 ar9580_1p0_rx_gain_table, 433 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2); 434 INIT_INI_ARRAY(&ah->iniModesTxGain, 435 ar9580_1p0_low_ob_db_tx_gain_table, 436 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table), 437 5); 438 439 INIT_INI_ARRAY(&ah->iniModesAdditional, 440 ar9580_1p0_modes_fast_clock, 441 ARRAY_SIZE(ar9580_1p0_modes_fast_clock), 442 3); 443 } else { 444 /* mac */ 445 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 446 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 447 ar9300_2p2_mac_core, 448 ARRAY_SIZE(ar9300_2p2_mac_core), 2); 449 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 450 ar9300_2p2_mac_postamble, 451 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5); 452 453 /* bb */ 454 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 455 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 456 ar9300_2p2_baseband_core, 457 ARRAY_SIZE(ar9300_2p2_baseband_core), 2); 458 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 459 ar9300_2p2_baseband_postamble, 460 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5); 461 462 /* radio */ 463 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 464 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 465 ar9300_2p2_radio_core, 466 ARRAY_SIZE(ar9300_2p2_radio_core), 2); 467 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 468 ar9300_2p2_radio_postamble, 469 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5); 470 471 /* soc */ 472 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 473 ar9300_2p2_soc_preamble, 474 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2); 475 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 476 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 477 ar9300_2p2_soc_postamble, 478 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5); 479 480 /* rx/tx gain */ 481 INIT_INI_ARRAY(&ah->iniModesRxGain, 482 ar9300Common_rx_gain_table_2p2, 483 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2); 484 INIT_INI_ARRAY(&ah->iniModesTxGain, 485 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 486 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), 487 5); 488 489 /* Load PCIE SERDES settings from INI */ 490 491 /* Awake Setting */ 492 493 INIT_INI_ARRAY(&ah->iniPcieSerdes, 494 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, 495 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2), 496 2); 497 498 /* Sleep Setting */ 499 500 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 501 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, 502 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2), 503 2); 504 505 /* Fast clock modal settings */ 506 INIT_INI_ARRAY(&ah->iniModesAdditional, 507 ar9300Modes_fast_clock_2p2, 508 ARRAY_SIZE(ar9300Modes_fast_clock_2p2), 509 3); 510 } 511 } 512 513 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 514 { 515 if (AR_SREV_9330_12(ah)) 516 INIT_INI_ARRAY(&ah->iniModesTxGain, 517 ar9331_modes_lowest_ob_db_tx_gain_1p2, 518 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2), 519 5); 520 else if (AR_SREV_9330_11(ah)) 521 INIT_INI_ARRAY(&ah->iniModesTxGain, 522 ar9331_modes_lowest_ob_db_tx_gain_1p1, 523 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1), 524 5); 525 else if (AR_SREV_9340(ah)) 526 INIT_INI_ARRAY(&ah->iniModesTxGain, 527 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 528 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 529 5); 530 else if (AR_SREV_9485_11(ah)) 531 INIT_INI_ARRAY(&ah->iniModesTxGain, 532 ar9485_modes_lowest_ob_db_tx_gain_1_1, 533 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), 534 5); 535 else if (AR_SREV_9580(ah)) 536 INIT_INI_ARRAY(&ah->iniModesTxGain, 537 ar9580_1p0_lowest_ob_db_tx_gain_table, 538 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table), 539 5); 540 else if (AR_SREV_9462_10(ah)) 541 INIT_INI_ARRAY(&ah->iniModesTxGain, 542 ar9462_modes_low_ob_db_tx_gain_table_1p0, 543 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0), 544 5); 545 else if (AR_SREV_9462_20(ah)) 546 INIT_INI_ARRAY(&ah->iniModesTxGain, 547 ar9462_modes_low_ob_db_tx_gain_table_2p0, 548 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0), 549 5); 550 else 551 INIT_INI_ARRAY(&ah->iniModesTxGain, 552 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 553 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2), 554 5); 555 } 556 557 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 558 { 559 if (AR_SREV_9330_12(ah)) 560 INIT_INI_ARRAY(&ah->iniModesTxGain, 561 ar9331_modes_high_ob_db_tx_gain_1p2, 562 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2), 563 5); 564 else if (AR_SREV_9330_11(ah)) 565 INIT_INI_ARRAY(&ah->iniModesTxGain, 566 ar9331_modes_high_ob_db_tx_gain_1p1, 567 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1), 568 5); 569 else if (AR_SREV_9340(ah)) 570 INIT_INI_ARRAY(&ah->iniModesTxGain, 571 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 572 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 573 5); 574 else if (AR_SREV_9485_11(ah)) 575 INIT_INI_ARRAY(&ah->iniModesTxGain, 576 ar9485Modes_high_ob_db_tx_gain_1_1, 577 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1), 578 5); 579 else if (AR_SREV_9580(ah)) 580 INIT_INI_ARRAY(&ah->iniModesTxGain, 581 ar9580_1p0_high_ob_db_tx_gain_table, 582 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table), 583 5); 584 else if (AR_SREV_9462_10(ah)) 585 INIT_INI_ARRAY(&ah->iniModesTxGain, 586 ar9462_modes_high_ob_db_tx_gain_table_1p0, 587 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0), 588 5); 589 else if (AR_SREV_9462_20(ah)) 590 INIT_INI_ARRAY(&ah->iniModesTxGain, 591 ar9462_modes_high_ob_db_tx_gain_table_2p0, 592 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0), 593 5); 594 else 595 INIT_INI_ARRAY(&ah->iniModesTxGain, 596 ar9300Modes_high_ob_db_tx_gain_table_2p2, 597 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2), 598 5); 599 } 600 601 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) 602 { 603 if (AR_SREV_9330_12(ah)) 604 INIT_INI_ARRAY(&ah->iniModesTxGain, 605 ar9331_modes_low_ob_db_tx_gain_1p2, 606 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2), 607 5); 608 else if (AR_SREV_9330_11(ah)) 609 INIT_INI_ARRAY(&ah->iniModesTxGain, 610 ar9331_modes_low_ob_db_tx_gain_1p1, 611 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1), 612 5); 613 else if (AR_SREV_9340(ah)) 614 INIT_INI_ARRAY(&ah->iniModesTxGain, 615 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 616 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 617 5); 618 else if (AR_SREV_9485_11(ah)) 619 INIT_INI_ARRAY(&ah->iniModesTxGain, 620 ar9485Modes_low_ob_db_tx_gain_1_1, 621 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1), 622 5); 623 else if (AR_SREV_9580(ah)) 624 INIT_INI_ARRAY(&ah->iniModesTxGain, 625 ar9580_1p0_low_ob_db_tx_gain_table, 626 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table), 627 5); 628 else 629 INIT_INI_ARRAY(&ah->iniModesTxGain, 630 ar9300Modes_low_ob_db_tx_gain_table_2p2, 631 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2), 632 5); 633 } 634 635 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) 636 { 637 if (AR_SREV_9330_12(ah)) 638 INIT_INI_ARRAY(&ah->iniModesTxGain, 639 ar9331_modes_high_power_tx_gain_1p2, 640 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2), 641 5); 642 else if (AR_SREV_9330_11(ah)) 643 INIT_INI_ARRAY(&ah->iniModesTxGain, 644 ar9331_modes_high_power_tx_gain_1p1, 645 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1), 646 5); 647 else if (AR_SREV_9340(ah)) 648 INIT_INI_ARRAY(&ah->iniModesTxGain, 649 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 650 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 651 5); 652 else if (AR_SREV_9485_11(ah)) 653 INIT_INI_ARRAY(&ah->iniModesTxGain, 654 ar9485Modes_high_power_tx_gain_1_1, 655 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1), 656 5); 657 else if (AR_SREV_9580(ah)) 658 INIT_INI_ARRAY(&ah->iniModesTxGain, 659 ar9580_1p0_high_power_tx_gain_table, 660 ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table), 661 5); 662 else 663 INIT_INI_ARRAY(&ah->iniModesTxGain, 664 ar9300Modes_high_power_tx_gain_table_2p2, 665 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2), 666 5); 667 } 668 669 static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 670 { 671 switch (ar9003_hw_get_tx_gain_idx(ah)) { 672 case 0: 673 default: 674 ar9003_tx_gain_table_mode0(ah); 675 break; 676 case 1: 677 ar9003_tx_gain_table_mode1(ah); 678 break; 679 case 2: 680 ar9003_tx_gain_table_mode2(ah); 681 break; 682 case 3: 683 ar9003_tx_gain_table_mode3(ah); 684 break; 685 } 686 } 687 688 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 689 { 690 if (AR_SREV_9330_12(ah)) 691 INIT_INI_ARRAY(&ah->iniModesRxGain, 692 ar9331_common_rx_gain_1p2, 693 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 694 2); 695 else if (AR_SREV_9330_11(ah)) 696 INIT_INI_ARRAY(&ah->iniModesRxGain, 697 ar9331_common_rx_gain_1p1, 698 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 699 2); 700 else if (AR_SREV_9340(ah)) 701 INIT_INI_ARRAY(&ah->iniModesRxGain, 702 ar9340Common_rx_gain_table_1p0, 703 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0), 704 2); 705 else if (AR_SREV_9485_11(ah)) 706 INIT_INI_ARRAY(&ah->iniModesRxGain, 707 ar9485Common_wo_xlna_rx_gain_1_1, 708 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 709 2); 710 else if (AR_SREV_9580(ah)) 711 INIT_INI_ARRAY(&ah->iniModesRxGain, 712 ar9580_1p0_rx_gain_table, 713 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 714 2); 715 else if (AR_SREV_9462_10(ah)) 716 INIT_INI_ARRAY(&ah->iniModesRxGain, 717 ar9462_common_rx_gain_table_1p0, 718 ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 719 2); 720 else if (AR_SREV_9462_20(ah)) 721 INIT_INI_ARRAY(&ah->iniModesRxGain, 722 ar9462_common_rx_gain_table_2p0, 723 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 724 2); 725 else 726 INIT_INI_ARRAY(&ah->iniModesRxGain, 727 ar9300Common_rx_gain_table_2p2, 728 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 729 2); 730 } 731 732 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 733 { 734 if (AR_SREV_9330_12(ah)) 735 INIT_INI_ARRAY(&ah->iniModesRxGain, 736 ar9331_common_wo_xlna_rx_gain_1p2, 737 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2), 738 2); 739 else if (AR_SREV_9330_11(ah)) 740 INIT_INI_ARRAY(&ah->iniModesRxGain, 741 ar9331_common_wo_xlna_rx_gain_1p1, 742 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1), 743 2); 744 else if (AR_SREV_9340(ah)) 745 INIT_INI_ARRAY(&ah->iniModesRxGain, 746 ar9340Common_wo_xlna_rx_gain_table_1p0, 747 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0), 748 2); 749 else if (AR_SREV_9485_11(ah)) 750 INIT_INI_ARRAY(&ah->iniModesRxGain, 751 ar9485Common_wo_xlna_rx_gain_1_1, 752 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 753 2); 754 else if (AR_SREV_9462_10(ah)) 755 INIT_INI_ARRAY(&ah->iniModesRxGain, 756 ar9462_common_wo_xlna_rx_gain_table_1p0, 757 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0), 758 2); 759 else if (AR_SREV_9462_20(ah)) 760 INIT_INI_ARRAY(&ah->iniModesRxGain, 761 ar9462_common_wo_xlna_rx_gain_table_2p0, 762 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0), 763 2); 764 else if (AR_SREV_9580(ah)) 765 INIT_INI_ARRAY(&ah->iniModesRxGain, 766 ar9580_1p0_wo_xlna_rx_gain_table, 767 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table), 768 2); 769 else 770 INIT_INI_ARRAY(&ah->iniModesRxGain, 771 ar9300Common_wo_xlna_rx_gain_table_2p2, 772 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2), 773 2); 774 } 775 776 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 777 { 778 if (AR_SREV_9462_10(ah)) 779 INIT_INI_ARRAY(&ah->iniModesRxGain, 780 ar9462_common_mixed_rx_gain_table_1p0, 781 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2); 782 else if (AR_SREV_9462_20(ah)) 783 INIT_INI_ARRAY(&ah->iniModesRxGain, 784 ar9462_common_mixed_rx_gain_table_2p0, 785 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2); 786 } 787 788 static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 789 { 790 switch (ar9003_hw_get_rx_gain_idx(ah)) { 791 case 0: 792 default: 793 ar9003_rx_gain_table_mode0(ah); 794 break; 795 case 1: 796 ar9003_rx_gain_table_mode1(ah); 797 break; 798 case 2: 799 ar9003_rx_gain_table_mode2(ah); 800 break; 801 } 802 } 803 804 /* set gain table pointers according to values read from the eeprom */ 805 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) 806 { 807 ar9003_tx_gain_table_apply(ah); 808 ar9003_rx_gain_table_apply(ah); 809 } 810 811 /* 812 * Helper for ASPM support. 813 * 814 * Disable PLL when in L0s as well as receiver clock when in L1. 815 * This power saving option must be enabled through the SerDes. 816 * 817 * Programming the SerDes must go through the same 288 bit serial shift 818 * register as the other analog registers. Hence the 9 writes. 819 */ 820 static void ar9003_hw_configpcipowersave(struct ath_hw *ah, 821 bool power_off) 822 { 823 /* Nothing to do on restore for 11N */ 824 if (!power_off /* !restore */) { 825 /* set bit 19 to allow forcing of pcie core into L1 state */ 826 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 827 828 /* Several PCIe massages to ensure proper behaviour */ 829 if (ah->config.pcie_waen) 830 REG_WRITE(ah, AR_WA, ah->config.pcie_waen); 831 else 832 REG_WRITE(ah, AR_WA, ah->WARegVal); 833 } 834 835 /* 836 * Configire PCIE after Ini init. SERDES values now come from ini file 837 * This enables PCIe low power mode. 838 */ 839 if (ah->config.pcieSerDesWrite) { 840 unsigned int i; 841 struct ar5416IniArray *array; 842 843 array = power_off ? &ah->iniPcieSerdes : 844 &ah->iniPcieSerdesLowPower; 845 846 for (i = 0; i < array->ia_rows; i++) { 847 REG_WRITE(ah, 848 INI_RA(array, i, 0), 849 INI_RA(array, i, 1)); 850 } 851 } 852 } 853 854 /* Sets up the AR9003 hardware familiy callbacks */ 855 void ar9003_hw_attach_ops(struct ath_hw *ah) 856 { 857 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 858 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 859 860 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs; 861 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; 862 863 ops->config_pci_powersave = ar9003_hw_configpcipowersave; 864 865 ar9003_hw_attach_phy_ops(ah); 866 ar9003_hw_attach_calib_ops(ah); 867 ar9003_hw_attach_mac_ops(ah); 868 } 869