1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "ar9003_mac.h" 19 #include "ar9003_2p2_initvals.h" 20 #include "ar9003_buffalo_initvals.h" 21 #include "ar9485_initvals.h" 22 #include "ar9340_initvals.h" 23 #include "ar9330_1p1_initvals.h" 24 #include "ar9330_1p2_initvals.h" 25 #include "ar955x_1p0_initvals.h" 26 #include "ar9580_1p0_initvals.h" 27 #include "ar9462_2p0_initvals.h" 28 #include "ar9462_2p1_initvals.h" 29 #include "ar9565_1p0_initvals.h" 30 #include "ar9565_1p1_initvals.h" 31 #include "ar953x_initvals.h" 32 #include "ar956x_initvals.h" 33 34 /* General hardware code for the AR9003 hadware family */ 35 36 /* 37 * The AR9003 family uses a new INI format (pre, core, post 38 * arrays per subsystem). This provides support for the 39 * AR9003 2.2 chipsets. 40 */ 41 static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 42 { 43 if (AR_SREV_9330_11(ah)) { 44 /* mac */ 45 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 46 ar9331_1p1_mac_core); 47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 48 ar9331_1p1_mac_postamble); 49 50 /* bb */ 51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 52 ar9331_1p1_baseband_core); 53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 54 ar9331_1p1_baseband_postamble); 55 56 /* radio */ 57 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 58 ar9331_1p1_radio_core); 59 60 /* soc */ 61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 62 ar9331_1p1_soc_preamble); 63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 64 ar9331_1p1_soc_postamble); 65 66 /* rx/tx gain */ 67 INIT_INI_ARRAY(&ah->iniModesRxGain, 68 ar9331_common_rx_gain_1p1); 69 INIT_INI_ARRAY(&ah->iniModesTxGain, 70 ar9331_modes_lowest_ob_db_tx_gain_1p1); 71 72 /* Japan 2484 Mhz CCK */ 73 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 74 ar9331_1p1_baseband_core_txfir_coeff_japan_2484); 75 76 /* additional clock settings */ 77 if (ah->is_clk_25mhz) 78 INIT_INI_ARRAY(&ah->iniAdditional, 79 ar9331_1p1_xtal_25M); 80 else 81 INIT_INI_ARRAY(&ah->iniAdditional, 82 ar9331_1p1_xtal_40M); 83 } else if (AR_SREV_9330_12(ah)) { 84 /* mac */ 85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 86 ar9331_1p2_mac_core); 87 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 88 ar9331_1p2_mac_postamble); 89 90 /* bb */ 91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 92 ar9331_1p2_baseband_core); 93 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 94 ar9331_1p2_baseband_postamble); 95 96 /* radio */ 97 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 98 ar9331_1p2_radio_core); 99 100 /* soc */ 101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 102 ar9331_1p2_soc_preamble); 103 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 104 ar9331_1p2_soc_postamble); 105 106 /* rx/tx gain */ 107 INIT_INI_ARRAY(&ah->iniModesRxGain, 108 ar9331_common_rx_gain_1p2); 109 INIT_INI_ARRAY(&ah->iniModesTxGain, 110 ar9331_modes_lowest_ob_db_tx_gain_1p2); 111 112 /* Japan 2484 Mhz CCK */ 113 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 114 ar9331_1p2_baseband_core_txfir_coeff_japan_2484); 115 116 /* additional clock settings */ 117 if (ah->is_clk_25mhz) 118 INIT_INI_ARRAY(&ah->iniAdditional, 119 ar9331_1p2_xtal_25M); 120 else 121 INIT_INI_ARRAY(&ah->iniAdditional, 122 ar9331_1p2_xtal_40M); 123 } else if (AR_SREV_9340(ah)) { 124 /* mac */ 125 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 126 ar9340_1p0_mac_core); 127 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 128 ar9340_1p0_mac_postamble); 129 130 /* bb */ 131 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 132 ar9340_1p0_baseband_core); 133 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 134 ar9340_1p0_baseband_postamble); 135 136 /* radio */ 137 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 138 ar9340_1p0_radio_core); 139 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 140 ar9340_1p0_radio_postamble); 141 142 /* soc */ 143 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 144 ar9340_1p0_soc_preamble); 145 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 146 ar9340_1p0_soc_postamble); 147 148 /* rx/tx gain */ 149 INIT_INI_ARRAY(&ah->iniModesRxGain, 150 ar9340Common_wo_xlna_rx_gain_table_1p0); 151 INIT_INI_ARRAY(&ah->iniModesTxGain, 152 ar9340Modes_high_ob_db_tx_gain_table_1p0); 153 154 INIT_INI_ARRAY(&ah->iniModesFastClock, 155 ar9340Modes_fast_clock_1p0); 156 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 157 ar9340_1p0_baseband_core_txfir_coeff_japan_2484); 158 INIT_INI_ARRAY(&ah->ini_dfs, 159 ar9340_1p0_baseband_postamble_dfs_channel); 160 161 if (!ah->is_clk_25mhz) 162 INIT_INI_ARRAY(&ah->iniAdditional, 163 ar9340_1p0_radio_core_40M); 164 } else if (AR_SREV_9485_11_OR_LATER(ah)) { 165 /* mac */ 166 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 167 ar9485_1_1_mac_core); 168 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 169 ar9485_1_1_mac_postamble); 170 171 /* bb */ 172 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1); 173 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 174 ar9485_1_1_baseband_core); 175 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 176 ar9485_1_1_baseband_postamble); 177 178 /* radio */ 179 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 180 ar9485_1_1_radio_core); 181 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 182 ar9485_1_1_radio_postamble); 183 184 /* soc */ 185 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 186 ar9485_1_1_soc_preamble); 187 188 /* rx/tx gain */ 189 INIT_INI_ARRAY(&ah->iniModesRxGain, 190 ar9485Common_wo_xlna_rx_gain_1_1); 191 INIT_INI_ARRAY(&ah->iniModesTxGain, 192 ar9485_modes_lowest_ob_db_tx_gain_1_1); 193 194 /* Japan 2484 Mhz CCK */ 195 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 196 ar9485_1_1_baseband_core_txfir_coeff_japan_2484); 197 198 if (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) { 199 INIT_INI_ARRAY(&ah->iniPcieSerdes, 200 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1); 201 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 202 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1); 203 } else { 204 INIT_INI_ARRAY(&ah->iniPcieSerdes, 205 ar9485_1_1_pcie_phy_clkreq_disable_L1); 206 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 207 ar9485_1_1_pcie_phy_clkreq_disable_L1); 208 } 209 } else if (AR_SREV_9462_21(ah)) { 210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 211 ar9462_2p1_mac_core); 212 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 213 ar9462_2p1_mac_postamble); 214 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 215 ar9462_2p1_baseband_core); 216 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 217 ar9462_2p1_baseband_postamble); 218 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 219 ar9462_2p1_radio_core); 220 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 221 ar9462_2p1_radio_postamble); 222 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 223 ar9462_2p1_radio_postamble_sys2ant); 224 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 225 ar9462_2p1_soc_preamble); 226 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 227 ar9462_2p1_soc_postamble); 228 INIT_INI_ARRAY(&ah->iniModesRxGain, 229 ar9462_2p1_common_rx_gain); 230 INIT_INI_ARRAY(&ah->iniModesFastClock, 231 ar9462_2p1_modes_fast_clock); 232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 233 ar9462_2p1_baseband_core_txfir_coeff_japan_2484); 234 235 /* Awake -> Sleep Setting */ 236 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 237 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) { 238 INIT_INI_ARRAY(&ah->iniPcieSerdes, 239 ar9462_2p1_pciephy_clkreq_disable_L1); 240 } 241 242 /* Sleep -> Awake Setting */ 243 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 244 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) { 245 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 246 ar9462_2p1_pciephy_clkreq_disable_L1); 247 } 248 } else if (AR_SREV_9462_20(ah)) { 249 250 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); 251 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 252 ar9462_2p0_mac_postamble); 253 254 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 255 ar9462_2p0_baseband_core); 256 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 257 ar9462_2p0_baseband_postamble); 258 259 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 260 ar9462_2p0_radio_core); 261 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 262 ar9462_2p0_radio_postamble); 263 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 264 ar9462_2p0_radio_postamble_sys2ant); 265 266 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 267 ar9462_2p0_soc_preamble); 268 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 269 ar9462_2p0_soc_postamble); 270 271 INIT_INI_ARRAY(&ah->iniModesRxGain, 272 ar9462_2p0_common_rx_gain); 273 274 /* Awake -> Sleep Setting */ 275 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 276 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) { 277 INIT_INI_ARRAY(&ah->iniPcieSerdes, 278 ar9462_2p0_pciephy_clkreq_disable_L1); 279 } 280 281 /* Sleep -> Awake Setting */ 282 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 283 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) { 284 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 285 ar9462_2p0_pciephy_clkreq_disable_L1); 286 } 287 288 /* Fast clock modal settings */ 289 INIT_INI_ARRAY(&ah->iniModesFastClock, 290 ar9462_2p0_modes_fast_clock); 291 292 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 293 ar9462_2p0_baseband_core_txfir_coeff_japan_2484); 294 } else if (AR_SREV_9550(ah)) { 295 /* mac */ 296 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 297 ar955x_1p0_mac_core); 298 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 299 ar955x_1p0_mac_postamble); 300 301 /* bb */ 302 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 303 ar955x_1p0_baseband_core); 304 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 305 ar955x_1p0_baseband_postamble); 306 307 /* radio */ 308 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 309 ar955x_1p0_radio_core); 310 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 311 ar955x_1p0_radio_postamble); 312 313 /* soc */ 314 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 315 ar955x_1p0_soc_preamble); 316 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 317 ar955x_1p0_soc_postamble); 318 319 /* rx/tx gain */ 320 INIT_INI_ARRAY(&ah->iniModesRxGain, 321 ar955x_1p0_common_wo_xlna_rx_gain_table); 322 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 323 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 324 INIT_INI_ARRAY(&ah->iniModesTxGain, 325 ar955x_1p0_modes_xpa_tx_gain_table); 326 327 /* Fast clock modal settings */ 328 INIT_INI_ARRAY(&ah->iniModesFastClock, 329 ar955x_1p0_modes_fast_clock); 330 } else if (AR_SREV_9531(ah)) { 331 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 332 qca953x_1p0_mac_core); 333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 334 qca953x_1p0_mac_postamble); 335 if (AR_SREV_9531_20(ah)) { 336 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 337 qca953x_2p0_baseband_core); 338 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 339 qca953x_2p0_baseband_postamble); 340 } else { 341 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 342 qca953x_1p0_baseband_core); 343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 344 qca953x_1p0_baseband_postamble); 345 } 346 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 347 qca953x_1p0_radio_core); 348 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 349 qca953x_1p0_radio_postamble); 350 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 351 qca953x_1p0_soc_preamble); 352 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 353 qca953x_1p0_soc_postamble); 354 355 if (AR_SREV_9531_20(ah)) { 356 INIT_INI_ARRAY(&ah->iniModesRxGain, 357 qca953x_2p0_common_wo_xlna_rx_gain_table); 358 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 359 qca953x_2p0_common_wo_xlna_rx_gain_bounds); 360 } else { 361 INIT_INI_ARRAY(&ah->iniModesRxGain, 362 qca953x_1p0_common_wo_xlna_rx_gain_table); 363 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 364 qca953x_1p0_common_wo_xlna_rx_gain_bounds); 365 } 366 367 if (AR_SREV_9531_20(ah)) 368 INIT_INI_ARRAY(&ah->iniModesTxGain, 369 qca953x_2p0_modes_no_xpa_tx_gain_table); 370 else if (AR_SREV_9531_11(ah)) 371 INIT_INI_ARRAY(&ah->iniModesTxGain, 372 qca953x_1p1_modes_no_xpa_tx_gain_table); 373 else 374 INIT_INI_ARRAY(&ah->iniModesTxGain, 375 qca953x_1p0_modes_no_xpa_tx_gain_table); 376 377 INIT_INI_ARRAY(&ah->iniModesFastClock, 378 qca953x_1p0_modes_fast_clock); 379 } else if (AR_SREV_9561(ah)) { 380 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 381 qca956x_1p0_mac_core); 382 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 383 qca956x_1p0_mac_postamble); 384 385 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 386 qca956x_1p0_baseband_core); 387 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 388 qca956x_1p0_baseband_postamble); 389 390 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 391 qca956x_1p0_radio_core); 392 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 393 qca956x_1p0_radio_postamble); 394 395 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 396 qca956x_1p0_soc_preamble); 397 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 398 qca956x_1p0_soc_postamble); 399 400 INIT_INI_ARRAY(&ah->iniModesRxGain, 401 qca956x_1p0_common_wo_xlna_rx_gain_table); 402 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 403 qca956x_1p0_common_wo_xlna_rx_gain_bounds); 404 INIT_INI_ARRAY(&ah->iniModesTxGain, 405 qca956x_1p0_modes_no_xpa_tx_gain_table); 406 407 INIT_INI_ARRAY(&ah->ini_dfs, 408 qca956x_1p0_baseband_postamble_dfs_channel); 409 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 410 qca956x_1p0_baseband_core_txfir_coeff_japan_2484); 411 INIT_INI_ARRAY(&ah->iniModesFastClock, 412 qca956x_1p0_modes_fast_clock); 413 } else if (AR_SREV_9580(ah)) { 414 /* mac */ 415 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 416 ar9580_1p0_mac_core); 417 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 418 ar9580_1p0_mac_postamble); 419 420 /* bb */ 421 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 422 ar9580_1p0_baseband_core); 423 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 424 ar9580_1p0_baseband_postamble); 425 426 /* radio */ 427 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 428 ar9580_1p0_radio_core); 429 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 430 ar9580_1p0_radio_postamble); 431 432 /* soc */ 433 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 434 ar9580_1p0_soc_preamble); 435 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 436 ar9580_1p0_soc_postamble); 437 438 /* rx/tx gain */ 439 INIT_INI_ARRAY(&ah->iniModesRxGain, 440 ar9580_1p0_rx_gain_table); 441 INIT_INI_ARRAY(&ah->iniModesTxGain, 442 ar9580_1p0_low_ob_db_tx_gain_table); 443 444 INIT_INI_ARRAY(&ah->iniModesFastClock, 445 ar9580_1p0_modes_fast_clock); 446 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 447 ar9580_1p0_baseband_core_txfir_coeff_japan_2484); 448 INIT_INI_ARRAY(&ah->ini_dfs, 449 ar9580_1p0_baseband_postamble_dfs_channel); 450 } else if (AR_SREV_9565_11_OR_LATER(ah)) { 451 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 452 ar9565_1p1_mac_core); 453 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 454 ar9565_1p1_mac_postamble); 455 456 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 457 ar9565_1p1_baseband_core); 458 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 459 ar9565_1p1_baseband_postamble); 460 461 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 462 ar9565_1p1_radio_core); 463 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 464 ar9565_1p1_radio_postamble); 465 466 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 467 ar9565_1p1_soc_preamble); 468 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 469 ar9565_1p1_soc_postamble); 470 471 INIT_INI_ARRAY(&ah->iniModesRxGain, 472 ar9565_1p1_Common_rx_gain_table); 473 INIT_INI_ARRAY(&ah->iniModesTxGain, 474 ar9565_1p1_Modes_lowest_ob_db_tx_gain_table); 475 476 /* Awake -> Sleep Setting */ 477 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 478 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) { 479 INIT_INI_ARRAY(&ah->iniPcieSerdes, 480 ar9565_1p1_pciephy_clkreq_disable_L1); 481 } 482 483 /* Sleep -> Awake Setting */ 484 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 485 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) { 486 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 487 ar9565_1p1_pciephy_clkreq_disable_L1); 488 } 489 490 INIT_INI_ARRAY(&ah->iniModesFastClock, 491 ar9565_1p1_modes_fast_clock); 492 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 493 ar9565_1p1_baseband_core_txfir_coeff_japan_2484); 494 } else if (AR_SREV_9565(ah)) { 495 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 496 ar9565_1p0_mac_core); 497 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 498 ar9565_1p0_mac_postamble); 499 500 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 501 ar9565_1p0_baseband_core); 502 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 503 ar9565_1p0_baseband_postamble); 504 505 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 506 ar9565_1p0_radio_core); 507 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 508 ar9565_1p0_radio_postamble); 509 510 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 511 ar9565_1p0_soc_preamble); 512 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 513 ar9565_1p0_soc_postamble); 514 515 INIT_INI_ARRAY(&ah->iniModesRxGain, 516 ar9565_1p0_Common_rx_gain_table); 517 INIT_INI_ARRAY(&ah->iniModesTxGain, 518 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table); 519 520 /* Awake -> Sleep Setting */ 521 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 522 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D3)) { 523 INIT_INI_ARRAY(&ah->iniPcieSerdes, 524 ar9565_1p0_pciephy_clkreq_disable_L1); 525 } 526 527 /* Sleep -> Awake Setting */ 528 if ((ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_CONTROL) && 529 (ah->config.pll_pwrsave & AR_PCIE_PLL_PWRSAVE_ON_D0)) { 530 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 531 ar9565_1p0_pciephy_clkreq_disable_L1); 532 } 533 534 INIT_INI_ARRAY(&ah->iniModesFastClock, 535 ar9565_1p0_modes_fast_clock); 536 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 537 ar9565_1p0_baseband_core_txfir_coeff_japan_2484); 538 } else { 539 /* mac */ 540 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 541 ar9300_2p2_mac_core); 542 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 543 ar9300_2p2_mac_postamble); 544 545 /* bb */ 546 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 547 ar9300_2p2_baseband_core); 548 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 549 ar9300_2p2_baseband_postamble); 550 551 /* radio */ 552 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 553 ar9300_2p2_radio_core); 554 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 555 ar9300_2p2_radio_postamble); 556 557 /* soc */ 558 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 559 ar9300_2p2_soc_preamble); 560 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 561 ar9300_2p2_soc_postamble); 562 563 /* rx/tx gain */ 564 INIT_INI_ARRAY(&ah->iniModesRxGain, 565 ar9300Common_rx_gain_table_2p2); 566 INIT_INI_ARRAY(&ah->iniModesTxGain, 567 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 568 569 /* Load PCIE SERDES settings from INI */ 570 571 /* Awake Setting */ 572 573 INIT_INI_ARRAY(&ah->iniPcieSerdes, 574 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 575 576 /* Sleep Setting */ 577 578 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 579 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); 580 581 /* Fast clock modal settings */ 582 INIT_INI_ARRAY(&ah->iniModesFastClock, 583 ar9300Modes_fast_clock_2p2); 584 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 585 ar9300_2p2_baseband_core_txfir_coeff_japan_2484); 586 INIT_INI_ARRAY(&ah->ini_dfs, 587 ar9300_2p2_baseband_postamble_dfs_channel); 588 } 589 } 590 591 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 592 { 593 if (AR_SREV_9330_12(ah)) 594 INIT_INI_ARRAY(&ah->iniModesTxGain, 595 ar9331_modes_lowest_ob_db_tx_gain_1p2); 596 else if (AR_SREV_9330_11(ah)) 597 INIT_INI_ARRAY(&ah->iniModesTxGain, 598 ar9331_modes_lowest_ob_db_tx_gain_1p1); 599 else if (AR_SREV_9340(ah)) 600 INIT_INI_ARRAY(&ah->iniModesTxGain, 601 ar9340Modes_lowest_ob_db_tx_gain_table_1p0); 602 else if (AR_SREV_9485_11_OR_LATER(ah)) 603 INIT_INI_ARRAY(&ah->iniModesTxGain, 604 ar9485_modes_lowest_ob_db_tx_gain_1_1); 605 else if (AR_SREV_9550(ah)) 606 INIT_INI_ARRAY(&ah->iniModesTxGain, 607 ar955x_1p0_modes_xpa_tx_gain_table); 608 else if (AR_SREV_9531_10(ah)) 609 INIT_INI_ARRAY(&ah->iniModesTxGain, 610 qca953x_1p0_modes_xpa_tx_gain_table); 611 else if (AR_SREV_9531_11(ah)) 612 INIT_INI_ARRAY(&ah->iniModesTxGain, 613 qca953x_1p1_modes_xpa_tx_gain_table); 614 else if (AR_SREV_9531_20(ah)) 615 INIT_INI_ARRAY(&ah->iniModesTxGain, 616 qca953x_2p0_modes_xpa_tx_gain_table); 617 else if (AR_SREV_9561(ah)) 618 INIT_INI_ARRAY(&ah->iniModesTxGain, 619 qca956x_1p0_modes_xpa_tx_gain_table); 620 else if (AR_SREV_9580(ah)) 621 INIT_INI_ARRAY(&ah->iniModesTxGain, 622 ar9580_1p0_lowest_ob_db_tx_gain_table); 623 else if (AR_SREV_9462_21(ah)) 624 INIT_INI_ARRAY(&ah->iniModesTxGain, 625 ar9462_2p1_modes_low_ob_db_tx_gain); 626 else if (AR_SREV_9462_20(ah)) 627 INIT_INI_ARRAY(&ah->iniModesTxGain, 628 ar9462_2p0_modes_low_ob_db_tx_gain); 629 else if (AR_SREV_9565_11(ah)) 630 INIT_INI_ARRAY(&ah->iniModesTxGain, 631 ar9565_1p1_modes_low_ob_db_tx_gain_table); 632 else if (AR_SREV_9565(ah)) 633 INIT_INI_ARRAY(&ah->iniModesTxGain, 634 ar9565_1p0_modes_low_ob_db_tx_gain_table); 635 else 636 INIT_INI_ARRAY(&ah->iniModesTxGain, 637 ar9300Modes_lowest_ob_db_tx_gain_table_2p2); 638 } 639 640 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 641 { 642 if (AR_SREV_9330_12(ah)) 643 INIT_INI_ARRAY(&ah->iniModesTxGain, 644 ar9331_modes_high_ob_db_tx_gain_1p2); 645 else if (AR_SREV_9330_11(ah)) 646 INIT_INI_ARRAY(&ah->iniModesTxGain, 647 ar9331_modes_high_ob_db_tx_gain_1p1); 648 else if (AR_SREV_9340(ah)) 649 INIT_INI_ARRAY(&ah->iniModesTxGain, 650 ar9340Modes_high_ob_db_tx_gain_table_1p0); 651 else if (AR_SREV_9485_11_OR_LATER(ah)) 652 INIT_INI_ARRAY(&ah->iniModesTxGain, 653 ar9485Modes_high_ob_db_tx_gain_1_1); 654 else if (AR_SREV_9580(ah)) 655 INIT_INI_ARRAY(&ah->iniModesTxGain, 656 ar9580_1p0_high_ob_db_tx_gain_table); 657 else if (AR_SREV_9550(ah)) 658 INIT_INI_ARRAY(&ah->iniModesTxGain, 659 ar955x_1p0_modes_no_xpa_tx_gain_table); 660 else if (AR_SREV_9531(ah)) { 661 if (AR_SREV_9531_20(ah)) 662 INIT_INI_ARRAY(&ah->iniModesTxGain, 663 qca953x_2p0_modes_no_xpa_tx_gain_table); 664 else if (AR_SREV_9531_11(ah)) 665 INIT_INI_ARRAY(&ah->iniModesTxGain, 666 qca953x_1p1_modes_no_xpa_tx_gain_table); 667 else 668 INIT_INI_ARRAY(&ah->iniModesTxGain, 669 qca953x_1p0_modes_no_xpa_tx_gain_table); 670 } else if (AR_SREV_9561(ah)) 671 INIT_INI_ARRAY(&ah->iniModesTxGain, 672 qca956x_1p0_modes_no_xpa_tx_gain_table); 673 else if (AR_SREV_9462_21(ah)) 674 INIT_INI_ARRAY(&ah->iniModesTxGain, 675 ar9462_2p1_modes_high_ob_db_tx_gain); 676 else if (AR_SREV_9462_20(ah)) 677 INIT_INI_ARRAY(&ah->iniModesTxGain, 678 ar9462_2p0_modes_high_ob_db_tx_gain); 679 else if (AR_SREV_9565_11(ah)) 680 INIT_INI_ARRAY(&ah->iniModesTxGain, 681 ar9565_1p1_modes_high_ob_db_tx_gain_table); 682 else if (AR_SREV_9565(ah)) 683 INIT_INI_ARRAY(&ah->iniModesTxGain, 684 ar9565_1p0_modes_high_ob_db_tx_gain_table); 685 else 686 INIT_INI_ARRAY(&ah->iniModesTxGain, 687 ar9300Modes_high_ob_db_tx_gain_table_2p2); 688 } 689 690 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) 691 { 692 if (AR_SREV_9330_12(ah)) 693 INIT_INI_ARRAY(&ah->iniModesTxGain, 694 ar9331_modes_low_ob_db_tx_gain_1p2); 695 else if (AR_SREV_9330_11(ah)) 696 INIT_INI_ARRAY(&ah->iniModesTxGain, 697 ar9331_modes_low_ob_db_tx_gain_1p1); 698 else if (AR_SREV_9340(ah)) 699 INIT_INI_ARRAY(&ah->iniModesTxGain, 700 ar9340Modes_low_ob_db_tx_gain_table_1p0); 701 else if (AR_SREV_9485_11_OR_LATER(ah)) 702 INIT_INI_ARRAY(&ah->iniModesTxGain, 703 ar9485Modes_low_ob_db_tx_gain_1_1); 704 else if (AR_SREV_9580(ah)) 705 INIT_INI_ARRAY(&ah->iniModesTxGain, 706 ar9580_1p0_low_ob_db_tx_gain_table); 707 else if (AR_SREV_9561(ah)) 708 INIT_INI_ARRAY(&ah->iniModesTxGain, 709 qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table); 710 else if (AR_SREV_9565_11(ah)) 711 INIT_INI_ARRAY(&ah->iniModesTxGain, 712 ar9565_1p1_modes_low_ob_db_tx_gain_table); 713 else if (AR_SREV_9565(ah)) 714 INIT_INI_ARRAY(&ah->iniModesTxGain, 715 ar9565_1p0_modes_low_ob_db_tx_gain_table); 716 else 717 INIT_INI_ARRAY(&ah->iniModesTxGain, 718 ar9300Modes_low_ob_db_tx_gain_table_2p2); 719 } 720 721 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) 722 { 723 if (AR_SREV_9330_12(ah)) 724 INIT_INI_ARRAY(&ah->iniModesTxGain, 725 ar9331_modes_high_power_tx_gain_1p2); 726 else if (AR_SREV_9330_11(ah)) 727 INIT_INI_ARRAY(&ah->iniModesTxGain, 728 ar9331_modes_high_power_tx_gain_1p1); 729 else if (AR_SREV_9340(ah)) 730 INIT_INI_ARRAY(&ah->iniModesTxGain, 731 ar9340Modes_high_power_tx_gain_table_1p0); 732 else if (AR_SREV_9485_11_OR_LATER(ah)) 733 INIT_INI_ARRAY(&ah->iniModesTxGain, 734 ar9485Modes_high_power_tx_gain_1_1); 735 else if (AR_SREV_9580(ah)) 736 INIT_INI_ARRAY(&ah->iniModesTxGain, 737 ar9580_1p0_high_power_tx_gain_table); 738 else if (AR_SREV_9565_11(ah)) 739 INIT_INI_ARRAY(&ah->iniModesTxGain, 740 ar9565_1p1_modes_high_power_tx_gain_table); 741 else if (AR_SREV_9565(ah)) 742 INIT_INI_ARRAY(&ah->iniModesTxGain, 743 ar9565_1p0_modes_high_power_tx_gain_table); 744 else { 745 if (ah->config.tx_gain_buffalo) 746 INIT_INI_ARRAY(&ah->iniModesTxGain, 747 ar9300Modes_high_power_tx_gain_table_buffalo); 748 else 749 INIT_INI_ARRAY(&ah->iniModesTxGain, 750 ar9300Modes_high_power_tx_gain_table_2p2); 751 } 752 } 753 754 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) 755 { 756 if (AR_SREV_9340(ah)) 757 INIT_INI_ARRAY(&ah->iniModesTxGain, 758 ar9340Modes_mixed_ob_db_tx_gain_table_1p0); 759 else if (AR_SREV_9580(ah)) 760 INIT_INI_ARRAY(&ah->iniModesTxGain, 761 ar9580_1p0_mixed_ob_db_tx_gain_table); 762 else if (AR_SREV_9462_21(ah)) 763 INIT_INI_ARRAY(&ah->iniModesTxGain, 764 ar9462_2p1_modes_mix_ob_db_tx_gain); 765 else if (AR_SREV_9462_20(ah)) 766 INIT_INI_ARRAY(&ah->iniModesTxGain, 767 ar9462_2p0_modes_mix_ob_db_tx_gain); 768 else 769 INIT_INI_ARRAY(&ah->iniModesTxGain, 770 ar9300Modes_mixed_ob_db_tx_gain_table_2p2); 771 } 772 773 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah) 774 { 775 if (AR_SREV_9485_11_OR_LATER(ah)) 776 INIT_INI_ARRAY(&ah->iniModesTxGain, 777 ar9485Modes_green_ob_db_tx_gain_1_1); 778 else if (AR_SREV_9580(ah)) 779 INIT_INI_ARRAY(&ah->iniModesTxGain, 780 ar9580_1p0_type5_tx_gain_table); 781 else if (AR_SREV_9561(ah)) 782 INIT_INI_ARRAY(&ah->iniModesTxGain, 783 qca956x_1p0_modes_no_xpa_green_tx_gain_table); 784 else if (AR_SREV_9300_22(ah)) 785 INIT_INI_ARRAY(&ah->iniModesTxGain, 786 ar9300Modes_type5_tx_gain_table_2p2); 787 } 788 789 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah) 790 { 791 if (AR_SREV_9340(ah)) 792 INIT_INI_ARRAY(&ah->iniModesTxGain, 793 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0); 794 else if (AR_SREV_9485_11_OR_LATER(ah)) 795 INIT_INI_ARRAY(&ah->iniModesTxGain, 796 ar9485Modes_green_spur_ob_db_tx_gain_1_1); 797 else if (AR_SREV_9580(ah)) 798 INIT_INI_ARRAY(&ah->iniModesTxGain, 799 ar9580_1p0_type6_tx_gain_table); 800 } 801 802 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah) 803 { 804 if (AR_SREV_9340(ah)) 805 INIT_INI_ARRAY(&ah->iniModesTxGain, 806 ar9340_cus227_tx_gain_table_1p0); 807 } 808 809 typedef void (*ath_txgain_tab)(struct ath_hw *ah); 810 811 static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 812 { 813 static const ath_txgain_tab modes[] = { 814 ar9003_tx_gain_table_mode0, 815 ar9003_tx_gain_table_mode1, 816 ar9003_tx_gain_table_mode2, 817 ar9003_tx_gain_table_mode3, 818 ar9003_tx_gain_table_mode4, 819 ar9003_tx_gain_table_mode5, 820 ar9003_tx_gain_table_mode6, 821 ar9003_tx_gain_table_mode7, 822 }; 823 int idx = ar9003_hw_get_tx_gain_idx(ah); 824 825 if (idx >= ARRAY_SIZE(modes)) 826 idx = 0; 827 828 modes[idx](ah); 829 } 830 831 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 832 { 833 if (AR_SREV_9330_12(ah)) 834 INIT_INI_ARRAY(&ah->iniModesRxGain, 835 ar9331_common_rx_gain_1p2); 836 else if (AR_SREV_9330_11(ah)) 837 INIT_INI_ARRAY(&ah->iniModesRxGain, 838 ar9331_common_rx_gain_1p1); 839 else if (AR_SREV_9340(ah)) 840 INIT_INI_ARRAY(&ah->iniModesRxGain, 841 ar9340Common_rx_gain_table_1p0); 842 else if (AR_SREV_9485_11_OR_LATER(ah)) 843 INIT_INI_ARRAY(&ah->iniModesRxGain, 844 ar9485_common_rx_gain_1_1); 845 else if (AR_SREV_9550(ah)) { 846 INIT_INI_ARRAY(&ah->iniModesRxGain, 847 ar955x_1p0_common_rx_gain_table); 848 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 849 ar955x_1p0_common_rx_gain_bounds); 850 } else if (AR_SREV_9531(ah)) { 851 INIT_INI_ARRAY(&ah->iniModesRxGain, 852 qca953x_1p0_common_rx_gain_table); 853 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 854 qca953x_1p0_common_rx_gain_bounds); 855 } else if (AR_SREV_9561(ah)) { 856 INIT_INI_ARRAY(&ah->iniModesRxGain, 857 qca956x_1p0_common_rx_gain_table); 858 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 859 qca956x_1p0_common_rx_gain_bounds); 860 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 861 qca956x_1p0_xlna_only); 862 } else if (AR_SREV_9580(ah)) 863 INIT_INI_ARRAY(&ah->iniModesRxGain, 864 ar9580_1p0_rx_gain_table); 865 else if (AR_SREV_9462_21(ah)) 866 INIT_INI_ARRAY(&ah->iniModesRxGain, 867 ar9462_2p1_common_rx_gain); 868 else if (AR_SREV_9462_20(ah)) 869 INIT_INI_ARRAY(&ah->iniModesRxGain, 870 ar9462_2p0_common_rx_gain); 871 else if (AR_SREV_9565_11(ah)) 872 INIT_INI_ARRAY(&ah->iniModesRxGain, 873 ar9565_1p1_Common_rx_gain_table); 874 else if (AR_SREV_9565(ah)) 875 INIT_INI_ARRAY(&ah->iniModesRxGain, 876 ar9565_1p0_Common_rx_gain_table); 877 else 878 INIT_INI_ARRAY(&ah->iniModesRxGain, 879 ar9300Common_rx_gain_table_2p2); 880 } 881 882 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 883 { 884 if (AR_SREV_9330_12(ah)) 885 INIT_INI_ARRAY(&ah->iniModesRxGain, 886 ar9331_common_wo_xlna_rx_gain_1p2); 887 else if (AR_SREV_9330_11(ah)) 888 INIT_INI_ARRAY(&ah->iniModesRxGain, 889 ar9331_common_wo_xlna_rx_gain_1p1); 890 else if (AR_SREV_9340(ah)) 891 INIT_INI_ARRAY(&ah->iniModesRxGain, 892 ar9340Common_wo_xlna_rx_gain_table_1p0); 893 else if (AR_SREV_9485_11_OR_LATER(ah)) 894 INIT_INI_ARRAY(&ah->iniModesRxGain, 895 ar9485Common_wo_xlna_rx_gain_1_1); 896 else if (AR_SREV_9462_21(ah)) 897 INIT_INI_ARRAY(&ah->iniModesRxGain, 898 ar9462_2p1_common_wo_xlna_rx_gain); 899 else if (AR_SREV_9462_20(ah)) 900 INIT_INI_ARRAY(&ah->iniModesRxGain, 901 ar9462_2p0_common_wo_xlna_rx_gain); 902 else if (AR_SREV_9550(ah)) { 903 INIT_INI_ARRAY(&ah->iniModesRxGain, 904 ar955x_1p0_common_wo_xlna_rx_gain_table); 905 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 906 ar955x_1p0_common_wo_xlna_rx_gain_bounds); 907 } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) { 908 INIT_INI_ARRAY(&ah->iniModesRxGain, 909 qca953x_1p0_common_wo_xlna_rx_gain_table); 910 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 911 qca953x_1p0_common_wo_xlna_rx_gain_bounds); 912 } else if (AR_SREV_9531_20(ah)) { 913 INIT_INI_ARRAY(&ah->iniModesRxGain, 914 qca953x_2p0_common_wo_xlna_rx_gain_table); 915 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 916 qca953x_2p0_common_wo_xlna_rx_gain_bounds); 917 } else if (AR_SREV_9561(ah)) { 918 INIT_INI_ARRAY(&ah->iniModesRxGain, 919 qca956x_1p0_common_wo_xlna_rx_gain_table); 920 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 921 qca956x_1p0_common_wo_xlna_rx_gain_bounds); 922 } else if (AR_SREV_9580(ah)) 923 INIT_INI_ARRAY(&ah->iniModesRxGain, 924 ar9580_1p0_wo_xlna_rx_gain_table); 925 else if (AR_SREV_9565_11(ah)) 926 INIT_INI_ARRAY(&ah->iniModesRxGain, 927 ar9565_1p1_common_wo_xlna_rx_gain_table); 928 else if (AR_SREV_9565(ah)) 929 INIT_INI_ARRAY(&ah->iniModesRxGain, 930 ar9565_1p0_common_wo_xlna_rx_gain_table); 931 else 932 INIT_INI_ARRAY(&ah->iniModesRxGain, 933 ar9300Common_wo_xlna_rx_gain_table_2p2); 934 } 935 936 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 937 { 938 if (AR_SREV_9462_21(ah)) { 939 INIT_INI_ARRAY(&ah->iniModesRxGain, 940 ar9462_2p1_common_mixed_rx_gain); 941 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, 942 ar9462_2p1_baseband_core_mix_rxgain); 943 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 944 ar9462_2p1_baseband_postamble_mix_rxgain); 945 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 946 ar9462_2p1_baseband_postamble_5g_xlna); 947 } else if (AR_SREV_9462_20(ah)) { 948 INIT_INI_ARRAY(&ah->iniModesRxGain, 949 ar9462_2p0_common_mixed_rx_gain); 950 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, 951 ar9462_2p0_baseband_core_mix_rxgain); 952 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, 953 ar9462_2p0_baseband_postamble_mix_rxgain); 954 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 955 ar9462_2p0_baseband_postamble_5g_xlna); 956 } 957 } 958 959 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah) 960 { 961 if (AR_SREV_9462_21(ah)) { 962 INIT_INI_ARRAY(&ah->iniModesRxGain, 963 ar9462_2p1_common_5g_xlna_only_rxgain); 964 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 965 ar9462_2p1_baseband_postamble_5g_xlna); 966 } else if (AR_SREV_9462_20(ah)) { 967 INIT_INI_ARRAY(&ah->iniModesRxGain, 968 ar9462_2p0_common_5g_xlna_only_rxgain); 969 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, 970 ar9462_2p0_baseband_postamble_5g_xlna); 971 } 972 } 973 974 static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 975 { 976 switch (ar9003_hw_get_rx_gain_idx(ah)) { 977 case 0: 978 default: 979 ar9003_rx_gain_table_mode0(ah); 980 break; 981 case 1: 982 ar9003_rx_gain_table_mode1(ah); 983 break; 984 case 2: 985 ar9003_rx_gain_table_mode2(ah); 986 break; 987 case 3: 988 ar9003_rx_gain_table_mode3(ah); 989 break; 990 } 991 } 992 993 /* set gain table pointers according to values read from the eeprom */ 994 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) 995 { 996 ar9003_tx_gain_table_apply(ah); 997 ar9003_rx_gain_table_apply(ah); 998 } 999 1000 /* 1001 * Helper for ASPM support. 1002 * 1003 * Disable PLL when in L0s as well as receiver clock when in L1. 1004 * This power saving option must be enabled through the SerDes. 1005 * 1006 * Programming the SerDes must go through the same 288 bit serial shift 1007 * register as the other analog registers. Hence the 9 writes. 1008 */ 1009 static void ar9003_hw_configpcipowersave(struct ath_hw *ah, 1010 bool power_off) 1011 { 1012 unsigned int i; 1013 struct ar5416IniArray *array; 1014 1015 /* 1016 * Increase L1 Entry Latency. Some WB222 boards don't have 1017 * this change in eeprom/OTP. 1018 * 1019 */ 1020 if (AR_SREV_9462(ah)) { 1021 u32 val = ah->config.aspm_l1_fix; 1022 if ((val & 0xff000000) == 0x17000000) { 1023 val &= 0x00ffffff; 1024 val |= 0x27000000; 1025 REG_WRITE(ah, 0x570c, val); 1026 } 1027 } 1028 1029 /* Nothing to do on restore for 11N */ 1030 if (!power_off /* !restore */) { 1031 /* set bit 19 to allow forcing of pcie core into L1 state */ 1032 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 1033 REG_WRITE(ah, AR_WA, ah->WARegVal); 1034 } 1035 1036 /* 1037 * Configire PCIE after Ini init. SERDES values now come from ini file 1038 * This enables PCIe low power mode. 1039 */ 1040 array = power_off ? &ah->iniPcieSerdes : 1041 &ah->iniPcieSerdesLowPower; 1042 1043 for (i = 0; i < array->ia_rows; i++) { 1044 REG_WRITE(ah, 1045 INI_RA(array, i, 0), 1046 INI_RA(array, i, 1)); 1047 } 1048 } 1049 1050 static void ar9003_hw_init_hang_checks(struct ath_hw *ah) 1051 { 1052 /* 1053 * All chips support detection of BB/MAC hangs. 1054 */ 1055 ah->config.hw_hang_checks |= HW_BB_WATCHDOG; 1056 ah->config.hw_hang_checks |= HW_MAC_HANG; 1057 1058 /* 1059 * This is not required for AR9580 1.0 1060 */ 1061 if (AR_SREV_9300_22(ah)) 1062 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR; 1063 1064 if (AR_SREV_9330(ah)) 1065 ah->bb_watchdog_timeout_ms = 85; 1066 else 1067 ah->bb_watchdog_timeout_ms = 25; 1068 } 1069 1070 /* 1071 * MAC HW hang check 1072 * ================= 1073 * 1074 * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1. 1075 * 1076 * The state of each DCU chain (mapped to TX queues) is available from these 1077 * DMA debug registers: 1078 * 1079 * Chain 0 state : Bits 4:0 of AR_DMADBG_4 1080 * Chain 1 state : Bits 9:5 of AR_DMADBG_4 1081 * Chain 2 state : Bits 14:10 of AR_DMADBG_4 1082 * Chain 3 state : Bits 19:15 of AR_DMADBG_4 1083 * Chain 4 state : Bits 24:20 of AR_DMADBG_4 1084 * Chain 5 state : Bits 29:25 of AR_DMADBG_4 1085 * Chain 6 state : Bits 4:0 of AR_DMADBG_5 1086 * Chain 7 state : Bits 9:5 of AR_DMADBG_5 1087 * Chain 8 state : Bits 14:10 of AR_DMADBG_5 1088 * Chain 9 state : Bits 19:15 of AR_DMADBG_5 1089 * 1090 * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done. 1091 */ 1092 1093 #define NUM_STATUS_READS 50 1094 1095 static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue) 1096 { 1097 u32 dma_dbg_chain, dma_dbg_complete; 1098 u8 dcu_chain_state, dcu_complete_state; 1099 int i; 1100 1101 for (i = 0; i < NUM_STATUS_READS; i++) { 1102 if (queue < 6) 1103 dma_dbg_chain = REG_READ(ah, AR_DMADBG_4); 1104 else 1105 dma_dbg_chain = REG_READ(ah, AR_DMADBG_5); 1106 1107 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6); 1108 1109 dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f; 1110 dcu_complete_state = dma_dbg_complete & 0x3; 1111 1112 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1)) 1113 return false; 1114 } 1115 1116 ath_dbg(ath9k_hw_common(ah), RESET, 1117 "MAC Hang signature found for queue: %d\n", queue); 1118 1119 return true; 1120 } 1121 1122 static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) 1123 { 1124 u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg; 1125 u8 dcu_chain_state, dcu_complete_state; 1126 bool dcu_wait_frdone = false; 1127 unsigned long chk_dcu = 0; 1128 unsigned int i = 0; 1129 1130 dma_dbg_4 = REG_READ(ah, AR_DMADBG_4); 1131 dma_dbg_5 = REG_READ(ah, AR_DMADBG_5); 1132 dma_dbg_6 = REG_READ(ah, AR_DMADBG_6); 1133 1134 dcu_complete_state = dma_dbg_6 & 0x3; 1135 if (dcu_complete_state != 0x1) 1136 goto exit; 1137 1138 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1139 if (i < 6) 1140 chk_dbg = dma_dbg_4; 1141 else 1142 chk_dbg = dma_dbg_5; 1143 1144 dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f; 1145 if (dcu_chain_state == 0x6) { 1146 dcu_wait_frdone = true; 1147 chk_dcu |= BIT(i); 1148 } 1149 } 1150 1151 if ((dcu_complete_state == 0x1) && dcu_wait_frdone) { 1152 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) { 1153 if (ath9k_hw_verify_hang(ah, i)) 1154 return true; 1155 } 1156 } 1157 exit: 1158 return false; 1159 } 1160 1161 /* Sets up the AR9003 hardware familiy callbacks */ 1162 void ar9003_hw_attach_ops(struct ath_hw *ah) 1163 { 1164 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1165 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 1166 1167 ar9003_hw_init_mode_regs(ah); 1168 1169 if (AR_SREV_9003_PCOEM(ah)) { 1170 WARN_ON(!ah->iniPcieSerdes.ia_array); 1171 WARN_ON(!ah->iniPcieSerdesLowPower.ia_array); 1172 } 1173 1174 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; 1175 priv_ops->init_hang_checks = ar9003_hw_init_hang_checks; 1176 priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang; 1177 1178 ops->config_pci_powersave = ar9003_hw_configpcipowersave; 1179 1180 ar9003_hw_attach_phy_ops(ah); 1181 ar9003_hw_attach_calib_ops(ah); 1182 ar9003_hw_attach_mac_ops(ah); 1183 ar9003_hw_attach_aic_ops(ah); 1184 } 1185