1 /* 2 * Copyright (c) 2010-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <asm/unaligned.h> 18 #include "hw.h" 19 #include "ar9003_phy.h" 20 #include "ar9003_eeprom.h" 21 22 #define COMP_HDR_LEN 4 23 #define COMP_CKSUM_LEN 2 24 25 #define LE16(x) __constant_cpu_to_le16(x) 26 #define LE32(x) __constant_cpu_to_le32(x) 27 28 /* Local defines to distinguish between extension and control CTL's */ 29 #define EXT_ADDITIVE (0x8000) 30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 33 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 34 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */ 35 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */ 36 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */ 37 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */ 38 39 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 40 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 41 42 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) 43 44 #define EEPROM_DATA_LEN_9485 1088 45 46 static int ar9003_hw_power_interpolate(int32_t x, 47 int32_t *px, int32_t *py, u_int16_t np); 48 49 50 static const struct ar9300_eeprom ar9300_default = { 51 .eepromVersion = 2, 52 .templateVersion = 2, 53 .macAddr = {0, 2, 3, 4, 5, 6}, 54 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 56 .baseEepHeader = { 57 .regDmn = { LE16(0), LE16(0x1f) }, 58 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 59 .opCapFlags = { 60 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 61 .eepMisc = 0, 62 }, 63 .rfSilent = 0, 64 .blueToothOptions = 0, 65 .deviceCap = 0, 66 .deviceType = 5, /* takes lower byte in eeprom location */ 67 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 68 .params_for_tuning_caps = {0, 0}, 69 .featureEnable = 0x0c, 70 /* 71 * bit0 - enable tx temp comp - disabled 72 * bit1 - enable tx volt comp - disabled 73 * bit2 - enable fastClock - enabled 74 * bit3 - enable doubling - enabled 75 * bit4 - enable internal regulator - disabled 76 * bit5 - enable pa predistortion - disabled 77 */ 78 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 79 .eepromWriteEnableGpio = 3, 80 .wlanDisableGpio = 0, 81 .wlanLedGpio = 8, 82 .rxBandSelectGpio = 0xff, 83 .txrxgain = 0, 84 .swreg = 0, 85 }, 86 .modalHeader2G = { 87 /* ar9300_modal_eep_header 2g */ 88 /* 4 idle,t1,t2,b(4 bits per setting) */ 89 .antCtrlCommon = LE32(0x110), 90 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 91 .antCtrlCommon2 = LE32(0x22222), 92 93 /* 94 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 95 * rx1, rx12, b (2 bits each) 96 */ 97 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, 98 99 /* 100 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 101 * for ar9280 (0xa20c/b20c 5:0) 102 */ 103 .xatten1DB = {0, 0, 0}, 104 105 /* 106 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 107 * for ar9280 (0xa20c/b20c 16:12 108 */ 109 .xatten1Margin = {0, 0, 0}, 110 .tempSlope = 36, 111 .voltSlope = 0, 112 113 /* 114 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 115 * channels in usual fbin coding format 116 */ 117 .spurChans = {0, 0, 0, 0, 0}, 118 119 /* 120 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 121 * if the register is per chain 122 */ 123 .noiseFloorThreshCh = {-1, 0, 0}, 124 .ob = {1, 1, 1},/* 3 chain */ 125 .db_stage2 = {1, 1, 1}, /* 3 chain */ 126 .db_stage3 = {0, 0, 0}, 127 .db_stage4 = {0, 0, 0}, 128 .xpaBiasLvl = 0, 129 .txFrameToDataStart = 0x0e, 130 .txFrameToPaOn = 0x0e, 131 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 132 .antennaGain = 0, 133 .switchSettling = 0x2c, 134 .adcDesiredSize = -30, 135 .txEndToXpaOff = 0, 136 .txEndToRxOn = 0x2, 137 .txFrameToXpaOn = 0xe, 138 .thresh62 = 28, 139 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 140 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 141 .futureModal = { 142 0, 0, 0, 0, 0, 0, 0, 0, 143 }, 144 }, 145 .base_ext1 = { 146 .ant_div_control = 0, 147 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 148 }, 149 .calFreqPier2G = { 150 FREQ2FBIN(2412, 1), 151 FREQ2FBIN(2437, 1), 152 FREQ2FBIN(2472, 1), 153 }, 154 /* ar9300_cal_data_per_freq_op_loop 2g */ 155 .calPierData2G = { 156 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 157 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 158 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 159 }, 160 .calTarget_freqbin_Cck = { 161 FREQ2FBIN(2412, 1), 162 FREQ2FBIN(2484, 1), 163 }, 164 .calTarget_freqbin_2G = { 165 FREQ2FBIN(2412, 1), 166 FREQ2FBIN(2437, 1), 167 FREQ2FBIN(2472, 1) 168 }, 169 .calTarget_freqbin_2GHT20 = { 170 FREQ2FBIN(2412, 1), 171 FREQ2FBIN(2437, 1), 172 FREQ2FBIN(2472, 1) 173 }, 174 .calTarget_freqbin_2GHT40 = { 175 FREQ2FBIN(2412, 1), 176 FREQ2FBIN(2437, 1), 177 FREQ2FBIN(2472, 1) 178 }, 179 .calTargetPowerCck = { 180 /* 1L-5L,5S,11L,11S */ 181 { {36, 36, 36, 36} }, 182 { {36, 36, 36, 36} }, 183 }, 184 .calTargetPower2G = { 185 /* 6-24,36,48,54 */ 186 { {32, 32, 28, 24} }, 187 { {32, 32, 28, 24} }, 188 { {32, 32, 28, 24} }, 189 }, 190 .calTargetPower2GHT20 = { 191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 192 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 193 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 194 }, 195 .calTargetPower2GHT40 = { 196 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 197 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 198 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} }, 199 }, 200 .ctlIndex_2G = { 201 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 202 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 203 }, 204 .ctl_freqbin_2G = { 205 { 206 FREQ2FBIN(2412, 1), 207 FREQ2FBIN(2417, 1), 208 FREQ2FBIN(2457, 1), 209 FREQ2FBIN(2462, 1) 210 }, 211 { 212 FREQ2FBIN(2412, 1), 213 FREQ2FBIN(2417, 1), 214 FREQ2FBIN(2462, 1), 215 0xFF, 216 }, 217 218 { 219 FREQ2FBIN(2412, 1), 220 FREQ2FBIN(2417, 1), 221 FREQ2FBIN(2462, 1), 222 0xFF, 223 }, 224 { 225 FREQ2FBIN(2422, 1), 226 FREQ2FBIN(2427, 1), 227 FREQ2FBIN(2447, 1), 228 FREQ2FBIN(2452, 1) 229 }, 230 231 { 232 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 233 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 234 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 235 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 236 }, 237 238 { 239 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 240 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 241 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 242 0, 243 }, 244 245 { 246 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 247 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 248 FREQ2FBIN(2472, 1), 249 0, 250 }, 251 252 { 253 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 254 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 255 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 256 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 257 }, 258 259 { 260 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 261 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 262 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 263 }, 264 265 { 266 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 267 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 268 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 269 0 270 }, 271 272 { 273 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 274 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 275 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 276 0 277 }, 278 279 { 280 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 281 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 282 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 283 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 284 } 285 }, 286 .ctlPowerData_2G = { 287 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 288 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 289 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 290 291 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 293 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 294 295 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 296 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 297 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 298 299 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 300 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 301 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 302 }, 303 .modalHeader5G = { 304 /* 4 idle,t1,t2,b (4 bits per setting) */ 305 .antCtrlCommon = LE32(0x110), 306 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 307 .antCtrlCommon2 = LE32(0x22222), 308 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 309 .antCtrlChain = { 310 LE16(0x000), LE16(0x000), LE16(0x000), 311 }, 312 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 313 .xatten1DB = {0, 0, 0}, 314 315 /* 316 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 317 * for merlin (0xa20c/b20c 16:12 318 */ 319 .xatten1Margin = {0, 0, 0}, 320 .tempSlope = 68, 321 .voltSlope = 0, 322 /* spurChans spur channels in usual fbin coding format */ 323 .spurChans = {0, 0, 0, 0, 0}, 324 /* noiseFloorThreshCh Check if the register is per chain */ 325 .noiseFloorThreshCh = {-1, 0, 0}, 326 .ob = {3, 3, 3}, /* 3 chain */ 327 .db_stage2 = {3, 3, 3}, /* 3 chain */ 328 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ 329 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ 330 .xpaBiasLvl = 0, 331 .txFrameToDataStart = 0x0e, 332 .txFrameToPaOn = 0x0e, 333 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 334 .antennaGain = 0, 335 .switchSettling = 0x2d, 336 .adcDesiredSize = -30, 337 .txEndToXpaOff = 0, 338 .txEndToRxOn = 0x2, 339 .txFrameToXpaOn = 0xe, 340 .thresh62 = 28, 341 .papdRateMaskHt20 = LE32(0x0c80c080), 342 .papdRateMaskHt40 = LE32(0x0080c080), 343 .futureModal = { 344 0, 0, 0, 0, 0, 0, 0, 0, 345 }, 346 }, 347 .base_ext2 = { 348 .tempSlopeLow = 0, 349 .tempSlopeHigh = 0, 350 .xatten1DBLow = {0, 0, 0}, 351 .xatten1MarginLow = {0, 0, 0}, 352 .xatten1DBHigh = {0, 0, 0}, 353 .xatten1MarginHigh = {0, 0, 0} 354 }, 355 .calFreqPier5G = { 356 FREQ2FBIN(5180, 0), 357 FREQ2FBIN(5220, 0), 358 FREQ2FBIN(5320, 0), 359 FREQ2FBIN(5400, 0), 360 FREQ2FBIN(5500, 0), 361 FREQ2FBIN(5600, 0), 362 FREQ2FBIN(5725, 0), 363 FREQ2FBIN(5825, 0) 364 }, 365 .calPierData5G = { 366 { 367 {0, 0, 0, 0, 0}, 368 {0, 0, 0, 0, 0}, 369 {0, 0, 0, 0, 0}, 370 {0, 0, 0, 0, 0}, 371 {0, 0, 0, 0, 0}, 372 {0, 0, 0, 0, 0}, 373 {0, 0, 0, 0, 0}, 374 {0, 0, 0, 0, 0}, 375 }, 376 { 377 {0, 0, 0, 0, 0}, 378 {0, 0, 0, 0, 0}, 379 {0, 0, 0, 0, 0}, 380 {0, 0, 0, 0, 0}, 381 {0, 0, 0, 0, 0}, 382 {0, 0, 0, 0, 0}, 383 {0, 0, 0, 0, 0}, 384 {0, 0, 0, 0, 0}, 385 }, 386 { 387 {0, 0, 0, 0, 0}, 388 {0, 0, 0, 0, 0}, 389 {0, 0, 0, 0, 0}, 390 {0, 0, 0, 0, 0}, 391 {0, 0, 0, 0, 0}, 392 {0, 0, 0, 0, 0}, 393 {0, 0, 0, 0, 0}, 394 {0, 0, 0, 0, 0}, 395 }, 396 397 }, 398 .calTarget_freqbin_5G = { 399 FREQ2FBIN(5180, 0), 400 FREQ2FBIN(5220, 0), 401 FREQ2FBIN(5320, 0), 402 FREQ2FBIN(5400, 0), 403 FREQ2FBIN(5500, 0), 404 FREQ2FBIN(5600, 0), 405 FREQ2FBIN(5725, 0), 406 FREQ2FBIN(5825, 0) 407 }, 408 .calTarget_freqbin_5GHT20 = { 409 FREQ2FBIN(5180, 0), 410 FREQ2FBIN(5240, 0), 411 FREQ2FBIN(5320, 0), 412 FREQ2FBIN(5500, 0), 413 FREQ2FBIN(5700, 0), 414 FREQ2FBIN(5745, 0), 415 FREQ2FBIN(5725, 0), 416 FREQ2FBIN(5825, 0) 417 }, 418 .calTarget_freqbin_5GHT40 = { 419 FREQ2FBIN(5180, 0), 420 FREQ2FBIN(5240, 0), 421 FREQ2FBIN(5320, 0), 422 FREQ2FBIN(5500, 0), 423 FREQ2FBIN(5700, 0), 424 FREQ2FBIN(5745, 0), 425 FREQ2FBIN(5725, 0), 426 FREQ2FBIN(5825, 0) 427 }, 428 .calTargetPower5G = { 429 /* 6-24,36,48,54 */ 430 { {20, 20, 20, 10} }, 431 { {20, 20, 20, 10} }, 432 { {20, 20, 20, 10} }, 433 { {20, 20, 20, 10} }, 434 { {20, 20, 20, 10} }, 435 { {20, 20, 20, 10} }, 436 { {20, 20, 20, 10} }, 437 { {20, 20, 20, 10} }, 438 }, 439 .calTargetPower5GHT20 = { 440 /* 441 * 0_8_16,1-3_9-11_17-19, 442 * 4,5,6,7,12,13,14,15,20,21,22,23 443 */ 444 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 445 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 446 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 447 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 448 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 449 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 450 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 451 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 452 }, 453 .calTargetPower5GHT40 = { 454 /* 455 * 0_8_16,1-3_9-11_17-19, 456 * 4,5,6,7,12,13,14,15,20,21,22,23 457 */ 458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 462 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 463 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 464 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 465 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} }, 466 }, 467 .ctlIndex_5G = { 468 0x10, 0x16, 0x18, 0x40, 0x46, 469 0x48, 0x30, 0x36, 0x38 470 }, 471 .ctl_freqbin_5G = { 472 { 473 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 474 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 475 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 476 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 477 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 478 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 479 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 480 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 481 }, 482 { 483 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 484 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 485 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 486 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 487 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 488 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 489 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 490 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 491 }, 492 493 { 494 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 495 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 496 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 497 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 498 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 499 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 500 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 501 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 502 }, 503 504 { 505 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 506 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 507 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 508 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 509 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 510 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 511 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 512 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 513 }, 514 515 { 516 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 517 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 518 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 519 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 520 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 521 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 522 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 523 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 524 }, 525 526 { 527 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 528 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 529 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 530 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 531 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 532 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 533 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 534 /* Data[5].ctlEdges[7].bChannel */ 0xFF 535 }, 536 537 { 538 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 539 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 540 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 541 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 542 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 543 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 544 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 545 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 546 }, 547 548 { 549 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 550 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 551 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 552 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 553 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 554 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 555 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 556 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 557 }, 558 559 { 560 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 561 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 562 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 563 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 564 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 565 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 566 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 567 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 568 } 569 }, 570 .ctlPowerData_5G = { 571 { 572 { 573 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 574 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 575 } 576 }, 577 { 578 { 579 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 580 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 581 } 582 }, 583 { 584 { 585 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 586 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 587 } 588 }, 589 { 590 { 591 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 592 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 593 } 594 }, 595 { 596 { 597 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 598 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 599 } 600 }, 601 { 602 { 603 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 604 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 605 } 606 }, 607 { 608 { 609 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 610 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 611 } 612 }, 613 { 614 { 615 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 616 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 617 } 618 }, 619 { 620 { 621 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 622 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 623 } 624 }, 625 } 626 }; 627 628 static const struct ar9300_eeprom ar9300_x113 = { 629 .eepromVersion = 2, 630 .templateVersion = 6, 631 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 632 .custData = {"x113-023-f0000"}, 633 .baseEepHeader = { 634 .regDmn = { LE16(0), LE16(0x1f) }, 635 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 636 .opCapFlags = { 637 .opFlags = AR5416_OPFLAGS_11A, 638 .eepMisc = 0, 639 }, 640 .rfSilent = 0, 641 .blueToothOptions = 0, 642 .deviceCap = 0, 643 .deviceType = 5, /* takes lower byte in eeprom location */ 644 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 645 .params_for_tuning_caps = {0, 0}, 646 .featureEnable = 0x0d, 647 /* 648 * bit0 - enable tx temp comp - disabled 649 * bit1 - enable tx volt comp - disabled 650 * bit2 - enable fastClock - enabled 651 * bit3 - enable doubling - enabled 652 * bit4 - enable internal regulator - disabled 653 * bit5 - enable pa predistortion - disabled 654 */ 655 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 656 .eepromWriteEnableGpio = 6, 657 .wlanDisableGpio = 0, 658 .wlanLedGpio = 8, 659 .rxBandSelectGpio = 0xff, 660 .txrxgain = 0x21, 661 .swreg = 0, 662 }, 663 .modalHeader2G = { 664 /* ar9300_modal_eep_header 2g */ 665 /* 4 idle,t1,t2,b(4 bits per setting) */ 666 .antCtrlCommon = LE32(0x110), 667 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 668 .antCtrlCommon2 = LE32(0x44444), 669 670 /* 671 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 672 * rx1, rx12, b (2 bits each) 673 */ 674 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, 675 676 /* 677 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 678 * for ar9280 (0xa20c/b20c 5:0) 679 */ 680 .xatten1DB = {0, 0, 0}, 681 682 /* 683 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 684 * for ar9280 (0xa20c/b20c 16:12 685 */ 686 .xatten1Margin = {0, 0, 0}, 687 .tempSlope = 25, 688 .voltSlope = 0, 689 690 /* 691 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 692 * channels in usual fbin coding format 693 */ 694 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 695 696 /* 697 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 698 * if the register is per chain 699 */ 700 .noiseFloorThreshCh = {-1, 0, 0}, 701 .ob = {1, 1, 1},/* 3 chain */ 702 .db_stage2 = {1, 1, 1}, /* 3 chain */ 703 .db_stage3 = {0, 0, 0}, 704 .db_stage4 = {0, 0, 0}, 705 .xpaBiasLvl = 0, 706 .txFrameToDataStart = 0x0e, 707 .txFrameToPaOn = 0x0e, 708 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 709 .antennaGain = 0, 710 .switchSettling = 0x2c, 711 .adcDesiredSize = -30, 712 .txEndToXpaOff = 0, 713 .txEndToRxOn = 0x2, 714 .txFrameToXpaOn = 0xe, 715 .thresh62 = 28, 716 .papdRateMaskHt20 = LE32(0x0c80c080), 717 .papdRateMaskHt40 = LE32(0x0080c080), 718 .futureModal = { 719 0, 0, 0, 0, 0, 0, 0, 0, 720 }, 721 }, 722 .base_ext1 = { 723 .ant_div_control = 0, 724 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 725 }, 726 .calFreqPier2G = { 727 FREQ2FBIN(2412, 1), 728 FREQ2FBIN(2437, 1), 729 FREQ2FBIN(2472, 1), 730 }, 731 /* ar9300_cal_data_per_freq_op_loop 2g */ 732 .calPierData2G = { 733 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 734 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 735 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 736 }, 737 .calTarget_freqbin_Cck = { 738 FREQ2FBIN(2412, 1), 739 FREQ2FBIN(2472, 1), 740 }, 741 .calTarget_freqbin_2G = { 742 FREQ2FBIN(2412, 1), 743 FREQ2FBIN(2437, 1), 744 FREQ2FBIN(2472, 1) 745 }, 746 .calTarget_freqbin_2GHT20 = { 747 FREQ2FBIN(2412, 1), 748 FREQ2FBIN(2437, 1), 749 FREQ2FBIN(2472, 1) 750 }, 751 .calTarget_freqbin_2GHT40 = { 752 FREQ2FBIN(2412, 1), 753 FREQ2FBIN(2437, 1), 754 FREQ2FBIN(2472, 1) 755 }, 756 .calTargetPowerCck = { 757 /* 1L-5L,5S,11L,11S */ 758 { {34, 34, 34, 34} }, 759 { {34, 34, 34, 34} }, 760 }, 761 .calTargetPower2G = { 762 /* 6-24,36,48,54 */ 763 { {34, 34, 32, 32} }, 764 { {34, 34, 32, 32} }, 765 { {34, 34, 32, 32} }, 766 }, 767 .calTargetPower2GHT20 = { 768 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, 769 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, 770 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} }, 771 }, 772 .calTargetPower2GHT40 = { 773 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 774 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 775 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 776 }, 777 .ctlIndex_2G = { 778 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 779 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 780 }, 781 .ctl_freqbin_2G = { 782 { 783 FREQ2FBIN(2412, 1), 784 FREQ2FBIN(2417, 1), 785 FREQ2FBIN(2457, 1), 786 FREQ2FBIN(2462, 1) 787 }, 788 { 789 FREQ2FBIN(2412, 1), 790 FREQ2FBIN(2417, 1), 791 FREQ2FBIN(2462, 1), 792 0xFF, 793 }, 794 795 { 796 FREQ2FBIN(2412, 1), 797 FREQ2FBIN(2417, 1), 798 FREQ2FBIN(2462, 1), 799 0xFF, 800 }, 801 { 802 FREQ2FBIN(2422, 1), 803 FREQ2FBIN(2427, 1), 804 FREQ2FBIN(2447, 1), 805 FREQ2FBIN(2452, 1) 806 }, 807 808 { 809 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 810 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 811 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 812 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 813 }, 814 815 { 816 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 817 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 818 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 819 0, 820 }, 821 822 { 823 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 824 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 825 FREQ2FBIN(2472, 1), 826 0, 827 }, 828 829 { 830 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 831 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 832 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 833 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 834 }, 835 836 { 837 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 838 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 839 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 840 }, 841 842 { 843 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 844 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 845 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 846 0 847 }, 848 849 { 850 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 851 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 852 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 853 0 854 }, 855 856 { 857 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 858 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 859 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 860 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 861 } 862 }, 863 .ctlPowerData_2G = { 864 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 865 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 866 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 867 868 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 869 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 870 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 871 872 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 873 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 874 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 875 876 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 877 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 878 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 879 }, 880 .modalHeader5G = { 881 /* 4 idle,t1,t2,b (4 bits per setting) */ 882 .antCtrlCommon = LE32(0x220), 883 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 884 .antCtrlCommon2 = LE32(0x11111), 885 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 886 .antCtrlChain = { 887 LE16(0x150), LE16(0x150), LE16(0x150), 888 }, 889 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 890 .xatten1DB = {0, 0, 0}, 891 892 /* 893 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 894 * for merlin (0xa20c/b20c 16:12 895 */ 896 .xatten1Margin = {0, 0, 0}, 897 .tempSlope = 68, 898 .voltSlope = 0, 899 /* spurChans spur channels in usual fbin coding format */ 900 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0}, 901 /* noiseFloorThreshCh Check if the register is per chain */ 902 .noiseFloorThreshCh = {-1, 0, 0}, 903 .ob = {3, 3, 3}, /* 3 chain */ 904 .db_stage2 = {3, 3, 3}, /* 3 chain */ 905 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ 906 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ 907 .xpaBiasLvl = 0xf, 908 .txFrameToDataStart = 0x0e, 909 .txFrameToPaOn = 0x0e, 910 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 911 .antennaGain = 0, 912 .switchSettling = 0x2d, 913 .adcDesiredSize = -30, 914 .txEndToXpaOff = 0, 915 .txEndToRxOn = 0x2, 916 .txFrameToXpaOn = 0xe, 917 .thresh62 = 28, 918 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 919 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 920 .futureModal = { 921 0, 0, 0, 0, 0, 0, 0, 0, 922 }, 923 }, 924 .base_ext2 = { 925 .tempSlopeLow = 72, 926 .tempSlopeHigh = 105, 927 .xatten1DBLow = {0, 0, 0}, 928 .xatten1MarginLow = {0, 0, 0}, 929 .xatten1DBHigh = {0, 0, 0}, 930 .xatten1MarginHigh = {0, 0, 0} 931 }, 932 .calFreqPier5G = { 933 FREQ2FBIN(5180, 0), 934 FREQ2FBIN(5240, 0), 935 FREQ2FBIN(5320, 0), 936 FREQ2FBIN(5400, 0), 937 FREQ2FBIN(5500, 0), 938 FREQ2FBIN(5600, 0), 939 FREQ2FBIN(5745, 0), 940 FREQ2FBIN(5785, 0) 941 }, 942 .calPierData5G = { 943 { 944 {0, 0, 0, 0, 0}, 945 {0, 0, 0, 0, 0}, 946 {0, 0, 0, 0, 0}, 947 {0, 0, 0, 0, 0}, 948 {0, 0, 0, 0, 0}, 949 {0, 0, 0, 0, 0}, 950 {0, 0, 0, 0, 0}, 951 {0, 0, 0, 0, 0}, 952 }, 953 { 954 {0, 0, 0, 0, 0}, 955 {0, 0, 0, 0, 0}, 956 {0, 0, 0, 0, 0}, 957 {0, 0, 0, 0, 0}, 958 {0, 0, 0, 0, 0}, 959 {0, 0, 0, 0, 0}, 960 {0, 0, 0, 0, 0}, 961 {0, 0, 0, 0, 0}, 962 }, 963 { 964 {0, 0, 0, 0, 0}, 965 {0, 0, 0, 0, 0}, 966 {0, 0, 0, 0, 0}, 967 {0, 0, 0, 0, 0}, 968 {0, 0, 0, 0, 0}, 969 {0, 0, 0, 0, 0}, 970 {0, 0, 0, 0, 0}, 971 {0, 0, 0, 0, 0}, 972 }, 973 974 }, 975 .calTarget_freqbin_5G = { 976 FREQ2FBIN(5180, 0), 977 FREQ2FBIN(5220, 0), 978 FREQ2FBIN(5320, 0), 979 FREQ2FBIN(5400, 0), 980 FREQ2FBIN(5500, 0), 981 FREQ2FBIN(5600, 0), 982 FREQ2FBIN(5745, 0), 983 FREQ2FBIN(5785, 0) 984 }, 985 .calTarget_freqbin_5GHT20 = { 986 FREQ2FBIN(5180, 0), 987 FREQ2FBIN(5240, 0), 988 FREQ2FBIN(5320, 0), 989 FREQ2FBIN(5400, 0), 990 FREQ2FBIN(5500, 0), 991 FREQ2FBIN(5700, 0), 992 FREQ2FBIN(5745, 0), 993 FREQ2FBIN(5825, 0) 994 }, 995 .calTarget_freqbin_5GHT40 = { 996 FREQ2FBIN(5190, 0), 997 FREQ2FBIN(5230, 0), 998 FREQ2FBIN(5320, 0), 999 FREQ2FBIN(5410, 0), 1000 FREQ2FBIN(5510, 0), 1001 FREQ2FBIN(5670, 0), 1002 FREQ2FBIN(5755, 0), 1003 FREQ2FBIN(5825, 0) 1004 }, 1005 .calTargetPower5G = { 1006 /* 6-24,36,48,54 */ 1007 { {42, 40, 40, 34} }, 1008 { {42, 40, 40, 34} }, 1009 { {42, 40, 40, 34} }, 1010 { {42, 40, 40, 34} }, 1011 { {42, 40, 40, 34} }, 1012 { {42, 40, 40, 34} }, 1013 { {42, 40, 40, 34} }, 1014 { {42, 40, 40, 34} }, 1015 }, 1016 .calTargetPower5GHT20 = { 1017 /* 1018 * 0_8_16,1-3_9-11_17-19, 1019 * 4,5,6,7,12,13,14,15,20,21,22,23 1020 */ 1021 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1022 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1023 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1024 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1025 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1026 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} }, 1027 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} }, 1028 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} }, 1029 }, 1030 .calTargetPower5GHT40 = { 1031 /* 1032 * 0_8_16,1-3_9-11_17-19, 1033 * 4,5,6,7,12,13,14,15,20,21,22,23 1034 */ 1035 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1036 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1037 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1038 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1039 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1040 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} }, 1041 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} }, 1042 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} }, 1043 }, 1044 .ctlIndex_5G = { 1045 0x10, 0x16, 0x18, 0x40, 0x46, 1046 0x48, 0x30, 0x36, 0x38 1047 }, 1048 .ctl_freqbin_5G = { 1049 { 1050 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1051 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1052 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1053 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1054 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 1055 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1056 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1057 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1058 }, 1059 { 1060 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1061 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1062 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1063 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1064 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 1065 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1066 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1067 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1068 }, 1069 1070 { 1071 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1072 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1073 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1074 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 1075 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 1076 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 1077 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 1078 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 1079 }, 1080 1081 { 1082 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1083 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1084 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 1085 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 1086 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1087 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1088 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 1089 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 1090 }, 1091 1092 { 1093 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1094 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1095 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 1096 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 1097 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 1098 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 1099 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 1100 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 1101 }, 1102 1103 { 1104 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1105 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 1106 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 1107 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1108 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 1109 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1110 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 1111 /* Data[5].ctlEdges[7].bChannel */ 0xFF 1112 }, 1113 1114 { 1115 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1116 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1117 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 1118 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 1119 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1120 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 1121 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 1122 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 1123 }, 1124 1125 { 1126 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1127 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1128 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 1129 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1130 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 1131 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1132 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1133 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1134 }, 1135 1136 { 1137 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1138 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1139 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1140 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1141 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 1142 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1143 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 1144 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 1145 } 1146 }, 1147 .ctlPowerData_5G = { 1148 { 1149 { 1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1151 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1152 } 1153 }, 1154 { 1155 { 1156 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1157 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1158 } 1159 }, 1160 { 1161 { 1162 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1163 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1164 } 1165 }, 1166 { 1167 { 1168 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1169 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1170 } 1171 }, 1172 { 1173 { 1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1175 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1176 } 1177 }, 1178 { 1179 { 1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1181 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1182 } 1183 }, 1184 { 1185 { 1186 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1187 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1188 } 1189 }, 1190 { 1191 { 1192 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1193 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1194 } 1195 }, 1196 { 1197 { 1198 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 1199 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1200 } 1201 }, 1202 } 1203 }; 1204 1205 1206 static const struct ar9300_eeprom ar9300_h112 = { 1207 .eepromVersion = 2, 1208 .templateVersion = 3, 1209 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 1210 .custData = {"h112-241-f0000"}, 1211 .baseEepHeader = { 1212 .regDmn = { LE16(0), LE16(0x1f) }, 1213 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 1214 .opCapFlags = { 1215 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 1216 .eepMisc = 0, 1217 }, 1218 .rfSilent = 0, 1219 .blueToothOptions = 0, 1220 .deviceCap = 0, 1221 .deviceType = 5, /* takes lower byte in eeprom location */ 1222 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 1223 .params_for_tuning_caps = {0, 0}, 1224 .featureEnable = 0x0d, 1225 /* 1226 * bit0 - enable tx temp comp - disabled 1227 * bit1 - enable tx volt comp - disabled 1228 * bit2 - enable fastClock - enabled 1229 * bit3 - enable doubling - enabled 1230 * bit4 - enable internal regulator - disabled 1231 * bit5 - enable pa predistortion - disabled 1232 */ 1233 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 1234 .eepromWriteEnableGpio = 6, 1235 .wlanDisableGpio = 0, 1236 .wlanLedGpio = 8, 1237 .rxBandSelectGpio = 0xff, 1238 .txrxgain = 0x10, 1239 .swreg = 0, 1240 }, 1241 .modalHeader2G = { 1242 /* ar9300_modal_eep_header 2g */ 1243 /* 4 idle,t1,t2,b(4 bits per setting) */ 1244 .antCtrlCommon = LE32(0x110), 1245 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 1246 .antCtrlCommon2 = LE32(0x44444), 1247 1248 /* 1249 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 1250 * rx1, rx12, b (2 bits each) 1251 */ 1252 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) }, 1253 1254 /* 1255 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 1256 * for ar9280 (0xa20c/b20c 5:0) 1257 */ 1258 .xatten1DB = {0, 0, 0}, 1259 1260 /* 1261 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 1262 * for ar9280 (0xa20c/b20c 16:12 1263 */ 1264 .xatten1Margin = {0, 0, 0}, 1265 .tempSlope = 25, 1266 .voltSlope = 0, 1267 1268 /* 1269 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 1270 * channels in usual fbin coding format 1271 */ 1272 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 1273 1274 /* 1275 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 1276 * if the register is per chain 1277 */ 1278 .noiseFloorThreshCh = {-1, 0, 0}, 1279 .ob = {1, 1, 1},/* 3 chain */ 1280 .db_stage2 = {1, 1, 1}, /* 3 chain */ 1281 .db_stage3 = {0, 0, 0}, 1282 .db_stage4 = {0, 0, 0}, 1283 .xpaBiasLvl = 0, 1284 .txFrameToDataStart = 0x0e, 1285 .txFrameToPaOn = 0x0e, 1286 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 1287 .antennaGain = 0, 1288 .switchSettling = 0x2c, 1289 .adcDesiredSize = -30, 1290 .txEndToXpaOff = 0, 1291 .txEndToRxOn = 0x2, 1292 .txFrameToXpaOn = 0xe, 1293 .thresh62 = 28, 1294 .papdRateMaskHt20 = LE32(0x80c080), 1295 .papdRateMaskHt40 = LE32(0x80c080), 1296 .futureModal = { 1297 0, 0, 0, 0, 0, 0, 0, 0, 1298 }, 1299 }, 1300 .base_ext1 = { 1301 .ant_div_control = 0, 1302 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 1303 }, 1304 .calFreqPier2G = { 1305 FREQ2FBIN(2412, 1), 1306 FREQ2FBIN(2437, 1), 1307 FREQ2FBIN(2472, 1), 1308 }, 1309 /* ar9300_cal_data_per_freq_op_loop 2g */ 1310 .calPierData2G = { 1311 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1312 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1313 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1314 }, 1315 .calTarget_freqbin_Cck = { 1316 FREQ2FBIN(2412, 1), 1317 FREQ2FBIN(2484, 1), 1318 }, 1319 .calTarget_freqbin_2G = { 1320 FREQ2FBIN(2412, 1), 1321 FREQ2FBIN(2437, 1), 1322 FREQ2FBIN(2472, 1) 1323 }, 1324 .calTarget_freqbin_2GHT20 = { 1325 FREQ2FBIN(2412, 1), 1326 FREQ2FBIN(2437, 1), 1327 FREQ2FBIN(2472, 1) 1328 }, 1329 .calTarget_freqbin_2GHT40 = { 1330 FREQ2FBIN(2412, 1), 1331 FREQ2FBIN(2437, 1), 1332 FREQ2FBIN(2472, 1) 1333 }, 1334 .calTargetPowerCck = { 1335 /* 1L-5L,5S,11L,11S */ 1336 { {34, 34, 34, 34} }, 1337 { {34, 34, 34, 34} }, 1338 }, 1339 .calTargetPower2G = { 1340 /* 6-24,36,48,54 */ 1341 { {34, 34, 32, 32} }, 1342 { {34, 34, 32, 32} }, 1343 { {34, 34, 32, 32} }, 1344 }, 1345 .calTargetPower2GHT20 = { 1346 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, 1347 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, 1348 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} }, 1349 }, 1350 .calTargetPower2GHT40 = { 1351 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, 1352 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, 1353 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} }, 1354 }, 1355 .ctlIndex_2G = { 1356 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 1357 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 1358 }, 1359 .ctl_freqbin_2G = { 1360 { 1361 FREQ2FBIN(2412, 1), 1362 FREQ2FBIN(2417, 1), 1363 FREQ2FBIN(2457, 1), 1364 FREQ2FBIN(2462, 1) 1365 }, 1366 { 1367 FREQ2FBIN(2412, 1), 1368 FREQ2FBIN(2417, 1), 1369 FREQ2FBIN(2462, 1), 1370 0xFF, 1371 }, 1372 1373 { 1374 FREQ2FBIN(2412, 1), 1375 FREQ2FBIN(2417, 1), 1376 FREQ2FBIN(2462, 1), 1377 0xFF, 1378 }, 1379 { 1380 FREQ2FBIN(2422, 1), 1381 FREQ2FBIN(2427, 1), 1382 FREQ2FBIN(2447, 1), 1383 FREQ2FBIN(2452, 1) 1384 }, 1385 1386 { 1387 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1388 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1389 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1390 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 1391 }, 1392 1393 { 1394 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1395 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1396 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1397 0, 1398 }, 1399 1400 { 1401 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1402 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1403 FREQ2FBIN(2472, 1), 1404 0, 1405 }, 1406 1407 { 1408 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 1409 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 1410 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 1411 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 1412 }, 1413 1414 { 1415 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1416 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1417 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1418 }, 1419 1420 { 1421 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1422 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1423 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1424 0 1425 }, 1426 1427 { 1428 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 1429 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 1430 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 1431 0 1432 }, 1433 1434 { 1435 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 1436 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 1437 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 1438 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 1439 } 1440 }, 1441 .ctlPowerData_2G = { 1442 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1443 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1444 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 1445 1446 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 1447 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1448 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1449 1450 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 1451 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1452 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1453 1454 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1455 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 1456 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 1457 }, 1458 .modalHeader5G = { 1459 /* 4 idle,t1,t2,b (4 bits per setting) */ 1460 .antCtrlCommon = LE32(0x220), 1461 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 1462 .antCtrlCommon2 = LE32(0x44444), 1463 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 1464 .antCtrlChain = { 1465 LE16(0x150), LE16(0x150), LE16(0x150), 1466 }, 1467 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 1468 .xatten1DB = {0, 0, 0}, 1469 1470 /* 1471 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 1472 * for merlin (0xa20c/b20c 16:12 1473 */ 1474 .xatten1Margin = {0, 0, 0}, 1475 .tempSlope = 45, 1476 .voltSlope = 0, 1477 /* spurChans spur channels in usual fbin coding format */ 1478 .spurChans = {0, 0, 0, 0, 0}, 1479 /* noiseFloorThreshCh Check if the register is per chain */ 1480 .noiseFloorThreshCh = {-1, 0, 0}, 1481 .ob = {3, 3, 3}, /* 3 chain */ 1482 .db_stage2 = {3, 3, 3}, /* 3 chain */ 1483 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ 1484 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ 1485 .xpaBiasLvl = 0, 1486 .txFrameToDataStart = 0x0e, 1487 .txFrameToPaOn = 0x0e, 1488 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 1489 .antennaGain = 0, 1490 .switchSettling = 0x2d, 1491 .adcDesiredSize = -30, 1492 .txEndToXpaOff = 0, 1493 .txEndToRxOn = 0x2, 1494 .txFrameToXpaOn = 0xe, 1495 .thresh62 = 28, 1496 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 1497 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 1498 .futureModal = { 1499 0, 0, 0, 0, 0, 0, 0, 0, 1500 }, 1501 }, 1502 .base_ext2 = { 1503 .tempSlopeLow = 40, 1504 .tempSlopeHigh = 50, 1505 .xatten1DBLow = {0, 0, 0}, 1506 .xatten1MarginLow = {0, 0, 0}, 1507 .xatten1DBHigh = {0, 0, 0}, 1508 .xatten1MarginHigh = {0, 0, 0} 1509 }, 1510 .calFreqPier5G = { 1511 FREQ2FBIN(5180, 0), 1512 FREQ2FBIN(5220, 0), 1513 FREQ2FBIN(5320, 0), 1514 FREQ2FBIN(5400, 0), 1515 FREQ2FBIN(5500, 0), 1516 FREQ2FBIN(5600, 0), 1517 FREQ2FBIN(5700, 0), 1518 FREQ2FBIN(5825, 0) 1519 }, 1520 .calPierData5G = { 1521 { 1522 {0, 0, 0, 0, 0}, 1523 {0, 0, 0, 0, 0}, 1524 {0, 0, 0, 0, 0}, 1525 {0, 0, 0, 0, 0}, 1526 {0, 0, 0, 0, 0}, 1527 {0, 0, 0, 0, 0}, 1528 {0, 0, 0, 0, 0}, 1529 {0, 0, 0, 0, 0}, 1530 }, 1531 { 1532 {0, 0, 0, 0, 0}, 1533 {0, 0, 0, 0, 0}, 1534 {0, 0, 0, 0, 0}, 1535 {0, 0, 0, 0, 0}, 1536 {0, 0, 0, 0, 0}, 1537 {0, 0, 0, 0, 0}, 1538 {0, 0, 0, 0, 0}, 1539 {0, 0, 0, 0, 0}, 1540 }, 1541 { 1542 {0, 0, 0, 0, 0}, 1543 {0, 0, 0, 0, 0}, 1544 {0, 0, 0, 0, 0}, 1545 {0, 0, 0, 0, 0}, 1546 {0, 0, 0, 0, 0}, 1547 {0, 0, 0, 0, 0}, 1548 {0, 0, 0, 0, 0}, 1549 {0, 0, 0, 0, 0}, 1550 }, 1551 1552 }, 1553 .calTarget_freqbin_5G = { 1554 FREQ2FBIN(5180, 0), 1555 FREQ2FBIN(5240, 0), 1556 FREQ2FBIN(5320, 0), 1557 FREQ2FBIN(5400, 0), 1558 FREQ2FBIN(5500, 0), 1559 FREQ2FBIN(5600, 0), 1560 FREQ2FBIN(5700, 0), 1561 FREQ2FBIN(5825, 0) 1562 }, 1563 .calTarget_freqbin_5GHT20 = { 1564 FREQ2FBIN(5180, 0), 1565 FREQ2FBIN(5240, 0), 1566 FREQ2FBIN(5320, 0), 1567 FREQ2FBIN(5400, 0), 1568 FREQ2FBIN(5500, 0), 1569 FREQ2FBIN(5700, 0), 1570 FREQ2FBIN(5745, 0), 1571 FREQ2FBIN(5825, 0) 1572 }, 1573 .calTarget_freqbin_5GHT40 = { 1574 FREQ2FBIN(5180, 0), 1575 FREQ2FBIN(5240, 0), 1576 FREQ2FBIN(5320, 0), 1577 FREQ2FBIN(5400, 0), 1578 FREQ2FBIN(5500, 0), 1579 FREQ2FBIN(5700, 0), 1580 FREQ2FBIN(5745, 0), 1581 FREQ2FBIN(5825, 0) 1582 }, 1583 .calTargetPower5G = { 1584 /* 6-24,36,48,54 */ 1585 { {30, 30, 28, 24} }, 1586 { {30, 30, 28, 24} }, 1587 { {30, 30, 28, 24} }, 1588 { {30, 30, 28, 24} }, 1589 { {30, 30, 28, 24} }, 1590 { {30, 30, 28, 24} }, 1591 { {30, 30, 28, 24} }, 1592 { {30, 30, 28, 24} }, 1593 }, 1594 .calTargetPower5GHT20 = { 1595 /* 1596 * 0_8_16,1-3_9-11_17-19, 1597 * 4,5,6,7,12,13,14,15,20,21,22,23 1598 */ 1599 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, 1600 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} }, 1601 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, 1602 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} }, 1603 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, 1604 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} }, 1605 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, 1606 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} }, 1607 }, 1608 .calTargetPower5GHT40 = { 1609 /* 1610 * 0_8_16,1-3_9-11_17-19, 1611 * 4,5,6,7,12,13,14,15,20,21,22,23 1612 */ 1613 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, 1614 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} }, 1615 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, 1616 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} }, 1617 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, 1618 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} }, 1619 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, 1620 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} }, 1621 }, 1622 .ctlIndex_5G = { 1623 0x10, 0x16, 0x18, 0x40, 0x46, 1624 0x48, 0x30, 0x36, 0x38 1625 }, 1626 .ctl_freqbin_5G = { 1627 { 1628 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1629 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1630 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1631 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1632 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 1633 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1634 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1635 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1636 }, 1637 { 1638 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1639 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1640 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 1641 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1642 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 1643 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1644 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1645 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1646 }, 1647 1648 { 1649 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1650 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1651 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1652 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 1653 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 1654 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 1655 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 1656 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 1657 }, 1658 1659 { 1660 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1661 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1662 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 1663 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 1664 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1665 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1666 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 1667 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 1668 }, 1669 1670 { 1671 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1672 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1673 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 1674 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 1675 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 1676 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 1677 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 1678 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 1679 }, 1680 1681 { 1682 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1683 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 1684 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 1685 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1686 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 1687 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1688 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 1689 /* Data[5].ctlEdges[7].bChannel */ 0xFF 1690 }, 1691 1692 { 1693 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1694 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 1695 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 1696 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 1697 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 1698 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 1699 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 1700 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 1701 }, 1702 1703 { 1704 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 1705 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 1706 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 1707 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 1708 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 1709 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 1710 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 1711 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 1712 }, 1713 1714 { 1715 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 1716 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 1717 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 1718 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 1719 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 1720 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 1721 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 1722 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 1723 } 1724 }, 1725 .ctlPowerData_5G = { 1726 { 1727 { 1728 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1729 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1730 } 1731 }, 1732 { 1733 { 1734 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1735 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1736 } 1737 }, 1738 { 1739 { 1740 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1741 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1742 } 1743 }, 1744 { 1745 { 1746 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1747 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1748 } 1749 }, 1750 { 1751 { 1752 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1753 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1754 } 1755 }, 1756 { 1757 { 1758 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1759 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 1760 } 1761 }, 1762 { 1763 { 1764 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1765 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 1766 } 1767 }, 1768 { 1769 { 1770 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1771 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 1772 } 1773 }, 1774 { 1775 { 1776 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 1777 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 1778 } 1779 }, 1780 } 1781 }; 1782 1783 1784 static const struct ar9300_eeprom ar9300_x112 = { 1785 .eepromVersion = 2, 1786 .templateVersion = 5, 1787 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 1788 .custData = {"x112-041-f0000"}, 1789 .baseEepHeader = { 1790 .regDmn = { LE16(0), LE16(0x1f) }, 1791 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */ 1792 .opCapFlags = { 1793 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 1794 .eepMisc = 0, 1795 }, 1796 .rfSilent = 0, 1797 .blueToothOptions = 0, 1798 .deviceCap = 0, 1799 .deviceType = 5, /* takes lower byte in eeprom location */ 1800 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 1801 .params_for_tuning_caps = {0, 0}, 1802 .featureEnable = 0x0d, 1803 /* 1804 * bit0 - enable tx temp comp - disabled 1805 * bit1 - enable tx volt comp - disabled 1806 * bit2 - enable fastclock - enabled 1807 * bit3 - enable doubling - enabled 1808 * bit4 - enable internal regulator - disabled 1809 * bit5 - enable pa predistortion - disabled 1810 */ 1811 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 1812 .eepromWriteEnableGpio = 6, 1813 .wlanDisableGpio = 0, 1814 .wlanLedGpio = 8, 1815 .rxBandSelectGpio = 0xff, 1816 .txrxgain = 0x0, 1817 .swreg = 0, 1818 }, 1819 .modalHeader2G = { 1820 /* ar9300_modal_eep_header 2g */ 1821 /* 4 idle,t1,t2,b(4 bits per setting) */ 1822 .antCtrlCommon = LE32(0x110), 1823 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 1824 .antCtrlCommon2 = LE32(0x22222), 1825 1826 /* 1827 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r, 1828 * rx1, rx12, b (2 bits each) 1829 */ 1830 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, 1831 1832 /* 1833 * xatten1DB[AR9300_max_chains]; 3 xatten1_db 1834 * for ar9280 (0xa20c/b20c 5:0) 1835 */ 1836 .xatten1DB = {0x1b, 0x1b, 0x1b}, 1837 1838 /* 1839 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin 1840 * for ar9280 (0xa20c/b20c 16:12 1841 */ 1842 .xatten1Margin = {0x15, 0x15, 0x15}, 1843 .tempSlope = 50, 1844 .voltSlope = 0, 1845 1846 /* 1847 * spurChans[OSPrey_eeprom_modal_sPURS]; spur 1848 * channels in usual fbin coding format 1849 */ 1850 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 1851 1852 /* 1853 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check 1854 * if the register is per chain 1855 */ 1856 .noiseFloorThreshCh = {-1, 0, 0}, 1857 .ob = {1, 1, 1},/* 3 chain */ 1858 .db_stage2 = {1, 1, 1}, /* 3 chain */ 1859 .db_stage3 = {0, 0, 0}, 1860 .db_stage4 = {0, 0, 0}, 1861 .xpaBiasLvl = 0, 1862 .txFrameToDataStart = 0x0e, 1863 .txFrameToPaOn = 0x0e, 1864 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 1865 .antennaGain = 0, 1866 .switchSettling = 0x2c, 1867 .adcDesiredSize = -30, 1868 .txEndToXpaOff = 0, 1869 .txEndToRxOn = 0x2, 1870 .txFrameToXpaOn = 0xe, 1871 .thresh62 = 28, 1872 .papdRateMaskHt20 = LE32(0x0c80c080), 1873 .papdRateMaskHt40 = LE32(0x0080c080), 1874 .futureModal = { 1875 0, 0, 0, 0, 0, 0, 0, 0, 1876 }, 1877 }, 1878 .base_ext1 = { 1879 .ant_div_control = 0, 1880 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 1881 }, 1882 .calFreqPier2G = { 1883 FREQ2FBIN(2412, 1), 1884 FREQ2FBIN(2437, 1), 1885 FREQ2FBIN(2472, 1), 1886 }, 1887 /* ar9300_cal_data_per_freq_op_loop 2g */ 1888 .calPierData2G = { 1889 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1890 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1891 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 1892 }, 1893 .calTarget_freqbin_Cck = { 1894 FREQ2FBIN(2412, 1), 1895 FREQ2FBIN(2472, 1), 1896 }, 1897 .calTarget_freqbin_2G = { 1898 FREQ2FBIN(2412, 1), 1899 FREQ2FBIN(2437, 1), 1900 FREQ2FBIN(2472, 1) 1901 }, 1902 .calTarget_freqbin_2GHT20 = { 1903 FREQ2FBIN(2412, 1), 1904 FREQ2FBIN(2437, 1), 1905 FREQ2FBIN(2472, 1) 1906 }, 1907 .calTarget_freqbin_2GHT40 = { 1908 FREQ2FBIN(2412, 1), 1909 FREQ2FBIN(2437, 1), 1910 FREQ2FBIN(2472, 1) 1911 }, 1912 .calTargetPowerCck = { 1913 /* 1L-5L,5S,11L,11s */ 1914 { {38, 38, 38, 38} }, 1915 { {38, 38, 38, 38} }, 1916 }, 1917 .calTargetPower2G = { 1918 /* 6-24,36,48,54 */ 1919 { {38, 38, 36, 34} }, 1920 { {38, 38, 36, 34} }, 1921 { {38, 38, 34, 32} }, 1922 }, 1923 .calTargetPower2GHT20 = { 1924 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, 1925 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} }, 1926 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} }, 1927 }, 1928 .calTargetPower2GHT40 = { 1929 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, 1930 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} }, 1931 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} }, 1932 }, 1933 .ctlIndex_2G = { 1934 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 1935 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 1936 }, 1937 .ctl_freqbin_2G = { 1938 { 1939 FREQ2FBIN(2412, 1), 1940 FREQ2FBIN(2417, 1), 1941 FREQ2FBIN(2457, 1), 1942 FREQ2FBIN(2462, 1) 1943 }, 1944 { 1945 FREQ2FBIN(2412, 1), 1946 FREQ2FBIN(2417, 1), 1947 FREQ2FBIN(2462, 1), 1948 0xFF, 1949 }, 1950 1951 { 1952 FREQ2FBIN(2412, 1), 1953 FREQ2FBIN(2417, 1), 1954 FREQ2FBIN(2462, 1), 1955 0xFF, 1956 }, 1957 { 1958 FREQ2FBIN(2422, 1), 1959 FREQ2FBIN(2427, 1), 1960 FREQ2FBIN(2447, 1), 1961 FREQ2FBIN(2452, 1) 1962 }, 1963 1964 { 1965 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1966 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1967 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 1968 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1), 1969 }, 1970 1971 { 1972 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1973 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1974 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 1975 0, 1976 }, 1977 1978 { 1979 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1980 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1981 FREQ2FBIN(2472, 1), 1982 0, 1983 }, 1984 1985 { 1986 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), 1987 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), 1988 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), 1989 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), 1990 }, 1991 1992 { 1993 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 1994 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 1995 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 1996 }, 1997 1998 { 1999 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 2000 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 2001 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 2002 0 2003 }, 2004 2005 { 2006 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1), 2007 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1), 2008 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1), 2009 0 2010 }, 2011 2012 { 2013 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1), 2014 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1), 2015 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1), 2016 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1), 2017 } 2018 }, 2019 .ctlPowerData_2G = { 2020 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2021 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2022 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 2023 2024 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 2025 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2026 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2027 2028 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 2029 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2030 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2031 2032 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2033 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2034 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2035 }, 2036 .modalHeader5G = { 2037 /* 4 idle,t1,t2,b (4 bits per setting) */ 2038 .antCtrlCommon = LE32(0x110), 2039 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 2040 .antCtrlCommon2 = LE32(0x22222), 2041 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 2042 .antCtrlChain = { 2043 LE16(0x0), LE16(0x0), LE16(0x0), 2044 }, 2045 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */ 2046 .xatten1DB = {0x13, 0x19, 0x17}, 2047 2048 /* 2049 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin 2050 * for merlin (0xa20c/b20c 16:12 2051 */ 2052 .xatten1Margin = {0x19, 0x19, 0x19}, 2053 .tempSlope = 70, 2054 .voltSlope = 15, 2055 /* spurChans spur channels in usual fbin coding format */ 2056 .spurChans = {0, 0, 0, 0, 0}, 2057 /* noiseFloorThreshch check if the register is per chain */ 2058 .noiseFloorThreshCh = {-1, 0, 0}, 2059 .ob = {3, 3, 3}, /* 3 chain */ 2060 .db_stage2 = {3, 3, 3}, /* 3 chain */ 2061 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ 2062 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ 2063 .xpaBiasLvl = 0, 2064 .txFrameToDataStart = 0x0e, 2065 .txFrameToPaOn = 0x0e, 2066 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 2067 .antennaGain = 0, 2068 .switchSettling = 0x2d, 2069 .adcDesiredSize = -30, 2070 .txEndToXpaOff = 0, 2071 .txEndToRxOn = 0x2, 2072 .txFrameToXpaOn = 0xe, 2073 .thresh62 = 28, 2074 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2075 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2076 .futureModal = { 2077 0, 0, 0, 0, 0, 0, 0, 0, 2078 }, 2079 }, 2080 .base_ext2 = { 2081 .tempSlopeLow = 72, 2082 .tempSlopeHigh = 105, 2083 .xatten1DBLow = {0x10, 0x14, 0x10}, 2084 .xatten1MarginLow = {0x19, 0x19 , 0x19}, 2085 .xatten1DBHigh = {0x1d, 0x20, 0x24}, 2086 .xatten1MarginHigh = {0x10, 0x10, 0x10} 2087 }, 2088 .calFreqPier5G = { 2089 FREQ2FBIN(5180, 0), 2090 FREQ2FBIN(5220, 0), 2091 FREQ2FBIN(5320, 0), 2092 FREQ2FBIN(5400, 0), 2093 FREQ2FBIN(5500, 0), 2094 FREQ2FBIN(5600, 0), 2095 FREQ2FBIN(5700, 0), 2096 FREQ2FBIN(5785, 0) 2097 }, 2098 .calPierData5G = { 2099 { 2100 {0, 0, 0, 0, 0}, 2101 {0, 0, 0, 0, 0}, 2102 {0, 0, 0, 0, 0}, 2103 {0, 0, 0, 0, 0}, 2104 {0, 0, 0, 0, 0}, 2105 {0, 0, 0, 0, 0}, 2106 {0, 0, 0, 0, 0}, 2107 {0, 0, 0, 0, 0}, 2108 }, 2109 { 2110 {0, 0, 0, 0, 0}, 2111 {0, 0, 0, 0, 0}, 2112 {0, 0, 0, 0, 0}, 2113 {0, 0, 0, 0, 0}, 2114 {0, 0, 0, 0, 0}, 2115 {0, 0, 0, 0, 0}, 2116 {0, 0, 0, 0, 0}, 2117 {0, 0, 0, 0, 0}, 2118 }, 2119 { 2120 {0, 0, 0, 0, 0}, 2121 {0, 0, 0, 0, 0}, 2122 {0, 0, 0, 0, 0}, 2123 {0, 0, 0, 0, 0}, 2124 {0, 0, 0, 0, 0}, 2125 {0, 0, 0, 0, 0}, 2126 {0, 0, 0, 0, 0}, 2127 {0, 0, 0, 0, 0}, 2128 }, 2129 2130 }, 2131 .calTarget_freqbin_5G = { 2132 FREQ2FBIN(5180, 0), 2133 FREQ2FBIN(5220, 0), 2134 FREQ2FBIN(5320, 0), 2135 FREQ2FBIN(5400, 0), 2136 FREQ2FBIN(5500, 0), 2137 FREQ2FBIN(5600, 0), 2138 FREQ2FBIN(5725, 0), 2139 FREQ2FBIN(5825, 0) 2140 }, 2141 .calTarget_freqbin_5GHT20 = { 2142 FREQ2FBIN(5180, 0), 2143 FREQ2FBIN(5220, 0), 2144 FREQ2FBIN(5320, 0), 2145 FREQ2FBIN(5400, 0), 2146 FREQ2FBIN(5500, 0), 2147 FREQ2FBIN(5600, 0), 2148 FREQ2FBIN(5725, 0), 2149 FREQ2FBIN(5825, 0) 2150 }, 2151 .calTarget_freqbin_5GHT40 = { 2152 FREQ2FBIN(5180, 0), 2153 FREQ2FBIN(5220, 0), 2154 FREQ2FBIN(5320, 0), 2155 FREQ2FBIN(5400, 0), 2156 FREQ2FBIN(5500, 0), 2157 FREQ2FBIN(5600, 0), 2158 FREQ2FBIN(5725, 0), 2159 FREQ2FBIN(5825, 0) 2160 }, 2161 .calTargetPower5G = { 2162 /* 6-24,36,48,54 */ 2163 { {32, 32, 28, 26} }, 2164 { {32, 32, 28, 26} }, 2165 { {32, 32, 28, 26} }, 2166 { {32, 32, 26, 24} }, 2167 { {32, 32, 26, 24} }, 2168 { {32, 32, 24, 22} }, 2169 { {30, 30, 24, 22} }, 2170 { {30, 30, 24, 22} }, 2171 }, 2172 .calTargetPower5GHT20 = { 2173 /* 2174 * 0_8_16,1-3_9-11_17-19, 2175 * 4,5,6,7,12,13,14,15,20,21,22,23 2176 */ 2177 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, 2178 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, 2179 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} }, 2180 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} }, 2181 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} }, 2182 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} }, 2183 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, 2184 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} }, 2185 }, 2186 .calTargetPower5GHT40 = { 2187 /* 2188 * 0_8_16,1-3_9-11_17-19, 2189 * 4,5,6,7,12,13,14,15,20,21,22,23 2190 */ 2191 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, 2192 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, 2193 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} }, 2194 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} }, 2195 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} }, 2196 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, 2197 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, 2198 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} }, 2199 }, 2200 .ctlIndex_5G = { 2201 0x10, 0x16, 0x18, 0x40, 0x46, 2202 0x48, 0x30, 0x36, 0x38 2203 }, 2204 .ctl_freqbin_5G = { 2205 { 2206 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2207 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2208 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), 2209 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), 2210 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0), 2211 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2212 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), 2213 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) 2214 }, 2215 { 2216 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2217 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2218 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0), 2219 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), 2220 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0), 2221 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2222 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), 2223 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) 2224 }, 2225 2226 { 2227 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), 2228 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), 2229 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), 2230 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0), 2231 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0), 2232 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0), 2233 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0), 2234 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0) 2235 }, 2236 2237 { 2238 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2239 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), 2240 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0), 2241 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0), 2242 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), 2243 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2244 /* Data[3].ctledges[6].bchannel */ 0xFF, 2245 /* Data[3].ctledges[7].bchannel */ 0xFF, 2246 }, 2247 2248 { 2249 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2250 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2251 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0), 2252 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0), 2253 /* Data[4].ctledges[4].bchannel */ 0xFF, 2254 /* Data[4].ctledges[5].bchannel */ 0xFF, 2255 /* Data[4].ctledges[6].bchannel */ 0xFF, 2256 /* Data[4].ctledges[7].bchannel */ 0xFF, 2257 }, 2258 2259 { 2260 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), 2261 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0), 2262 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0), 2263 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), 2264 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0), 2265 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), 2266 /* Data[5].ctledges[6].bchannel */ 0xFF, 2267 /* Data[5].ctledges[7].bchannel */ 0xFF 2268 }, 2269 2270 { 2271 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2272 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0), 2273 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0), 2274 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0), 2275 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0), 2276 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0), 2277 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0), 2278 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0) 2279 }, 2280 2281 { 2282 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0), 2283 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0), 2284 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0), 2285 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0), 2286 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0), 2287 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0), 2288 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0), 2289 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0) 2290 }, 2291 2292 { 2293 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0), 2294 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0), 2295 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0), 2296 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0), 2297 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0), 2298 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0), 2299 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0), 2300 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0) 2301 } 2302 }, 2303 .ctlPowerData_5G = { 2304 { 2305 { 2306 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2307 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2308 } 2309 }, 2310 { 2311 { 2312 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2313 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2314 } 2315 }, 2316 { 2317 { 2318 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2319 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2320 } 2321 }, 2322 { 2323 { 2324 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2325 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2326 } 2327 }, 2328 { 2329 { 2330 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2331 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2332 } 2333 }, 2334 { 2335 { 2336 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2337 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2338 } 2339 }, 2340 { 2341 { 2342 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2343 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2344 } 2345 }, 2346 { 2347 { 2348 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2349 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2350 } 2351 }, 2352 { 2353 { 2354 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 2355 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2356 } 2357 }, 2358 } 2359 }; 2360 2361 static const struct ar9300_eeprom ar9300_h116 = { 2362 .eepromVersion = 2, 2363 .templateVersion = 4, 2364 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, 2365 .custData = {"h116-041-f0000"}, 2366 .baseEepHeader = { 2367 .regDmn = { LE16(0), LE16(0x1f) }, 2368 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */ 2369 .opCapFlags = { 2370 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A, 2371 .eepMisc = 0, 2372 }, 2373 .rfSilent = 0, 2374 .blueToothOptions = 0, 2375 .deviceCap = 0, 2376 .deviceType = 5, /* takes lower byte in eeprom location */ 2377 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET, 2378 .params_for_tuning_caps = {0, 0}, 2379 .featureEnable = 0x0d, 2380 /* 2381 * bit0 - enable tx temp comp - disabled 2382 * bit1 - enable tx volt comp - disabled 2383 * bit2 - enable fastClock - enabled 2384 * bit3 - enable doubling - enabled 2385 * bit4 - enable internal regulator - disabled 2386 * bit5 - enable pa predistortion - disabled 2387 */ 2388 .miscConfiguration = 0, /* bit0 - turn down drivestrength */ 2389 .eepromWriteEnableGpio = 6, 2390 .wlanDisableGpio = 0, 2391 .wlanLedGpio = 8, 2392 .rxBandSelectGpio = 0xff, 2393 .txrxgain = 0x10, 2394 .swreg = 0, 2395 }, 2396 .modalHeader2G = { 2397 /* ar9300_modal_eep_header 2g */ 2398 /* 4 idle,t1,t2,b(4 bits per setting) */ 2399 .antCtrlCommon = LE32(0x110), 2400 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 2401 .antCtrlCommon2 = LE32(0x44444), 2402 2403 /* 2404 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r, 2405 * rx1, rx12, b (2 bits each) 2406 */ 2407 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) }, 2408 2409 /* 2410 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db 2411 * for ar9280 (0xa20c/b20c 5:0) 2412 */ 2413 .xatten1DB = {0x1f, 0x1f, 0x1f}, 2414 2415 /* 2416 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 2417 * for ar9280 (0xa20c/b20c 16:12 2418 */ 2419 .xatten1Margin = {0x12, 0x12, 0x12}, 2420 .tempSlope = 25, 2421 .voltSlope = 0, 2422 2423 /* 2424 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur 2425 * channels in usual fbin coding format 2426 */ 2427 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0}, 2428 2429 /* 2430 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check 2431 * if the register is per chain 2432 */ 2433 .noiseFloorThreshCh = {-1, 0, 0}, 2434 .ob = {1, 1, 1},/* 3 chain */ 2435 .db_stage2 = {1, 1, 1}, /* 3 chain */ 2436 .db_stage3 = {0, 0, 0}, 2437 .db_stage4 = {0, 0, 0}, 2438 .xpaBiasLvl = 0, 2439 .txFrameToDataStart = 0x0e, 2440 .txFrameToPaOn = 0x0e, 2441 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 2442 .antennaGain = 0, 2443 .switchSettling = 0x2c, 2444 .adcDesiredSize = -30, 2445 .txEndToXpaOff = 0, 2446 .txEndToRxOn = 0x2, 2447 .txFrameToXpaOn = 0xe, 2448 .thresh62 = 28, 2449 .papdRateMaskHt20 = LE32(0x0c80C080), 2450 .papdRateMaskHt40 = LE32(0x0080C080), 2451 .futureModal = { 2452 0, 0, 0, 0, 0, 0, 0, 0, 2453 }, 2454 }, 2455 .base_ext1 = { 2456 .ant_div_control = 0, 2457 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 2458 }, 2459 .calFreqPier2G = { 2460 FREQ2FBIN(2412, 1), 2461 FREQ2FBIN(2437, 1), 2462 FREQ2FBIN(2472, 1), 2463 }, 2464 /* ar9300_cal_data_per_freq_op_loop 2g */ 2465 .calPierData2G = { 2466 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 2467 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 2468 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} }, 2469 }, 2470 .calTarget_freqbin_Cck = { 2471 FREQ2FBIN(2412, 1), 2472 FREQ2FBIN(2472, 1), 2473 }, 2474 .calTarget_freqbin_2G = { 2475 FREQ2FBIN(2412, 1), 2476 FREQ2FBIN(2437, 1), 2477 FREQ2FBIN(2472, 1) 2478 }, 2479 .calTarget_freqbin_2GHT20 = { 2480 FREQ2FBIN(2412, 1), 2481 FREQ2FBIN(2437, 1), 2482 FREQ2FBIN(2472, 1) 2483 }, 2484 .calTarget_freqbin_2GHT40 = { 2485 FREQ2FBIN(2412, 1), 2486 FREQ2FBIN(2437, 1), 2487 FREQ2FBIN(2472, 1) 2488 }, 2489 .calTargetPowerCck = { 2490 /* 1L-5L,5S,11L,11S */ 2491 { {34, 34, 34, 34} }, 2492 { {34, 34, 34, 34} }, 2493 }, 2494 .calTargetPower2G = { 2495 /* 6-24,36,48,54 */ 2496 { {34, 34, 32, 32} }, 2497 { {34, 34, 32, 32} }, 2498 { {34, 34, 32, 32} }, 2499 }, 2500 .calTargetPower2GHT20 = { 2501 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, 2502 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, 2503 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} }, 2504 }, 2505 .calTargetPower2GHT40 = { 2506 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 2507 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 2508 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} }, 2509 }, 2510 .ctlIndex_2G = { 2511 0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 2512 0x45, 0x47, 0x31, 0x32, 0x35, 0x37, 2513 }, 2514 .ctl_freqbin_2G = { 2515 { 2516 FREQ2FBIN(2412, 1), 2517 FREQ2FBIN(2417, 1), 2518 FREQ2FBIN(2457, 1), 2519 FREQ2FBIN(2462, 1) 2520 }, 2521 { 2522 FREQ2FBIN(2412, 1), 2523 FREQ2FBIN(2417, 1), 2524 FREQ2FBIN(2462, 1), 2525 0xFF, 2526 }, 2527 2528 { 2529 FREQ2FBIN(2412, 1), 2530 FREQ2FBIN(2417, 1), 2531 FREQ2FBIN(2462, 1), 2532 0xFF, 2533 }, 2534 { 2535 FREQ2FBIN(2422, 1), 2536 FREQ2FBIN(2427, 1), 2537 FREQ2FBIN(2447, 1), 2538 FREQ2FBIN(2452, 1) 2539 }, 2540 2541 { 2542 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2543 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2544 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2545 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1), 2546 }, 2547 2548 { 2549 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2550 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2551 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2552 0, 2553 }, 2554 2555 { 2556 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2557 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2558 FREQ2FBIN(2472, 1), 2559 0, 2560 }, 2561 2562 { 2563 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 2564 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 2565 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 2566 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 2567 }, 2568 2569 { 2570 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2571 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2572 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2573 }, 2574 2575 { 2576 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2577 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2578 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2579 0 2580 }, 2581 2582 { 2583 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1), 2584 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1), 2585 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1), 2586 0 2587 }, 2588 2589 { 2590 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1), 2591 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1), 2592 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1), 2593 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1), 2594 } 2595 }, 2596 .ctlPowerData_2G = { 2597 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2598 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2599 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 2600 2601 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } }, 2602 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2603 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2604 2605 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } }, 2606 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2607 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2608 2609 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2610 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2611 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } }, 2612 }, 2613 .modalHeader5G = { 2614 /* 4 idle,t1,t2,b (4 bits per setting) */ 2615 .antCtrlCommon = LE32(0x220), 2616 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */ 2617 .antCtrlCommon2 = LE32(0x44444), 2618 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */ 2619 .antCtrlChain = { 2620 LE16(0x150), LE16(0x150), LE16(0x150), 2621 }, 2622 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 2623 .xatten1DB = {0x19, 0x19, 0x19}, 2624 2625 /* 2626 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin 2627 * for merlin (0xa20c/b20c 16:12 2628 */ 2629 .xatten1Margin = {0x14, 0x14, 0x14}, 2630 .tempSlope = 70, 2631 .voltSlope = 0, 2632 /* spurChans spur channels in usual fbin coding format */ 2633 .spurChans = {0, 0, 0, 0, 0}, 2634 /* noiseFloorThreshCh Check if the register is per chain */ 2635 .noiseFloorThreshCh = {-1, 0, 0}, 2636 .ob = {3, 3, 3}, /* 3 chain */ 2637 .db_stage2 = {3, 3, 3}, /* 3 chain */ 2638 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */ 2639 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */ 2640 .xpaBiasLvl = 0, 2641 .txFrameToDataStart = 0x0e, 2642 .txFrameToPaOn = 0x0e, 2643 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */ 2644 .antennaGain = 0, 2645 .switchSettling = 0x2d, 2646 .adcDesiredSize = -30, 2647 .txEndToXpaOff = 0, 2648 .txEndToRxOn = 0x2, 2649 .txFrameToXpaOn = 0xe, 2650 .thresh62 = 28, 2651 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2652 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2653 .futureModal = { 2654 0, 0, 0, 0, 0, 0, 0, 0, 2655 }, 2656 }, 2657 .base_ext2 = { 2658 .tempSlopeLow = 35, 2659 .tempSlopeHigh = 50, 2660 .xatten1DBLow = {0, 0, 0}, 2661 .xatten1MarginLow = {0, 0, 0}, 2662 .xatten1DBHigh = {0, 0, 0}, 2663 .xatten1MarginHigh = {0, 0, 0} 2664 }, 2665 .calFreqPier5G = { 2666 FREQ2FBIN(5180, 0), 2667 FREQ2FBIN(5220, 0), 2668 FREQ2FBIN(5320, 0), 2669 FREQ2FBIN(5400, 0), 2670 FREQ2FBIN(5500, 0), 2671 FREQ2FBIN(5600, 0), 2672 FREQ2FBIN(5700, 0), 2673 FREQ2FBIN(5785, 0) 2674 }, 2675 .calPierData5G = { 2676 { 2677 {0, 0, 0, 0, 0}, 2678 {0, 0, 0, 0, 0}, 2679 {0, 0, 0, 0, 0}, 2680 {0, 0, 0, 0, 0}, 2681 {0, 0, 0, 0, 0}, 2682 {0, 0, 0, 0, 0}, 2683 {0, 0, 0, 0, 0}, 2684 {0, 0, 0, 0, 0}, 2685 }, 2686 { 2687 {0, 0, 0, 0, 0}, 2688 {0, 0, 0, 0, 0}, 2689 {0, 0, 0, 0, 0}, 2690 {0, 0, 0, 0, 0}, 2691 {0, 0, 0, 0, 0}, 2692 {0, 0, 0, 0, 0}, 2693 {0, 0, 0, 0, 0}, 2694 {0, 0, 0, 0, 0}, 2695 }, 2696 { 2697 {0, 0, 0, 0, 0}, 2698 {0, 0, 0, 0, 0}, 2699 {0, 0, 0, 0, 0}, 2700 {0, 0, 0, 0, 0}, 2701 {0, 0, 0, 0, 0}, 2702 {0, 0, 0, 0, 0}, 2703 {0, 0, 0, 0, 0}, 2704 {0, 0, 0, 0, 0}, 2705 }, 2706 2707 }, 2708 .calTarget_freqbin_5G = { 2709 FREQ2FBIN(5180, 0), 2710 FREQ2FBIN(5240, 0), 2711 FREQ2FBIN(5320, 0), 2712 FREQ2FBIN(5400, 0), 2713 FREQ2FBIN(5500, 0), 2714 FREQ2FBIN(5600, 0), 2715 FREQ2FBIN(5700, 0), 2716 FREQ2FBIN(5825, 0) 2717 }, 2718 .calTarget_freqbin_5GHT20 = { 2719 FREQ2FBIN(5180, 0), 2720 FREQ2FBIN(5240, 0), 2721 FREQ2FBIN(5320, 0), 2722 FREQ2FBIN(5400, 0), 2723 FREQ2FBIN(5500, 0), 2724 FREQ2FBIN(5700, 0), 2725 FREQ2FBIN(5745, 0), 2726 FREQ2FBIN(5825, 0) 2727 }, 2728 .calTarget_freqbin_5GHT40 = { 2729 FREQ2FBIN(5180, 0), 2730 FREQ2FBIN(5240, 0), 2731 FREQ2FBIN(5320, 0), 2732 FREQ2FBIN(5400, 0), 2733 FREQ2FBIN(5500, 0), 2734 FREQ2FBIN(5700, 0), 2735 FREQ2FBIN(5745, 0), 2736 FREQ2FBIN(5825, 0) 2737 }, 2738 .calTargetPower5G = { 2739 /* 6-24,36,48,54 */ 2740 { {30, 30, 28, 24} }, 2741 { {30, 30, 28, 24} }, 2742 { {30, 30, 28, 24} }, 2743 { {30, 30, 28, 24} }, 2744 { {30, 30, 28, 24} }, 2745 { {30, 30, 28, 24} }, 2746 { {30, 30, 28, 24} }, 2747 { {30, 30, 28, 24} }, 2748 }, 2749 .calTargetPower5GHT20 = { 2750 /* 2751 * 0_8_16,1-3_9-11_17-19, 2752 * 4,5,6,7,12,13,14,15,20,21,22,23 2753 */ 2754 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, 2755 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} }, 2756 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, 2757 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} }, 2758 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, 2759 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} }, 2760 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, 2761 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} }, 2762 }, 2763 .calTargetPower5GHT40 = { 2764 /* 2765 * 0_8_16,1-3_9-11_17-19, 2766 * 4,5,6,7,12,13,14,15,20,21,22,23 2767 */ 2768 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, 2769 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} }, 2770 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, 2771 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} }, 2772 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, 2773 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} }, 2774 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, 2775 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} }, 2776 }, 2777 .ctlIndex_5G = { 2778 0x10, 0x16, 0x18, 0x40, 0x46, 2779 0x48, 0x30, 0x36, 0x38 2780 }, 2781 .ctl_freqbin_5G = { 2782 { 2783 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2784 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2785 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 2786 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 2787 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0), 2788 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2789 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 2790 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 2791 }, 2792 { 2793 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2794 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2795 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0), 2796 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 2797 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0), 2798 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2799 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 2800 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 2801 }, 2802 2803 { 2804 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 2805 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 2806 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 2807 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0), 2808 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0), 2809 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0), 2810 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0), 2811 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0) 2812 }, 2813 2814 { 2815 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2816 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 2817 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0), 2818 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0), 2819 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 2820 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2821 /* Data[3].ctlEdges[6].bChannel */ 0xFF, 2822 /* Data[3].ctlEdges[7].bChannel */ 0xFF, 2823 }, 2824 2825 { 2826 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2827 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2828 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0), 2829 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0), 2830 /* Data[4].ctlEdges[4].bChannel */ 0xFF, 2831 /* Data[4].ctlEdges[5].bChannel */ 0xFF, 2832 /* Data[4].ctlEdges[6].bChannel */ 0xFF, 2833 /* Data[4].ctlEdges[7].bChannel */ 0xFF, 2834 }, 2835 2836 { 2837 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 2838 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0), 2839 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0), 2840 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 2841 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0), 2842 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 2843 /* Data[5].ctlEdges[6].bChannel */ 0xFF, 2844 /* Data[5].ctlEdges[7].bChannel */ 0xFF 2845 }, 2846 2847 { 2848 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2849 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0), 2850 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0), 2851 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0), 2852 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0), 2853 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0), 2854 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0), 2855 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0) 2856 }, 2857 2858 { 2859 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0), 2860 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0), 2861 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0), 2862 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0), 2863 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0), 2864 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0), 2865 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0), 2866 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0) 2867 }, 2868 2869 { 2870 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0), 2871 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0), 2872 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0), 2873 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0), 2874 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0), 2875 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0), 2876 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0), 2877 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0) 2878 } 2879 }, 2880 .ctlPowerData_5G = { 2881 { 2882 { 2883 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2884 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2885 } 2886 }, 2887 { 2888 { 2889 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2890 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2891 } 2892 }, 2893 { 2894 { 2895 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2896 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2897 } 2898 }, 2899 { 2900 { 2901 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2902 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2903 } 2904 }, 2905 { 2906 { 2907 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2908 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2909 } 2910 }, 2911 { 2912 { 2913 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2914 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0), 2915 } 2916 }, 2917 { 2918 { 2919 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2920 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1), 2921 } 2922 }, 2923 { 2924 { 2925 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2926 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0), 2927 } 2928 }, 2929 { 2930 { 2931 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1), 2932 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1), 2933 } 2934 }, 2935 } 2936 }; 2937 2938 2939 static const struct ar9300_eeprom *ar9300_eep_templates[] = { 2940 &ar9300_default, 2941 &ar9300_x112, 2942 &ar9300_h116, 2943 &ar9300_h112, 2944 &ar9300_x113, 2945 }; 2946 2947 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id) 2948 { 2949 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0])) 2950 int it; 2951 2952 for (it = 0; it < N_LOOP; it++) 2953 if (ar9300_eep_templates[it]->templateVersion == id) 2954 return ar9300_eep_templates[it]; 2955 return NULL; 2956 #undef N_LOOP 2957 } 2958 2959 2960 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 2961 { 2962 if (fbin == AR5416_BCHAN_UNUSED) 2963 return fbin; 2964 2965 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 2966 } 2967 2968 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah) 2969 { 2970 return 0; 2971 } 2972 2973 static int interpolate(int x, int xa, int xb, int ya, int yb) 2974 { 2975 int bf, factor, plus; 2976 2977 bf = 2 * (yb - ya) * (x - xa) / (xb - xa); 2978 factor = bf / 2; 2979 plus = bf % 2; 2980 return ya + factor + plus; 2981 } 2982 2983 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, 2984 enum eeprom_param param) 2985 { 2986 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 2987 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; 2988 2989 switch (param) { 2990 case EEP_MAC_LSW: 2991 return get_unaligned_be16(eep->macAddr); 2992 case EEP_MAC_MID: 2993 return get_unaligned_be16(eep->macAddr + 2); 2994 case EEP_MAC_MSW: 2995 return get_unaligned_be16(eep->macAddr + 4); 2996 case EEP_REG_0: 2997 return le16_to_cpu(pBase->regDmn[0]); 2998 case EEP_OP_CAP: 2999 return pBase->deviceCap; 3000 case EEP_OP_MODE: 3001 return pBase->opCapFlags.opFlags; 3002 case EEP_RF_SILENT: 3003 return pBase->rfSilent; 3004 case EEP_TX_MASK: 3005 return (pBase->txrxMask >> 4) & 0xf; 3006 case EEP_RX_MASK: 3007 return pBase->txrxMask & 0xf; 3008 case EEP_DRIVE_STRENGTH: 3009 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1 3010 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH; 3011 case EEP_INTERNAL_REGULATOR: 3012 /* Bit 4 is internal regulator flag */ 3013 return (pBase->featureEnable & 0x10) >> 4; 3014 case EEP_SWREG: 3015 return le32_to_cpu(pBase->swreg); 3016 case EEP_PAPRD: 3017 return !!(pBase->featureEnable & BIT(5)); 3018 case EEP_CHAIN_MASK_REDUCE: 3019 return (pBase->miscConfiguration >> 0x3) & 0x1; 3020 case EEP_ANT_DIV_CTL1: 3021 return eep->base_ext1.ant_div_control; 3022 case EEP_ANTENNA_GAIN_5G: 3023 return eep->modalHeader5G.antennaGain; 3024 case EEP_ANTENNA_GAIN_2G: 3025 return eep->modalHeader2G.antennaGain; 3026 default: 3027 return 0; 3028 } 3029 } 3030 3031 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address, 3032 u8 *buffer) 3033 { 3034 u16 val; 3035 3036 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val))) 3037 return false; 3038 3039 *buffer = (val >> (8 * (address % 2))) & 0xff; 3040 return true; 3041 } 3042 3043 static bool ar9300_eeprom_read_word(struct ath_common *common, int address, 3044 u8 *buffer) 3045 { 3046 u16 val; 3047 3048 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val))) 3049 return false; 3050 3051 buffer[0] = val >> 8; 3052 buffer[1] = val & 0xff; 3053 3054 return true; 3055 } 3056 3057 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, 3058 int count) 3059 { 3060 struct ath_common *common = ath9k_hw_common(ah); 3061 int i; 3062 3063 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { 3064 ath_dbg(common, ATH_DBG_EEPROM, 3065 "eeprom address not in range\n"); 3066 return false; 3067 } 3068 3069 /* 3070 * Since we're reading the bytes in reverse order from a little-endian 3071 * word stream, an even address means we only use the lower half of 3072 * the 16-bit word at that address 3073 */ 3074 if (address % 2 == 0) { 3075 if (!ar9300_eeprom_read_byte(common, address--, buffer++)) 3076 goto error; 3077 3078 count--; 3079 } 3080 3081 for (i = 0; i < count / 2; i++) { 3082 if (!ar9300_eeprom_read_word(common, address, buffer)) 3083 goto error; 3084 3085 address -= 2; 3086 buffer += 2; 3087 } 3088 3089 if (count % 2) 3090 if (!ar9300_eeprom_read_byte(common, address, buffer)) 3091 goto error; 3092 3093 return true; 3094 3095 error: 3096 ath_dbg(common, ATH_DBG_EEPROM, 3097 "unable to read eeprom region at offset %d\n", address); 3098 return false; 3099 } 3100 3101 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data) 3102 { 3103 REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); 3104 3105 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE, 3106 AR9300_OTP_STATUS_VALID, 1000)) 3107 return false; 3108 3109 *data = REG_READ(ah, AR9300_OTP_READ_DATA); 3110 return true; 3111 } 3112 3113 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, 3114 int count) 3115 { 3116 u32 data; 3117 int i; 3118 3119 for (i = 0; i < count; i++) { 3120 int offset = 8 * ((address - i) % 4); 3121 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data)) 3122 return false; 3123 3124 buffer[i] = (data >> offset) & 0xff; 3125 } 3126 3127 return true; 3128 } 3129 3130 3131 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, 3132 int *length, int *major, int *minor) 3133 { 3134 unsigned long value[4]; 3135 3136 value[0] = best[0]; 3137 value[1] = best[1]; 3138 value[2] = best[2]; 3139 value[3] = best[3]; 3140 *code = ((value[0] >> 5) & 0x0007); 3141 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020); 3142 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f); 3143 *major = (value[2] & 0x000f); 3144 *minor = (value[3] & 0x00ff); 3145 } 3146 3147 static u16 ar9300_comp_cksum(u8 *data, int dsize) 3148 { 3149 int it, checksum = 0; 3150 3151 for (it = 0; it < dsize; it++) { 3152 checksum += data[it]; 3153 checksum &= 0xffff; 3154 } 3155 3156 return checksum; 3157 } 3158 3159 static bool ar9300_uncompress_block(struct ath_hw *ah, 3160 u8 *mptr, 3161 int mdataSize, 3162 u8 *block, 3163 int size) 3164 { 3165 int it; 3166 int spot; 3167 int offset; 3168 int length; 3169 struct ath_common *common = ath9k_hw_common(ah); 3170 3171 spot = 0; 3172 3173 for (it = 0; it < size; it += (length+2)) { 3174 offset = block[it]; 3175 offset &= 0xff; 3176 spot += offset; 3177 length = block[it+1]; 3178 length &= 0xff; 3179 3180 if (length > 0 && spot >= 0 && spot+length <= mdataSize) { 3181 ath_dbg(common, ATH_DBG_EEPROM, 3182 "Restore at %d: spot=%d offset=%d length=%d\n", 3183 it, spot, offset, length); 3184 memcpy(&mptr[spot], &block[it+2], length); 3185 spot += length; 3186 } else if (length > 0) { 3187 ath_dbg(common, ATH_DBG_EEPROM, 3188 "Bad restore at %d: spot=%d offset=%d length=%d\n", 3189 it, spot, offset, length); 3190 return false; 3191 } 3192 } 3193 return true; 3194 } 3195 3196 static int ar9300_compress_decision(struct ath_hw *ah, 3197 int it, 3198 int code, 3199 int reference, 3200 u8 *mptr, 3201 u8 *word, int length, int mdata_size) 3202 { 3203 struct ath_common *common = ath9k_hw_common(ah); 3204 const struct ar9300_eeprom *eep = NULL; 3205 3206 switch (code) { 3207 case _CompressNone: 3208 if (length != mdata_size) { 3209 ath_dbg(common, ATH_DBG_EEPROM, 3210 "EEPROM structure size mismatch memory=%d eeprom=%d\n", 3211 mdata_size, length); 3212 return -1; 3213 } 3214 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); 3215 ath_dbg(common, ATH_DBG_EEPROM, 3216 "restored eeprom %d: uncompressed, length %d\n", 3217 it, length); 3218 break; 3219 case _CompressBlock: 3220 if (reference == 0) { 3221 } else { 3222 eep = ar9003_eeprom_struct_find_by_id(reference); 3223 if (eep == NULL) { 3224 ath_dbg(common, ATH_DBG_EEPROM, 3225 "can't find reference eeprom struct %d\n", 3226 reference); 3227 return -1; 3228 } 3229 memcpy(mptr, eep, mdata_size); 3230 } 3231 ath_dbg(common, ATH_DBG_EEPROM, 3232 "restore eeprom %d: block, reference %d, length %d\n", 3233 it, reference, length); 3234 ar9300_uncompress_block(ah, mptr, mdata_size, 3235 (u8 *) (word + COMP_HDR_LEN), length); 3236 break; 3237 default: 3238 ath_dbg(common, ATH_DBG_EEPROM, 3239 "unknown compression code %d\n", code); 3240 return -1; 3241 } 3242 return 0; 3243 } 3244 3245 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, 3246 int count); 3247 3248 static bool ar9300_check_header(void *data) 3249 { 3250 u32 *word = data; 3251 return !(*word == 0 || *word == ~0); 3252 } 3253 3254 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, 3255 int base_addr) 3256 { 3257 u8 header[4]; 3258 3259 if (!read(ah, base_addr, header, 4)) 3260 return false; 3261 3262 return ar9300_check_header(header); 3263 } 3264 3265 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, 3266 int mdata_size) 3267 { 3268 struct ath_common *common = ath9k_hw_common(ah); 3269 u16 *data = (u16 *) mptr; 3270 int i; 3271 3272 for (i = 0; i < mdata_size / 2; i++, data++) 3273 ath9k_hw_nvram_read(common, i, data); 3274 3275 return 0; 3276 } 3277 /* 3278 * Read the configuration data from the eeprom. 3279 * The data can be put in any specified memory buffer. 3280 * 3281 * Returns -1 on error. 3282 * Returns address of next memory location on success. 3283 */ 3284 static int ar9300_eeprom_restore_internal(struct ath_hw *ah, 3285 u8 *mptr, int mdata_size) 3286 { 3287 #define MDEFAULT 15 3288 #define MSTATE 100 3289 int cptr; 3290 u8 *word; 3291 int code; 3292 int reference, length, major, minor; 3293 int osize; 3294 int it; 3295 u16 checksum, mchecksum; 3296 struct ath_common *common = ath9k_hw_common(ah); 3297 eeprom_read_op read; 3298 3299 if (ath9k_hw_use_flash(ah)) 3300 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size); 3301 3302 word = kzalloc(2048, GFP_KERNEL); 3303 if (!word) 3304 return -ENOMEM; 3305 3306 memcpy(mptr, &ar9300_default, mdata_size); 3307 3308 read = ar9300_read_eeprom; 3309 if (AR_SREV_9485(ah)) 3310 cptr = AR9300_BASE_ADDR_4K; 3311 else if (AR_SREV_9330(ah)) 3312 cptr = AR9300_BASE_ADDR_512; 3313 else 3314 cptr = AR9300_BASE_ADDR; 3315 ath_dbg(common, ATH_DBG_EEPROM, 3316 "Trying EEPROM access at Address 0x%04x\n", cptr); 3317 if (ar9300_check_eeprom_header(ah, read, cptr)) 3318 goto found; 3319 3320 cptr = AR9300_BASE_ADDR_512; 3321 ath_dbg(common, ATH_DBG_EEPROM, 3322 "Trying EEPROM access at Address 0x%04x\n", cptr); 3323 if (ar9300_check_eeprom_header(ah, read, cptr)) 3324 goto found; 3325 3326 read = ar9300_read_otp; 3327 cptr = AR9300_BASE_ADDR; 3328 ath_dbg(common, ATH_DBG_EEPROM, 3329 "Trying OTP access at Address 0x%04x\n", cptr); 3330 if (ar9300_check_eeprom_header(ah, read, cptr)) 3331 goto found; 3332 3333 cptr = AR9300_BASE_ADDR_512; 3334 ath_dbg(common, ATH_DBG_EEPROM, 3335 "Trying OTP access at Address 0x%04x\n", cptr); 3336 if (ar9300_check_eeprom_header(ah, read, cptr)) 3337 goto found; 3338 3339 goto fail; 3340 3341 found: 3342 ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n"); 3343 3344 for (it = 0; it < MSTATE; it++) { 3345 if (!read(ah, cptr, word, COMP_HDR_LEN)) 3346 goto fail; 3347 3348 if (!ar9300_check_header(word)) 3349 break; 3350 3351 ar9300_comp_hdr_unpack(word, &code, &reference, 3352 &length, &major, &minor); 3353 ath_dbg(common, ATH_DBG_EEPROM, 3354 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n", 3355 cptr, code, reference, length, major, minor); 3356 if ((!AR_SREV_9485(ah) && length >= 1024) || 3357 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) { 3358 ath_dbg(common, ATH_DBG_EEPROM, 3359 "Skipping bad header\n"); 3360 cptr -= COMP_HDR_LEN; 3361 continue; 3362 } 3363 3364 osize = length; 3365 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); 3366 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); 3367 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]); 3368 ath_dbg(common, ATH_DBG_EEPROM, 3369 "checksum %x %x\n", checksum, mchecksum); 3370 if (checksum == mchecksum) { 3371 ar9300_compress_decision(ah, it, code, reference, mptr, 3372 word, length, mdata_size); 3373 } else { 3374 ath_dbg(common, ATH_DBG_EEPROM, 3375 "skipping block with bad checksum\n"); 3376 } 3377 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); 3378 } 3379 3380 kfree(word); 3381 return cptr; 3382 3383 fail: 3384 kfree(word); 3385 return -1; 3386 } 3387 3388 /* 3389 * Restore the configuration structure by reading the eeprom. 3390 * This function destroys any existing in-memory structure 3391 * content. 3392 */ 3393 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) 3394 { 3395 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; 3396 3397 if (ar9300_eeprom_restore_internal(ah, mptr, 3398 sizeof(struct ar9300_eeprom)) < 0) 3399 return false; 3400 3401 return true; 3402 } 3403 3404 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) 3405 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size, 3406 struct ar9300_modal_eep_header *modal_hdr) 3407 { 3408 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); 3409 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1])); 3410 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2])); 3411 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); 3412 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2)); 3413 PR_EEP("Ant. Gain", modal_hdr->antennaGain); 3414 PR_EEP("Switch Settle", modal_hdr->switchSettling); 3415 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]); 3416 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]); 3417 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]); 3418 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]); 3419 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]); 3420 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]); 3421 PR_EEP("Temp Slope", modal_hdr->tempSlope); 3422 PR_EEP("Volt Slope", modal_hdr->voltSlope); 3423 PR_EEP("spur Channels0", modal_hdr->spurChans[0]); 3424 PR_EEP("spur Channels1", modal_hdr->spurChans[1]); 3425 PR_EEP("spur Channels2", modal_hdr->spurChans[2]); 3426 PR_EEP("spur Channels3", modal_hdr->spurChans[3]); 3427 PR_EEP("spur Channels4", modal_hdr->spurChans[4]); 3428 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); 3429 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); 3430 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]); 3431 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); 3432 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); 3433 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); 3434 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); 3435 PR_EEP("txClip", modal_hdr->txClip); 3436 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); 3437 PR_EEP("Chain0 ob", modal_hdr->ob[0]); 3438 PR_EEP("Chain1 ob", modal_hdr->ob[1]); 3439 PR_EEP("Chain2 ob", modal_hdr->ob[2]); 3440 3441 PR_EEP("Chain0 db_stage2", modal_hdr->db_stage2[0]); 3442 PR_EEP("Chain1 db_stage2", modal_hdr->db_stage2[1]); 3443 PR_EEP("Chain2 db_stage2", modal_hdr->db_stage2[2]); 3444 PR_EEP("Chain0 db_stage3", modal_hdr->db_stage3[0]); 3445 PR_EEP("Chain1 db_stage3", modal_hdr->db_stage3[1]); 3446 PR_EEP("Chain2 db_stage3", modal_hdr->db_stage3[2]); 3447 PR_EEP("Chain0 db_stage4", modal_hdr->db_stage4[0]); 3448 PR_EEP("Chain1 db_stage4", modal_hdr->db_stage4[1]); 3449 PR_EEP("Chain2 db_stage4", modal_hdr->db_stage4[2]); 3450 3451 return len; 3452 } 3453 3454 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 3455 u8 *buf, u32 len, u32 size) 3456 { 3457 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3458 struct ar9300_base_eep_hdr *pBase; 3459 3460 if (!dump_base_hdr) { 3461 len += snprintf(buf + len, size - len, 3462 "%20s :\n", "2GHz modal Header"); 3463 len += ar9003_dump_modal_eeprom(buf, len, size, 3464 &eep->modalHeader2G); 3465 len += snprintf(buf + len, size - len, 3466 "%20s :\n", "5GHz modal Header"); 3467 len += ar9003_dump_modal_eeprom(buf, len, size, 3468 &eep->modalHeader5G); 3469 goto out; 3470 } 3471 3472 pBase = &eep->baseEepHeader; 3473 3474 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion); 3475 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); 3476 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); 3477 PR_EEP("TX Mask", (pBase->txrxMask >> 4)); 3478 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f)); 3479 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags & 3480 AR5416_OPFLAGS_11A)); 3481 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags & 3482 AR5416_OPFLAGS_11G)); 3483 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags & 3484 AR5416_OPFLAGS_N_2G_HT20)); 3485 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags & 3486 AR5416_OPFLAGS_N_2G_HT40)); 3487 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags & 3488 AR5416_OPFLAGS_N_5G_HT20)); 3489 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags & 3490 AR5416_OPFLAGS_N_5G_HT40)); 3491 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01)); 3492 PR_EEP("RF Silent", pBase->rfSilent); 3493 PR_EEP("BT option", pBase->blueToothOptions); 3494 PR_EEP("Device Cap", pBase->deviceCap); 3495 PR_EEP("Device Type", pBase->deviceType); 3496 PR_EEP("Power Table Offset", pBase->pwrTableOffset); 3497 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]); 3498 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]); 3499 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0))); 3500 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1))); 3501 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2))); 3502 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3))); 3503 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4))); 3504 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5))); 3505 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0))); 3506 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1); 3507 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio); 3508 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio); 3509 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio); 3510 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio); 3511 PR_EEP("Tx Gain", pBase->txrxgain >> 4); 3512 PR_EEP("Rx Gain", pBase->txrxgain & 0xf); 3513 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg)); 3514 3515 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", 3516 ah->eeprom.ar9300_eep.macAddr); 3517 out: 3518 if (len > size) 3519 len = size; 3520 3521 return len; 3522 } 3523 #else 3524 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, 3525 u8 *buf, u32 len, u32 size) 3526 { 3527 return 0; 3528 } 3529 #endif 3530 3531 /* XXX: review hardware docs */ 3532 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) 3533 { 3534 return ah->eeprom.ar9300_eep.eepromVersion; 3535 } 3536 3537 /* XXX: could be read from the eepromVersion, not sure yet */ 3538 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) 3539 { 3540 return 0; 3541 } 3542 3543 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz) 3544 { 3545 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3546 3547 if (is2ghz) 3548 return eep->modalHeader2G.xpaBiasLvl; 3549 else 3550 return eep->modalHeader5G.xpaBiasLvl; 3551 } 3552 3553 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) 3554 { 3555 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz); 3556 3557 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3558 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3559 else if (AR_SREV_9462(ah)) 3560 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3561 else { 3562 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3563 REG_RMW_FIELD(ah, AR_CH0_THERM, 3564 AR_CH0_THERM_XPABIASLVL_MSB, 3565 bias >> 2); 3566 REG_RMW_FIELD(ah, AR_CH0_THERM, 3567 AR_CH0_THERM_XPASHORT2GND, 1); 3568 } 3569 } 3570 3571 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz) 3572 { 3573 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3574 __le32 val; 3575 3576 if (is_2ghz) 3577 val = eep->modalHeader2G.switchcomspdt; 3578 else 3579 val = eep->modalHeader5G.switchcomspdt; 3580 return le32_to_cpu(val); 3581 } 3582 3583 3584 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) 3585 { 3586 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3587 __le32 val; 3588 3589 if (is2ghz) 3590 val = eep->modalHeader2G.antCtrlCommon; 3591 else 3592 val = eep->modalHeader5G.antCtrlCommon; 3593 return le32_to_cpu(val); 3594 } 3595 3596 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) 3597 { 3598 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3599 __le32 val; 3600 3601 if (is2ghz) 3602 val = eep->modalHeader2G.antCtrlCommon2; 3603 else 3604 val = eep->modalHeader5G.antCtrlCommon2; 3605 return le32_to_cpu(val); 3606 } 3607 3608 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, 3609 int chain, 3610 bool is2ghz) 3611 { 3612 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3613 __le16 val = 0; 3614 3615 if (chain >= 0 && chain < AR9300_MAX_CHAINS) { 3616 if (is2ghz) 3617 val = eep->modalHeader2G.antCtrlChain[chain]; 3618 else 3619 val = eep->modalHeader5G.antCtrlChain[chain]; 3620 } 3621 3622 return le16_to_cpu(val); 3623 } 3624 3625 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 3626 { 3627 int chain; 3628 u32 regval; 3629 u32 ant_div_ctl1; 3630 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = { 3631 AR_PHY_SWITCH_CHAIN_0, 3632 AR_PHY_SWITCH_CHAIN_1, 3633 AR_PHY_SWITCH_CHAIN_2, 3634 }; 3635 3636 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); 3637 3638 if (AR_SREV_9462(ah)) { 3639 if (AR_SREV_9462_10(ah)) { 3640 value &= ~AR_SWITCH_TABLE_COM_SPDT; 3641 value |= 0x00100000; 3642 } 3643 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3644 AR_SWITCH_TABLE_COM_AR9462_ALL, value); 3645 } else 3646 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3647 AR_SWITCH_TABLE_COM_ALL, value); 3648 3649 3650 /* 3651 * AR9462 defines new switch table for BT/WLAN, 3652 * here's new field name in XXX.ref for both 2G and 5G. 3653 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) 3654 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX 3655 * SWITCH_TABLE_COM_SPDT_WLAN_RX 3656 * 3657 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX 3658 * SWITCH_TABLE_COM_SPDT_WLAN_TX 3659 * 3660 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3661 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3662 */ 3663 if (AR_SREV_9462_20_OR_LATER(ah)) { 3664 value = ar9003_switch_com_spdt_get(ah, is2ghz); 3665 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, 3666 AR_SWITCH_TABLE_COM_SPDT_ALL, value); 3667 } 3668 3669 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); 3670 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); 3671 3672 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 3673 if ((ah->rxchainmask & BIT(chain)) || 3674 (ah->txchainmask & BIT(chain))) { 3675 value = ar9003_hw_ant_ctrl_chain_get(ah, chain, 3676 is2ghz); 3677 REG_RMW_FIELD(ah, switch_chain_reg[chain], 3678 AR_SWITCH_TABLE_ALL, value); 3679 } 3680 } 3681 3682 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 3683 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); 3684 /* 3685 * main_lnaconf, alt_lnaconf, main_tb, alt_tb 3686 * are the fields present 3687 */ 3688 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3689 regval &= (~AR_ANT_DIV_CTRL_ALL); 3690 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; 3691 /* enable_lnadiv */ 3692 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV); 3693 regval |= ((value >> 6) & 0x1) << 3694 AR_PHY_9485_ANT_DIV_LNADIV_S; 3695 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 3696 3697 /*enable fast_div */ 3698 regval = REG_READ(ah, AR_PHY_CCK_DETECT); 3699 regval &= (~AR_FAST_DIV_ENABLE); 3700 regval |= ((value >> 7) & 0x1) << 3701 AR_FAST_DIV_ENABLE_S; 3702 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); 3703 ant_div_ctl1 = 3704 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 3705 /* check whether antenna diversity is enabled */ 3706 if ((ant_div_ctl1 >> 0x6) == 0x3) { 3707 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); 3708 /* 3709 * clear bits 25-30 main_lnaconf, alt_lnaconf, 3710 * main_tb, alt_tb 3711 */ 3712 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF | 3713 AR_PHY_9485_ANT_DIV_ALT_LNACONF | 3714 AR_PHY_9485_ANT_DIV_ALT_GAINTB | 3715 AR_PHY_9485_ANT_DIV_MAIN_GAINTB)); 3716 /* by default use LNA1 for the main antenna */ 3717 regval |= (AR_PHY_9485_ANT_DIV_LNA1 << 3718 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S); 3719 regval |= (AR_PHY_9485_ANT_DIV_LNA2 << 3720 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S); 3721 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); 3722 } 3723 3724 3725 } 3726 3727 } 3728 3729 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) 3730 { 3731 int drive_strength; 3732 unsigned long reg; 3733 3734 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH); 3735 3736 if (!drive_strength) 3737 return; 3738 3739 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); 3740 reg &= ~0x00ffffc0; 3741 reg |= 0x5 << 21; 3742 reg |= 0x5 << 18; 3743 reg |= 0x5 << 15; 3744 reg |= 0x5 << 12; 3745 reg |= 0x5 << 9; 3746 reg |= 0x5 << 6; 3747 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); 3748 3749 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); 3750 reg &= ~0xffffffe0; 3751 reg |= 0x5 << 29; 3752 reg |= 0x5 << 26; 3753 reg |= 0x5 << 23; 3754 reg |= 0x5 << 20; 3755 reg |= 0x5 << 17; 3756 reg |= 0x5 << 14; 3757 reg |= 0x5 << 11; 3758 reg |= 0x5 << 8; 3759 reg |= 0x5 << 5; 3760 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); 3761 3762 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); 3763 reg &= ~0xff800000; 3764 reg |= 0x5 << 29; 3765 reg |= 0x5 << 26; 3766 reg |= 0x5 << 23; 3767 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); 3768 } 3769 3770 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, 3771 struct ath9k_channel *chan) 3772 { 3773 int f[3], t[3]; 3774 u16 value; 3775 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3776 3777 if (chain >= 0 && chain < 3) { 3778 if (IS_CHAN_2GHZ(chan)) 3779 return eep->modalHeader2G.xatten1DB[chain]; 3780 else if (eep->base_ext2.xatten1DBLow[chain] != 0) { 3781 t[0] = eep->base_ext2.xatten1DBLow[chain]; 3782 f[0] = 5180; 3783 t[1] = eep->modalHeader5G.xatten1DB[chain]; 3784 f[1] = 5500; 3785 t[2] = eep->base_ext2.xatten1DBHigh[chain]; 3786 f[2] = 5785; 3787 value = ar9003_hw_power_interpolate((s32) chan->channel, 3788 f, t, 3); 3789 return value; 3790 } else 3791 return eep->modalHeader5G.xatten1DB[chain]; 3792 } 3793 3794 return 0; 3795 } 3796 3797 3798 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, 3799 struct ath9k_channel *chan) 3800 { 3801 int f[3], t[3]; 3802 u16 value; 3803 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3804 3805 if (chain >= 0 && chain < 3) { 3806 if (IS_CHAN_2GHZ(chan)) 3807 return eep->modalHeader2G.xatten1Margin[chain]; 3808 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { 3809 t[0] = eep->base_ext2.xatten1MarginLow[chain]; 3810 f[0] = 5180; 3811 t[1] = eep->modalHeader5G.xatten1Margin[chain]; 3812 f[1] = 5500; 3813 t[2] = eep->base_ext2.xatten1MarginHigh[chain]; 3814 f[2] = 5785; 3815 value = ar9003_hw_power_interpolate((s32) chan->channel, 3816 f, t, 3); 3817 return value; 3818 } else 3819 return eep->modalHeader5G.xatten1Margin[chain]; 3820 } 3821 3822 return 0; 3823 } 3824 3825 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan) 3826 { 3827 int i; 3828 u16 value; 3829 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0, 3830 AR_PHY_EXT_ATTEN_CTL_1, 3831 AR_PHY_EXT_ATTEN_CTL_2, 3832 }; 3833 3834 /* Test value. if 0 then attenuation is unused. Don't load anything. */ 3835 for (i = 0; i < 3; i++) { 3836 if (ah->txchainmask & BIT(i)) { 3837 value = ar9003_hw_atten_chain_get(ah, i, chan); 3838 REG_RMW_FIELD(ah, ext_atten_reg[i], 3839 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value); 3840 3841 value = ar9003_hw_atten_chain_get_margin(ah, i, chan); 3842 REG_RMW_FIELD(ah, ext_atten_reg[i], 3843 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, 3844 value); 3845 } 3846 } 3847 } 3848 3849 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set) 3850 { 3851 int timeout = 100; 3852 3853 while (pmu_set != REG_READ(ah, pmu_reg)) { 3854 if (timeout-- == 0) 3855 return false; 3856 REG_WRITE(ah, pmu_reg, pmu_set); 3857 udelay(10); 3858 } 3859 3860 return true; 3861 } 3862 3863 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 3864 { 3865 int internal_regulator = 3866 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); 3867 u32 reg_val; 3868 3869 if (internal_regulator) { 3870 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 3871 int reg_pmu_set; 3872 3873 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; 3874 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3875 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3876 return; 3877 3878 if (AR_SREV_9330(ah)) { 3879 if (ah->is_clk_25mhz) { 3880 reg_pmu_set = (3 << 1) | (8 << 4) | 3881 (3 << 8) | (1 << 14) | 3882 (6 << 17) | (1 << 20) | 3883 (3 << 24); 3884 } else { 3885 reg_pmu_set = (4 << 1) | (7 << 4) | 3886 (3 << 8) | (1 << 14) | 3887 (6 << 17) | (1 << 20) | 3888 (3 << 24); 3889 } 3890 } else { 3891 reg_pmu_set = (5 << 1) | (7 << 4) | 3892 (2 << 8) | (2 << 14) | 3893 (6 << 17) | (1 << 20) | 3894 (3 << 24) | (1 << 28); 3895 } 3896 3897 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); 3898 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set)) 3899 return; 3900 3901 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000) 3902 | (4 << 26); 3903 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3904 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3905 return; 3906 3907 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000) 3908 | (1 << 21); 3909 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3910 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3911 return; 3912 } else if (AR_SREV_9462(ah)) { 3913 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); 3914 REG_WRITE(ah, AR_PHY_PMU1, reg_val); 3915 } else { 3916 /* Internal regulator is ON. Write swreg register. */ 3917 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); 3918 REG_WRITE(ah, AR_RTC_REG_CONTROL1, 3919 REG_READ(ah, AR_RTC_REG_CONTROL1) & 3920 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM)); 3921 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); 3922 /* Set REG_CONTROL1.SWREG_PROGRAM */ 3923 REG_WRITE(ah, AR_RTC_REG_CONTROL1, 3924 REG_READ(ah, 3925 AR_RTC_REG_CONTROL1) | 3926 AR_RTC_REG_CONTROL1_SWREG_PROGRAM); 3927 } 3928 } else { 3929 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { 3930 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); 3931 while (REG_READ_FIELD(ah, AR_PHY_PMU2, 3932 AR_PHY_PMU2_PGM)) 3933 udelay(10); 3934 3935 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); 3936 while (!REG_READ_FIELD(ah, AR_PHY_PMU1, 3937 AR_PHY_PMU1_PWD)) 3938 udelay(10); 3939 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1); 3940 while (!REG_READ_FIELD(ah, AR_PHY_PMU2, 3941 AR_PHY_PMU2_PGM)) 3942 udelay(10); 3943 } else if (AR_SREV_9462(ah)) 3944 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); 3945 else { 3946 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | 3947 AR_RTC_FORCE_SWREG_PRD; 3948 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val); 3949 } 3950 } 3951 3952 } 3953 3954 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) 3955 { 3956 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 3957 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; 3958 3959 if (eep->baseEepHeader.featureEnable & 0x40) { 3960 tuning_caps_param &= 0x7f; 3961 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, 3962 tuning_caps_param); 3963 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC, 3964 tuning_caps_param); 3965 } 3966 } 3967 3968 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, 3969 struct ath9k_channel *chan) 3970 { 3971 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan)); 3972 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan)); 3973 ar9003_hw_drive_strength_apply(ah); 3974 ar9003_hw_atten_apply(ah, chan); 3975 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah)) 3976 ar9003_hw_internal_regulator_apply(ah); 3977 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3978 ar9003_hw_apply_tuning_caps(ah); 3979 } 3980 3981 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, 3982 struct ath9k_channel *chan) 3983 { 3984 } 3985 3986 /* 3987 * Returns the interpolated y value corresponding to the specified x value 3988 * from the np ordered pairs of data (px,py). 3989 * The pairs do not have to be in any order. 3990 * If the specified x value is less than any of the px, 3991 * the returned y value is equal to the py for the lowest px. 3992 * If the specified x value is greater than any of the px, 3993 * the returned y value is equal to the py for the highest px. 3994 */ 3995 static int ar9003_hw_power_interpolate(int32_t x, 3996 int32_t *px, int32_t *py, u_int16_t np) 3997 { 3998 int ip = 0; 3999 int lx = 0, ly = 0, lhave = 0; 4000 int hx = 0, hy = 0, hhave = 0; 4001 int dx = 0; 4002 int y = 0; 4003 4004 lhave = 0; 4005 hhave = 0; 4006 4007 /* identify best lower and higher x calibration measurement */ 4008 for (ip = 0; ip < np; ip++) { 4009 dx = x - px[ip]; 4010 4011 /* this measurement is higher than our desired x */ 4012 if (dx <= 0) { 4013 if (!hhave || dx > (x - hx)) { 4014 /* new best higher x measurement */ 4015 hx = px[ip]; 4016 hy = py[ip]; 4017 hhave = 1; 4018 } 4019 } 4020 /* this measurement is lower than our desired x */ 4021 if (dx >= 0) { 4022 if (!lhave || dx < (x - lx)) { 4023 /* new best lower x measurement */ 4024 lx = px[ip]; 4025 ly = py[ip]; 4026 lhave = 1; 4027 } 4028 } 4029 } 4030 4031 /* the low x is good */ 4032 if (lhave) { 4033 /* so is the high x */ 4034 if (hhave) { 4035 /* they're the same, so just pick one */ 4036 if (hx == lx) 4037 y = ly; 4038 else /* interpolate */ 4039 y = interpolate(x, lx, hx, ly, hy); 4040 } else /* only low is good, use it */ 4041 y = ly; 4042 } else if (hhave) /* only high is good, use it */ 4043 y = hy; 4044 else /* nothing is good,this should never happen unless np=0, ???? */ 4045 y = -(1 << 30); 4046 return y; 4047 } 4048 4049 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, 4050 u16 rateIndex, u16 freq, bool is2GHz) 4051 { 4052 u16 numPiers, i; 4053 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4054 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4055 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4056 struct cal_tgt_pow_legacy *pEepromTargetPwr; 4057 u8 *pFreqBin; 4058 4059 if (is2GHz) { 4060 numPiers = AR9300_NUM_2G_20_TARGET_POWERS; 4061 pEepromTargetPwr = eep->calTargetPower2G; 4062 pFreqBin = eep->calTarget_freqbin_2G; 4063 } else { 4064 numPiers = AR9300_NUM_5G_20_TARGET_POWERS; 4065 pEepromTargetPwr = eep->calTargetPower5G; 4066 pFreqBin = eep->calTarget_freqbin_5G; 4067 } 4068 4069 /* 4070 * create array of channels and targetpower from 4071 * targetpower piers stored on eeprom 4072 */ 4073 for (i = 0; i < numPiers; i++) { 4074 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); 4075 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4076 } 4077 4078 /* interpolate to get target power for given frequency */ 4079 return (u8) ar9003_hw_power_interpolate((s32) freq, 4080 freqArray, 4081 targetPowerArray, numPiers); 4082 } 4083 4084 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, 4085 u16 rateIndex, 4086 u16 freq, bool is2GHz) 4087 { 4088 u16 numPiers, i; 4089 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4090 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; 4091 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4092 struct cal_tgt_pow_ht *pEepromTargetPwr; 4093 u8 *pFreqBin; 4094 4095 if (is2GHz) { 4096 numPiers = AR9300_NUM_2G_20_TARGET_POWERS; 4097 pEepromTargetPwr = eep->calTargetPower2GHT20; 4098 pFreqBin = eep->calTarget_freqbin_2GHT20; 4099 } else { 4100 numPiers = AR9300_NUM_5G_20_TARGET_POWERS; 4101 pEepromTargetPwr = eep->calTargetPower5GHT20; 4102 pFreqBin = eep->calTarget_freqbin_5GHT20; 4103 } 4104 4105 /* 4106 * create array of channels and targetpower 4107 * from targetpower piers stored on eeprom 4108 */ 4109 for (i = 0; i < numPiers; i++) { 4110 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); 4111 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4112 } 4113 4114 /* interpolate to get target power for given frequency */ 4115 return (u8) ar9003_hw_power_interpolate((s32) freq, 4116 freqArray, 4117 targetPowerArray, numPiers); 4118 } 4119 4120 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, 4121 u16 rateIndex, 4122 u16 freq, bool is2GHz) 4123 { 4124 u16 numPiers, i; 4125 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS]; 4126 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS]; 4127 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4128 struct cal_tgt_pow_ht *pEepromTargetPwr; 4129 u8 *pFreqBin; 4130 4131 if (is2GHz) { 4132 numPiers = AR9300_NUM_2G_40_TARGET_POWERS; 4133 pEepromTargetPwr = eep->calTargetPower2GHT40; 4134 pFreqBin = eep->calTarget_freqbin_2GHT40; 4135 } else { 4136 numPiers = AR9300_NUM_5G_40_TARGET_POWERS; 4137 pEepromTargetPwr = eep->calTargetPower5GHT40; 4138 pFreqBin = eep->calTarget_freqbin_5GHT40; 4139 } 4140 4141 /* 4142 * create array of channels and targetpower from 4143 * targetpower piers stored on eeprom 4144 */ 4145 for (i = 0; i < numPiers; i++) { 4146 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz); 4147 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4148 } 4149 4150 /* interpolate to get target power for given frequency */ 4151 return (u8) ar9003_hw_power_interpolate((s32) freq, 4152 freqArray, 4153 targetPowerArray, numPiers); 4154 } 4155 4156 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, 4157 u16 rateIndex, u16 freq) 4158 { 4159 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i; 4160 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; 4161 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; 4162 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4163 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; 4164 u8 *pFreqBin = eep->calTarget_freqbin_Cck; 4165 4166 /* 4167 * create array of channels and targetpower from 4168 * targetpower piers stored on eeprom 4169 */ 4170 for (i = 0; i < numPiers; i++) { 4171 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1); 4172 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; 4173 } 4174 4175 /* interpolate to get target power for given frequency */ 4176 return (u8) ar9003_hw_power_interpolate((s32) freq, 4177 freqArray, 4178 targetPowerArray, numPiers); 4179 } 4180 4181 /* Set tx power registers to array of values passed in */ 4182 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray) 4183 { 4184 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 4185 /* make sure forced gain is not set */ 4186 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); 4187 4188 /* Write the OFDM power per rate set */ 4189 4190 /* 6 (LSB), 9, 12, 18 (MSB) */ 4191 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0), 4192 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | 4193 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) | 4194 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | 4195 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); 4196 4197 /* 24 (LSB), 36, 48, 54 (MSB) */ 4198 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), 4199 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) | 4200 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) | 4201 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) | 4202 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0)); 4203 4204 /* Write the CCK power per rate set */ 4205 4206 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 4207 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), 4208 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) | 4209 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | 4210 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */ 4211 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)); 4212 4213 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 4214 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), 4215 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) | 4216 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) | 4217 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) | 4218 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) 4219 ); 4220 4221 /* Write the power for duplicated frames - HT40 */ 4222 4223 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */ 4224 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), 4225 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) | 4226 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) | 4227 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) | 4228 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0) 4229 ); 4230 4231 /* Write the HT20 power per rate set */ 4232 4233 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 4234 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), 4235 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) | 4236 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) | 4237 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) | 4238 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0) 4239 ); 4240 4241 /* 6 (LSB), 7, 12, 13 (MSB) */ 4242 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), 4243 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) | 4244 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) | 4245 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) | 4246 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0) 4247 ); 4248 4249 /* 14 (LSB), 15, 20, 21 */ 4250 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9), 4251 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) | 4252 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) | 4253 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) | 4254 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0) 4255 ); 4256 4257 /* Mixed HT20 and HT40 rates */ 4258 4259 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 4260 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), 4261 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) | 4262 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) | 4263 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) | 4264 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0) 4265 ); 4266 4267 /* 4268 * Write the HT40 power per rate set 4269 * correct PAR difference between HT40 and HT20/LEGACY 4270 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) 4271 */ 4272 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), 4273 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) | 4274 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) | 4275 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) | 4276 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0) 4277 ); 4278 4279 /* 6 (LSB), 7, 12, 13 (MSB) */ 4280 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), 4281 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) | 4282 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) | 4283 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) | 4284 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0) 4285 ); 4286 4287 /* 14 (LSB), 15, 20, 21 */ 4288 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), 4289 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) | 4290 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) | 4291 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) | 4292 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0) 4293 ); 4294 4295 return 0; 4296 #undef POW_SM 4297 } 4298 4299 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, 4300 u8 *targetPowerValT2) 4301 { 4302 /* XXX: hard code for now, need to get from eeprom struct */ 4303 u8 ht40PowerIncForPdadc = 0; 4304 bool is2GHz = false; 4305 unsigned int i = 0; 4306 struct ath_common *common = ath9k_hw_common(ah); 4307 4308 if (freq < 4000) 4309 is2GHz = true; 4310 4311 targetPowerValT2[ALL_TARGET_LEGACY_6_24] = 4312 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq, 4313 is2GHz); 4314 targetPowerValT2[ALL_TARGET_LEGACY_36] = 4315 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq, 4316 is2GHz); 4317 targetPowerValT2[ALL_TARGET_LEGACY_48] = 4318 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq, 4319 is2GHz); 4320 targetPowerValT2[ALL_TARGET_LEGACY_54] = 4321 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq, 4322 is2GHz); 4323 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] = 4324 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L, 4325 freq); 4326 targetPowerValT2[ALL_TARGET_LEGACY_5S] = 4327 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq); 4328 targetPowerValT2[ALL_TARGET_LEGACY_11L] = 4329 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq); 4330 targetPowerValT2[ALL_TARGET_LEGACY_11S] = 4331 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq); 4332 targetPowerValT2[ALL_TARGET_HT20_0_8_16] = 4333 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, 4334 is2GHz); 4335 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] = 4336 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, 4337 freq, is2GHz); 4338 targetPowerValT2[ALL_TARGET_HT20_4] = 4339 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq, 4340 is2GHz); 4341 targetPowerValT2[ALL_TARGET_HT20_5] = 4342 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq, 4343 is2GHz); 4344 targetPowerValT2[ALL_TARGET_HT20_6] = 4345 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq, 4346 is2GHz); 4347 targetPowerValT2[ALL_TARGET_HT20_7] = 4348 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq, 4349 is2GHz); 4350 targetPowerValT2[ALL_TARGET_HT20_12] = 4351 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq, 4352 is2GHz); 4353 targetPowerValT2[ALL_TARGET_HT20_13] = 4354 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq, 4355 is2GHz); 4356 targetPowerValT2[ALL_TARGET_HT20_14] = 4357 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq, 4358 is2GHz); 4359 targetPowerValT2[ALL_TARGET_HT20_15] = 4360 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq, 4361 is2GHz); 4362 targetPowerValT2[ALL_TARGET_HT20_20] = 4363 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq, 4364 is2GHz); 4365 targetPowerValT2[ALL_TARGET_HT20_21] = 4366 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq, 4367 is2GHz); 4368 targetPowerValT2[ALL_TARGET_HT20_22] = 4369 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq, 4370 is2GHz); 4371 targetPowerValT2[ALL_TARGET_HT20_23] = 4372 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq, 4373 is2GHz); 4374 targetPowerValT2[ALL_TARGET_HT40_0_8_16] = 4375 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, 4376 is2GHz) + ht40PowerIncForPdadc; 4377 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] = 4378 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, 4379 freq, 4380 is2GHz) + ht40PowerIncForPdadc; 4381 targetPowerValT2[ALL_TARGET_HT40_4] = 4382 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq, 4383 is2GHz) + ht40PowerIncForPdadc; 4384 targetPowerValT2[ALL_TARGET_HT40_5] = 4385 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq, 4386 is2GHz) + ht40PowerIncForPdadc; 4387 targetPowerValT2[ALL_TARGET_HT40_6] = 4388 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq, 4389 is2GHz) + ht40PowerIncForPdadc; 4390 targetPowerValT2[ALL_TARGET_HT40_7] = 4391 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq, 4392 is2GHz) + ht40PowerIncForPdadc; 4393 targetPowerValT2[ALL_TARGET_HT40_12] = 4394 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq, 4395 is2GHz) + ht40PowerIncForPdadc; 4396 targetPowerValT2[ALL_TARGET_HT40_13] = 4397 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq, 4398 is2GHz) + ht40PowerIncForPdadc; 4399 targetPowerValT2[ALL_TARGET_HT40_14] = 4400 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq, 4401 is2GHz) + ht40PowerIncForPdadc; 4402 targetPowerValT2[ALL_TARGET_HT40_15] = 4403 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq, 4404 is2GHz) + ht40PowerIncForPdadc; 4405 targetPowerValT2[ALL_TARGET_HT40_20] = 4406 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq, 4407 is2GHz) + ht40PowerIncForPdadc; 4408 targetPowerValT2[ALL_TARGET_HT40_21] = 4409 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq, 4410 is2GHz) + ht40PowerIncForPdadc; 4411 targetPowerValT2[ALL_TARGET_HT40_22] = 4412 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq, 4413 is2GHz) + ht40PowerIncForPdadc; 4414 targetPowerValT2[ALL_TARGET_HT40_23] = 4415 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, 4416 is2GHz) + ht40PowerIncForPdadc; 4417 4418 for (i = 0; i < ar9300RateSize; i++) { 4419 ath_dbg(common, ATH_DBG_EEPROM, 4420 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); 4421 } 4422 } 4423 4424 static int ar9003_hw_cal_pier_get(struct ath_hw *ah, 4425 int mode, 4426 int ipier, 4427 int ichain, 4428 int *pfrequency, 4429 int *pcorrection, 4430 int *ptemperature, int *pvoltage) 4431 { 4432 u8 *pCalPier; 4433 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct; 4434 int is2GHz; 4435 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4436 struct ath_common *common = ath9k_hw_common(ah); 4437 4438 if (ichain >= AR9300_MAX_CHAINS) { 4439 ath_dbg(common, ATH_DBG_EEPROM, 4440 "Invalid chain index, must be less than %d\n", 4441 AR9300_MAX_CHAINS); 4442 return -1; 4443 } 4444 4445 if (mode) { /* 5GHz */ 4446 if (ipier >= AR9300_NUM_5G_CAL_PIERS) { 4447 ath_dbg(common, ATH_DBG_EEPROM, 4448 "Invalid 5GHz cal pier index, must be less than %d\n", 4449 AR9300_NUM_5G_CAL_PIERS); 4450 return -1; 4451 } 4452 pCalPier = &(eep->calFreqPier5G[ipier]); 4453 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); 4454 is2GHz = 0; 4455 } else { 4456 if (ipier >= AR9300_NUM_2G_CAL_PIERS) { 4457 ath_dbg(common, ATH_DBG_EEPROM, 4458 "Invalid 2GHz cal pier index, must be less than %d\n", 4459 AR9300_NUM_2G_CAL_PIERS); 4460 return -1; 4461 } 4462 4463 pCalPier = &(eep->calFreqPier2G[ipier]); 4464 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); 4465 is2GHz = 1; 4466 } 4467 4468 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz); 4469 *pcorrection = pCalPierStruct->refPower; 4470 *ptemperature = pCalPierStruct->tempMeas; 4471 *pvoltage = pCalPierStruct->voltMeas; 4472 4473 return 0; 4474 } 4475 4476 static int ar9003_hw_power_control_override(struct ath_hw *ah, 4477 int frequency, 4478 int *correction, 4479 int *voltage, int *temperature) 4480 { 4481 int tempSlope = 0; 4482 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4483 int f[3], t[3]; 4484 4485 REG_RMW(ah, AR_PHY_TPC_11_B0, 4486 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4487 AR_PHY_TPC_OLPC_GAIN_DELTA); 4488 if (ah->caps.tx_chainmask & BIT(1)) 4489 REG_RMW(ah, AR_PHY_TPC_11_B1, 4490 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4491 AR_PHY_TPC_OLPC_GAIN_DELTA); 4492 if (ah->caps.tx_chainmask & BIT(2)) 4493 REG_RMW(ah, AR_PHY_TPC_11_B2, 4494 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4495 AR_PHY_TPC_OLPC_GAIN_DELTA); 4496 4497 /* enable open loop power control on chip */ 4498 REG_RMW(ah, AR_PHY_TPC_6_B0, 4499 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4500 AR_PHY_TPC_6_ERROR_EST_MODE); 4501 if (ah->caps.tx_chainmask & BIT(1)) 4502 REG_RMW(ah, AR_PHY_TPC_6_B1, 4503 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4504 AR_PHY_TPC_6_ERROR_EST_MODE); 4505 if (ah->caps.tx_chainmask & BIT(2)) 4506 REG_RMW(ah, AR_PHY_TPC_6_B2, 4507 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4508 AR_PHY_TPC_6_ERROR_EST_MODE); 4509 4510 /* 4511 * enable temperature compensation 4512 * Need to use register names 4513 */ 4514 if (frequency < 4000) 4515 tempSlope = eep->modalHeader2G.tempSlope; 4516 else if (eep->base_ext2.tempSlopeLow != 0) { 4517 t[0] = eep->base_ext2.tempSlopeLow; 4518 f[0] = 5180; 4519 t[1] = eep->modalHeader5G.tempSlope; 4520 f[1] = 5500; 4521 t[2] = eep->base_ext2.tempSlopeHigh; 4522 f[2] = 5785; 4523 tempSlope = ar9003_hw_power_interpolate((s32) frequency, 4524 f, t, 3); 4525 } else 4526 tempSlope = eep->modalHeader5G.tempSlope; 4527 4528 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); 4529 4530 if (AR_SREV_9462_20(ah)) 4531 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, 4532 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope); 4533 4534 4535 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, 4536 temperature[0]); 4537 4538 return 0; 4539 } 4540 4541 /* Apply the recorded correction values. */ 4542 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) 4543 { 4544 int ichain, ipier, npier; 4545 int mode; 4546 int lfrequency[AR9300_MAX_CHAINS], 4547 lcorrection[AR9300_MAX_CHAINS], 4548 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS]; 4549 int hfrequency[AR9300_MAX_CHAINS], 4550 hcorrection[AR9300_MAX_CHAINS], 4551 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS]; 4552 int fdiff; 4553 int correction[AR9300_MAX_CHAINS], 4554 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS]; 4555 int pfrequency, pcorrection, ptemperature, pvoltage; 4556 struct ath_common *common = ath9k_hw_common(ah); 4557 4558 mode = (frequency >= 4000); 4559 if (mode) 4560 npier = AR9300_NUM_5G_CAL_PIERS; 4561 else 4562 npier = AR9300_NUM_2G_CAL_PIERS; 4563 4564 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { 4565 lfrequency[ichain] = 0; 4566 hfrequency[ichain] = 100000; 4567 } 4568 /* identify best lower and higher frequency calibration measurement */ 4569 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { 4570 for (ipier = 0; ipier < npier; ipier++) { 4571 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain, 4572 &pfrequency, &pcorrection, 4573 &ptemperature, &pvoltage)) { 4574 fdiff = frequency - pfrequency; 4575 4576 /* 4577 * this measurement is higher than 4578 * our desired frequency 4579 */ 4580 if (fdiff <= 0) { 4581 if (hfrequency[ichain] <= 0 || 4582 hfrequency[ichain] >= 100000 || 4583 fdiff > 4584 (frequency - hfrequency[ichain])) { 4585 /* 4586 * new best higher 4587 * frequency measurement 4588 */ 4589 hfrequency[ichain] = pfrequency; 4590 hcorrection[ichain] = 4591 pcorrection; 4592 htemperature[ichain] = 4593 ptemperature; 4594 hvoltage[ichain] = pvoltage; 4595 } 4596 } 4597 if (fdiff >= 0) { 4598 if (lfrequency[ichain] <= 0 4599 || fdiff < 4600 (frequency - lfrequency[ichain])) { 4601 /* 4602 * new best lower 4603 * frequency measurement 4604 */ 4605 lfrequency[ichain] = pfrequency; 4606 lcorrection[ichain] = 4607 pcorrection; 4608 ltemperature[ichain] = 4609 ptemperature; 4610 lvoltage[ichain] = pvoltage; 4611 } 4612 } 4613 } 4614 } 4615 } 4616 4617 /* interpolate */ 4618 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { 4619 ath_dbg(common, ATH_DBG_EEPROM, 4620 "ch=%d f=%d low=%d %d h=%d %d\n", 4621 ichain, frequency, lfrequency[ichain], 4622 lcorrection[ichain], hfrequency[ichain], 4623 hcorrection[ichain]); 4624 /* they're the same, so just pick one */ 4625 if (hfrequency[ichain] == lfrequency[ichain]) { 4626 correction[ichain] = lcorrection[ichain]; 4627 voltage[ichain] = lvoltage[ichain]; 4628 temperature[ichain] = ltemperature[ichain]; 4629 } 4630 /* the low frequency is good */ 4631 else if (frequency - lfrequency[ichain] < 1000) { 4632 /* so is the high frequency, interpolate */ 4633 if (hfrequency[ichain] - frequency < 1000) { 4634 4635 correction[ichain] = interpolate(frequency, 4636 lfrequency[ichain], 4637 hfrequency[ichain], 4638 lcorrection[ichain], 4639 hcorrection[ichain]); 4640 4641 temperature[ichain] = interpolate(frequency, 4642 lfrequency[ichain], 4643 hfrequency[ichain], 4644 ltemperature[ichain], 4645 htemperature[ichain]); 4646 4647 voltage[ichain] = interpolate(frequency, 4648 lfrequency[ichain], 4649 hfrequency[ichain], 4650 lvoltage[ichain], 4651 hvoltage[ichain]); 4652 } 4653 /* only low is good, use it */ 4654 else { 4655 correction[ichain] = lcorrection[ichain]; 4656 temperature[ichain] = ltemperature[ichain]; 4657 voltage[ichain] = lvoltage[ichain]; 4658 } 4659 } 4660 /* only high is good, use it */ 4661 else if (hfrequency[ichain] - frequency < 1000) { 4662 correction[ichain] = hcorrection[ichain]; 4663 temperature[ichain] = htemperature[ichain]; 4664 voltage[ichain] = hvoltage[ichain]; 4665 } else { /* nothing is good, presume 0???? */ 4666 correction[ichain] = 0; 4667 temperature[ichain] = 0; 4668 voltage[ichain] = 0; 4669 } 4670 } 4671 4672 ar9003_hw_power_control_override(ah, frequency, correction, voltage, 4673 temperature); 4674 4675 ath_dbg(common, ATH_DBG_EEPROM, 4676 "for frequency=%d, calibration correction = %d %d %d\n", 4677 frequency, correction[0], correction[1], correction[2]); 4678 4679 return 0; 4680 } 4681 4682 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, 4683 int idx, 4684 int edge, 4685 bool is2GHz) 4686 { 4687 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; 4688 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; 4689 4690 if (is2GHz) 4691 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]); 4692 else 4693 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]); 4694 } 4695 4696 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, 4697 int idx, 4698 unsigned int edge, 4699 u16 freq, 4700 bool is2GHz) 4701 { 4702 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; 4703 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; 4704 4705 u8 *ctl_freqbin = is2GHz ? 4706 &eep->ctl_freqbin_2G[idx][0] : 4707 &eep->ctl_freqbin_5G[idx][0]; 4708 4709 if (is2GHz) { 4710 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && 4711 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1])) 4712 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]); 4713 } else { 4714 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && 4715 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1])) 4716 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); 4717 } 4718 4719 return MAX_RATE_POWER; 4720 } 4721 4722 /* 4723 * Find the maximum conformance test limit for the given channel and CTL info 4724 */ 4725 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, 4726 u16 freq, int idx, bool is2GHz) 4727 { 4728 u16 twiceMaxEdgePower = MAX_RATE_POWER; 4729 u8 *ctl_freqbin = is2GHz ? 4730 &eep->ctl_freqbin_2G[idx][0] : 4731 &eep->ctl_freqbin_5G[idx][0]; 4732 u16 num_edges = is2GHz ? 4733 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G; 4734 unsigned int edge; 4735 4736 /* Get the edge power */ 4737 for (edge = 0; 4738 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED); 4739 edge++) { 4740 /* 4741 * If there's an exact channel match or an inband flag set 4742 * on the lower channel use the given rdEdgePower 4743 */ 4744 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) { 4745 twiceMaxEdgePower = 4746 ar9003_hw_get_direct_edge_power(eep, idx, 4747 edge, is2GHz); 4748 break; 4749 } else if ((edge > 0) && 4750 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge], 4751 is2GHz))) { 4752 twiceMaxEdgePower = 4753 ar9003_hw_get_indirect_edge_power(eep, idx, 4754 edge, freq, 4755 is2GHz); 4756 /* 4757 * Leave loop - no more affecting edges possible in 4758 * this monotonic increasing list 4759 */ 4760 break; 4761 } 4762 } 4763 return twiceMaxEdgePower; 4764 } 4765 4766 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, 4767 struct ath9k_channel *chan, 4768 u8 *pPwrArray, u16 cfgCtl, 4769 u8 antenna_reduction, 4770 u16 powerLimit) 4771 { 4772 struct ath_common *common = ath9k_hw_common(ah); 4773 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; 4774 u16 twiceMaxEdgePower = MAX_RATE_POWER; 4775 int i; 4776 u16 scaledPower = 0, minCtlPower; 4777 static const u16 ctlModesFor11a[] = { 4778 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 4779 }; 4780 static const u16 ctlModesFor11g[] = { 4781 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, 4782 CTL_11G_EXT, CTL_2GHT40 4783 }; 4784 u16 numCtlModes; 4785 const u16 *pCtlMode; 4786 u16 ctlMode, freq; 4787 struct chan_centers centers; 4788 u8 *ctlIndex; 4789 u8 ctlNum; 4790 u16 twiceMinEdgePower; 4791 bool is2ghz = IS_CHAN_2GHZ(chan); 4792 4793 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 4794 scaledPower = powerLimit - antenna_reduction; 4795 4796 /* 4797 * Reduce scaled Power by number of chains active to get 4798 * to per chain tx power level 4799 */ 4800 switch (ar5416_get_ntxchains(ah->txchainmask)) { 4801 case 1: 4802 break; 4803 case 2: 4804 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN) 4805 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; 4806 else 4807 scaledPower = 0; 4808 break; 4809 case 3: 4810 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN) 4811 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; 4812 else 4813 scaledPower = 0; 4814 break; 4815 } 4816 4817 scaledPower = max((u16)0, scaledPower); 4818 4819 /* 4820 * Get target powers from EEPROM - our baseline for TX Power 4821 */ 4822 if (is2ghz) { 4823 /* Setup for CTL modes */ 4824 /* CTL_11B, CTL_11G, CTL_2GHT20 */ 4825 numCtlModes = 4826 ARRAY_SIZE(ctlModesFor11g) - 4827 SUB_NUM_CTL_MODES_AT_2G_40; 4828 pCtlMode = ctlModesFor11g; 4829 if (IS_CHAN_HT40(chan)) 4830 /* All 2G CTL's */ 4831 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 4832 } else { 4833 /* Setup for CTL modes */ 4834 /* CTL_11A, CTL_5GHT20 */ 4835 numCtlModes = ARRAY_SIZE(ctlModesFor11a) - 4836 SUB_NUM_CTL_MODES_AT_5G_40; 4837 pCtlMode = ctlModesFor11a; 4838 if (IS_CHAN_HT40(chan)) 4839 /* All 5G CTL's */ 4840 numCtlModes = ARRAY_SIZE(ctlModesFor11a); 4841 } 4842 4843 /* 4844 * For MIMO, need to apply regulatory caps individually across 4845 * dynamically running modes: CCK, OFDM, HT20, HT40 4846 * 4847 * The outer loop walks through each possible applicable runtime mode. 4848 * The inner loop walks through each ctlIndex entry in EEPROM. 4849 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 4850 */ 4851 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 4852 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 4853 (pCtlMode[ctlMode] == CTL_2GHT40); 4854 if (isHt40CtlMode) 4855 freq = centers.synth_center; 4856 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 4857 freq = centers.ext_center; 4858 else 4859 freq = centers.ctl_center; 4860 4861 ath_dbg(common, ATH_DBG_REGULATORY, 4862 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", 4863 ctlMode, numCtlModes, isHt40CtlMode, 4864 (pCtlMode[ctlMode] & EXT_ADDITIVE)); 4865 4866 /* walk through each CTL index stored in EEPROM */ 4867 if (is2ghz) { 4868 ctlIndex = pEepData->ctlIndex_2G; 4869 ctlNum = AR9300_NUM_CTLS_2G; 4870 } else { 4871 ctlIndex = pEepData->ctlIndex_5G; 4872 ctlNum = AR9300_NUM_CTLS_5G; 4873 } 4874 4875 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { 4876 ath_dbg(common, ATH_DBG_REGULATORY, 4877 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", 4878 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], 4879 chan->channel); 4880 4881 /* 4882 * compare test group from regulatory 4883 * channel list with test mode from pCtlMode 4884 * list 4885 */ 4886 if ((((cfgCtl & ~CTL_MODE_M) | 4887 (pCtlMode[ctlMode] & CTL_MODE_M)) == 4888 ctlIndex[i]) || 4889 (((cfgCtl & ~CTL_MODE_M) | 4890 (pCtlMode[ctlMode] & CTL_MODE_M)) == 4891 ((ctlIndex[i] & CTL_MODE_M) | 4892 SD_NO_CTL))) { 4893 twiceMinEdgePower = 4894 ar9003_hw_get_max_edge_power(pEepData, 4895 freq, i, 4896 is2ghz); 4897 4898 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) 4899 /* 4900 * Find the minimum of all CTL 4901 * edge powers that apply to 4902 * this channel 4903 */ 4904 twiceMaxEdgePower = 4905 min(twiceMaxEdgePower, 4906 twiceMinEdgePower); 4907 else { 4908 /* specific */ 4909 twiceMaxEdgePower = 4910 twiceMinEdgePower; 4911 break; 4912 } 4913 } 4914 } 4915 4916 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 4917 4918 ath_dbg(common, ATH_DBG_REGULATORY, 4919 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", 4920 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, 4921 scaledPower, minCtlPower); 4922 4923 /* Apply ctl mode to correct target power set */ 4924 switch (pCtlMode[ctlMode]) { 4925 case CTL_11B: 4926 for (i = ALL_TARGET_LEGACY_1L_5L; 4927 i <= ALL_TARGET_LEGACY_11S; i++) 4928 pPwrArray[i] = 4929 (u8)min((u16)pPwrArray[i], 4930 minCtlPower); 4931 break; 4932 case CTL_11A: 4933 case CTL_11G: 4934 for (i = ALL_TARGET_LEGACY_6_24; 4935 i <= ALL_TARGET_LEGACY_54; i++) 4936 pPwrArray[i] = 4937 (u8)min((u16)pPwrArray[i], 4938 minCtlPower); 4939 break; 4940 case CTL_5GHT20: 4941 case CTL_2GHT20: 4942 for (i = ALL_TARGET_HT20_0_8_16; 4943 i <= ALL_TARGET_HT20_21; i++) 4944 pPwrArray[i] = 4945 (u8)min((u16)pPwrArray[i], 4946 minCtlPower); 4947 pPwrArray[ALL_TARGET_HT20_22] = 4948 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22], 4949 minCtlPower); 4950 pPwrArray[ALL_TARGET_HT20_23] = 4951 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23], 4952 minCtlPower); 4953 break; 4954 case CTL_5GHT40: 4955 case CTL_2GHT40: 4956 for (i = ALL_TARGET_HT40_0_8_16; 4957 i <= ALL_TARGET_HT40_23; i++) 4958 pPwrArray[i] = 4959 (u8)min((u16)pPwrArray[i], 4960 minCtlPower); 4961 break; 4962 default: 4963 break; 4964 } 4965 } /* end ctl mode checking */ 4966 } 4967 4968 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx) 4969 { 4970 u8 mod_idx = mcs_idx % 8; 4971 4972 if (mod_idx <= 3) 4973 return mod_idx ? (base_pwridx + 1) : base_pwridx; 4974 else 4975 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2; 4976 } 4977 4978 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, 4979 struct ath9k_channel *chan, u16 cfgCtl, 4980 u8 twiceAntennaReduction, 4981 u8 powerLimit, bool test) 4982 { 4983 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 4984 struct ath_common *common = ath9k_hw_common(ah); 4985 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 4986 struct ar9300_modal_eep_header *modal_hdr; 4987 u8 targetPowerValT2[ar9300RateSize]; 4988 u8 target_power_val_t2_eep[ar9300RateSize]; 4989 unsigned int i = 0, paprd_scale_factor = 0; 4990 u8 pwr_idx, min_pwridx = 0; 4991 4992 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2); 4993 4994 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) { 4995 if (IS_CHAN_2GHZ(chan)) 4996 modal_hdr = &eep->modalHeader2G; 4997 else 4998 modal_hdr = &eep->modalHeader5G; 4999 5000 ah->paprd_ratemask = 5001 le32_to_cpu(modal_hdr->papdRateMaskHt20) & 5002 AR9300_PAPRD_RATE_MASK; 5003 5004 ah->paprd_ratemask_ht40 = 5005 le32_to_cpu(modal_hdr->papdRateMaskHt40) & 5006 AR9300_PAPRD_RATE_MASK; 5007 5008 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan); 5009 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 : 5010 ALL_TARGET_HT20_0_8_16; 5011 5012 if (!ah->paprd_table_write_done) { 5013 memcpy(target_power_val_t2_eep, targetPowerValT2, 5014 sizeof(targetPowerValT2)); 5015 for (i = 0; i < 24; i++) { 5016 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx); 5017 if (ah->paprd_ratemask & (1 << i)) { 5018 if (targetPowerValT2[pwr_idx] && 5019 targetPowerValT2[pwr_idx] == 5020 target_power_val_t2_eep[pwr_idx]) 5021 targetPowerValT2[pwr_idx] -= 5022 paprd_scale_factor; 5023 } 5024 } 5025 } 5026 memcpy(target_power_val_t2_eep, targetPowerValT2, 5027 sizeof(targetPowerValT2)); 5028 } 5029 5030 ar9003_hw_set_power_per_rate_table(ah, chan, 5031 targetPowerValT2, cfgCtl, 5032 twiceAntennaReduction, 5033 powerLimit); 5034 5035 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) { 5036 for (i = 0; i < ar9300RateSize; i++) { 5037 if ((ah->paprd_ratemask & (1 << i)) && 5038 (abs(targetPowerValT2[i] - 5039 target_power_val_t2_eep[i]) > 5040 paprd_scale_factor)) { 5041 ah->paprd_ratemask &= ~(1 << i); 5042 ath_dbg(common, ATH_DBG_EEPROM, 5043 "paprd disabled for mcs %d\n", i); 5044 } 5045 } 5046 } 5047 5048 regulatory->max_power_level = 0; 5049 for (i = 0; i < ar9300RateSize; i++) { 5050 if (targetPowerValT2[i] > regulatory->max_power_level) 5051 regulatory->max_power_level = targetPowerValT2[i]; 5052 } 5053 5054 if (test) 5055 return; 5056 5057 for (i = 0; i < ar9300RateSize; i++) { 5058 ath_dbg(common, ATH_DBG_EEPROM, 5059 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); 5060 } 5061 5062 ah->txpower_limit = regulatory->max_power_level; 5063 5064 /* Write target power array to registers */ 5065 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); 5066 ar9003_hw_calibration_apply(ah, chan->channel); 5067 5068 if (IS_CHAN_2GHZ(chan)) { 5069 if (IS_CHAN_HT40(chan)) 5070 i = ALL_TARGET_HT40_0_8_16; 5071 else 5072 i = ALL_TARGET_HT20_0_8_16; 5073 } else { 5074 if (IS_CHAN_HT40(chan)) 5075 i = ALL_TARGET_HT40_7; 5076 else 5077 i = ALL_TARGET_HT20_7; 5078 } 5079 ah->paprd_target_power = targetPowerValT2[i]; 5080 } 5081 5082 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, 5083 u16 i, bool is2GHz) 5084 { 5085 return AR_NO_SPUR; 5086 } 5087 5088 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) 5089 { 5090 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5091 5092 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ 5093 } 5094 5095 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) 5096 { 5097 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5098 5099 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ 5100 } 5101 5102 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz) 5103 { 5104 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5105 5106 if (is_2ghz) 5107 return eep->modalHeader2G.spurChans; 5108 else 5109 return eep->modalHeader5G.spurChans; 5110 } 5111 5112 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, 5113 struct ath9k_channel *chan) 5114 { 5115 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 5116 5117 if (IS_CHAN_2GHZ(chan)) 5118 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20), 5119 AR9300_PAPRD_SCALE_1); 5120 else { 5121 if (chan->channel >= 5700) 5122 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20), 5123 AR9300_PAPRD_SCALE_1); 5124 else if (chan->channel >= 5400) 5125 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), 5126 AR9300_PAPRD_SCALE_2); 5127 else 5128 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40), 5129 AR9300_PAPRD_SCALE_1); 5130 } 5131 } 5132 5133 const struct eeprom_ops eep_ar9300_ops = { 5134 .check_eeprom = ath9k_hw_ar9300_check_eeprom, 5135 .get_eeprom = ath9k_hw_ar9300_get_eeprom, 5136 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom, 5137 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom, 5138 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver, 5139 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev, 5140 .set_board_values = ath9k_hw_ar9300_set_board_values, 5141 .set_addac = ath9k_hw_ar9300_set_addac, 5142 .set_txpower = ath9k_hw_ar9300_set_txpower, 5143 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel 5144 }; 5145