1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 22 /* All code below is for AR5008, AR9001, AR9002 */ 23 24 static const int firstep_table[] = 25 /* level: 0 1 2 3 4 5 6 7 8 */ 26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 27 28 static const int cycpwrThr1_table[] = 29 /* level: 0 1 2 3 4 5 6 7 8 */ 30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ 31 32 /* 33 * register values to turn OFDM weak signal detection OFF 34 */ 35 static const int m1ThreshLow_off = 127; 36 static const int m2ThreshLow_off = 127; 37 static const int m1Thresh_off = 127; 38 static const int m2Thresh_off = 127; 39 static const int m2CountThr_off = 31; 40 static const int m2CountThrLow_off = 63; 41 static const int m1ThreshLowExt_off = 127; 42 static const int m2ThreshLowExt_off = 127; 43 static const int m1ThreshExt_off = 127; 44 static const int m2ThreshExt_off = 127; 45 46 47 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array, 48 int col) 49 { 50 int i; 51 52 for (i = 0; i < array->ia_rows; i++) 53 bank[i] = INI_RA(array, i, col); 54 } 55 56 57 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \ 58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr)) 59 60 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array, 61 u32 *data, unsigned int *writecnt) 62 { 63 int r; 64 65 ENABLE_REGWRITE_BUFFER(ah); 66 67 for (r = 0; r < array->ia_rows; r++) { 68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 69 DO_DELAY(*writecnt); 70 } 71 72 REGWRITE_BUFFER_FLUSH(ah); 73 } 74 75 /** 76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 77 * @rfbuf: 78 * @reg32: 79 * @numBits: 80 * @firstBit: 81 * @column: 82 * 83 * Performs analog "swizzling" of parameters into their location. 84 * Used on external AR2133/AR5133 radios. 85 */ 86 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 87 u32 numBits, u32 firstBit, 88 u32 column) 89 { 90 u32 tmp32, mask, arrayEntry, lastBit; 91 int32_t bitPosition, bitsLeft; 92 93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 94 arrayEntry = (firstBit - 1) / 8; 95 bitPosition = (firstBit - 1) % 8; 96 bitsLeft = numBits; 97 while (bitsLeft > 0) { 98 lastBit = (bitPosition + bitsLeft > 8) ? 99 8 : bitPosition + bitsLeft; 100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 101 (column * 8); 102 rfBuf[arrayEntry] &= ~mask; 103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 104 (column * 8)) & mask; 105 bitsLeft -= 8 - bitPosition; 106 tmp32 = tmp32 >> (8 - bitPosition); 107 bitPosition = 0; 108 arrayEntry++; 109 } 110 } 111 112 /* 113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 114 * rf_pwd_icsyndiv. 115 * 116 * Theoretical Rules: 117 * if 2 GHz band 118 * if forceBiasAuto 119 * if synth_freq < 2412 120 * bias = 0 121 * else if 2412 <= synth_freq <= 2422 122 * bias = 1 123 * else // synth_freq > 2422 124 * bias = 2 125 * else if forceBias > 0 126 * bias = forceBias & 7 127 * else 128 * no change, use value from ini file 129 * else 130 * no change, invalid band 131 * 132 * 1st Mod: 133 * 2422 also uses value of 2 134 * <approved> 135 * 136 * 2nd Mod: 137 * Less than 2412 uses value of 0, 2412 and above uses value of 2 138 */ 139 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 140 { 141 struct ath_common *common = ath9k_hw_common(ah); 142 u32 tmp_reg; 143 int reg_writes = 0; 144 u32 new_bias = 0; 145 146 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 147 return; 148 149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 150 151 if (synth_freq < 2412) 152 new_bias = 0; 153 else if (synth_freq < 2422) 154 new_bias = 1; 155 else 156 new_bias = 2; 157 158 /* pre-reverse this field */ 159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 160 161 ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 162 new_bias, synth_freq); 163 164 /* swizzle rf_pwd_icsyndiv */ 165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 166 167 /* write Bank 6 with new params */ 168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes); 169 } 170 171 /** 172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 173 * @ah: atheros hardware structure 174 * @chan: 175 * 176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 177 * the channel value. Assumes writes enabled to analog bus and bank6 register 178 * cache in ah->analogBank6Data. 179 */ 180 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 181 { 182 struct ath_common *common = ath9k_hw_common(ah); 183 u32 channelSel = 0; 184 u32 bModeSynth = 0; 185 u32 aModeRefSel = 0; 186 u32 reg32 = 0; 187 u16 freq; 188 struct chan_centers centers; 189 190 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 191 freq = centers.synth_center; 192 193 if (freq < 4800) { 194 u32 txctl; 195 196 if (((freq - 2192) % 5) == 0) { 197 channelSel = ((freq - 672) * 2 - 3040) / 10; 198 bModeSynth = 0; 199 } else if (((freq - 2224) % 5) == 0) { 200 channelSel = ((freq - 704) * 2 - 3040) / 10; 201 bModeSynth = 1; 202 } else { 203 ath_err(common, "Invalid channel %u MHz\n", freq); 204 return -EINVAL; 205 } 206 207 channelSel = (channelSel << 2) & 0xff; 208 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 209 210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 211 if (freq == 2484) { 212 213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 215 } else { 216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 218 } 219 220 } else if ((freq % 20) == 0 && freq >= 5120) { 221 channelSel = 222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 223 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 224 } else if ((freq % 10) == 0) { 225 channelSel = 226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 228 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 229 else 230 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 231 } else if ((freq % 5) == 0) { 232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 233 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 234 } else { 235 ath_err(common, "Invalid channel %u MHz\n", freq); 236 return -EINVAL; 237 } 238 239 ar5008_hw_force_bias(ah, freq); 240 241 reg32 = 242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 243 (1 << 5) | 0x1; 244 245 REG_WRITE(ah, AR_PHY(0x37), reg32); 246 247 ah->curchan = chan; 248 ah->curchan_rad_index = -1; 249 250 return 0; 251 } 252 253 /** 254 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 255 * @ah: atheros hardware structure 256 * @chan: 257 * 258 * For non single-chip solutions. Converts to baseband spur frequency given the 259 * input channel frequency and compute register settings below. 260 */ 261 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 262 struct ath9k_channel *chan) 263 { 264 int bb_spur = AR_NO_SPUR; 265 int bin, cur_bin; 266 int spur_freq_sd; 267 int spur_delta_phase; 268 int denominator; 269 int upper, lower, cur_vit_mask; 270 int tmp, new; 271 int i; 272 static int pilot_mask_reg[4] = { 273 AR_PHY_TIMING7, AR_PHY_TIMING8, 274 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 275 }; 276 static int chan_mask_reg[4] = { 277 AR_PHY_TIMING9, AR_PHY_TIMING10, 278 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 279 }; 280 static int inc[4] = { 0, 100, 0, 0 }; 281 282 int8_t mask_m[123]; 283 int8_t mask_p[123]; 284 int8_t mask_amt; 285 int tmp_mask; 286 int cur_bb_spur; 287 bool is2GHz = IS_CHAN_2GHZ(chan); 288 289 memset(&mask_m, 0, sizeof(int8_t) * 123); 290 memset(&mask_p, 0, sizeof(int8_t) * 123); 291 292 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 293 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 294 if (AR_NO_SPUR == cur_bb_spur) 295 break; 296 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 297 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 298 bb_spur = cur_bb_spur; 299 break; 300 } 301 } 302 303 if (AR_NO_SPUR == bb_spur) 304 return; 305 306 bin = bb_spur * 32; 307 308 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 309 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 310 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 311 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 312 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 313 314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 315 316 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 317 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 318 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 319 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 320 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 321 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 322 323 spur_delta_phase = ((bb_spur * 524288) / 100) & 324 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 325 326 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 327 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 328 329 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 330 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 331 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 332 REG_WRITE(ah, AR_PHY_TIMING11, new); 333 334 cur_bin = -6000; 335 upper = bin + 100; 336 lower = bin - 100; 337 338 for (i = 0; i < 4; i++) { 339 int pilot_mask = 0; 340 int chan_mask = 0; 341 int bp = 0; 342 for (bp = 0; bp < 30; bp++) { 343 if ((cur_bin > lower) && (cur_bin < upper)) { 344 pilot_mask = pilot_mask | 0x1 << bp; 345 chan_mask = chan_mask | 0x1 << bp; 346 } 347 cur_bin += 100; 348 } 349 cur_bin += inc[i]; 350 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 351 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 352 } 353 354 cur_vit_mask = 6100; 355 upper = bin + 120; 356 lower = bin - 120; 357 358 for (i = 0; i < 123; i++) { 359 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 360 361 /* workaround for gcc bug #37014 */ 362 volatile int tmp_v = abs(cur_vit_mask - bin); 363 364 if (tmp_v < 75) 365 mask_amt = 1; 366 else 367 mask_amt = 0; 368 if (cur_vit_mask < 0) 369 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 370 else 371 mask_p[cur_vit_mask / 100] = mask_amt; 372 } 373 cur_vit_mask -= 100; 374 } 375 376 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 377 | (mask_m[48] << 26) | (mask_m[49] << 24) 378 | (mask_m[50] << 22) | (mask_m[51] << 20) 379 | (mask_m[52] << 18) | (mask_m[53] << 16) 380 | (mask_m[54] << 14) | (mask_m[55] << 12) 381 | (mask_m[56] << 10) | (mask_m[57] << 8) 382 | (mask_m[58] << 6) | (mask_m[59] << 4) 383 | (mask_m[60] << 2) | (mask_m[61] << 0); 384 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 385 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 386 387 tmp_mask = (mask_m[31] << 28) 388 | (mask_m[32] << 26) | (mask_m[33] << 24) 389 | (mask_m[34] << 22) | (mask_m[35] << 20) 390 | (mask_m[36] << 18) | (mask_m[37] << 16) 391 | (mask_m[48] << 14) | (mask_m[39] << 12) 392 | (mask_m[40] << 10) | (mask_m[41] << 8) 393 | (mask_m[42] << 6) | (mask_m[43] << 4) 394 | (mask_m[44] << 2) | (mask_m[45] << 0); 395 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 396 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 397 398 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 399 | (mask_m[18] << 26) | (mask_m[18] << 24) 400 | (mask_m[20] << 22) | (mask_m[20] << 20) 401 | (mask_m[22] << 18) | (mask_m[22] << 16) 402 | (mask_m[24] << 14) | (mask_m[24] << 12) 403 | (mask_m[25] << 10) | (mask_m[26] << 8) 404 | (mask_m[27] << 6) | (mask_m[28] << 4) 405 | (mask_m[29] << 2) | (mask_m[30] << 0); 406 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 407 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 408 409 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 410 | (mask_m[2] << 26) | (mask_m[3] << 24) 411 | (mask_m[4] << 22) | (mask_m[5] << 20) 412 | (mask_m[6] << 18) | (mask_m[7] << 16) 413 | (mask_m[8] << 14) | (mask_m[9] << 12) 414 | (mask_m[10] << 10) | (mask_m[11] << 8) 415 | (mask_m[12] << 6) | (mask_m[13] << 4) 416 | (mask_m[14] << 2) | (mask_m[15] << 0); 417 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 418 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 419 420 tmp_mask = (mask_p[15] << 28) 421 | (mask_p[14] << 26) | (mask_p[13] << 24) 422 | (mask_p[12] << 22) | (mask_p[11] << 20) 423 | (mask_p[10] << 18) | (mask_p[9] << 16) 424 | (mask_p[8] << 14) | (mask_p[7] << 12) 425 | (mask_p[6] << 10) | (mask_p[5] << 8) 426 | (mask_p[4] << 6) | (mask_p[3] << 4) 427 | (mask_p[2] << 2) | (mask_p[1] << 0); 428 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 429 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 430 431 tmp_mask = (mask_p[30] << 28) 432 | (mask_p[29] << 26) | (mask_p[28] << 24) 433 | (mask_p[27] << 22) | (mask_p[26] << 20) 434 | (mask_p[25] << 18) | (mask_p[24] << 16) 435 | (mask_p[23] << 14) | (mask_p[22] << 12) 436 | (mask_p[21] << 10) | (mask_p[20] << 8) 437 | (mask_p[19] << 6) | (mask_p[18] << 4) 438 | (mask_p[17] << 2) | (mask_p[16] << 0); 439 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 440 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 441 442 tmp_mask = (mask_p[45] << 28) 443 | (mask_p[44] << 26) | (mask_p[43] << 24) 444 | (mask_p[42] << 22) | (mask_p[41] << 20) 445 | (mask_p[40] << 18) | (mask_p[39] << 16) 446 | (mask_p[38] << 14) | (mask_p[37] << 12) 447 | (mask_p[36] << 10) | (mask_p[35] << 8) 448 | (mask_p[34] << 6) | (mask_p[33] << 4) 449 | (mask_p[32] << 2) | (mask_p[31] << 0); 450 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 451 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 452 453 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 454 | (mask_p[59] << 26) | (mask_p[58] << 24) 455 | (mask_p[57] << 22) | (mask_p[56] << 20) 456 | (mask_p[55] << 18) | (mask_p[54] << 16) 457 | (mask_p[53] << 14) | (mask_p[52] << 12) 458 | (mask_p[51] << 10) | (mask_p[50] << 8) 459 | (mask_p[49] << 6) | (mask_p[48] << 4) 460 | (mask_p[47] << 2) | (mask_p[46] << 0); 461 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 462 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 463 } 464 465 /** 466 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 467 * @ah: atheros hardware structure 468 * 469 * Only required for older devices with external AR2133/AR5133 radios. 470 */ 471 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 472 { 473 #define ATH_ALLOC_BANK(bank, size) do { \ 474 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \ 475 if (!bank) { \ 476 ath_err(common, "Cannot allocate RF banks\n"); \ 477 return -ENOMEM; \ 478 } \ 479 } while (0); 480 481 struct ath_common *common = ath9k_hw_common(ah); 482 483 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 484 485 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows); 486 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows); 487 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows); 488 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows); 489 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows); 490 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows); 491 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows); 492 ATH_ALLOC_BANK(ah->addac5416_21, 493 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns); 494 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows); 495 496 return 0; 497 #undef ATH_ALLOC_BANK 498 } 499 500 501 /** 502 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers 503 * @ah: atheros hardware struture 504 * For the external AR2133/AR5133 radios banks. 505 */ 506 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah) 507 { 508 #define ATH_FREE_BANK(bank) do { \ 509 kfree(bank); \ 510 bank = NULL; \ 511 } while (0); 512 513 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 514 515 ATH_FREE_BANK(ah->analogBank0Data); 516 ATH_FREE_BANK(ah->analogBank1Data); 517 ATH_FREE_BANK(ah->analogBank2Data); 518 ATH_FREE_BANK(ah->analogBank3Data); 519 ATH_FREE_BANK(ah->analogBank6Data); 520 ATH_FREE_BANK(ah->analogBank6TPCData); 521 ATH_FREE_BANK(ah->analogBank7Data); 522 ATH_FREE_BANK(ah->addac5416_21); 523 ATH_FREE_BANK(ah->bank6Temp); 524 525 #undef ATH_FREE_BANK 526 } 527 528 /* * 529 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 530 * @ah: atheros hardware structure 531 * @chan: 532 * @modesIndex: 533 * 534 * Used for the external AR2133/AR5133 radios. 535 * 536 * Reads the EEPROM header info from the device structure and programs 537 * all rf registers. This routine requires access to the analog 538 * rf device. This is not required for single-chip devices. 539 */ 540 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 541 struct ath9k_channel *chan, 542 u16 modesIndex) 543 { 544 u32 eepMinorRev; 545 u32 ob5GHz = 0, db5GHz = 0; 546 u32 ob2GHz = 0, db2GHz = 0; 547 int regWrites = 0; 548 549 /* 550 * Software does not need to program bank data 551 * for single chip devices, that is AR9280 or anything 552 * after that. 553 */ 554 if (AR_SREV_9280_20_OR_LATER(ah)) 555 return true; 556 557 /* Setup rf parameters */ 558 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 559 560 /* Setup Bank 0 Write */ 561 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1); 562 563 /* Setup Bank 1 Write */ 564 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1); 565 566 /* Setup Bank 2 Write */ 567 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1); 568 569 /* Setup Bank 6 Write */ 570 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3, 571 modesIndex); 572 { 573 int i; 574 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) { 575 ah->analogBank6Data[i] = 576 INI_RA(&ah->iniBank6TPC, i, modesIndex); 577 } 578 } 579 580 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 581 if (eepMinorRev >= 2) { 582 if (IS_CHAN_2GHZ(chan)) { 583 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 584 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 585 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 586 ob2GHz, 3, 197, 0); 587 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 588 db2GHz, 3, 194, 0); 589 } else { 590 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 591 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 592 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 593 ob5GHz, 3, 203, 0); 594 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 595 db5GHz, 3, 200, 0); 596 } 597 } 598 599 /* Setup Bank 7 Setup */ 600 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1); 601 602 /* Write Analog registers */ 603 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 604 regWrites); 605 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, 606 regWrites); 607 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, 608 regWrites); 609 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, 610 regWrites); 611 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data, 612 regWrites); 613 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, 614 regWrites); 615 616 return true; 617 } 618 619 static void ar5008_hw_init_bb(struct ath_hw *ah, 620 struct ath9k_channel *chan) 621 { 622 u32 synthDelay; 623 624 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 625 if (IS_CHAN_B(chan)) 626 synthDelay = (4 * synthDelay) / 22; 627 else 628 synthDelay /= 10; 629 630 if (IS_CHAN_HALF_RATE(chan)) 631 synthDelay *= 2; 632 else if (IS_CHAN_QUARTER_RATE(chan)) 633 synthDelay *= 4; 634 635 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 636 637 udelay(synthDelay + BASE_ACTIVATE_DELAY); 638 } 639 640 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 641 { 642 int rx_chainmask, tx_chainmask; 643 644 rx_chainmask = ah->rxchainmask; 645 tx_chainmask = ah->txchainmask; 646 647 648 switch (rx_chainmask) { 649 case 0x5: 650 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 651 AR_PHY_SWAP_ALT_CHAIN); 652 case 0x3: 653 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 654 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 655 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 656 break; 657 } 658 case 0x1: 659 case 0x2: 660 case 0x7: 661 ENABLE_REGWRITE_BUFFER(ah); 662 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 663 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 664 break; 665 default: 666 ENABLE_REGWRITE_BUFFER(ah); 667 break; 668 } 669 670 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 671 672 REGWRITE_BUFFER_FLUSH(ah); 673 674 if (tx_chainmask == 0x5) { 675 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 676 AR_PHY_SWAP_ALT_CHAIN); 677 } 678 if (AR_SREV_9100(ah)) 679 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 680 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 681 } 682 683 static void ar5008_hw_override_ini(struct ath_hw *ah, 684 struct ath9k_channel *chan) 685 { 686 u32 val; 687 688 /* 689 * Set the RX_ABORT and RX_DIS and clear if off only after 690 * RXE is set for MAC. This prevents frames with corrupted 691 * descriptor status. 692 */ 693 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 694 695 if (AR_SREV_9280_20_OR_LATER(ah)) { 696 val = REG_READ(ah, AR_PCU_MISC_MODE2); 697 698 if (!AR_SREV_9271(ah)) 699 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 700 701 if (AR_SREV_9287_11_OR_LATER(ah)) 702 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 703 704 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 705 } 706 707 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, 708 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 709 710 if (AR_SREV_9280_20_OR_LATER(ah)) 711 return; 712 /* 713 * Disable BB clock gating 714 * Necessary to avoid issues on AR5416 2.0 715 */ 716 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 717 718 /* 719 * Disable RIFS search on some chips to avoid baseband 720 * hang issues. 721 */ 722 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 723 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 724 val &= ~AR_PHY_RIFS_INIT_DELAY; 725 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 726 } 727 } 728 729 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 730 struct ath9k_channel *chan) 731 { 732 u32 phymode; 733 u32 enableDacFifo = 0; 734 735 if (AR_SREV_9285_12_OR_LATER(ah)) 736 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 737 AR_PHY_FC_ENABLE_DAC_FIFO); 738 739 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 740 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 741 742 if (IS_CHAN_HT40(chan)) { 743 phymode |= AR_PHY_FC_DYN2040_EN; 744 745 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 746 (chan->chanmode == CHANNEL_G_HT40PLUS)) 747 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 748 749 } 750 REG_WRITE(ah, AR_PHY_TURBO, phymode); 751 752 ath9k_hw_set11nmac2040(ah); 753 754 ENABLE_REGWRITE_BUFFER(ah); 755 756 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 757 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 758 759 REGWRITE_BUFFER_FLUSH(ah); 760 } 761 762 763 static int ar5008_hw_process_ini(struct ath_hw *ah, 764 struct ath9k_channel *chan) 765 { 766 struct ath_common *common = ath9k_hw_common(ah); 767 int i, regWrites = 0; 768 u32 modesIndex, freqIndex; 769 770 switch (chan->chanmode) { 771 case CHANNEL_A: 772 case CHANNEL_A_HT20: 773 modesIndex = 1; 774 freqIndex = 1; 775 break; 776 case CHANNEL_A_HT40PLUS: 777 case CHANNEL_A_HT40MINUS: 778 modesIndex = 2; 779 freqIndex = 1; 780 break; 781 case CHANNEL_G: 782 case CHANNEL_G_HT20: 783 case CHANNEL_B: 784 modesIndex = 4; 785 freqIndex = 2; 786 break; 787 case CHANNEL_G_HT40PLUS: 788 case CHANNEL_G_HT40MINUS: 789 modesIndex = 3; 790 freqIndex = 2; 791 break; 792 793 default: 794 return -EINVAL; 795 } 796 797 /* 798 * Set correct baseband to analog shift setting to 799 * access analog chips. 800 */ 801 REG_WRITE(ah, AR_PHY(0), 0x00000007); 802 803 /* Write ADDAC shifts */ 804 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 805 if (ah->eep_ops->set_addac) 806 ah->eep_ops->set_addac(ah, chan); 807 808 if (AR_SREV_5416_22_OR_LATER(ah)) { 809 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 810 } else { 811 struct ar5416IniArray temp; 812 u32 addacSize = 813 sizeof(u32) * ah->iniAddac.ia_rows * 814 ah->iniAddac.ia_columns; 815 816 /* For AR5416 2.0/2.1 */ 817 memcpy(ah->addac5416_21, 818 ah->iniAddac.ia_array, addacSize); 819 820 /* override CLKDRV value at [row, column] = [31, 1] */ 821 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; 822 823 temp.ia_array = ah->addac5416_21; 824 temp.ia_columns = ah->iniAddac.ia_columns; 825 temp.ia_rows = ah->iniAddac.ia_rows; 826 REG_WRITE_ARRAY(&temp, 1, regWrites); 827 } 828 829 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 830 831 ENABLE_REGWRITE_BUFFER(ah); 832 833 for (i = 0; i < ah->iniModes.ia_rows; i++) { 834 u32 reg = INI_RA(&ah->iniModes, i, 0); 835 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 836 837 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 838 val &= ~AR_AN_TOP2_PWDCLKIND; 839 840 REG_WRITE(ah, reg, val); 841 842 if (reg >= 0x7800 && reg < 0x78a0 843 && ah->config.analog_shiftreg 844 && (common->bus_ops->ath_bus_type != ATH_USB)) { 845 udelay(100); 846 } 847 848 DO_DELAY(regWrites); 849 } 850 851 REGWRITE_BUFFER_FLUSH(ah); 852 853 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 854 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 855 856 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 857 AR_SREV_9287_11_OR_LATER(ah)) 858 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 859 860 if (AR_SREV_9271_10(ah)) 861 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only, 862 modesIndex, regWrites); 863 864 ENABLE_REGWRITE_BUFFER(ah); 865 866 /* Write common array parameters */ 867 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 868 u32 reg = INI_RA(&ah->iniCommon, i, 0); 869 u32 val = INI_RA(&ah->iniCommon, i, 1); 870 871 REG_WRITE(ah, reg, val); 872 873 if (reg >= 0x7800 && reg < 0x78a0 874 && ah->config.analog_shiftreg 875 && (common->bus_ops->ath_bus_type != ATH_USB)) { 876 udelay(100); 877 } 878 879 DO_DELAY(regWrites); 880 } 881 882 REGWRITE_BUFFER_FLUSH(ah); 883 884 if (AR_SREV_9271(ah)) { 885 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1) 886 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271, 887 modesIndex, regWrites); 888 else 889 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, 890 modesIndex, regWrites); 891 } 892 893 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 894 895 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) { 896 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 897 regWrites); 898 } 899 900 ar5008_hw_override_ini(ah, chan); 901 ar5008_hw_set_channel_regs(ah, chan); 902 ar5008_hw_init_chain_masks(ah); 903 ath9k_olc_init(ah); 904 ath9k_hw_apply_txpower(ah, chan); 905 906 /* Write analog registers */ 907 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 908 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 909 return -EIO; 910 } 911 912 return 0; 913 } 914 915 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 916 { 917 u32 rfMode = 0; 918 919 if (chan == NULL) 920 return; 921 922 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) 923 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 924 925 if (!AR_SREV_9280_20_OR_LATER(ah)) 926 rfMode |= (IS_CHAN_5GHZ(chan)) ? 927 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 928 929 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 930 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 931 932 REG_WRITE(ah, AR_PHY_MODE, rfMode); 933 } 934 935 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 936 { 937 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 938 } 939 940 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 941 struct ath9k_channel *chan) 942 { 943 u32 coef_scaled, ds_coef_exp, ds_coef_man; 944 u32 clockMhzScaled = 0x64000000; 945 struct chan_centers centers; 946 947 if (IS_CHAN_HALF_RATE(chan)) 948 clockMhzScaled = clockMhzScaled >> 1; 949 else if (IS_CHAN_QUARTER_RATE(chan)) 950 clockMhzScaled = clockMhzScaled >> 2; 951 952 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 953 coef_scaled = clockMhzScaled / centers.synth_center; 954 955 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 956 &ds_coef_exp); 957 958 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 959 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 960 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 961 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 962 963 coef_scaled = (9 * coef_scaled) / 10; 964 965 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 966 &ds_coef_exp); 967 968 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 969 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 970 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 971 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 972 } 973 974 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 975 { 976 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 977 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 978 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 979 } 980 981 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 982 { 983 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 984 if (IS_CHAN_B(ah->curchan)) 985 synthDelay = (4 * synthDelay) / 22; 986 else 987 synthDelay /= 10; 988 989 udelay(synthDelay + BASE_ACTIVATE_DELAY); 990 991 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 992 } 993 994 static void ar5008_restore_chainmask(struct ath_hw *ah) 995 { 996 int rx_chainmask = ah->rxchainmask; 997 998 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 999 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1000 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1001 } 1002 } 1003 1004 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 1005 struct ath9k_channel *chan) 1006 { 1007 u32 pll; 1008 1009 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 1010 1011 if (chan && IS_CHAN_HALF_RATE(chan)) 1012 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 1013 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1014 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 1015 1016 if (chan && IS_CHAN_5GHZ(chan)) 1017 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 1018 else 1019 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 1020 1021 return pll; 1022 } 1023 1024 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 1025 struct ath9k_channel *chan) 1026 { 1027 u32 pll; 1028 1029 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1030 1031 if (chan && IS_CHAN_HALF_RATE(chan)) 1032 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1033 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 1034 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1035 1036 if (chan && IS_CHAN_5GHZ(chan)) 1037 pll |= SM(0xa, AR_RTC_PLL_DIV); 1038 else 1039 pll |= SM(0xb, AR_RTC_PLL_DIV); 1040 1041 return pll; 1042 } 1043 1044 static bool ar5008_hw_ani_control_old(struct ath_hw *ah, 1045 enum ath9k_ani_cmd cmd, 1046 int param) 1047 { 1048 struct ar5416AniState *aniState = &ah->curchan->ani; 1049 struct ath_common *common = ath9k_hw_common(ah); 1050 1051 switch (cmd & ah->ani_function) { 1052 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 1053 u32 level = param; 1054 1055 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { 1056 ath_dbg(common, ATH_DBG_ANI, 1057 "level out of range (%u > %zu)\n", 1058 level, ARRAY_SIZE(ah->totalSizeDesired)); 1059 return false; 1060 } 1061 1062 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1063 AR_PHY_DESIRED_SZ_TOT_DES, 1064 ah->totalSizeDesired[level]); 1065 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 1066 AR_PHY_AGC_CTL1_COARSE_LOW, 1067 ah->coarse_low[level]); 1068 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 1069 AR_PHY_AGC_CTL1_COARSE_HIGH, 1070 ah->coarse_high[level]); 1071 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1072 AR_PHY_FIND_SIG_FIRPWR, 1073 ah->firpwr[level]); 1074 1075 if (level > aniState->noiseImmunityLevel) 1076 ah->stats.ast_ani_niup++; 1077 else if (level < aniState->noiseImmunityLevel) 1078 ah->stats.ast_ani_nidown++; 1079 aniState->noiseImmunityLevel = level; 1080 break; 1081 } 1082 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 1083 static const int m1ThreshLow[] = { 127, 50 }; 1084 static const int m2ThreshLow[] = { 127, 40 }; 1085 static const int m1Thresh[] = { 127, 0x4d }; 1086 static const int m2Thresh[] = { 127, 0x40 }; 1087 static const int m2CountThr[] = { 31, 16 }; 1088 static const int m2CountThrLow[] = { 63, 48 }; 1089 u32 on = param ? 1 : 0; 1090 1091 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1092 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1093 m1ThreshLow[on]); 1094 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1095 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1096 m2ThreshLow[on]); 1097 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1098 AR_PHY_SFCORR_M1_THRESH, 1099 m1Thresh[on]); 1100 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1101 AR_PHY_SFCORR_M2_THRESH, 1102 m2Thresh[on]); 1103 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1104 AR_PHY_SFCORR_M2COUNT_THR, 1105 m2CountThr[on]); 1106 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1107 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1108 m2CountThrLow[on]); 1109 1110 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1111 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 1112 m1ThreshLow[on]); 1113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1114 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 1115 m2ThreshLow[on]); 1116 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1117 AR_PHY_SFCORR_EXT_M1_THRESH, 1118 m1Thresh[on]); 1119 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1120 AR_PHY_SFCORR_EXT_M2_THRESH, 1121 m2Thresh[on]); 1122 1123 if (on) 1124 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1125 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1126 else 1127 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1128 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1129 1130 if (!on != aniState->ofdmWeakSigDetectOff) { 1131 if (on) 1132 ah->stats.ast_ani_ofdmon++; 1133 else 1134 ah->stats.ast_ani_ofdmoff++; 1135 aniState->ofdmWeakSigDetectOff = !on; 1136 } 1137 break; 1138 } 1139 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{ 1140 static const int weakSigThrCck[] = { 8, 6 }; 1141 u32 high = param ? 1 : 0; 1142 1143 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, 1144 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, 1145 weakSigThrCck[high]); 1146 if (high != aniState->cckWeakSigThreshold) { 1147 if (high) 1148 ah->stats.ast_ani_cckhigh++; 1149 else 1150 ah->stats.ast_ani_ccklow++; 1151 aniState->cckWeakSigThreshold = high; 1152 } 1153 break; 1154 } 1155 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1156 static const int firstep[] = { 0, 4, 8 }; 1157 u32 level = param; 1158 1159 if (level >= ARRAY_SIZE(firstep)) { 1160 ath_dbg(common, ATH_DBG_ANI, 1161 "level out of range (%u > %zu)\n", 1162 level, ARRAY_SIZE(firstep)); 1163 return false; 1164 } 1165 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1166 AR_PHY_FIND_SIG_FIRSTEP, 1167 firstep[level]); 1168 if (level > aniState->firstepLevel) 1169 ah->stats.ast_ani_stepup++; 1170 else if (level < aniState->firstepLevel) 1171 ah->stats.ast_ani_stepdown++; 1172 aniState->firstepLevel = level; 1173 break; 1174 } 1175 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1176 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; 1177 u32 level = param; 1178 1179 if (level >= ARRAY_SIZE(cycpwrThr1)) { 1180 ath_dbg(common, ATH_DBG_ANI, 1181 "level out of range (%u > %zu)\n", 1182 level, ARRAY_SIZE(cycpwrThr1)); 1183 return false; 1184 } 1185 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1186 AR_PHY_TIMING5_CYCPWR_THR1, 1187 cycpwrThr1[level]); 1188 if (level > aniState->spurImmunityLevel) 1189 ah->stats.ast_ani_spurup++; 1190 else if (level < aniState->spurImmunityLevel) 1191 ah->stats.ast_ani_spurdown++; 1192 aniState->spurImmunityLevel = level; 1193 break; 1194 } 1195 case ATH9K_ANI_PRESENT: 1196 break; 1197 default: 1198 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); 1199 return false; 1200 } 1201 1202 ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n"); 1203 ath_dbg(common, ATH_DBG_ANI, 1204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n", 1205 aniState->noiseImmunityLevel, 1206 aniState->spurImmunityLevel, 1207 !aniState->ofdmWeakSigDetectOff); 1208 ath_dbg(common, ATH_DBG_ANI, 1209 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n", 1210 aniState->cckWeakSigThreshold, 1211 aniState->firstepLevel, 1212 aniState->listenTime); 1213 ath_dbg(common, ATH_DBG_ANI, 1214 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", 1215 aniState->ofdmPhyErrCount, 1216 aniState->cckPhyErrCount); 1217 1218 return true; 1219 } 1220 1221 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 1222 enum ath9k_ani_cmd cmd, 1223 int param) 1224 { 1225 struct ath_common *common = ath9k_hw_common(ah); 1226 struct ath9k_channel *chan = ah->curchan; 1227 struct ar5416AniState *aniState = &chan->ani; 1228 s32 value, value2; 1229 1230 switch (cmd & ah->ani_function) { 1231 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 1232 /* 1233 * on == 1 means ofdm weak signal detection is ON 1234 * on == 1 is the default, for less noise immunity 1235 * 1236 * on == 0 means ofdm weak signal detection is OFF 1237 * on == 0 means more noise imm 1238 */ 1239 u32 on = param ? 1 : 0; 1240 /* 1241 * make register setting for default 1242 * (weak sig detect ON) come from INI file 1243 */ 1244 int m1ThreshLow = on ? 1245 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 1246 int m2ThreshLow = on ? 1247 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 1248 int m1Thresh = on ? 1249 aniState->iniDef.m1Thresh : m1Thresh_off; 1250 int m2Thresh = on ? 1251 aniState->iniDef.m2Thresh : m2Thresh_off; 1252 int m2CountThr = on ? 1253 aniState->iniDef.m2CountThr : m2CountThr_off; 1254 int m2CountThrLow = on ? 1255 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 1256 int m1ThreshLowExt = on ? 1257 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 1258 int m2ThreshLowExt = on ? 1259 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 1260 int m1ThreshExt = on ? 1261 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 1262 int m2ThreshExt = on ? 1263 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 1264 1265 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1266 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 1267 m1ThreshLow); 1268 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1269 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 1270 m2ThreshLow); 1271 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1272 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 1273 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1274 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 1275 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 1276 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 1277 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 1278 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 1279 m2CountThrLow); 1280 1281 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1282 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 1283 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1284 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 1285 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1286 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 1287 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 1288 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 1289 1290 if (on) 1291 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 1292 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1293 else 1294 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1295 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1296 1297 if (!on != aniState->ofdmWeakSigDetectOff) { 1298 ath_dbg(common, ATH_DBG_ANI, 1299 "** ch %d: ofdm weak signal: %s=>%s\n", 1300 chan->channel, 1301 !aniState->ofdmWeakSigDetectOff ? 1302 "on" : "off", 1303 on ? "on" : "off"); 1304 if (on) 1305 ah->stats.ast_ani_ofdmon++; 1306 else 1307 ah->stats.ast_ani_ofdmoff++; 1308 aniState->ofdmWeakSigDetectOff = !on; 1309 } 1310 break; 1311 } 1312 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1313 u32 level = param; 1314 1315 if (level >= ARRAY_SIZE(firstep_table)) { 1316 ath_dbg(common, ATH_DBG_ANI, 1317 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", 1318 level, ARRAY_SIZE(firstep_table)); 1319 return false; 1320 } 1321 1322 /* 1323 * make register setting relative to default 1324 * from INI file & cap value 1325 */ 1326 value = firstep_table[level] - 1327 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1328 aniState->iniDef.firstep; 1329 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1330 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1331 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1332 value = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1333 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1334 AR_PHY_FIND_SIG_FIRSTEP, 1335 value); 1336 /* 1337 * we need to set first step low register too 1338 * make register setting relative to default 1339 * from INI file & cap value 1340 */ 1341 value2 = firstep_table[level] - 1342 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1343 aniState->iniDef.firstepLow; 1344 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1345 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1346 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) 1347 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; 1348 1349 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1350 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); 1351 1352 if (level != aniState->firstepLevel) { 1353 ath_dbg(common, ATH_DBG_ANI, 1354 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1355 chan->channel, 1356 aniState->firstepLevel, 1357 level, 1358 ATH9K_ANI_FIRSTEP_LVL_NEW, 1359 value, 1360 aniState->iniDef.firstep); 1361 ath_dbg(common, ATH_DBG_ANI, 1362 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1363 chan->channel, 1364 aniState->firstepLevel, 1365 level, 1366 ATH9K_ANI_FIRSTEP_LVL_NEW, 1367 value2, 1368 aniState->iniDef.firstepLow); 1369 if (level > aniState->firstepLevel) 1370 ah->stats.ast_ani_stepup++; 1371 else if (level < aniState->firstepLevel) 1372 ah->stats.ast_ani_stepdown++; 1373 aniState->firstepLevel = level; 1374 } 1375 break; 1376 } 1377 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1378 u32 level = param; 1379 1380 if (level >= ARRAY_SIZE(cycpwrThr1_table)) { 1381 ath_dbg(common, ATH_DBG_ANI, 1382 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", 1383 level, ARRAY_SIZE(cycpwrThr1_table)); 1384 return false; 1385 } 1386 /* 1387 * make register setting relative to default 1388 * from INI file & cap value 1389 */ 1390 value = cycpwrThr1_table[level] - 1391 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1392 aniState->iniDef.cycpwrThr1; 1393 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1394 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1395 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1396 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1397 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1398 AR_PHY_TIMING5_CYCPWR_THR1, 1399 value); 1400 1401 /* 1402 * set AR_PHY_EXT_CCA for extension channel 1403 * make register setting relative to default 1404 * from INI file & cap value 1405 */ 1406 value2 = cycpwrThr1_table[level] - 1407 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1408 aniState->iniDef.cycpwrThr1Ext; 1409 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1410 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1411 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) 1412 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; 1413 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1414 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); 1415 1416 if (level != aniState->spurImmunityLevel) { 1417 ath_dbg(common, ATH_DBG_ANI, 1418 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1419 chan->channel, 1420 aniState->spurImmunityLevel, 1421 level, 1422 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1423 value, 1424 aniState->iniDef.cycpwrThr1); 1425 ath_dbg(common, ATH_DBG_ANI, 1426 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1427 chan->channel, 1428 aniState->spurImmunityLevel, 1429 level, 1430 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1431 value2, 1432 aniState->iniDef.cycpwrThr1Ext); 1433 if (level > aniState->spurImmunityLevel) 1434 ah->stats.ast_ani_spurup++; 1435 else if (level < aniState->spurImmunityLevel) 1436 ah->stats.ast_ani_spurdown++; 1437 aniState->spurImmunityLevel = level; 1438 } 1439 break; 1440 } 1441 case ATH9K_ANI_MRC_CCK: 1442 /* 1443 * You should not see this as AR5008, AR9001, AR9002 1444 * does not have hardware support for MRC CCK. 1445 */ 1446 WARN_ON(1); 1447 break; 1448 case ATH9K_ANI_PRESENT: 1449 break; 1450 default: 1451 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); 1452 return false; 1453 } 1454 1455 ath_dbg(common, ATH_DBG_ANI, 1456 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1457 aniState->spurImmunityLevel, 1458 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1459 aniState->firstepLevel, 1460 !aniState->mrcCCKOff ? "on" : "off", 1461 aniState->listenTime, 1462 aniState->ofdmPhyErrCount, 1463 aniState->cckPhyErrCount); 1464 return true; 1465 } 1466 1467 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1468 int16_t nfarray[NUM_NF_READINGS]) 1469 { 1470 int16_t nf; 1471 1472 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1473 nfarray[0] = sign_extend32(nf, 8); 1474 1475 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1476 nfarray[1] = sign_extend32(nf, 8); 1477 1478 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1479 nfarray[2] = sign_extend32(nf, 8); 1480 1481 if (!IS_CHAN_HT40(ah->curchan)) 1482 return; 1483 1484 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1485 nfarray[3] = sign_extend32(nf, 8); 1486 1487 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1488 nfarray[4] = sign_extend32(nf, 8); 1489 1490 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1491 nfarray[5] = sign_extend32(nf, 8); 1492 } 1493 1494 /* 1495 * Initialize the ANI register values with default (ini) values. 1496 * This routine is called during a (full) hardware reset after 1497 * all the registers are initialised from the INI. 1498 */ 1499 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1500 { 1501 struct ath_common *common = ath9k_hw_common(ah); 1502 struct ath9k_channel *chan = ah->curchan; 1503 struct ar5416AniState *aniState = &chan->ani; 1504 struct ath9k_ani_default *iniDef; 1505 u32 val; 1506 1507 iniDef = &aniState->iniDef; 1508 1509 ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", 1510 ah->hw_version.macVersion, 1511 ah->hw_version.macRev, 1512 ah->opmode, 1513 chan->channel, 1514 chan->channelFlags); 1515 1516 val = REG_READ(ah, AR_PHY_SFCORR); 1517 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1518 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1519 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1520 1521 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1522 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1523 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1524 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1525 1526 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1527 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1528 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1529 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1530 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1531 iniDef->firstep = REG_READ_FIELD(ah, 1532 AR_PHY_FIND_SIG, 1533 AR_PHY_FIND_SIG_FIRSTEP); 1534 iniDef->firstepLow = REG_READ_FIELD(ah, 1535 AR_PHY_FIND_SIG_LOW, 1536 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1537 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1538 AR_PHY_TIMING5, 1539 AR_PHY_TIMING5_CYCPWR_THR1); 1540 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1541 AR_PHY_EXT_CCA, 1542 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1543 1544 /* these levels just got reset to defaults by the INI */ 1545 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1546 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1547 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1548 aniState->mrcCCKOff = true; /* not available on pre AR9003 */ 1549 } 1550 1551 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1552 { 1553 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1554 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1555 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1556 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1557 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1558 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1559 } 1560 1561 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1562 struct ath_hw_radar_conf *conf) 1563 { 1564 u32 radar_0 = 0, radar_1 = 0; 1565 1566 if (!conf) { 1567 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1568 return; 1569 } 1570 1571 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1572 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1573 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1574 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1575 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1576 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1577 1578 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1579 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1580 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1581 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1582 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1583 1584 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1585 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1586 if (conf->ext_channel) 1587 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1588 else 1589 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1590 } 1591 1592 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1593 { 1594 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1595 1596 conf->fir_power = -33; 1597 conf->radar_rssi = 20; 1598 conf->pulse_height = 10; 1599 conf->pulse_rssi = 24; 1600 conf->pulse_inband = 15; 1601 conf->pulse_maxlen = 255; 1602 conf->pulse_inband_step = 12; 1603 conf->radar_inband = 8; 1604 } 1605 1606 void ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1607 { 1608 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1609 static const u32 ar5416_cca_regs[6] = { 1610 AR_PHY_CCA, 1611 AR_PHY_CH1_CCA, 1612 AR_PHY_CH2_CCA, 1613 AR_PHY_EXT_CCA, 1614 AR_PHY_CH1_EXT_CCA, 1615 AR_PHY_CH2_EXT_CCA 1616 }; 1617 1618 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1619 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1620 1621 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks; 1622 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks; 1623 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1624 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1625 priv_ops->init_bb = ar5008_hw_init_bb; 1626 priv_ops->process_ini = ar5008_hw_process_ini; 1627 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1628 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1629 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1630 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1631 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1632 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1633 priv_ops->do_getnf = ar5008_hw_do_getnf; 1634 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1635 1636 if (modparam_force_new_ani) { 1637 priv_ops->ani_control = ar5008_hw_ani_control_new; 1638 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1639 } else 1640 priv_ops->ani_control = ar5008_hw_ani_control_old; 1641 1642 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1643 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1644 else 1645 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1646 1647 ar5008_hw_set_nf_limits(ah); 1648 ar5008_hw_set_radar_conf(ah); 1649 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1650 } 1651