1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "hw.h" 18 #include "hw-ops.h" 19 #include "../regd.h" 20 #include "ar9002_phy.h" 21 #include "ar5008_initvals.h" 22 23 /* All code below is for AR5008, AR9001, AR9002 */ 24 25 static const int firstep_table[] = 26 /* level: 0 1 2 3 4 5 6 7 8 */ 27 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ 28 29 /* 30 * register values to turn OFDM weak signal detection OFF 31 */ 32 static const int m1ThreshLow_off = 127; 33 static const int m2ThreshLow_off = 127; 34 static const int m1Thresh_off = 127; 35 static const int m2Thresh_off = 127; 36 static const int m2CountThr_off = 31; 37 static const int m2CountThrLow_off = 63; 38 static const int m1ThreshLowExt_off = 127; 39 static const int m2ThreshLowExt_off = 127; 40 static const int m1ThreshExt_off = 127; 41 static const int m2ThreshExt_off = 127; 42 43 static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0); 44 static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1); 45 static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2); 46 static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3); 47 static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7); 48 49 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) 50 { 51 struct ar5416IniArray *array = &ah->iniBank6; 52 u32 *data = ah->analogBank6Data; 53 int r; 54 55 ENABLE_REGWRITE_BUFFER(ah); 56 57 for (r = 0; r < array->ia_rows; r++) { 58 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 59 DO_DELAY(*writecnt); 60 } 61 62 REGWRITE_BUFFER_FLUSH(ah); 63 } 64 65 /** 66 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 67 * @rfbuf: 68 * @reg32: 69 * @numBits: 70 * @firstBit: 71 * @column: 72 * 73 * Performs analog "swizzling" of parameters into their location. 74 * Used on external AR2133/AR5133 radios. 75 */ 76 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 77 u32 numBits, u32 firstBit, 78 u32 column) 79 { 80 u32 tmp32, mask, arrayEntry, lastBit; 81 int32_t bitPosition, bitsLeft; 82 83 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); 84 arrayEntry = (firstBit - 1) / 8; 85 bitPosition = (firstBit - 1) % 8; 86 bitsLeft = numBits; 87 while (bitsLeft > 0) { 88 lastBit = (bitPosition + bitsLeft > 8) ? 89 8 : bitPosition + bitsLeft; 90 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 91 (column * 8); 92 rfBuf[arrayEntry] &= ~mask; 93 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 94 (column * 8)) & mask; 95 bitsLeft -= 8 - bitPosition; 96 tmp32 = tmp32 >> (8 - bitPosition); 97 bitPosition = 0; 98 arrayEntry++; 99 } 100 } 101 102 /* 103 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing 104 * rf_pwd_icsyndiv. 105 * 106 * Theoretical Rules: 107 * if 2 GHz band 108 * if forceBiasAuto 109 * if synth_freq < 2412 110 * bias = 0 111 * else if 2412 <= synth_freq <= 2422 112 * bias = 1 113 * else // synth_freq > 2422 114 * bias = 2 115 * else if forceBias > 0 116 * bias = forceBias & 7 117 * else 118 * no change, use value from ini file 119 * else 120 * no change, invalid band 121 * 122 * 1st Mod: 123 * 2422 also uses value of 2 124 * <approved> 125 * 126 * 2nd Mod: 127 * Less than 2412 uses value of 0, 2412 and above uses value of 2 128 */ 129 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 130 { 131 struct ath_common *common = ath9k_hw_common(ah); 132 u32 tmp_reg; 133 int reg_writes = 0; 134 u32 new_bias = 0; 135 136 if (!AR_SREV_5416(ah) || synth_freq >= 3000) 137 return; 138 139 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); 140 141 if (synth_freq < 2412) 142 new_bias = 0; 143 else if (synth_freq < 2422) 144 new_bias = 1; 145 else 146 new_bias = 2; 147 148 /* pre-reverse this field */ 149 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); 150 151 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", 152 new_bias, synth_freq); 153 154 /* swizzle rf_pwd_icsyndiv */ 155 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 156 157 /* write Bank 6 with new params */ 158 ar5008_write_bank6(ah, ®_writes); 159 } 160 161 /** 162 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 163 * @ah: atheros hardware structure 164 * @chan: 165 * 166 * For the external AR2133/AR5133 radios, takes the MHz channel value and set 167 * the channel value. Assumes writes enabled to analog bus and bank6 register 168 * cache in ah->analogBank6Data. 169 */ 170 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 171 { 172 struct ath_common *common = ath9k_hw_common(ah); 173 u32 channelSel = 0; 174 u32 bModeSynth = 0; 175 u32 aModeRefSel = 0; 176 u32 reg32 = 0; 177 u16 freq; 178 struct chan_centers centers; 179 180 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 181 freq = centers.synth_center; 182 183 if (freq < 4800) { 184 u32 txctl; 185 186 if (((freq - 2192) % 5) == 0) { 187 channelSel = ((freq - 672) * 2 - 3040) / 10; 188 bModeSynth = 0; 189 } else if (((freq - 2224) % 5) == 0) { 190 channelSel = ((freq - 704) * 2 - 3040) / 10; 191 bModeSynth = 1; 192 } else { 193 ath_err(common, "Invalid channel %u MHz\n", freq); 194 return -EINVAL; 195 } 196 197 channelSel = (channelSel << 2) & 0xff; 198 channelSel = ath9k_hw_reverse_bits(channelSel, 8); 199 200 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 201 if (freq == 2484) { 202 203 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 204 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 205 } else { 206 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 207 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 208 } 209 210 } else if ((freq % 20) == 0 && freq >= 5120) { 211 channelSel = 212 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8); 213 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 214 } else if ((freq % 10) == 0) { 215 channelSel = 216 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8); 217 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 218 aModeRefSel = ath9k_hw_reverse_bits(2, 2); 219 else 220 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 221 } else if ((freq % 5) == 0) { 222 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 223 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 224 } else { 225 ath_err(common, "Invalid channel %u MHz\n", freq); 226 return -EINVAL; 227 } 228 229 ar5008_hw_force_bias(ah, freq); 230 231 reg32 = 232 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 233 (1 << 5) | 0x1; 234 235 REG_WRITE(ah, AR_PHY(0x37), reg32); 236 237 ah->curchan = chan; 238 239 return 0; 240 } 241 242 /** 243 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios 244 * @ah: atheros hardware structure 245 * @chan: 246 * 247 * For non single-chip solutions. Converts to baseband spur frequency given the 248 * input channel frequency and compute register settings below. 249 */ 250 static void ar5008_hw_spur_mitigate(struct ath_hw *ah, 251 struct ath9k_channel *chan) 252 { 253 int bb_spur = AR_NO_SPUR; 254 int bin, cur_bin; 255 int spur_freq_sd; 256 int spur_delta_phase; 257 int denominator; 258 int upper, lower, cur_vit_mask; 259 int tmp, new; 260 int i; 261 static int pilot_mask_reg[4] = { 262 AR_PHY_TIMING7, AR_PHY_TIMING8, 263 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 264 }; 265 static int chan_mask_reg[4] = { 266 AR_PHY_TIMING9, AR_PHY_TIMING10, 267 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 268 }; 269 static int inc[4] = { 0, 100, 0, 0 }; 270 271 int8_t mask_m[123]; 272 int8_t mask_p[123]; 273 int8_t mask_amt; 274 int tmp_mask; 275 int cur_bb_spur; 276 bool is2GHz = IS_CHAN_2GHZ(chan); 277 278 memset(&mask_m, 0, sizeof(int8_t) * 123); 279 memset(&mask_p, 0, sizeof(int8_t) * 123); 280 281 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 282 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); 283 if (AR_NO_SPUR == cur_bb_spur) 284 break; 285 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 286 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 287 bb_spur = cur_bb_spur; 288 break; 289 } 290 } 291 292 if (AR_NO_SPUR == bb_spur) 293 return; 294 295 bin = bb_spur * 32; 296 297 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); 298 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 299 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 300 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 301 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 302 303 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 304 305 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 306 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 307 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 308 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 309 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 310 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 311 312 spur_delta_phase = ((bb_spur * 524288) / 100) & 313 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 314 315 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400; 316 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 317 318 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 319 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 320 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 321 REG_WRITE(ah, AR_PHY_TIMING11, new); 322 323 cur_bin = -6000; 324 upper = bin + 100; 325 lower = bin - 100; 326 327 for (i = 0; i < 4; i++) { 328 int pilot_mask = 0; 329 int chan_mask = 0; 330 int bp = 0; 331 for (bp = 0; bp < 30; bp++) { 332 if ((cur_bin > lower) && (cur_bin < upper)) { 333 pilot_mask = pilot_mask | 0x1 << bp; 334 chan_mask = chan_mask | 0x1 << bp; 335 } 336 cur_bin += 100; 337 } 338 cur_bin += inc[i]; 339 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 340 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 341 } 342 343 cur_vit_mask = 6100; 344 upper = bin + 120; 345 lower = bin - 120; 346 347 for (i = 0; i < 123; i++) { 348 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 349 350 /* workaround for gcc bug #37014 */ 351 volatile int tmp_v = abs(cur_vit_mask - bin); 352 353 if (tmp_v < 75) 354 mask_amt = 1; 355 else 356 mask_amt = 0; 357 if (cur_vit_mask < 0) 358 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 359 else 360 mask_p[cur_vit_mask / 100] = mask_amt; 361 } 362 cur_vit_mask -= 100; 363 } 364 365 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 366 | (mask_m[48] << 26) | (mask_m[49] << 24) 367 | (mask_m[50] << 22) | (mask_m[51] << 20) 368 | (mask_m[52] << 18) | (mask_m[53] << 16) 369 | (mask_m[54] << 14) | (mask_m[55] << 12) 370 | (mask_m[56] << 10) | (mask_m[57] << 8) 371 | (mask_m[58] << 6) | (mask_m[59] << 4) 372 | (mask_m[60] << 2) | (mask_m[61] << 0); 373 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 374 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 375 376 tmp_mask = (mask_m[31] << 28) 377 | (mask_m[32] << 26) | (mask_m[33] << 24) 378 | (mask_m[34] << 22) | (mask_m[35] << 20) 379 | (mask_m[36] << 18) | (mask_m[37] << 16) 380 | (mask_m[48] << 14) | (mask_m[39] << 12) 381 | (mask_m[40] << 10) | (mask_m[41] << 8) 382 | (mask_m[42] << 6) | (mask_m[43] << 4) 383 | (mask_m[44] << 2) | (mask_m[45] << 0); 384 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 385 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 386 387 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 388 | (mask_m[18] << 26) | (mask_m[18] << 24) 389 | (mask_m[20] << 22) | (mask_m[20] << 20) 390 | (mask_m[22] << 18) | (mask_m[22] << 16) 391 | (mask_m[24] << 14) | (mask_m[24] << 12) 392 | (mask_m[25] << 10) | (mask_m[26] << 8) 393 | (mask_m[27] << 6) | (mask_m[28] << 4) 394 | (mask_m[29] << 2) | (mask_m[30] << 0); 395 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 396 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 397 398 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28) 399 | (mask_m[2] << 26) | (mask_m[3] << 24) 400 | (mask_m[4] << 22) | (mask_m[5] << 20) 401 | (mask_m[6] << 18) | (mask_m[7] << 16) 402 | (mask_m[8] << 14) | (mask_m[9] << 12) 403 | (mask_m[10] << 10) | (mask_m[11] << 8) 404 | (mask_m[12] << 6) | (mask_m[13] << 4) 405 | (mask_m[14] << 2) | (mask_m[15] << 0); 406 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 407 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 408 409 tmp_mask = (mask_p[15] << 28) 410 | (mask_p[14] << 26) | (mask_p[13] << 24) 411 | (mask_p[12] << 22) | (mask_p[11] << 20) 412 | (mask_p[10] << 18) | (mask_p[9] << 16) 413 | (mask_p[8] << 14) | (mask_p[7] << 12) 414 | (mask_p[6] << 10) | (mask_p[5] << 8) 415 | (mask_p[4] << 6) | (mask_p[3] << 4) 416 | (mask_p[2] << 2) | (mask_p[1] << 0); 417 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 418 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 419 420 tmp_mask = (mask_p[30] << 28) 421 | (mask_p[29] << 26) | (mask_p[28] << 24) 422 | (mask_p[27] << 22) | (mask_p[26] << 20) 423 | (mask_p[25] << 18) | (mask_p[24] << 16) 424 | (mask_p[23] << 14) | (mask_p[22] << 12) 425 | (mask_p[21] << 10) | (mask_p[20] << 8) 426 | (mask_p[19] << 6) | (mask_p[18] << 4) 427 | (mask_p[17] << 2) | (mask_p[16] << 0); 428 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 429 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 430 431 tmp_mask = (mask_p[45] << 28) 432 | (mask_p[44] << 26) | (mask_p[43] << 24) 433 | (mask_p[42] << 22) | (mask_p[41] << 20) 434 | (mask_p[40] << 18) | (mask_p[39] << 16) 435 | (mask_p[38] << 14) | (mask_p[37] << 12) 436 | (mask_p[36] << 10) | (mask_p[35] << 8) 437 | (mask_p[34] << 6) | (mask_p[33] << 4) 438 | (mask_p[32] << 2) | (mask_p[31] << 0); 439 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 440 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 441 442 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 443 | (mask_p[59] << 26) | (mask_p[58] << 24) 444 | (mask_p[57] << 22) | (mask_p[56] << 20) 445 | (mask_p[55] << 18) | (mask_p[54] << 16) 446 | (mask_p[53] << 14) | (mask_p[52] << 12) 447 | (mask_p[51] << 10) | (mask_p[50] << 8) 448 | (mask_p[49] << 6) | (mask_p[48] << 4) 449 | (mask_p[47] << 2) | (mask_p[46] << 0); 450 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 451 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 452 } 453 454 /** 455 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming 456 * @ah: atheros hardware structure 457 * 458 * Only required for older devices with external AR2133/AR5133 radios. 459 */ 460 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah) 461 { 462 int size = ah->iniBank6.ia_rows * sizeof(u32); 463 464 if (AR_SREV_9280_20_OR_LATER(ah)) 465 return 0; 466 467 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL); 468 if (!ah->analogBank6Data) 469 return -ENOMEM; 470 471 return 0; 472 } 473 474 475 /* * 476 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM 477 * @ah: atheros hardware structure 478 * @chan: 479 * @modesIndex: 480 * 481 * Used for the external AR2133/AR5133 radios. 482 * 483 * Reads the EEPROM header info from the device structure and programs 484 * all rf registers. This routine requires access to the analog 485 * rf device. This is not required for single-chip devices. 486 */ 487 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah, 488 struct ath9k_channel *chan, 489 u16 modesIndex) 490 { 491 u32 eepMinorRev; 492 u32 ob5GHz = 0, db5GHz = 0; 493 u32 ob2GHz = 0, db2GHz = 0; 494 int regWrites = 0; 495 int i; 496 497 /* 498 * Software does not need to program bank data 499 * for single chip devices, that is AR9280 or anything 500 * after that. 501 */ 502 if (AR_SREV_9280_20_OR_LATER(ah)) 503 return true; 504 505 /* Setup rf parameters */ 506 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 507 508 for (i = 0; i < ah->iniBank6.ia_rows; i++) 509 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex); 510 511 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ 512 if (eepMinorRev >= 2) { 513 if (IS_CHAN_2GHZ(chan)) { 514 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 515 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 516 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 517 ob2GHz, 3, 197, 0); 518 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 519 db2GHz, 3, 194, 0); 520 } else { 521 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 522 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 523 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 524 ob5GHz, 3, 203, 0); 525 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, 526 db5GHz, 3, 200, 0); 527 } 528 } 529 530 /* Write Analog registers */ 531 REG_WRITE_ARRAY(&bank0, 1, regWrites); 532 REG_WRITE_ARRAY(&bank1, 1, regWrites); 533 REG_WRITE_ARRAY(&bank2, 1, regWrites); 534 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites); 535 ar5008_write_bank6(ah, ®Writes); 536 REG_WRITE_ARRAY(&bank7, 1, regWrites); 537 538 return true; 539 } 540 541 static void ar5008_hw_init_bb(struct ath_hw *ah, 542 struct ath9k_channel *chan) 543 { 544 u32 synthDelay; 545 546 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 547 548 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 549 550 ath9k_hw_synth_delay(ah, chan, synthDelay); 551 } 552 553 static void ar5008_hw_init_chain_masks(struct ath_hw *ah) 554 { 555 int rx_chainmask, tx_chainmask; 556 557 rx_chainmask = ah->rxchainmask; 558 tx_chainmask = ah->txchainmask; 559 560 561 switch (rx_chainmask) { 562 case 0x5: 563 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 564 AR_PHY_SWAP_ALT_CHAIN); 565 case 0x3: 566 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { 567 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 568 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 569 break; 570 } 571 case 0x1: 572 case 0x2: 573 case 0x7: 574 ENABLE_REGWRITE_BUFFER(ah); 575 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 576 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 577 break; 578 default: 579 ENABLE_REGWRITE_BUFFER(ah); 580 break; 581 } 582 583 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 584 585 REGWRITE_BUFFER_FLUSH(ah); 586 587 if (tx_chainmask == 0x5) { 588 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 589 AR_PHY_SWAP_ALT_CHAIN); 590 } 591 if (AR_SREV_9100(ah)) 592 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 593 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 594 } 595 596 static void ar5008_hw_override_ini(struct ath_hw *ah, 597 struct ath9k_channel *chan) 598 { 599 u32 val; 600 601 /* 602 * Set the RX_ABORT and RX_DIS and clear if off only after 603 * RXE is set for MAC. This prevents frames with corrupted 604 * descriptor status. 605 */ 606 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 607 608 if (AR_SREV_9280_20_OR_LATER(ah)) { 609 /* 610 * For AR9280 and above, there is a new feature that allows 611 * Multicast search based on both MAC Address and Key ID. 612 * By default, this feature is enabled. But since the driver 613 * is not using this feature, we switch it off; otherwise 614 * multicast search based on MAC addr only will fail. 615 */ 616 val = REG_READ(ah, AR_PCU_MISC_MODE2) & 617 (~AR_ADHOC_MCAST_KEYID_ENABLE); 618 619 if (!AR_SREV_9271(ah)) 620 val &= ~AR_PCU_MISC_MODE2_HWWAR1; 621 622 if (AR_SREV_9287_11_OR_LATER(ah)) 623 val = val & (~AR_PCU_MISC_MODE2_HWWAR2); 624 625 val |= AR_PCU_MISC_MODE2_CFP_IGNORE; 626 627 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); 628 } 629 630 if (AR_SREV_9280_20_OR_LATER(ah)) 631 return; 632 /* 633 * Disable BB clock gating 634 * Necessary to avoid issues on AR5416 2.0 635 */ 636 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 637 638 /* 639 * Disable RIFS search on some chips to avoid baseband 640 * hang issues. 641 */ 642 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { 643 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); 644 val &= ~AR_PHY_RIFS_INIT_DELAY; 645 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); 646 } 647 } 648 649 static void ar5008_hw_set_channel_regs(struct ath_hw *ah, 650 struct ath9k_channel *chan) 651 { 652 u32 phymode; 653 u32 enableDacFifo = 0; 654 655 if (AR_SREV_9285_12_OR_LATER(ah)) 656 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 657 AR_PHY_FC_ENABLE_DAC_FIFO); 658 659 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 660 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo; 661 662 if (IS_CHAN_HT40(chan)) { 663 phymode |= AR_PHY_FC_DYN2040_EN; 664 665 if (IS_CHAN_HT40PLUS(chan)) 666 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 667 668 } 669 REG_WRITE(ah, AR_PHY_TURBO, phymode); 670 671 ath9k_hw_set11nmac2040(ah, chan); 672 673 ENABLE_REGWRITE_BUFFER(ah); 674 675 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 676 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 677 678 REGWRITE_BUFFER_FLUSH(ah); 679 } 680 681 682 static int ar5008_hw_process_ini(struct ath_hw *ah, 683 struct ath9k_channel *chan) 684 { 685 struct ath_common *common = ath9k_hw_common(ah); 686 int i, regWrites = 0; 687 u32 modesIndex, freqIndex; 688 689 if (IS_CHAN_5GHZ(chan)) { 690 freqIndex = 1; 691 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; 692 } else { 693 freqIndex = 2; 694 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; 695 } 696 697 /* 698 * Set correct baseband to analog shift setting to 699 * access analog chips. 700 */ 701 REG_WRITE(ah, AR_PHY(0), 0x00000007); 702 703 /* Write ADDAC shifts */ 704 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 705 if (ah->eep_ops->set_addac) 706 ah->eep_ops->set_addac(ah, chan); 707 708 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); 709 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 710 711 ENABLE_REGWRITE_BUFFER(ah); 712 713 for (i = 0; i < ah->iniModes.ia_rows; i++) { 714 u32 reg = INI_RA(&ah->iniModes, i, 0); 715 u32 val = INI_RA(&ah->iniModes, i, modesIndex); 716 717 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup) 718 val &= ~AR_AN_TOP2_PWDCLKIND; 719 720 REG_WRITE(ah, reg, val); 721 722 if (reg >= 0x7800 && reg < 0x78a0 723 && ah->config.analog_shiftreg 724 && (common->bus_ops->ath_bus_type != ATH_USB)) { 725 udelay(100); 726 } 727 728 DO_DELAY(regWrites); 729 } 730 731 REGWRITE_BUFFER_FLUSH(ah); 732 733 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah)) 734 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); 735 736 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) || 737 AR_SREV_9287_11_OR_LATER(ah)) 738 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 739 740 if (AR_SREV_9271_10(ah)) { 741 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); 742 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa); 743 } 744 745 ENABLE_REGWRITE_BUFFER(ah); 746 747 /* Write common array parameters */ 748 for (i = 0; i < ah->iniCommon.ia_rows; i++) { 749 u32 reg = INI_RA(&ah->iniCommon, i, 0); 750 u32 val = INI_RA(&ah->iniCommon, i, 1); 751 752 REG_WRITE(ah, reg, val); 753 754 if (reg >= 0x7800 && reg < 0x78a0 755 && ah->config.analog_shiftreg 756 && (common->bus_ops->ath_bus_type != ATH_USB)) { 757 udelay(100); 758 } 759 760 DO_DELAY(regWrites); 761 } 762 763 REGWRITE_BUFFER_FLUSH(ah); 764 765 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); 766 767 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 768 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, 769 regWrites); 770 771 ar5008_hw_override_ini(ah, chan); 772 ar5008_hw_set_channel_regs(ah, chan); 773 ar5008_hw_init_chain_masks(ah); 774 ath9k_olc_init(ah); 775 ath9k_hw_apply_txpower(ah, chan, false); 776 777 /* Write analog registers */ 778 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 779 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n"); 780 return -EIO; 781 } 782 783 return 0; 784 } 785 786 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) 787 { 788 u32 rfMode = 0; 789 790 if (chan == NULL) 791 return; 792 793 if (IS_CHAN_2GHZ(chan)) 794 rfMode |= AR_PHY_MODE_DYNAMIC; 795 else 796 rfMode |= AR_PHY_MODE_OFDM; 797 798 if (!AR_SREV_9280_20_OR_LATER(ah)) 799 rfMode |= (IS_CHAN_5GHZ(chan)) ? 800 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 801 802 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 803 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); 804 805 REG_WRITE(ah, AR_PHY_MODE, rfMode); 806 } 807 808 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah) 809 { 810 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 811 } 812 813 static void ar5008_hw_set_delta_slope(struct ath_hw *ah, 814 struct ath9k_channel *chan) 815 { 816 u32 coef_scaled, ds_coef_exp, ds_coef_man; 817 u32 clockMhzScaled = 0x64000000; 818 struct chan_centers centers; 819 820 if (IS_CHAN_HALF_RATE(chan)) 821 clockMhzScaled = clockMhzScaled >> 1; 822 else if (IS_CHAN_QUARTER_RATE(chan)) 823 clockMhzScaled = clockMhzScaled >> 2; 824 825 ath9k_hw_get_channel_centers(ah, chan, ¢ers); 826 coef_scaled = clockMhzScaled / centers.synth_center; 827 828 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 829 &ds_coef_exp); 830 831 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 832 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 833 REG_RMW_FIELD(ah, AR_PHY_TIMING3, 834 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 835 836 coef_scaled = (9 * coef_scaled) / 10; 837 838 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, 839 &ds_coef_exp); 840 841 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 842 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 843 REG_RMW_FIELD(ah, AR_PHY_HALFGI, 844 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 845 } 846 847 static bool ar5008_hw_rfbus_req(struct ath_hw *ah) 848 { 849 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 850 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 851 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); 852 } 853 854 static void ar5008_hw_rfbus_done(struct ath_hw *ah) 855 { 856 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 857 858 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); 859 860 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 861 } 862 863 static void ar5008_restore_chainmask(struct ath_hw *ah) 864 { 865 int rx_chainmask = ah->rxchainmask; 866 867 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 868 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 869 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 870 } 871 } 872 873 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah, 874 struct ath9k_channel *chan) 875 { 876 u32 pll; 877 878 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 879 880 if (chan && IS_CHAN_HALF_RATE(chan)) 881 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 882 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 883 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 884 885 if (chan && IS_CHAN_5GHZ(chan)) 886 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 887 else 888 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 889 890 return pll; 891 } 892 893 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah, 894 struct ath9k_channel *chan) 895 { 896 u32 pll; 897 898 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 899 900 if (chan && IS_CHAN_HALF_RATE(chan)) 901 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 902 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 903 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 904 905 if (chan && IS_CHAN_5GHZ(chan)) 906 pll |= SM(0xa, AR_RTC_PLL_DIV); 907 else 908 pll |= SM(0xb, AR_RTC_PLL_DIV); 909 910 return pll; 911 } 912 913 static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 914 enum ath9k_ani_cmd cmd, 915 int param) 916 { 917 struct ath_common *common = ath9k_hw_common(ah); 918 struct ath9k_channel *chan = ah->curchan; 919 struct ar5416AniState *aniState = &ah->ani; 920 s32 value; 921 922 switch (cmd & ah->ani_function) { 923 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ 924 /* 925 * on == 1 means ofdm weak signal detection is ON 926 * on == 1 is the default, for less noise immunity 927 * 928 * on == 0 means ofdm weak signal detection is OFF 929 * on == 0 means more noise imm 930 */ 931 u32 on = param ? 1 : 0; 932 /* 933 * make register setting for default 934 * (weak sig detect ON) come from INI file 935 */ 936 int m1ThreshLow = on ? 937 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; 938 int m2ThreshLow = on ? 939 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; 940 int m1Thresh = on ? 941 aniState->iniDef.m1Thresh : m1Thresh_off; 942 int m2Thresh = on ? 943 aniState->iniDef.m2Thresh : m2Thresh_off; 944 int m2CountThr = on ? 945 aniState->iniDef.m2CountThr : m2CountThr_off; 946 int m2CountThrLow = on ? 947 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; 948 int m1ThreshLowExt = on ? 949 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; 950 int m2ThreshLowExt = on ? 951 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; 952 int m1ThreshExt = on ? 953 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; 954 int m2ThreshExt = on ? 955 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; 956 957 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 958 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 959 m1ThreshLow); 960 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 961 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 962 m2ThreshLow); 963 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 964 AR_PHY_SFCORR_M1_THRESH, m1Thresh); 965 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 966 AR_PHY_SFCORR_M2_THRESH, m2Thresh); 967 REG_RMW_FIELD(ah, AR_PHY_SFCORR, 968 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); 969 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, 970 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 971 m2CountThrLow); 972 973 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 974 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); 975 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 976 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); 977 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 978 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); 979 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, 980 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); 981 982 if (on) 983 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, 984 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 985 else 986 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 987 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 988 989 if (on != aniState->ofdmWeakSigDetect) { 990 ath_dbg(common, ANI, 991 "** ch %d: ofdm weak signal: %s=>%s\n", 992 chan->channel, 993 aniState->ofdmWeakSigDetect ? 994 "on" : "off", 995 on ? "on" : "off"); 996 if (on) 997 ah->stats.ast_ani_ofdmon++; 998 else 999 ah->stats.ast_ani_ofdmoff++; 1000 aniState->ofdmWeakSigDetect = on; 1001 } 1002 break; 1003 } 1004 case ATH9K_ANI_FIRSTEP_LEVEL:{ 1005 u32 level = param; 1006 1007 value = level * 2; 1008 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 1009 AR_PHY_FIND_SIG_FIRSTEP, value); 1010 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, 1011 AR_PHY_FIND_SIG_FIRSTEP_LOW, value); 1012 1013 if (level != aniState->firstepLevel) { 1014 ath_dbg(common, ANI, 1015 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", 1016 chan->channel, 1017 aniState->firstepLevel, 1018 level, 1019 ATH9K_ANI_FIRSTEP_LVL, 1020 value, 1021 aniState->iniDef.firstep); 1022 ath_dbg(common, ANI, 1023 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", 1024 chan->channel, 1025 aniState->firstepLevel, 1026 level, 1027 ATH9K_ANI_FIRSTEP_LVL, 1028 value, 1029 aniState->iniDef.firstepLow); 1030 if (level > aniState->firstepLevel) 1031 ah->stats.ast_ani_stepup++; 1032 else if (level < aniState->firstepLevel) 1033 ah->stats.ast_ani_stepdown++; 1034 aniState->firstepLevel = level; 1035 } 1036 break; 1037 } 1038 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ 1039 u32 level = param; 1040 1041 value = (level + 1) * 2; 1042 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 1043 AR_PHY_TIMING5_CYCPWR_THR1, value); 1044 1045 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, 1046 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1); 1047 1048 if (level != aniState->spurImmunityLevel) { 1049 ath_dbg(common, ANI, 1050 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", 1051 chan->channel, 1052 aniState->spurImmunityLevel, 1053 level, 1054 ATH9K_ANI_SPUR_IMMUNE_LVL, 1055 value, 1056 aniState->iniDef.cycpwrThr1); 1057 ath_dbg(common, ANI, 1058 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", 1059 chan->channel, 1060 aniState->spurImmunityLevel, 1061 level, 1062 ATH9K_ANI_SPUR_IMMUNE_LVL, 1063 value, 1064 aniState->iniDef.cycpwrThr1Ext); 1065 if (level > aniState->spurImmunityLevel) 1066 ah->stats.ast_ani_spurup++; 1067 else if (level < aniState->spurImmunityLevel) 1068 ah->stats.ast_ani_spurdown++; 1069 aniState->spurImmunityLevel = level; 1070 } 1071 break; 1072 } 1073 case ATH9K_ANI_MRC_CCK: 1074 /* 1075 * You should not see this as AR5008, AR9001, AR9002 1076 * does not have hardware support for MRC CCK. 1077 */ 1078 WARN_ON(1); 1079 break; 1080 default: 1081 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); 1082 return false; 1083 } 1084 1085 ath_dbg(common, ANI, 1086 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1087 aniState->spurImmunityLevel, 1088 aniState->ofdmWeakSigDetect ? "on" : "off", 1089 aniState->firstepLevel, 1090 aniState->mrcCCK ? "on" : "off", 1091 aniState->listenTime, 1092 aniState->ofdmPhyErrCount, 1093 aniState->cckPhyErrCount); 1094 return true; 1095 } 1096 1097 static void ar5008_hw_do_getnf(struct ath_hw *ah, 1098 int16_t nfarray[NUM_NF_READINGS]) 1099 { 1100 int16_t nf; 1101 1102 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); 1103 nfarray[0] = sign_extend32(nf, 8); 1104 1105 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); 1106 nfarray[1] = sign_extend32(nf, 8); 1107 1108 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); 1109 nfarray[2] = sign_extend32(nf, 8); 1110 1111 if (!IS_CHAN_HT40(ah->curchan)) 1112 return; 1113 1114 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); 1115 nfarray[3] = sign_extend32(nf, 8); 1116 1117 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); 1118 nfarray[4] = sign_extend32(nf, 8); 1119 1120 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); 1121 nfarray[5] = sign_extend32(nf, 8); 1122 } 1123 1124 /* 1125 * Initialize the ANI register values with default (ini) values. 1126 * This routine is called during a (full) hardware reset after 1127 * all the registers are initialised from the INI. 1128 */ 1129 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) 1130 { 1131 struct ath_common *common = ath9k_hw_common(ah); 1132 struct ath9k_channel *chan = ah->curchan; 1133 struct ar5416AniState *aniState = &ah->ani; 1134 struct ath9k_ani_default *iniDef; 1135 u32 val; 1136 1137 iniDef = &aniState->iniDef; 1138 1139 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", 1140 ah->hw_version.macVersion, 1141 ah->hw_version.macRev, 1142 ah->opmode, 1143 chan->channel); 1144 1145 val = REG_READ(ah, AR_PHY_SFCORR); 1146 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); 1147 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); 1148 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); 1149 1150 val = REG_READ(ah, AR_PHY_SFCORR_LOW); 1151 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); 1152 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); 1153 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); 1154 1155 val = REG_READ(ah, AR_PHY_SFCORR_EXT); 1156 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); 1157 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); 1158 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); 1159 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); 1160 iniDef->firstep = REG_READ_FIELD(ah, 1161 AR_PHY_FIND_SIG, 1162 AR_PHY_FIND_SIG_FIRSTEP); 1163 iniDef->firstepLow = REG_READ_FIELD(ah, 1164 AR_PHY_FIND_SIG_LOW, 1165 AR_PHY_FIND_SIG_FIRSTEP_LOW); 1166 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, 1167 AR_PHY_TIMING5, 1168 AR_PHY_TIMING5_CYCPWR_THR1); 1169 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, 1170 AR_PHY_EXT_CCA, 1171 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1172 1173 /* these levels just got reset to defaults by the INI */ 1174 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 1175 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 1176 aniState->ofdmWeakSigDetect = true; 1177 aniState->mrcCCK = false; /* not available on pre AR9003 */ 1178 } 1179 1180 static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1181 { 1182 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 1183 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 1184 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 1185 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 1186 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 1187 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 1188 } 1189 1190 static void ar5008_hw_set_radar_params(struct ath_hw *ah, 1191 struct ath_hw_radar_conf *conf) 1192 { 1193 u32 radar_0 = 0, radar_1; 1194 1195 if (!conf) { 1196 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); 1197 return; 1198 } 1199 1200 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; 1201 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); 1202 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); 1203 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); 1204 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); 1205 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); 1206 1207 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); 1208 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH | 1209 AR_PHY_RADAR_1_RELPWR_THRESH); 1210 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; 1211 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; 1212 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); 1213 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); 1214 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); 1215 1216 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); 1217 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); 1218 if (conf->ext_channel) 1219 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1220 else 1221 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); 1222 } 1223 1224 static void ar5008_hw_set_radar_conf(struct ath_hw *ah) 1225 { 1226 struct ath_hw_radar_conf *conf = &ah->radar_conf; 1227 1228 conf->fir_power = -33; 1229 conf->radar_rssi = 20; 1230 conf->pulse_height = 10; 1231 conf->pulse_rssi = 15; 1232 conf->pulse_inband = 15; 1233 conf->pulse_maxlen = 255; 1234 conf->pulse_inband_step = 12; 1235 conf->radar_inband = 8; 1236 } 1237 1238 int ar5008_hw_attach_phy_ops(struct ath_hw *ah) 1239 { 1240 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 1241 static const u32 ar5416_cca_regs[6] = { 1242 AR_PHY_CCA, 1243 AR_PHY_CH1_CCA, 1244 AR_PHY_CH2_CCA, 1245 AR_PHY_EXT_CCA, 1246 AR_PHY_CH1_EXT_CCA, 1247 AR_PHY_CH2_EXT_CCA 1248 }; 1249 int ret; 1250 1251 ret = ar5008_hw_rf_alloc_ext_banks(ah); 1252 if (ret) 1253 return ret; 1254 1255 priv_ops->rf_set_freq = ar5008_hw_set_channel; 1256 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate; 1257 1258 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs; 1259 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs; 1260 priv_ops->init_bb = ar5008_hw_init_bb; 1261 priv_ops->process_ini = ar5008_hw_process_ini; 1262 priv_ops->set_rfmode = ar5008_hw_set_rfmode; 1263 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive; 1264 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope; 1265 priv_ops->rfbus_req = ar5008_hw_rfbus_req; 1266 priv_ops->rfbus_done = ar5008_hw_rfbus_done; 1267 priv_ops->restore_chainmask = ar5008_restore_chainmask; 1268 priv_ops->do_getnf = ar5008_hw_do_getnf; 1269 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1270 1271 priv_ops->ani_control = ar5008_hw_ani_control_new; 1272 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs; 1273 1274 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1275 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1276 else 1277 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control; 1278 1279 ar5008_hw_set_nf_limits(ah); 1280 ar5008_hw_set_radar_conf(ah); 1281 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs)); 1282 return 0; 1283 } 1284