1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include "hw.h" 20 #include "hw-ops.h" 21 22 struct ani_ofdm_level_entry { 23 int spur_immunity_level; 24 int fir_step_level; 25 int ofdm_weak_signal_on; 26 }; 27 28 /* values here are relative to the INI */ 29 30 /* 31 * Legend: 32 * 33 * SI: Spur immunity 34 * FS: FIR Step 35 * WS: OFDM / CCK Weak Signal detection 36 * MRC-CCK: Maximal Ratio Combining for CCK 37 */ 38 39 static const struct ani_ofdm_level_entry ofdm_level_table[] = { 40 /* SI FS WS */ 41 { 0, 0, 1 }, /* lvl 0 */ 42 { 1, 1, 1 }, /* lvl 1 */ 43 { 2, 2, 1 }, /* lvl 2 */ 44 { 3, 2, 1 }, /* lvl 3 (default) */ 45 { 4, 3, 1 }, /* lvl 4 */ 46 { 5, 4, 1 }, /* lvl 5 */ 47 { 6, 5, 1 }, /* lvl 6 */ 48 { 7, 6, 1 }, /* lvl 7 */ 49 { 7, 7, 1 }, /* lvl 8 */ 50 { 7, 8, 0 } /* lvl 9 */ 51 }; 52 #define ATH9K_ANI_OFDM_NUM_LEVEL \ 53 ARRAY_SIZE(ofdm_level_table) 54 #define ATH9K_ANI_OFDM_MAX_LEVEL \ 55 (ATH9K_ANI_OFDM_NUM_LEVEL-1) 56 #define ATH9K_ANI_OFDM_DEF_LEVEL \ 57 3 /* default level - matches the INI settings */ 58 59 /* 60 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm. 61 * With OFDM for single stream you just add up all antenna inputs, you're 62 * only interested in what you get after FFT. Signal aligment is also not 63 * required for OFDM because any phase difference adds up in the frequency 64 * domain. 65 * 66 * MRC requires extra work for use with CCK. You need to align the antenna 67 * signals from the different antenna before you can add the signals together. 68 * You need aligment of signals as CCK is in time domain, so addition can cancel 69 * your signal completely if phase is 180 degrees (think of adding sine waves). 70 * You also need to remove noise before the addition and this is where ANI 71 * MRC CCK comes into play. One of the antenna inputs may be stronger but 72 * lower SNR, so just adding after alignment can be dangerous. 73 * 74 * Regardless of alignment in time, the antenna signals add constructively after 75 * FFT and improve your reception. For more information: 76 * 77 * http://en.wikipedia.org/wiki/Maximal-ratio_combining 78 */ 79 80 struct ani_cck_level_entry { 81 int fir_step_level; 82 int mrc_cck_on; 83 }; 84 85 static const struct ani_cck_level_entry cck_level_table[] = { 86 /* FS MRC-CCK */ 87 { 0, 1 }, /* lvl 0 */ 88 { 1, 1 }, /* lvl 1 */ 89 { 2, 1 }, /* lvl 2 (default) */ 90 { 3, 1 }, /* lvl 3 */ 91 { 4, 0 }, /* lvl 4 */ 92 { 5, 0 }, /* lvl 5 */ 93 { 6, 0 }, /* lvl 6 */ 94 { 7, 0 }, /* lvl 7 (only for high rssi) */ 95 { 8, 0 } /* lvl 8 (only for high rssi) */ 96 }; 97 98 #define ATH9K_ANI_CCK_NUM_LEVEL \ 99 ARRAY_SIZE(cck_level_table) 100 #define ATH9K_ANI_CCK_MAX_LEVEL \ 101 (ATH9K_ANI_CCK_NUM_LEVEL-1) 102 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \ 103 (ATH9K_ANI_CCK_NUM_LEVEL-3) 104 #define ATH9K_ANI_CCK_DEF_LEVEL \ 105 2 /* default level - matches the INI settings */ 106 107 static bool use_new_ani(struct ath_hw *ah) 108 { 109 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani; 110 } 111 112 static void ath9k_hw_update_mibstats(struct ath_hw *ah, 113 struct ath9k_mib_stats *stats) 114 { 115 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); 116 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); 117 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); 118 stats->rts_good += REG_READ(ah, AR_RTS_OK); 119 stats->beacons += REG_READ(ah, AR_BEACON_CNT); 120 } 121 122 static void ath9k_ani_restart(struct ath_hw *ah) 123 { 124 struct ar5416AniState *aniState; 125 struct ath_common *common = ath9k_hw_common(ah); 126 u32 ofdm_base = 0, cck_base = 0; 127 128 if (!DO_ANI(ah)) 129 return; 130 131 aniState = &ah->curchan->ani; 132 aniState->listenTime = 0; 133 134 if (!use_new_ani(ah)) { 135 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high; 136 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; 137 } 138 139 ath_dbg(common, ATH_DBG_ANI, 140 "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base); 141 142 ENABLE_REGWRITE_BUFFER(ah); 143 144 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); 145 REG_WRITE(ah, AR_PHY_ERR_2, cck_base); 146 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 147 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 148 149 REGWRITE_BUFFER_FLUSH(ah); 150 151 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 152 153 aniState->ofdmPhyErrCount = 0; 154 aniState->cckPhyErrCount = 0; 155 } 156 157 static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah) 158 { 159 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 160 struct ar5416AniState *aniState; 161 int32_t rssi; 162 163 aniState = &ah->curchan->ani; 164 165 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 166 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 167 aniState->noiseImmunityLevel + 1)) { 168 return; 169 } 170 } 171 172 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) { 173 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 174 aniState->spurImmunityLevel + 1)) { 175 return; 176 } 177 } 178 179 if (ah->opmode == NL80211_IFTYPE_AP) { 180 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 181 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 182 aniState->firstepLevel + 1); 183 } 184 return; 185 } 186 rssi = BEACON_RSSI(ah); 187 if (rssi > aniState->rssiThrHigh) { 188 if (!aniState->ofdmWeakSigDetectOff) { 189 if (ath9k_hw_ani_control(ah, 190 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 191 false)) { 192 ath9k_hw_ani_control(ah, 193 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); 194 return; 195 } 196 } 197 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 198 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 199 aniState->firstepLevel + 1); 200 return; 201 } 202 } else if (rssi > aniState->rssiThrLow) { 203 if (aniState->ofdmWeakSigDetectOff) 204 ath9k_hw_ani_control(ah, 205 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 206 true); 207 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) 208 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 209 aniState->firstepLevel + 1); 210 return; 211 } else { 212 if ((conf->channel->band == IEEE80211_BAND_2GHZ) && 213 !conf_is_ht(conf)) { 214 if (!aniState->ofdmWeakSigDetectOff) 215 ath9k_hw_ani_control(ah, 216 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 217 false); 218 if (aniState->firstepLevel > 0) 219 ath9k_hw_ani_control(ah, 220 ATH9K_ANI_FIRSTEP_LEVEL, 0); 221 return; 222 } 223 } 224 } 225 226 static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah) 227 { 228 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 229 struct ar5416AniState *aniState; 230 int32_t rssi; 231 232 aniState = &ah->curchan->ani; 233 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 234 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 235 aniState->noiseImmunityLevel + 1)) { 236 return; 237 } 238 } 239 if (ah->opmode == NL80211_IFTYPE_AP) { 240 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 241 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 242 aniState->firstepLevel + 1); 243 } 244 return; 245 } 246 rssi = BEACON_RSSI(ah); 247 if (rssi > aniState->rssiThrLow) { 248 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) 249 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 250 aniState->firstepLevel + 1); 251 } else { 252 if ((conf->channel->band == IEEE80211_BAND_2GHZ) && 253 !conf_is_ht(conf)) { 254 if (aniState->firstepLevel > 0) 255 ath9k_hw_ani_control(ah, 256 ATH9K_ANI_FIRSTEP_LEVEL, 0); 257 } 258 } 259 } 260 261 /* Adjust the OFDM Noise Immunity Level */ 262 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) 263 { 264 struct ar5416AniState *aniState = &ah->curchan->ani; 265 struct ath_common *common = ath9k_hw_common(ah); 266 const struct ani_ofdm_level_entry *entry_ofdm; 267 const struct ani_cck_level_entry *entry_cck; 268 269 aniState->noiseFloor = BEACON_RSSI(ah); 270 271 ath_dbg(common, ATH_DBG_ANI, 272 "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 273 aniState->ofdmNoiseImmunityLevel, 274 immunityLevel, aniState->noiseFloor, 275 aniState->rssiThrLow, aniState->rssiThrHigh); 276 277 if (aniState->update_ani) 278 aniState->ofdmNoiseImmunityLevel = immunityLevel; 279 280 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 281 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 282 283 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level) 284 ath9k_hw_ani_control(ah, 285 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 286 entry_ofdm->spur_immunity_level); 287 288 if (aniState->firstepLevel != entry_ofdm->fir_step_level && 289 entry_ofdm->fir_step_level >= entry_cck->fir_step_level) 290 ath9k_hw_ani_control(ah, 291 ATH9K_ANI_FIRSTEP_LEVEL, 292 entry_ofdm->fir_step_level); 293 294 if ((ah->opmode != NL80211_IFTYPE_STATION && 295 ah->opmode != NL80211_IFTYPE_ADHOC) || 296 aniState->noiseFloor <= aniState->rssiThrHigh) { 297 if (aniState->ofdmWeakSigDetectOff) 298 /* force on ofdm weak sig detect */ 299 ath9k_hw_ani_control(ah, 300 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 301 true); 302 else if (aniState->ofdmWeakSigDetectOff == 303 entry_ofdm->ofdm_weak_signal_on) 304 ath9k_hw_ani_control(ah, 305 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 306 entry_ofdm->ofdm_weak_signal_on); 307 } 308 } 309 310 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) 311 { 312 struct ar5416AniState *aniState; 313 314 if (!DO_ANI(ah)) 315 return; 316 317 if (!use_new_ani(ah)) { 318 ath9k_hw_ani_ofdm_err_trigger_old(ah); 319 return; 320 } 321 322 aniState = &ah->curchan->ani; 323 324 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL) 325 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1); 326 } 327 328 /* 329 * Set the ANI settings to match an CCK level. 330 */ 331 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) 332 { 333 struct ar5416AniState *aniState = &ah->curchan->ani; 334 struct ath_common *common = ath9k_hw_common(ah); 335 const struct ani_ofdm_level_entry *entry_ofdm; 336 const struct ani_cck_level_entry *entry_cck; 337 338 aniState->noiseFloor = BEACON_RSSI(ah); 339 ath_dbg(common, ATH_DBG_ANI, 340 "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 341 aniState->cckNoiseImmunityLevel, immunityLevel, 342 aniState->noiseFloor, aniState->rssiThrLow, 343 aniState->rssiThrHigh); 344 345 if ((ah->opmode == NL80211_IFTYPE_STATION || 346 ah->opmode == NL80211_IFTYPE_ADHOC) && 347 aniState->noiseFloor <= aniState->rssiThrLow && 348 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI) 349 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI; 350 351 if (aniState->update_ani) 352 aniState->cckNoiseImmunityLevel = immunityLevel; 353 354 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 355 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 356 357 if (aniState->firstepLevel != entry_cck->fir_step_level && 358 entry_cck->fir_step_level >= entry_ofdm->fir_step_level) 359 ath9k_hw_ani_control(ah, 360 ATH9K_ANI_FIRSTEP_LEVEL, 361 entry_cck->fir_step_level); 362 363 /* Skip MRC CCK for pre AR9003 families */ 364 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah)) 365 return; 366 367 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on) 368 ath9k_hw_ani_control(ah, 369 ATH9K_ANI_MRC_CCK, 370 entry_cck->mrc_cck_on); 371 } 372 373 static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) 374 { 375 struct ar5416AniState *aniState; 376 377 if (!DO_ANI(ah)) 378 return; 379 380 if (!use_new_ani(ah)) { 381 ath9k_hw_ani_cck_err_trigger_old(ah); 382 return; 383 } 384 385 aniState = &ah->curchan->ani; 386 387 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL) 388 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1); 389 } 390 391 static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah) 392 { 393 struct ar5416AniState *aniState; 394 int32_t rssi; 395 396 aniState = &ah->curchan->ani; 397 398 if (ah->opmode == NL80211_IFTYPE_AP) { 399 if (aniState->firstepLevel > 0) { 400 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 401 aniState->firstepLevel - 1)) 402 return; 403 } 404 } else { 405 rssi = BEACON_RSSI(ah); 406 if (rssi > aniState->rssiThrHigh) { 407 /* XXX: Handle me */ 408 } else if (rssi > aniState->rssiThrLow) { 409 if (aniState->ofdmWeakSigDetectOff) { 410 if (ath9k_hw_ani_control(ah, 411 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 412 true) == true) 413 return; 414 } 415 if (aniState->firstepLevel > 0) { 416 if (ath9k_hw_ani_control(ah, 417 ATH9K_ANI_FIRSTEP_LEVEL, 418 aniState->firstepLevel - 1) == true) 419 return; 420 } 421 } else { 422 if (aniState->firstepLevel > 0) { 423 if (ath9k_hw_ani_control(ah, 424 ATH9K_ANI_FIRSTEP_LEVEL, 425 aniState->firstepLevel - 1) == true) 426 return; 427 } 428 } 429 } 430 431 if (aniState->spurImmunityLevel > 0) { 432 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 433 aniState->spurImmunityLevel - 1)) 434 return; 435 } 436 437 if (aniState->noiseImmunityLevel > 0) { 438 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 439 aniState->noiseImmunityLevel - 1); 440 return; 441 } 442 } 443 444 /* 445 * only lower either OFDM or CCK errors per turn 446 * we lower the other one next time 447 */ 448 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) 449 { 450 struct ar5416AniState *aniState; 451 452 aniState = &ah->curchan->ani; 453 454 if (!use_new_ani(ah)) { 455 ath9k_hw_ani_lower_immunity_old(ah); 456 return; 457 } 458 459 /* lower OFDM noise immunity */ 460 if (aniState->ofdmNoiseImmunityLevel > 0 && 461 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) { 462 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1); 463 return; 464 } 465 466 /* lower CCK noise immunity */ 467 if (aniState->cckNoiseImmunityLevel > 0) 468 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1); 469 } 470 471 static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) 472 { 473 struct ar5416AniState *aniState; 474 struct ath9k_channel *chan = ah->curchan; 475 struct ath_common *common = ath9k_hw_common(ah); 476 477 if (!DO_ANI(ah)) 478 return; 479 480 aniState = &ah->curchan->ani; 481 482 if (ah->opmode != NL80211_IFTYPE_STATION 483 && ah->opmode != NL80211_IFTYPE_ADHOC) { 484 ath_dbg(common, ATH_DBG_ANI, 485 "Reset ANI state opmode %u\n", ah->opmode); 486 ah->stats.ast_ani_reset++; 487 488 if (ah->opmode == NL80211_IFTYPE_AP) { 489 /* 490 * ath9k_hw_ani_control() will only process items set on 491 * ah->ani_function 492 */ 493 if (IS_CHAN_2GHZ(chan)) 494 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 495 ATH9K_ANI_FIRSTEP_LEVEL); 496 else 497 ah->ani_function = 0; 498 } 499 500 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); 501 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); 502 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0); 503 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 504 !ATH9K_ANI_USE_OFDM_WEAK_SIG); 505 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, 506 ATH9K_ANI_CCK_WEAK_SIG_THR); 507 508 ath9k_ani_restart(ah); 509 return; 510 } 511 512 if (aniState->noiseImmunityLevel != 0) 513 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 514 aniState->noiseImmunityLevel); 515 if (aniState->spurImmunityLevel != 0) 516 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 517 aniState->spurImmunityLevel); 518 if (aniState->ofdmWeakSigDetectOff) 519 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 520 !aniState->ofdmWeakSigDetectOff); 521 if (aniState->cckWeakSigThreshold) 522 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR, 523 aniState->cckWeakSigThreshold); 524 if (aniState->firstepLevel != 0) 525 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 526 aniState->firstepLevel); 527 528 ath9k_ani_restart(ah); 529 530 ENABLE_REGWRITE_BUFFER(ah); 531 532 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 533 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 534 535 REGWRITE_BUFFER_FLUSH(ah); 536 } 537 538 /* 539 * Restore the ANI parameters in the HAL and reset the statistics. 540 * This routine should be called for every hardware reset and for 541 * every channel change. 542 */ 543 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) 544 { 545 struct ar5416AniState *aniState = &ah->curchan->ani; 546 struct ath9k_channel *chan = ah->curchan; 547 struct ath_common *common = ath9k_hw_common(ah); 548 549 if (!DO_ANI(ah)) 550 return; 551 552 if (!use_new_ani(ah)) 553 return ath9k_ani_reset_old(ah, is_scanning); 554 555 BUG_ON(aniState == NULL); 556 ah->stats.ast_ani_reset++; 557 558 /* only allow a subset of functions in AP mode */ 559 if (ah->opmode == NL80211_IFTYPE_AP) { 560 if (IS_CHAN_2GHZ(chan)) { 561 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 562 ATH9K_ANI_FIRSTEP_LEVEL); 563 if (AR_SREV_9300_20_OR_LATER(ah)) 564 ah->ani_function |= ATH9K_ANI_MRC_CCK; 565 } else 566 ah->ani_function = 0; 567 } 568 569 /* always allow mode (on/off) to be controlled */ 570 ah->ani_function |= ATH9K_ANI_MODE; 571 572 if (is_scanning || 573 (ah->opmode != NL80211_IFTYPE_STATION && 574 ah->opmode != NL80211_IFTYPE_ADHOC)) { 575 /* 576 * If we're scanning or in AP mode, the defaults (ini) 577 * should be in place. For an AP we assume the historical 578 * levels for this channel are probably outdated so start 579 * from defaults instead. 580 */ 581 if (aniState->ofdmNoiseImmunityLevel != 582 ATH9K_ANI_OFDM_DEF_LEVEL || 583 aniState->cckNoiseImmunityLevel != 584 ATH9K_ANI_CCK_DEF_LEVEL) { 585 ath_dbg(common, ATH_DBG_ANI, 586 "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", 587 ah->opmode, 588 chan->channel, 589 chan->channelFlags, 590 is_scanning, 591 aniState->ofdmNoiseImmunityLevel, 592 aniState->cckNoiseImmunityLevel); 593 594 aniState->update_ani = false; 595 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); 596 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL); 597 } 598 } else { 599 /* 600 * restore historical levels for this channel 601 */ 602 ath_dbg(common, ATH_DBG_ANI, 603 "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", 604 ah->opmode, 605 chan->channel, 606 chan->channelFlags, 607 is_scanning, 608 aniState->ofdmNoiseImmunityLevel, 609 aniState->cckNoiseImmunityLevel); 610 611 aniState->update_ani = true; 612 ath9k_hw_set_ofdm_nil(ah, 613 aniState->ofdmNoiseImmunityLevel); 614 ath9k_hw_set_cck_nil(ah, 615 aniState->cckNoiseImmunityLevel); 616 } 617 618 /* 619 * enable phy counters if hw supports or if not, enable phy 620 * interrupts (so we can count each one) 621 */ 622 ath9k_ani_restart(ah); 623 624 ENABLE_REGWRITE_BUFFER(ah); 625 626 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 627 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 628 629 REGWRITE_BUFFER_FLUSH(ah); 630 } 631 632 static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) 633 { 634 struct ath_common *common = ath9k_hw_common(ah); 635 struct ar5416AniState *aniState = &ah->curchan->ani; 636 u32 ofdm_base = 0; 637 u32 cck_base = 0; 638 u32 ofdmPhyErrCnt, cckPhyErrCnt; 639 u32 phyCnt1, phyCnt2; 640 int32_t listenTime; 641 642 ath_hw_cycle_counters_update(common); 643 listenTime = ath_hw_get_listen_time(common); 644 645 if (listenTime <= 0) { 646 ah->stats.ast_ani_lneg_or_lzero++; 647 ath9k_ani_restart(ah); 648 return false; 649 } 650 651 if (!use_new_ani(ah)) { 652 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high; 653 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; 654 } 655 656 aniState->listenTime += listenTime; 657 658 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 659 660 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 661 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 662 663 if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { 664 if (phyCnt1 < ofdm_base) { 665 ath_dbg(common, ATH_DBG_ANI, 666 "phyCnt1 0x%x, resetting counter value to 0x%x\n", 667 phyCnt1, ofdm_base); 668 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); 669 REG_WRITE(ah, AR_PHY_ERR_MASK_1, 670 AR_PHY_ERR_OFDM_TIMING); 671 } 672 if (phyCnt2 < cck_base) { 673 ath_dbg(common, ATH_DBG_ANI, 674 "phyCnt2 0x%x, resetting counter value to 0x%x\n", 675 phyCnt2, cck_base); 676 REG_WRITE(ah, AR_PHY_ERR_2, cck_base); 677 REG_WRITE(ah, AR_PHY_ERR_MASK_2, 678 AR_PHY_ERR_CCK_TIMING); 679 } 680 return false; 681 } 682 683 ofdmPhyErrCnt = phyCnt1 - ofdm_base; 684 ah->stats.ast_ani_ofdmerrs += 685 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 686 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 687 688 cckPhyErrCnt = phyCnt2 - cck_base; 689 ah->stats.ast_ani_cckerrs += 690 cckPhyErrCnt - aniState->cckPhyErrCount; 691 aniState->cckPhyErrCount = cckPhyErrCnt; 692 return true; 693 } 694 695 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) 696 { 697 struct ar5416AniState *aniState; 698 struct ath_common *common = ath9k_hw_common(ah); 699 u32 ofdmPhyErrRate, cckPhyErrRate; 700 701 if (!DO_ANI(ah)) 702 return; 703 704 aniState = &ah->curchan->ani; 705 if (WARN_ON(!aniState)) 706 return; 707 708 if (!ath9k_hw_ani_read_counters(ah)) 709 return; 710 711 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 / 712 aniState->listenTime; 713 cckPhyErrRate = aniState->cckPhyErrCount * 1000 / 714 aniState->listenTime; 715 716 ath_dbg(common, ATH_DBG_ANI, 717 "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", 718 aniState->listenTime, 719 aniState->ofdmNoiseImmunityLevel, 720 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, 721 cckPhyErrRate, aniState->ofdmsTurn); 722 723 if (aniState->listenTime > 5 * ah->aniperiod) { 724 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low && 725 cckPhyErrRate <= ah->config.cck_trig_low) { 726 ath9k_hw_ani_lower_immunity(ah); 727 aniState->ofdmsTurn = !aniState->ofdmsTurn; 728 } 729 ath9k_ani_restart(ah); 730 } else if (aniState->listenTime > ah->aniperiod) { 731 /* check to see if need to raise immunity */ 732 if (ofdmPhyErrRate > ah->config.ofdm_trig_high && 733 (cckPhyErrRate <= ah->config.cck_trig_high || 734 aniState->ofdmsTurn)) { 735 ath9k_hw_ani_ofdm_err_trigger(ah); 736 ath9k_ani_restart(ah); 737 aniState->ofdmsTurn = false; 738 } else if (cckPhyErrRate > ah->config.cck_trig_high) { 739 ath9k_hw_ani_cck_err_trigger(ah); 740 ath9k_ani_restart(ah); 741 aniState->ofdmsTurn = true; 742 } 743 } 744 } 745 EXPORT_SYMBOL(ath9k_hw_ani_monitor); 746 747 void ath9k_enable_mib_counters(struct ath_hw *ah) 748 { 749 struct ath_common *common = ath9k_hw_common(ah); 750 751 ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n"); 752 753 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 754 755 ENABLE_REGWRITE_BUFFER(ah); 756 757 REG_WRITE(ah, AR_FILT_OFDM, 0); 758 REG_WRITE(ah, AR_FILT_CCK, 0); 759 REG_WRITE(ah, AR_MIBC, 760 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) 761 & 0x0f); 762 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 763 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 764 765 REGWRITE_BUFFER_FLUSH(ah); 766 } 767 768 /* Freeze the MIB counters, get the stats and then clear them */ 769 void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 770 { 771 struct ath_common *common = ath9k_hw_common(ah); 772 773 ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n"); 774 775 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 776 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 777 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 778 REG_WRITE(ah, AR_FILT_OFDM, 0); 779 REG_WRITE(ah, AR_FILT_CCK, 0); 780 } 781 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); 782 783 /* 784 * Process a MIB interrupt. We may potentially be invoked because 785 * any of the MIB counters overflow/trigger so don't assume we're 786 * here because a PHY error counter triggered. 787 */ 788 void ath9k_hw_proc_mib_event(struct ath_hw *ah) 789 { 790 u32 phyCnt1, phyCnt2; 791 792 /* Reset these counters regardless */ 793 REG_WRITE(ah, AR_FILT_OFDM, 0); 794 REG_WRITE(ah, AR_FILT_CCK, 0); 795 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) 796 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); 797 798 /* Clear the mib counters and save them in the stats */ 799 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 800 801 if (!DO_ANI(ah)) { 802 /* 803 * We must always clear the interrupt cause by 804 * resetting the phy error regs. 805 */ 806 REG_WRITE(ah, AR_PHY_ERR_1, 0); 807 REG_WRITE(ah, AR_PHY_ERR_2, 0); 808 return; 809 } 810 811 /* NB: these are not reset-on-read */ 812 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 813 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 814 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 815 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { 816 817 if (!use_new_ani(ah)) 818 ath9k_hw_ani_read_counters(ah); 819 820 /* NB: always restart to insure the h/w counters are reset */ 821 ath9k_ani_restart(ah); 822 } 823 } 824 EXPORT_SYMBOL(ath9k_hw_proc_mib_event); 825 826 void ath9k_hw_ani_setup(struct ath_hw *ah) 827 { 828 int i; 829 830 static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; 831 static const int coarseHigh[] = { -14, -14, -14, -14, -12 }; 832 static const int coarseLow[] = { -64, -64, -64, -64, -70 }; 833 static const int firpwr[] = { -78, -78, -78, -78, -80 }; 834 835 for (i = 0; i < 5; i++) { 836 ah->totalSizeDesired[i] = totalSizeDesired[i]; 837 ah->coarse_high[i] = coarseHigh[i]; 838 ah->coarse_low[i] = coarseLow[i]; 839 ah->firpwr[i] = firpwr[i]; 840 } 841 } 842 843 void ath9k_hw_ani_init(struct ath_hw *ah) 844 { 845 struct ath_common *common = ath9k_hw_common(ah); 846 int i; 847 848 ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n"); 849 850 if (use_new_ani(ah)) { 851 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; 852 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW; 853 854 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW; 855 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW; 856 } else { 857 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD; 858 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD; 859 860 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD; 861 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD; 862 } 863 864 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) { 865 struct ath9k_channel *chan = &ah->channels[i]; 866 struct ar5416AniState *ani = &chan->ani; 867 868 if (use_new_ani(ah)) { 869 ani->spurImmunityLevel = 870 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 871 872 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 873 874 if (AR_SREV_9300_20_OR_LATER(ah)) 875 ani->mrcCCKOff = 876 !ATH9K_ANI_ENABLE_MRC_CCK; 877 else 878 ani->mrcCCKOff = true; 879 880 ani->ofdmsTurn = true; 881 } else { 882 ani->spurImmunityLevel = 883 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD; 884 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD; 885 886 ani->cckWeakSigThreshold = 887 ATH9K_ANI_CCK_WEAK_SIG_THR; 888 } 889 890 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; 891 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; 892 ani->ofdmWeakSigDetectOff = 893 !ATH9K_ANI_USE_OFDM_WEAK_SIG; 894 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; 895 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; 896 ani->update_ani = false; 897 } 898 899 /* 900 * since we expect some ongoing maintenance on the tables, let's sanity 901 * check here default level should not modify INI setting. 902 */ 903 if (use_new_ani(ah)) { 904 ah->aniperiod = ATH9K_ANI_PERIOD_NEW; 905 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW; 906 } else { 907 ah->aniperiod = ATH9K_ANI_PERIOD_OLD; 908 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD; 909 } 910 911 if (ah->config.enable_ani) 912 ah->proc_phyerr |= HAL_PROCESS_ANI; 913 914 ath9k_ani_restart(ah); 915 ath9k_enable_mib_counters(ah); 916 } 917