1 /* 2 * Copyright (c) 2004-2010 Atheros Communications Inc. 3 * Copyright (c) 2011 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef TARGET_H 19 #define TARGET_H 20 21 #define AR6003_BOARD_DATA_SZ 1024 22 #define AR6003_BOARD_EXT_DATA_SZ 768 23 24 #define AR6004_BOARD_DATA_SZ 6144 25 #define AR6004_BOARD_EXT_DATA_SZ 0 26 27 #define RESET_CONTROL_ADDRESS 0x00000000 28 #define RESET_CONTROL_COLD_RST 0x00000100 29 #define RESET_CONTROL_MBOX_RST 0x00000004 30 31 #define CPU_CLOCK_STANDARD_S 0 32 #define CPU_CLOCK_STANDARD 0x00000003 33 #define CPU_CLOCK_ADDRESS 0x00000020 34 35 #define CLOCK_CONTROL_ADDRESS 0x00000028 36 #define CLOCK_CONTROL_LF_CLK32_S 2 37 #define CLOCK_CONTROL_LF_CLK32 0x00000004 38 39 #define SYSTEM_SLEEP_ADDRESS 0x000000c4 40 #define SYSTEM_SLEEP_DISABLE_S 0 41 #define SYSTEM_SLEEP_DISABLE 0x00000001 42 43 #define LPO_CAL_ADDRESS 0x000000e0 44 #define LPO_CAL_ENABLE_S 20 45 #define LPO_CAL_ENABLE 0x00100000 46 47 #define GPIO_PIN10_ADDRESS 0x00000050 48 #define GPIO_PIN11_ADDRESS 0x00000054 49 #define GPIO_PIN12_ADDRESS 0x00000058 50 #define GPIO_PIN13_ADDRESS 0x0000005c 51 52 #define HOST_INT_STATUS_ADDRESS 0x00000400 53 #define HOST_INT_STATUS_ERROR_S 7 54 #define HOST_INT_STATUS_ERROR 0x00000080 55 56 #define HOST_INT_STATUS_CPU_S 6 57 #define HOST_INT_STATUS_CPU 0x00000040 58 59 #define HOST_INT_STATUS_COUNTER_S 4 60 #define HOST_INT_STATUS_COUNTER 0x00000010 61 62 #define CPU_INT_STATUS_ADDRESS 0x00000401 63 64 #define ERROR_INT_STATUS_ADDRESS 0x00000402 65 #define ERROR_INT_STATUS_WAKEUP_S 2 66 #define ERROR_INT_STATUS_WAKEUP 0x00000004 67 68 #define ERROR_INT_STATUS_RX_UNDERFLOW_S 1 69 #define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002 70 71 #define ERROR_INT_STATUS_TX_OVERFLOW_S 0 72 #define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001 73 74 #define COUNTER_INT_STATUS_ADDRESS 0x00000403 75 #define COUNTER_INT_STATUS_COUNTER_S 0 76 #define COUNTER_INT_STATUS_COUNTER 0x000000ff 77 78 #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405 79 80 #define INT_STATUS_ENABLE_ADDRESS 0x00000418 81 #define INT_STATUS_ENABLE_ERROR_S 7 82 #define INT_STATUS_ENABLE_ERROR 0x00000080 83 84 #define INT_STATUS_ENABLE_CPU_S 6 85 #define INT_STATUS_ENABLE_CPU 0x00000040 86 87 #define INT_STATUS_ENABLE_INT_S 5 88 #define INT_STATUS_ENABLE_INT 0x00000020 89 #define INT_STATUS_ENABLE_COUNTER_S 4 90 #define INT_STATUS_ENABLE_COUNTER 0x00000010 91 92 #define INT_STATUS_ENABLE_MBOX_DATA_S 0 93 #define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f 94 95 #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419 96 #define CPU_INT_STATUS_ENABLE_BIT_S 0 97 #define CPU_INT_STATUS_ENABLE_BIT 0x000000ff 98 99 #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a 100 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_S 1 101 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002 102 103 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0 104 #define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001 105 106 #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b 107 #define COUNTER_INT_STATUS_ENABLE_BIT_S 0 108 #define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff 109 110 #define COUNT_ADDRESS 0x00000420 111 112 #define COUNT_DEC_ADDRESS 0x00000440 113 114 #define WINDOW_DATA_ADDRESS 0x00000474 115 #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478 116 #define WINDOW_READ_ADDR_ADDRESS 0x0000047c 117 #define CPU_DBG_SEL_ADDRESS 0x00000483 118 #define CPU_DBG_ADDRESS 0x00000484 119 120 #define LOCAL_SCRATCH_ADDRESS 0x000000c0 121 #define ATH6KL_OPTION_SLEEP_DISABLE 0x08 122 123 #define RTC_BASE_ADDRESS 0x00004000 124 #define GPIO_BASE_ADDRESS 0x00014000 125 #define MBOX_BASE_ADDRESS 0x00018000 126 #define ANALOG_INTF_BASE_ADDRESS 0x0001c000 127 128 /* real name of the register is unknown */ 129 #define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284) 130 131 #define SM(f, v) (((v) << f##_S) & f) 132 #define MS(f, v) (((v) & f) >> f##_S) 133 134 /* 135 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 136 * host_interest structure. 137 * 138 * Host Interest is shared between Host and Target in order to coordinate 139 * between the two, and is intended to remain constant (with additions only 140 * at the end). 141 */ 142 #define ATH6KL_AR6003_HI_START_ADDR 0x00540600 143 #define ATH6KL_AR6004_HI_START_ADDR 0x00400800 144 145 /* 146 * These are items that the Host may need to access 147 * via BMI or via the Diagnostic Window. The position 148 * of items in this structure must remain constant. 149 * across firmware revisions! 150 * 151 * Types for each item must be fixed size across target and host platforms. 152 * The structure is used only to calculate offset for each register with 153 * HI_ITEM() macro, no values are stored to it. 154 * 155 * More items may be added at the end. 156 */ 157 struct host_interest { 158 /* 159 * Pointer to application-defined area, if any. 160 * Set by Target application during startup. 161 */ 162 u32 hi_app_host_interest; /* 0x00 */ 163 164 /* Pointer to register dump area, valid after Target crash. */ 165 u32 hi_failure_state; /* 0x04 */ 166 167 /* Pointer to debug logging header */ 168 u32 hi_dbglog_hdr; /* 0x08 */ 169 170 u32 hi_unused1; /* 0x0c */ 171 172 /* 173 * General-purpose flag bits, similar to ATH6KL_OPTION_* flags. 174 * Can be used by application rather than by OS. 175 */ 176 u32 hi_option_flag; /* 0x10 */ 177 178 /* 179 * Boolean that determines whether or not to 180 * display messages on the serial port. 181 */ 182 u32 hi_serial_enable; /* 0x14 */ 183 184 /* Start address of DataSet index, if any */ 185 u32 hi_dset_list_head; /* 0x18 */ 186 187 /* Override Target application start address */ 188 u32 hi_app_start; /* 0x1c */ 189 190 /* Clock and voltage tuning */ 191 u32 hi_skip_clock_init; /* 0x20 */ 192 u32 hi_core_clock_setting; /* 0x24 */ 193 u32 hi_cpu_clock_setting; /* 0x28 */ 194 u32 hi_system_sleep_setting; /* 0x2c */ 195 u32 hi_xtal_control_setting; /* 0x30 */ 196 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 197 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 198 u32 hi_ref_voltage_trim_setting; /* 0x3c */ 199 u32 hi_clock_info; /* 0x40 */ 200 201 /* 202 * Flash configuration overrides, used only 203 * when firmware is not executing from flash. 204 * (When using flash, modify the global variables 205 * with equivalent names.) 206 */ 207 u32 hi_bank0_addr_value; /* 0x44 */ 208 u32 hi_bank0_read_value; /* 0x48 */ 209 u32 hi_bank0_write_value; /* 0x4c */ 210 u32 hi_bank0_config_value; /* 0x50 */ 211 212 /* Pointer to Board Data */ 213 u32 hi_board_data; /* 0x54 */ 214 u32 hi_board_data_initialized; /* 0x58 */ 215 216 u32 hi_dset_ram_index_tbl; /* 0x5c */ 217 218 u32 hi_desired_baud_rate; /* 0x60 */ 219 u32 hi_dbglog_config; /* 0x64 */ 220 u32 hi_end_ram_reserve_sz; /* 0x68 */ 221 u32 hi_mbox_io_block_sz; /* 0x6c */ 222 223 u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 224 u32 hi_mbox_isr_yield_limit; /* 0x74 */ 225 226 u32 hi_refclk_hz; /* 0x78 */ 227 u32 hi_ext_clk_detected; /* 0x7c */ 228 u32 hi_dbg_uart_txpin; /* 0x80 */ 229 u32 hi_dbg_uart_rxpin; /* 0x84 */ 230 u32 hi_hci_uart_baud; /* 0x88 */ 231 u32 hi_hci_uart_pin_assignments; /* 0x8C */ 232 /* 233 * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts 234 * pin 235 */ 236 u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 237 u32 hi_hci_uart_baud_step_val; /* 0x94 */ 238 239 u32 hi_allocram_start; /* 0x98 */ 240 u32 hi_allocram_sz; /* 0x9c */ 241 u32 hi_hci_bridge_flags; /* 0xa0 */ 242 u32 hi_hci_uart_support_pins; /* 0xa4 */ 243 /* 244 * NOTE: byte [0] = RESET pin (bit 7 is polarity), 245 * bytes[1]..bytes[3] are for future use 246 */ 247 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 248 /* 249 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 250 * [31:16]: wakeup timeout in ms 251 */ 252 253 /* Pointer to extended board data */ 254 u32 hi_board_ext_data; /* 0xac */ 255 u32 hi_board_ext_data_config; /* 0xb0 */ 256 257 /* 258 * Bit [0] : valid 259 * Bit[31:16: size 260 */ 261 /* 262 * hi_reset_flag is used to do some stuff when target reset. 263 * such as restore app_start after warm reset or 264 * preserve host Interest area, or preserve ROM data, literals etc. 265 */ 266 u32 hi_reset_flag; /* 0xb4 */ 267 /* indicate hi_reset_flag is valid */ 268 u32 hi_reset_flag_valid; /* 0xb8 */ 269 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 270 /* 271 * 0xbc - [31:0]: idle timeout in ms 272 */ 273 /* ACS flags */ 274 u32 hi_acs_flags; /* 0xc0 */ 275 u32 hi_console_flags; /* 0xc4 */ 276 u32 hi_nvram_state; /* 0xc8 */ 277 u32 hi_option_flag2; /* 0xcc */ 278 279 /* If non-zero, override values sent to Host in WMI_READY event. */ 280 u32 hi_sw_version_override; /* 0xd0 */ 281 u32 hi_abi_version_override; /* 0xd4 */ 282 283 /* 284 * Percentage of high priority RX traffic to total expected RX traffic - 285 * applicable only to ar6004 286 */ 287 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 288 289 /* test applications flags */ 290 u32 hi_test_apps_related ; /* 0xdc */ 291 /* location of test script */ 292 u32 hi_ota_testscript; /* 0xe0 */ 293 /* location of CAL data */ 294 u32 hi_cal_data; /* 0xe4 */ 295 /* Number of packet log buffers */ 296 u32 hi_pktlog_num_buffers; /* 0xe8 */ 297 298 } __packed; 299 300 #define HI_ITEM(item) offsetof(struct host_interest, item) 301 302 #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 303 304 #define HI_OPTION_FW_MODE_IBSS 0x0 305 #define HI_OPTION_FW_MODE_BSS_STA 0x1 306 #define HI_OPTION_FW_MODE_AP 0x2 307 308 #define HI_OPTION_FW_SUBMODE_NONE 0x0 309 #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 310 #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 311 #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 312 313 #define HI_OPTION_NUM_DEV_SHIFT 0x9 314 315 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 316 317 /* Fw Mode/SubMode Mask 318 |------------------------------------------------------------------------------| 319 | SUB | SUB | SUB | SUB | | | | 320 | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0| 321 | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) 322 |------------------------------------------------------------------------------| 323 */ 324 #define HI_OPTION_FW_MODE_BITS 0x2 325 #define HI_OPTION_FW_MODE_SHIFT 0xC 326 327 #define HI_OPTION_FW_SUBMODE_BITS 0x2 328 #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 329 330 /* Convert a Target virtual address into a Target physical address */ 331 #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) 332 #define AR6004_VTOP(vaddr) (vaddr) 333 334 #define TARG_VTOP(target_type, vaddr) \ 335 (((target_type) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ 336 (((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0)) 337 338 #define ATH6KL_FWLOG_PAYLOAD_SIZE 1500 339 340 struct ath6kl_dbglog_buf { 341 __le32 next; 342 __le32 buffer_addr; 343 __le32 bufsize; 344 __le32 length; 345 __le32 count; 346 __le32 free; 347 } __packed; 348 349 struct ath6kl_dbglog_hdr { 350 __le32 dbuf_addr; 351 __le32 dropped; 352 } __packed; 353 354 #endif 355