1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18c6efe578SStephen Rothwell #include <linux/moduleparam.h> 19f7830202SSangwook Lee #include <linux/errno.h> 2092ecbff4SSam Leffler #include <linux/of.h> 21bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 22bdcd8170SKalle Valo #include "core.h" 23bdcd8170SKalle Valo #include "cfg80211.h" 24bdcd8170SKalle Valo #include "target.h" 25bdcd8170SKalle Valo #include "debug.h" 26bdcd8170SKalle Valo #include "hif-ops.h" 27bdcd8170SKalle Valo 28bdcd8170SKalle Valo unsigned int debug_mask; 29003353b0SKalle Valo static unsigned int testmode; 308277de15SKalle Valo static bool suspend_cutpower; 31a10e2f2fSVasanthakumar Thiagarajan static unsigned int uart_debug; 32bdcd8170SKalle Valo 33bdcd8170SKalle Valo module_param(debug_mask, uint, 0644); 34003353b0SKalle Valo module_param(testmode, uint, 0644); 358277de15SKalle Valo module_param(suspend_cutpower, bool, 0444); 36a10e2f2fSVasanthakumar Thiagarajan module_param(uart_debug, uint, 0644); 37bdcd8170SKalle Valo 38856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = { 39856f4b31SKalle Valo { 400d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION, 41293badf4SKalle Valo .name = "ar6003 hw 2.0", 42856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 43856f4b31SKalle Valo .app_load_addr = 0x543180, 44856f4b31SKalle Valo .board_ext_data_addr = 0x57e500, 45856f4b31SKalle Valo .reserved_ram_size = 6912, 4639586bf2SRyan Hsu .refclk_hz = 26000000, 4739586bf2SRyan Hsu .uarttx_pin = 8, 48856f4b31SKalle Valo 49856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */ 50856f4b31SKalle Valo .app_start_override_addr = 0x944C00, 51d1a9421dSKalle Valo 52c0038972SKalle Valo .fw = { 53c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR, 54c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE, 55d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE, 56c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, 57c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE, 58c0038972SKalle Valo }, 59c0038972SKalle Valo 60d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, 61d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, 62856f4b31SKalle Valo }, 63856f4b31SKalle Valo { 640d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION, 65293badf4SKalle Valo .name = "ar6003 hw 2.1.1", 66856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74, 67856f4b31SKalle Valo .app_load_addr = 0x1234, 68856f4b31SKalle Valo .board_ext_data_addr = 0x542330, 69856f4b31SKalle Valo .reserved_ram_size = 512, 7039586bf2SRyan Hsu .refclk_hz = 26000000, 7139586bf2SRyan Hsu .uarttx_pin = 8, 72cd23c1c9SAlex Yang .testscript_addr = 0x57ef74, 73d1a9421dSKalle Valo 74c0038972SKalle Valo .fw = { 75c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR, 76c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE, 77d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, 78c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, 79c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE, 80cd23c1c9SAlex Yang .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE, 81cd23c1c9SAlex Yang .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE, 82c0038972SKalle Valo }, 83c0038972SKalle Valo 84d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 85d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 86856f4b31SKalle Valo }, 87856f4b31SKalle Valo { 880d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION, 89293badf4SKalle Valo .name = "ar6004 hw 1.0", 90856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 91856f4b31SKalle Valo .app_load_addr = 0x1234, 92856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 93856f4b31SKalle Valo .reserved_ram_size = 19456, 940d4d72bfSKalle Valo .board_addr = 0x433900, 9539586bf2SRyan Hsu .refclk_hz = 26000000, 9639586bf2SRyan Hsu .uarttx_pin = 11, 97d1a9421dSKalle Valo 98c0038972SKalle Valo .fw = { 99c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR, 100d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE, 101c0038972SKalle Valo }, 102c0038972SKalle Valo 103d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, 104d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, 105856f4b31SKalle Valo }, 106856f4b31SKalle Valo { 1070d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION, 108293badf4SKalle Valo .name = "ar6004 hw 1.1", 109856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 110856f4b31SKalle Valo .app_load_addr = 0x1234, 111856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 112856f4b31SKalle Valo .reserved_ram_size = 11264, 1130d4d72bfSKalle Valo .board_addr = 0x43d400, 11439586bf2SRyan Hsu .refclk_hz = 40000000, 11539586bf2SRyan Hsu .uarttx_pin = 11, 116d1a9421dSKalle Valo 117c0038972SKalle Valo .fw = { 118c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR, 119d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE, 120c0038972SKalle Valo }, 121c0038972SKalle Valo 122d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, 123d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, 124856f4b31SKalle Valo }, 125856f4b31SKalle Valo }; 126856f4b31SKalle Valo 127bdcd8170SKalle Valo /* 128bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 129bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 130bdcd8170SKalle Valo * here. 131bdcd8170SKalle Valo */ 132bdcd8170SKalle Valo 133bdcd8170SKalle Valo /* 134bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 135bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 136bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 137bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 138bdcd8170SKalle Valo * Use value of zero to disable keepalive support 139bdcd8170SKalle Valo * Default: 60 seconds 140bdcd8170SKalle Valo */ 141bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 142bdcd8170SKalle Valo 143bdcd8170SKalle Valo /* 144bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 145bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 146bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 147bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 148bdcd8170SKalle Valo * it sends a new connect event 149bdcd8170SKalle Valo */ 150bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 151bdcd8170SKalle Valo 152bdcd8170SKalle Valo 153bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 154bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 155bdcd8170SKalle Valo { 156bdcd8170SKalle Valo struct sk_buff *skb; 157bdcd8170SKalle Valo u16 reserved; 158bdcd8170SKalle Valo 159bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 160bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 1611df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 162bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 163bdcd8170SKalle Valo 164bdcd8170SKalle Valo if (skb) 165bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 166bdcd8170SKalle Valo return skb; 167bdcd8170SKalle Valo } 168bdcd8170SKalle Valo 169e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif) 170bdcd8170SKalle Valo { 1713450334fSVasanthakumar Thiagarajan vif->ssid_len = 0; 1723450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid)); 1733450334fSVasanthakumar Thiagarajan 1743450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH; 1753450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH; 1763450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT; 1773450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0; 1783450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT; 1793450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0; 1806f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 1818c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); 1828c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid)); 183f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0; 184bdcd8170SKalle Valo } 185bdcd8170SKalle Valo 186bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 187bdcd8170SKalle Valo { 188bdcd8170SKalle Valo u32 address, data; 189bdcd8170SKalle Valo struct host_app_area host_app_area; 190bdcd8170SKalle Valo 191bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 192bdcd8170SKalle Valo * instance in the host interest area */ 193bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 19431024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 195bdcd8170SKalle Valo 196addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data)) 197bdcd8170SKalle Valo return -EIO; 198bdcd8170SKalle Valo 19931024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 200cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); 201addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, 202addb44beSKalle Valo sizeof(struct host_app_area))) 203bdcd8170SKalle Valo return -EIO; 204bdcd8170SKalle Valo 205bdcd8170SKalle Valo return 0; 206bdcd8170SKalle Valo } 207bdcd8170SKalle Valo 208bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 209bdcd8170SKalle Valo u8 ac, 210bdcd8170SKalle Valo enum htc_endpoint_id ep) 211bdcd8170SKalle Valo { 212bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 213bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 214bdcd8170SKalle Valo } 215bdcd8170SKalle Valo 216bdcd8170SKalle Valo /* connect to a service */ 217bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 218bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 219bdcd8170SKalle Valo char *desc) 220bdcd8170SKalle Valo { 221bdcd8170SKalle Valo int status; 222bdcd8170SKalle Valo struct htc_service_connect_resp response; 223bdcd8170SKalle Valo 224bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 225bdcd8170SKalle Valo 226ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 227bdcd8170SKalle Valo if (status) { 228bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 229bdcd8170SKalle Valo desc, status); 230bdcd8170SKalle Valo return status; 231bdcd8170SKalle Valo } 232bdcd8170SKalle Valo 233bdcd8170SKalle Valo switch (con_req->svc_id) { 234bdcd8170SKalle Valo case WMI_CONTROL_SVC: 235bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 236bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 237bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 238bdcd8170SKalle Valo break; 239bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 240bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 241bdcd8170SKalle Valo break; 242bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 243bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 244bdcd8170SKalle Valo break; 245bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 246bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 247bdcd8170SKalle Valo break; 248bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 249bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 250bdcd8170SKalle Valo break; 251bdcd8170SKalle Valo default: 252bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 253bdcd8170SKalle Valo return -EINVAL; 254bdcd8170SKalle Valo } 255bdcd8170SKalle Valo 256bdcd8170SKalle Valo return 0; 257bdcd8170SKalle Valo } 258bdcd8170SKalle Valo 259bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 260bdcd8170SKalle Valo { 261bdcd8170SKalle Valo struct htc_service_connect_req connect; 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 264bdcd8170SKalle Valo 265bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 266bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 267bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 268bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 269bdcd8170SKalle Valo 270bdcd8170SKalle Valo /* 271bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 272bdcd8170SKalle Valo * gets called. 273bdcd8170SKalle Valo */ 274bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 275bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 276bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 277bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 278bdcd8170SKalle Valo 279bdcd8170SKalle Valo /* connect to control service */ 280bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 281bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 282bdcd8170SKalle Valo return -EIO; 283bdcd8170SKalle Valo 284bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 285bdcd8170SKalle Valo 286bdcd8170SKalle Valo /* 287bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 288bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 289bdcd8170SKalle Valo * (802.3) frames on the send path. 290bdcd8170SKalle Valo */ 291bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 292bdcd8170SKalle Valo 293bdcd8170SKalle Valo /* 294bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 295bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 296bdcd8170SKalle Valo * packets. 297bdcd8170SKalle Valo */ 298bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 299bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 300bdcd8170SKalle Valo 301bdcd8170SKalle Valo /* 302bdcd8170SKalle Valo * For the remaining data services set the connection flag to 303bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 304bdcd8170SKalle Valo */ 305bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 306bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 307bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 308bdcd8170SKalle Valo 309bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 310bdcd8170SKalle Valo 311bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 312bdcd8170SKalle Valo return -EIO; 313bdcd8170SKalle Valo 314bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 315bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 316bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 317bdcd8170SKalle Valo return -EIO; 318bdcd8170SKalle Valo 319bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 320bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 321bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 322bdcd8170SKalle Valo return -EIO; 323bdcd8170SKalle Valo 324bdcd8170SKalle Valo /* 325bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 326bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 327bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 328bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 329bdcd8170SKalle Valo * mailboxes. 330bdcd8170SKalle Valo */ 331bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 332bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 333bdcd8170SKalle Valo return -EIO; 334bdcd8170SKalle Valo 335bdcd8170SKalle Valo return 0; 336bdcd8170SKalle Valo } 337bdcd8170SKalle Valo 338e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif) 339bdcd8170SKalle Valo { 340e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif); 3413450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0; 3426f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 343f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0; 344bdcd8170SKalle Valo } 345bdcd8170SKalle Valo 346bdcd8170SKalle Valo /* 347bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 348bdcd8170SKalle Valo * target is in the BMI phase. 349bdcd8170SKalle Valo */ 350bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 351bdcd8170SKalle Valo u8 htc_ctrl_buf) 352bdcd8170SKalle Valo { 353bdcd8170SKalle Valo int status; 354bdcd8170SKalle Valo u32 blk_size; 355bdcd8170SKalle Valo 356bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 357bdcd8170SKalle Valo 358bdcd8170SKalle Valo if (htc_ctrl_buf) 359bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 360bdcd8170SKalle Valo 361bdcd8170SKalle Valo /* set the host interest area for the block size */ 362bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 363bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 364bdcd8170SKalle Valo HI_ITEM(hi_mbox_io_block_sz)), 365bdcd8170SKalle Valo (u8 *)&blk_size, 366bdcd8170SKalle Valo 4); 367bdcd8170SKalle Valo if (status) { 368bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 369bdcd8170SKalle Valo goto out; 370bdcd8170SKalle Valo } 371bdcd8170SKalle Valo 372bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 373bdcd8170SKalle Valo blk_size, 374bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 375bdcd8170SKalle Valo 376bdcd8170SKalle Valo if (mbox_isr_yield_val) { 377bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 378bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 379bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 380bdcd8170SKalle Valo HI_ITEM(hi_mbox_isr_yield_limit)), 381bdcd8170SKalle Valo (u8 *)&mbox_isr_yield_val, 382bdcd8170SKalle Valo 4); 383bdcd8170SKalle Valo if (status) { 384bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 385bdcd8170SKalle Valo goto out; 386bdcd8170SKalle Valo } 387bdcd8170SKalle Valo } 388bdcd8170SKalle Valo 389bdcd8170SKalle Valo out: 390bdcd8170SKalle Valo return status; 391bdcd8170SKalle Valo } 392bdcd8170SKalle Valo 3930ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 394bdcd8170SKalle Valo { 395bdcd8170SKalle Valo int status = 0; 3964dea08e0SJouni Malinen int ret; 397bdcd8170SKalle Valo 398bdcd8170SKalle Valo /* 399bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 400bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 401bdcd8170SKalle Valo * RxMetaVersion to 2. 402bdcd8170SKalle Valo */ 4030ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 404bdcd8170SKalle Valo ar->rx_meta_ver, 0, 0)) { 405bdcd8170SKalle Valo ath6kl_err("unable to set the rx frame format\n"); 406bdcd8170SKalle Valo status = -EIO; 407bdcd8170SKalle Valo } 408bdcd8170SKalle Valo 409bdcd8170SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) 4100ce59445SVasanthakumar Thiagarajan if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 411bdcd8170SKalle Valo IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) { 412bdcd8170SKalle Valo ath6kl_err("unable to set power save fail event policy\n"); 413bdcd8170SKalle Valo status = -EIO; 414bdcd8170SKalle Valo } 415bdcd8170SKalle Valo 416bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) 4170ce59445SVasanthakumar Thiagarajan if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 418bdcd8170SKalle Valo WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) { 419bdcd8170SKalle Valo ath6kl_err("unable to set barker preamble policy\n"); 420bdcd8170SKalle Valo status = -EIO; 421bdcd8170SKalle Valo } 422bdcd8170SKalle Valo 4230ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 424bdcd8170SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) { 425bdcd8170SKalle Valo ath6kl_err("unable to set keep alive interval\n"); 426bdcd8170SKalle Valo status = -EIO; 427bdcd8170SKalle Valo } 428bdcd8170SKalle Valo 4290ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 430bdcd8170SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT)) { 431bdcd8170SKalle Valo ath6kl_err("unable to set disconnect timeout\n"); 432bdcd8170SKalle Valo status = -EIO; 433bdcd8170SKalle Valo } 434bdcd8170SKalle Valo 435bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) 4360ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) { 437bdcd8170SKalle Valo ath6kl_err("unable to set txop bursting\n"); 438bdcd8170SKalle Valo status = -EIO; 439bdcd8170SKalle Valo } 440bdcd8170SKalle Valo 441b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4420ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 4436bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ | 4444dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4454dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4464dea08e0SJouni Malinen if (ret) { 4474dea08e0SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " 4486bbc7c35SJouni Malinen "capabilities (%d) - assuming P2P not " 4496bbc7c35SJouni Malinen "supported\n", ret); 4503db1cd5cSRusty Russell ar->p2p = false; 4516bbc7c35SJouni Malinen } 4526bbc7c35SJouni Malinen } 4536bbc7c35SJouni Malinen 454b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4556bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */ 4560ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); 4576bbc7c35SJouni Malinen if (ret) { 4586bbc7c35SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe " 4596bbc7c35SJouni Malinen "Request reporting (%d)\n", ret); 4606bbc7c35SJouni Malinen } 4614dea08e0SJouni Malinen } 4624dea08e0SJouni Malinen 463bdcd8170SKalle Valo return status; 464bdcd8170SKalle Valo } 465bdcd8170SKalle Valo 466bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 467bdcd8170SKalle Valo { 468bdcd8170SKalle Valo u32 param, ram_reserved_size; 4693226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0; 47039586bf2SRyan Hsu int i, status; 471bdcd8170SKalle Valo 472*f29af978SKalle Valo param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG); 473a10e2f2fSVasanthakumar Thiagarajan if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 474a10e2f2fSVasanthakumar Thiagarajan HI_ITEM(hi_serial_enable)), (u8 *)¶m, 4)) { 475a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n"); 476a10e2f2fSVasanthakumar Thiagarajan return -EIO; 477a10e2f2fSVasanthakumar Thiagarajan } 478a10e2f2fSVasanthakumar Thiagarajan 4797b85832dSVasanthakumar Thiagarajan /* 4807b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is 4817b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can 4827b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode 4837b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But 4847b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is 4857b85832dSVasanthakumar Thiagarajan * configured for now. 4867b85832dSVasanthakumar Thiagarajan */ 487dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA; 488bdcd8170SKalle Valo 48971f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 4907b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); 4917b85832dSVasanthakumar Thiagarajan 4927b85832dSVasanthakumar Thiagarajan /* 4933226f68aSVasanthakumar Thiagarajan * By default, submodes : 4943226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS 4957b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" 4967b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" 4977b85832dSVasanthakumar Thiagarajan */ 4983226f68aSVasanthakumar Thiagarajan 4993226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++) 5003226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE << 5013226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5023226f68aSVasanthakumar Thiagarajan 50371f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++) 5043226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5053226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5067b85832dSVasanthakumar Thiagarajan 507b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1) 5087b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 5097b85832dSVasanthakumar Thiagarajan 510bdcd8170SKalle Valo param = HTC_PROTOCOL_VERSION; 511bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 512bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 513bdcd8170SKalle Valo HI_ITEM(hi_app_host_interest)), 514bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 515bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 516bdcd8170SKalle Valo return -EIO; 517bdcd8170SKalle Valo } 518bdcd8170SKalle Valo 519bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 520bdcd8170SKalle Valo param = 0; 521bdcd8170SKalle Valo 522bdcd8170SKalle Valo if (ath6kl_bmi_read(ar, 523bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 524bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 525bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 526bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 527bdcd8170SKalle Valo return -EIO; 528bdcd8170SKalle Valo } 529bdcd8170SKalle Valo 53071f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); 5317b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; 5327b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; 5337b85832dSVasanthakumar Thiagarajan 534bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 535bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 536bdcd8170SKalle Valo 537bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 538bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 539bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 540bdcd8170SKalle Valo (u8 *)¶m, 541bdcd8170SKalle Valo 4) != 0) { 542bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 543bdcd8170SKalle Valo return -EIO; 544bdcd8170SKalle Valo } 545bdcd8170SKalle Valo 546bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 547bdcd8170SKalle Valo 548bdcd8170SKalle Valo /* 549bdcd8170SKalle Valo * Hardcode the address use for the extended board data 550bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 551bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 552bdcd8170SKalle Valo * at init time, we have to workaround this from host. 553bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 554bdcd8170SKalle Valo * but possible in theory. 555bdcd8170SKalle Valo */ 556bdcd8170SKalle Valo 557991b27eaSKalle Valo param = ar->hw.board_ext_data_addr; 558991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size; 559bdcd8170SKalle Valo 560991b27eaSKalle Valo if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 561bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 562bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 563bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 564bdcd8170SKalle Valo return -EIO; 565bdcd8170SKalle Valo } 566991b27eaSKalle Valo 567991b27eaSKalle Valo if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 568bdcd8170SKalle Valo HI_ITEM(hi_end_ram_reserve_sz)), 569bdcd8170SKalle Valo (u8 *)&ram_reserved_size, 4) != 0) { 570bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 571bdcd8170SKalle Valo return -EIO; 572bdcd8170SKalle Valo } 573bdcd8170SKalle Valo 574bdcd8170SKalle Valo /* set the block size for the target */ 575bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 576bdcd8170SKalle Valo /* use default number of control buffers */ 577bdcd8170SKalle Valo return -EIO; 578bdcd8170SKalle Valo 57939586bf2SRyan Hsu /* Configure GPIO AR600x UART */ 58039586bf2SRyan Hsu param = ar->hw.uarttx_pin; 58139586bf2SRyan Hsu status = ath6kl_bmi_write(ar, 58239586bf2SRyan Hsu ath6kl_get_hi_item_addr(ar, 58339586bf2SRyan Hsu HI_ITEM(hi_dbg_uart_txpin)), 58439586bf2SRyan Hsu (u8 *)¶m, 4); 58539586bf2SRyan Hsu if (status) 58639586bf2SRyan Hsu return status; 58739586bf2SRyan Hsu 58839586bf2SRyan Hsu /* Configure target refclk_hz */ 58939586bf2SRyan Hsu param = ar->hw.refclk_hz; 59039586bf2SRyan Hsu status = ath6kl_bmi_write(ar, 59139586bf2SRyan Hsu ath6kl_get_hi_item_addr(ar, 59239586bf2SRyan Hsu HI_ITEM(hi_refclk_hz)), 59339586bf2SRyan Hsu (u8 *)¶m, 4); 59439586bf2SRyan Hsu if (status) 59539586bf2SRyan Hsu return status; 59639586bf2SRyan Hsu 597bdcd8170SKalle Valo return 0; 598bdcd8170SKalle Valo } 599bdcd8170SKalle Valo 6008dafb70eSVasanthakumar Thiagarajan void ath6kl_core_free(struct ath6kl *ar) 601bdcd8170SKalle Valo { 6028dafb70eSVasanthakumar Thiagarajan wiphy_free(ar->wiphy); 603bdcd8170SKalle Valo } 604bdcd8170SKalle Valo 6056db8fa53SVasanthakumar Thiagarajan void ath6kl_core_cleanup(struct ath6kl *ar) 606bdcd8170SKalle Valo { 607b2e75698SKalle Valo ath6kl_hif_power_off(ar); 608b2e75698SKalle Valo 6096db8fa53SVasanthakumar Thiagarajan destroy_workqueue(ar->ath6kl_wq); 610bdcd8170SKalle Valo 6116db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) 6126db8fa53SVasanthakumar Thiagarajan ath6kl_htc_cleanup(ar->htc_target); 6136db8fa53SVasanthakumar Thiagarajan 6146db8fa53SVasanthakumar Thiagarajan ath6kl_cookie_cleanup(ar); 6156db8fa53SVasanthakumar Thiagarajan 6166db8fa53SVasanthakumar Thiagarajan ath6kl_cleanup_amsdu_rxbufs(ar); 6176db8fa53SVasanthakumar Thiagarajan 6186db8fa53SVasanthakumar Thiagarajan ath6kl_bmi_cleanup(ar); 6196db8fa53SVasanthakumar Thiagarajan 6206db8fa53SVasanthakumar Thiagarajan ath6kl_debug_cleanup(ar); 6216db8fa53SVasanthakumar Thiagarajan 6226db8fa53SVasanthakumar Thiagarajan kfree(ar->fw_board); 6236db8fa53SVasanthakumar Thiagarajan kfree(ar->fw_otp); 6246db8fa53SVasanthakumar Thiagarajan kfree(ar->fw); 6256db8fa53SVasanthakumar Thiagarajan kfree(ar->fw_patch); 626cd23c1c9SAlex Yang kfree(ar->fw_testscript); 6276db8fa53SVasanthakumar Thiagarajan 62846d33a21SKalle Valo ath6kl_cfg80211_cleanup(ar); 629bdcd8170SKalle Valo } 630bdcd8170SKalle Valo 631bdcd8170SKalle Valo /* firmware upload */ 632bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 633bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 634bdcd8170SKalle Valo { 635bdcd8170SKalle Valo const struct firmware *fw_entry; 636bdcd8170SKalle Valo int ret; 637bdcd8170SKalle Valo 638bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 639bdcd8170SKalle Valo if (ret) 640bdcd8170SKalle Valo return ret; 641bdcd8170SKalle Valo 642bdcd8170SKalle Valo *fw_len = fw_entry->size; 643bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 644bdcd8170SKalle Valo 645bdcd8170SKalle Valo if (*fw == NULL) 646bdcd8170SKalle Valo ret = -ENOMEM; 647bdcd8170SKalle Valo 648bdcd8170SKalle Valo release_firmware(fw_entry); 649bdcd8170SKalle Valo 650bdcd8170SKalle Valo return ret; 651bdcd8170SKalle Valo } 652bdcd8170SKalle Valo 65392ecbff4SSam Leffler #ifdef CONFIG_OF 65492ecbff4SSam Leffler /* 65592ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct 65692ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a 65792ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the 65892ecbff4SSam Leffler * appropriate board-specific file. 65992ecbff4SSam Leffler */ 66092ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 66192ecbff4SSam Leffler { 66292ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id"; 66392ecbff4SSam Leffler struct device_node *node; 66492ecbff4SSam Leffler char board_filename[64]; 66592ecbff4SSam Leffler const char *board_id; 66692ecbff4SSam Leffler int ret; 66792ecbff4SSam Leffler 66892ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") { 66992ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL); 67092ecbff4SSam Leffler if (board_id == NULL) { 67192ecbff4SSam Leffler ath6kl_warn("No \"%s\" property on %s node.\n", 67292ecbff4SSam Leffler board_id_prop, node->name); 67392ecbff4SSam Leffler continue; 67492ecbff4SSam Leffler } 67592ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename), 676c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); 67792ecbff4SSam Leffler 67892ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, 67992ecbff4SSam Leffler &ar->fw_board_len); 68092ecbff4SSam Leffler if (ret) { 68192ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n", 68292ecbff4SSam Leffler board_filename, ret); 68392ecbff4SSam Leffler continue; 68492ecbff4SSam Leffler } 68592ecbff4SSam Leffler return true; 68692ecbff4SSam Leffler } 68792ecbff4SSam Leffler return false; 68892ecbff4SSam Leffler } 68992ecbff4SSam Leffler #else 69092ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 69192ecbff4SSam Leffler { 69292ecbff4SSam Leffler return false; 69392ecbff4SSam Leffler } 69492ecbff4SSam Leffler #endif /* CONFIG_OF */ 69592ecbff4SSam Leffler 696bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 697bdcd8170SKalle Valo { 698bdcd8170SKalle Valo const char *filename; 699bdcd8170SKalle Valo int ret; 700bdcd8170SKalle Valo 701772c31eeSKalle Valo if (ar->fw_board != NULL) 702772c31eeSKalle Valo return 0; 703772c31eeSKalle Valo 704d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL)) 705d1a9421dSKalle Valo return -EINVAL; 706d1a9421dSKalle Valo 707d1a9421dSKalle Valo filename = ar->hw.fw_board; 708bdcd8170SKalle Valo 709bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 710bdcd8170SKalle Valo &ar->fw_board_len); 711bdcd8170SKalle Valo if (ret == 0) { 712bdcd8170SKalle Valo /* managed to get proper board file */ 713bdcd8170SKalle Valo return 0; 714bdcd8170SKalle Valo } 715bdcd8170SKalle Valo 71692ecbff4SSam Leffler if (check_device_tree(ar)) { 71792ecbff4SSam Leffler /* got board file from device tree */ 71892ecbff4SSam Leffler return 0; 71992ecbff4SSam Leffler } 72092ecbff4SSam Leffler 721bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 722bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 723bdcd8170SKalle Valo filename, ret); 724bdcd8170SKalle Valo 725d1a9421dSKalle Valo filename = ar->hw.fw_default_board; 726bdcd8170SKalle Valo 727bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 728bdcd8170SKalle Valo &ar->fw_board_len); 729bdcd8170SKalle Valo if (ret) { 730bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 731bdcd8170SKalle Valo filename, ret); 732bdcd8170SKalle Valo return ret; 733bdcd8170SKalle Valo } 734bdcd8170SKalle Valo 735bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 736bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 737bdcd8170SKalle Valo 738bdcd8170SKalle Valo return 0; 739bdcd8170SKalle Valo } 740bdcd8170SKalle Valo 741772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar) 742772c31eeSKalle Valo { 743c0038972SKalle Valo char filename[100]; 744772c31eeSKalle Valo int ret; 745772c31eeSKalle Valo 746772c31eeSKalle Valo if (ar->fw_otp != NULL) 747772c31eeSKalle Valo return 0; 748772c31eeSKalle Valo 749c0038972SKalle Valo if (ar->hw.fw.otp == NULL) { 750d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 751d1a9421dSKalle Valo "no OTP file configured for this hw\n"); 752772c31eeSKalle Valo return 0; 753772c31eeSKalle Valo } 754772c31eeSKalle Valo 755c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 756c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp); 757d1a9421dSKalle Valo 758772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 759772c31eeSKalle Valo &ar->fw_otp_len); 760772c31eeSKalle Valo if (ret) { 761772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 762772c31eeSKalle Valo filename, ret); 763772c31eeSKalle Valo return ret; 764772c31eeSKalle Valo } 765772c31eeSKalle Valo 766772c31eeSKalle Valo return 0; 767772c31eeSKalle Valo } 768772c31eeSKalle Valo 769772c31eeSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar) 770772c31eeSKalle Valo { 771c0038972SKalle Valo char filename[100]; 772772c31eeSKalle Valo int ret; 773772c31eeSKalle Valo 774772c31eeSKalle Valo if (ar->fw != NULL) 775772c31eeSKalle Valo return 0; 776772c31eeSKalle Valo 777772c31eeSKalle Valo if (testmode) { 778cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", 779cd23c1c9SAlex Yang testmode); 780cd23c1c9SAlex Yang if (testmode == 2) { 781cd23c1c9SAlex Yang if (ar->hw.fw.utf == NULL) { 782cd23c1c9SAlex Yang ath6kl_warn("testmode 2 not supported\n"); 783cd23c1c9SAlex Yang return -EOPNOTSUPP; 784cd23c1c9SAlex Yang } 785cd23c1c9SAlex Yang 786cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 787cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.utf); 788cd23c1c9SAlex Yang } else { 789c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) { 790cd23c1c9SAlex Yang ath6kl_warn("testmode 1 not supported\n"); 791772c31eeSKalle Valo return -EOPNOTSUPP; 792772c31eeSKalle Valo } 793772c31eeSKalle Valo 794c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 795c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd); 796cd23c1c9SAlex Yang } 797772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag); 798772c31eeSKalle Valo 799772c31eeSKalle Valo goto get_fw; 800772c31eeSKalle Valo } 801772c31eeSKalle Valo 802c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ 803c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL)) 804d1a9421dSKalle Valo return -EINVAL; 805d1a9421dSKalle Valo 806c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 807c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw); 808772c31eeSKalle Valo 809772c31eeSKalle Valo get_fw: 810772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 811772c31eeSKalle Valo if (ret) { 812772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 813772c31eeSKalle Valo filename, ret); 814772c31eeSKalle Valo return ret; 815772c31eeSKalle Valo } 816772c31eeSKalle Valo 817772c31eeSKalle Valo return 0; 818772c31eeSKalle Valo } 819772c31eeSKalle Valo 820772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar) 821772c31eeSKalle Valo { 822c0038972SKalle Valo char filename[100]; 823772c31eeSKalle Valo int ret; 824772c31eeSKalle Valo 825d1a9421dSKalle Valo if (ar->fw_patch != NULL) 826772c31eeSKalle Valo return 0; 827772c31eeSKalle Valo 828c0038972SKalle Valo if (ar->hw.fw.patch == NULL) 829d1a9421dSKalle Valo return 0; 830d1a9421dSKalle Valo 831c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 832c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch); 833d1a9421dSKalle Valo 834772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 835772c31eeSKalle Valo &ar->fw_patch_len); 836772c31eeSKalle Valo if (ret) { 837772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 838772c31eeSKalle Valo filename, ret); 839772c31eeSKalle Valo return ret; 840772c31eeSKalle Valo } 841772c31eeSKalle Valo 842772c31eeSKalle Valo return 0; 843772c31eeSKalle Valo } 844772c31eeSKalle Valo 845cd23c1c9SAlex Yang static int ath6kl_fetch_testscript_file(struct ath6kl *ar) 846cd23c1c9SAlex Yang { 847cd23c1c9SAlex Yang char filename[100]; 848cd23c1c9SAlex Yang int ret; 849cd23c1c9SAlex Yang 850cd23c1c9SAlex Yang if (testmode != 2) 851cd23c1c9SAlex Yang return 0; 852cd23c1c9SAlex Yang 853cd23c1c9SAlex Yang if (ar->fw_testscript != NULL) 854cd23c1c9SAlex Yang return 0; 855cd23c1c9SAlex Yang 856cd23c1c9SAlex Yang if (ar->hw.fw.testscript == NULL) 857cd23c1c9SAlex Yang return 0; 858cd23c1c9SAlex Yang 859cd23c1c9SAlex Yang snprintf(filename, sizeof(filename), "%s/%s", 860cd23c1c9SAlex Yang ar->hw.fw.dir, ar->hw.fw.testscript); 861cd23c1c9SAlex Yang 862cd23c1c9SAlex Yang ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript, 863cd23c1c9SAlex Yang &ar->fw_testscript_len); 864cd23c1c9SAlex Yang if (ret) { 865cd23c1c9SAlex Yang ath6kl_err("Failed to get testscript file %s: %d\n", 866cd23c1c9SAlex Yang filename, ret); 867cd23c1c9SAlex Yang return ret; 868cd23c1c9SAlex Yang } 869cd23c1c9SAlex Yang 870cd23c1c9SAlex Yang return 0; 871cd23c1c9SAlex Yang } 872cd23c1c9SAlex Yang 87350d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar) 874772c31eeSKalle Valo { 875772c31eeSKalle Valo int ret; 876772c31eeSKalle Valo 877772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar); 878772c31eeSKalle Valo if (ret) 879772c31eeSKalle Valo return ret; 880772c31eeSKalle Valo 881772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar); 882772c31eeSKalle Valo if (ret) 883772c31eeSKalle Valo return ret; 884772c31eeSKalle Valo 885772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar); 886772c31eeSKalle Valo if (ret) 887772c31eeSKalle Valo return ret; 888772c31eeSKalle Valo 889cd23c1c9SAlex Yang ret = ath6kl_fetch_testscript_file(ar); 890cd23c1c9SAlex Yang if (ret) 891cd23c1c9SAlex Yang return ret; 892cd23c1c9SAlex Yang 893772c31eeSKalle Valo return 0; 894772c31eeSKalle Valo } 895bdcd8170SKalle Valo 89665a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) 89750d41234SKalle Valo { 89850d41234SKalle Valo size_t magic_len, len, ie_len; 89950d41234SKalle Valo const struct firmware *fw; 90050d41234SKalle Valo struct ath6kl_fw_ie *hdr; 901c0038972SKalle Valo char filename[100]; 90250d41234SKalle Valo const u8 *data; 90397e0496dSKalle Valo int ret, ie_id, i, index, bit; 9048a137480SKalle Valo __le32 *val; 90550d41234SKalle Valo 90665a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); 90750d41234SKalle Valo 90850d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev); 90950d41234SKalle Valo if (ret) 91050d41234SKalle Valo return ret; 91150d41234SKalle Valo 91250d41234SKalle Valo data = fw->data; 91350d41234SKalle Valo len = fw->size; 91450d41234SKalle Valo 91550d41234SKalle Valo /* magic also includes the null byte, check that as well */ 91650d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; 91750d41234SKalle Valo 91850d41234SKalle Valo if (len < magic_len) { 91950d41234SKalle Valo ret = -EINVAL; 92050d41234SKalle Valo goto out; 92150d41234SKalle Valo } 92250d41234SKalle Valo 92350d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { 92450d41234SKalle Valo ret = -EINVAL; 92550d41234SKalle Valo goto out; 92650d41234SKalle Valo } 92750d41234SKalle Valo 92850d41234SKalle Valo len -= magic_len; 92950d41234SKalle Valo data += magic_len; 93050d41234SKalle Valo 93150d41234SKalle Valo /* loop elements */ 93250d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) { 93350d41234SKalle Valo /* hdr is unaligned! */ 93450d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data; 93550d41234SKalle Valo 93650d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id); 93750d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len); 93850d41234SKalle Valo 93950d41234SKalle Valo len -= sizeof(*hdr); 94050d41234SKalle Valo data += sizeof(*hdr); 94150d41234SKalle Valo 94250d41234SKalle Valo if (len < ie_len) { 94350d41234SKalle Valo ret = -EINVAL; 94450d41234SKalle Valo goto out; 94550d41234SKalle Valo } 94650d41234SKalle Valo 94750d41234SKalle Valo switch (ie_id) { 94850d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE: 949ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 9506bc36431SKalle Valo ie_len); 9516bc36431SKalle Valo 95250d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 95350d41234SKalle Valo 95450d41234SKalle Valo if (ar->fw_otp == NULL) { 95550d41234SKalle Valo ret = -ENOMEM; 95650d41234SKalle Valo goto out; 95750d41234SKalle Valo } 95850d41234SKalle Valo 95950d41234SKalle Valo ar->fw_otp_len = ie_len; 96050d41234SKalle Valo break; 96150d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE: 962ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 9636bc36431SKalle Valo ie_len); 9646bc36431SKalle Valo 96550d41234SKalle Valo ar->fw = kmemdup(data, ie_len, GFP_KERNEL); 96650d41234SKalle Valo 96750d41234SKalle Valo if (ar->fw == NULL) { 96850d41234SKalle Valo ret = -ENOMEM; 96950d41234SKalle Valo goto out; 97050d41234SKalle Valo } 97150d41234SKalle Valo 97250d41234SKalle Valo ar->fw_len = ie_len; 97350d41234SKalle Valo break; 97450d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE: 975ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 9766bc36431SKalle Valo ie_len); 9776bc36431SKalle Valo 97850d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 97950d41234SKalle Valo 98050d41234SKalle Valo if (ar->fw_patch == NULL) { 98150d41234SKalle Valo ret = -ENOMEM; 98250d41234SKalle Valo goto out; 98350d41234SKalle Valo } 98450d41234SKalle Valo 98550d41234SKalle Valo ar->fw_patch_len = ie_len; 98650d41234SKalle Valo break; 9878a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE: 9888a137480SKalle Valo val = (__le32 *) data; 9898a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val); 9906bc36431SKalle Valo 9916bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 9926bc36431SKalle Valo "found reserved ram size ie 0x%d\n", 9936bc36431SKalle Valo ar->hw.reserved_ram_size); 9948a137480SKalle Valo break; 99597e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES: 996277d90f4SKalle Valo if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8)) 997277d90f4SKalle Valo break; 998277d90f4SKalle Valo 9996bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1000ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n", 10016bc36431SKalle Valo ie_len); 10026bc36431SKalle Valo 100397e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { 1004277d90f4SKalle Valo index = i / 8; 100597e0496dSKalle Valo bit = i % 8; 100697e0496dSKalle Valo 100797e0496dSKalle Valo if (data[index] & (1 << bit)) 100897e0496dSKalle Valo __set_bit(i, ar->fw_capabilities); 100997e0496dSKalle Valo } 10106bc36431SKalle Valo 10116bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", 10126bc36431SKalle Valo ar->fw_capabilities, 10136bc36431SKalle Valo sizeof(ar->fw_capabilities)); 101497e0496dSKalle Valo break; 10151b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR: 10161b4304daSKalle Valo if (ie_len != sizeof(*val)) 10171b4304daSKalle Valo break; 10181b4304daSKalle Valo 10191b4304daSKalle Valo val = (__le32 *) data; 10201b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val); 10216bc36431SKalle Valo 10226bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 102303ef0250SKalle Valo "found patch address ie 0x%x\n", 10246bc36431SKalle Valo ar->hw.dataset_patch_addr); 10251b4304daSKalle Valo break; 102603ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR: 102703ef0250SKalle Valo if (ie_len != sizeof(*val)) 102803ef0250SKalle Valo break; 102903ef0250SKalle Valo 103003ef0250SKalle Valo val = (__le32 *) data; 103103ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val); 103203ef0250SKalle Valo 103303ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 103403ef0250SKalle Valo "found board address ie 0x%x\n", 103503ef0250SKalle Valo ar->hw.board_addr); 103603ef0250SKalle Valo break; 1037368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX: 1038368b1b0fSKalle Valo if (ie_len != sizeof(*val)) 1039368b1b0fSKalle Valo break; 1040368b1b0fSKalle Valo 1041368b1b0fSKalle Valo val = (__le32 *) data; 1042368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val), 1043368b1b0fSKalle Valo ATH6KL_VIF_MAX); 1044368b1b0fSKalle Valo 1045f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p) 1046f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2; 1047f143379dSVasanthakumar Thiagarajan 1048368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1049368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max); 1050368b1b0fSKalle Valo break; 105150d41234SKalle Valo default: 10526bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", 105350d41234SKalle Valo le32_to_cpup(&hdr->id)); 105450d41234SKalle Valo break; 105550d41234SKalle Valo } 105650d41234SKalle Valo 105750d41234SKalle Valo len -= ie_len; 105850d41234SKalle Valo data += ie_len; 105950d41234SKalle Valo }; 106050d41234SKalle Valo 106150d41234SKalle Valo ret = 0; 106250d41234SKalle Valo out: 106350d41234SKalle Valo release_firmware(fw); 106450d41234SKalle Valo 106550d41234SKalle Valo return ret; 106650d41234SKalle Valo } 106750d41234SKalle Valo 106850d41234SKalle Valo static int ath6kl_fetch_firmwares(struct ath6kl *ar) 106950d41234SKalle Valo { 107050d41234SKalle Valo int ret; 107150d41234SKalle Valo 107250d41234SKalle Valo ret = ath6kl_fetch_board_file(ar); 107350d41234SKalle Valo if (ret) 107450d41234SKalle Valo return ret; 107550d41234SKalle Valo 107665a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); 10776bc36431SKalle Valo if (ret == 0) { 107865a8b4ccSKalle Valo ar->fw_api = 3; 107965a8b4ccSKalle Valo goto out; 108065a8b4ccSKalle Valo } 108165a8b4ccSKalle Valo 108265a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); 108365a8b4ccSKalle Valo if (ret == 0) { 108465a8b4ccSKalle Valo ar->fw_api = 2; 108565a8b4ccSKalle Valo goto out; 10866bc36431SKalle Valo } 108750d41234SKalle Valo 108850d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar); 108950d41234SKalle Valo if (ret) 109050d41234SKalle Valo return ret; 109150d41234SKalle Valo 109265a8b4ccSKalle Valo ar->fw_api = 1; 109365a8b4ccSKalle Valo 109465a8b4ccSKalle Valo out: 109565a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); 10966bc36431SKalle Valo 109750d41234SKalle Valo return 0; 109850d41234SKalle Valo } 109950d41234SKalle Valo 1100bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 1101bdcd8170SKalle Valo { 1102bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 110331024d99SKevin Fang u32 board_data_size, board_ext_data_size; 1104bdcd8170SKalle Valo int ret; 1105bdcd8170SKalle Valo 1106772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL)) 1107772c31eeSKalle Valo return -ENOENT; 1108bdcd8170SKalle Valo 110931024d99SKevin Fang /* 111031024d99SKevin Fang * Determine where in Target RAM to write Board Data. 111131024d99SKevin Fang * For AR6004, host determine Target RAM address for 111231024d99SKevin Fang * writing board data. 111331024d99SKevin Fang */ 11140d4d72bfSKalle Valo if (ar->hw.board_addr != 0) { 11150d4d72bfSKalle Valo board_address = ar->hw.board_addr; 111631024d99SKevin Fang ath6kl_bmi_write(ar, 111731024d99SKevin Fang ath6kl_get_hi_item_addr(ar, 111831024d99SKevin Fang HI_ITEM(hi_board_data)), 111931024d99SKevin Fang (u8 *) &board_address, 4); 112031024d99SKevin Fang } else { 1121bdcd8170SKalle Valo ath6kl_bmi_read(ar, 1122bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1123bdcd8170SKalle Valo HI_ITEM(hi_board_data)), 1124bdcd8170SKalle Valo (u8 *) &board_address, 4); 112531024d99SKevin Fang } 112631024d99SKevin Fang 1127bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 1128bdcd8170SKalle Valo ath6kl_bmi_read(ar, 1129bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1130bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 1131bdcd8170SKalle Valo (u8 *) &board_ext_address, 4); 1132bdcd8170SKalle Valo 113350e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 && 113450e2740bSKalle Valo board_ext_address == 0) { 1135bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 1136bdcd8170SKalle Valo return -EINVAL; 1137bdcd8170SKalle Valo } 1138bdcd8170SKalle Valo 113931024d99SKevin Fang switch (ar->target_type) { 114031024d99SKevin Fang case TARGET_TYPE_AR6003: 114131024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 114231024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 114331024d99SKevin Fang break; 114431024d99SKevin Fang case TARGET_TYPE_AR6004: 114531024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 114631024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 114731024d99SKevin Fang break; 114831024d99SKevin Fang default: 114931024d99SKevin Fang WARN_ON(1); 115031024d99SKevin Fang return -EINVAL; 115131024d99SKevin Fang break; 115231024d99SKevin Fang } 115331024d99SKevin Fang 115450e2740bSKalle Valo if (board_ext_address && 115550e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) { 115631024d99SKevin Fang 1157bdcd8170SKalle Valo /* write extended board data */ 11586bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11596bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n", 11606bc36431SKalle Valo board_ext_address, board_ext_data_size); 11616bc36431SKalle Valo 1162bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 116331024d99SKevin Fang ar->fw_board + board_data_size, 116431024d99SKevin Fang board_ext_data_size); 1165bdcd8170SKalle Valo if (ret) { 1166bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 1167bdcd8170SKalle Valo ret); 1168bdcd8170SKalle Valo return ret; 1169bdcd8170SKalle Valo } 1170bdcd8170SKalle Valo 1171bdcd8170SKalle Valo /* record that extended board data is initialized */ 117231024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 117331024d99SKevin Fang 1174bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1175bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1176bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data_config)), 1177bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 1178bdcd8170SKalle Valo } 1179bdcd8170SKalle Valo 118031024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 1181bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 1182bdcd8170SKalle Valo ret = -EINVAL; 1183bdcd8170SKalle Valo return ret; 1184bdcd8170SKalle Valo } 1185bdcd8170SKalle Valo 11866bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", 11876bc36431SKalle Valo board_address, board_data_size); 11886bc36431SKalle Valo 1189bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 119031024d99SKevin Fang board_data_size); 1191bdcd8170SKalle Valo 1192bdcd8170SKalle Valo if (ret) { 1193bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 1194bdcd8170SKalle Valo return ret; 1195bdcd8170SKalle Valo } 1196bdcd8170SKalle Valo 1197bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 1198bdcd8170SKalle Valo param = 1; 1199bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1200bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1201bdcd8170SKalle Valo HI_ITEM(hi_board_data_initialized)), 1202bdcd8170SKalle Valo (u8 *)¶m, 4); 1203bdcd8170SKalle Valo 1204bdcd8170SKalle Valo return ret; 1205bdcd8170SKalle Valo } 1206bdcd8170SKalle Valo 1207bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 1208bdcd8170SKalle Valo { 1209bdcd8170SKalle Valo u32 address, param; 1210bef26a7fSKalle Valo bool from_hw = false; 1211bdcd8170SKalle Valo int ret; 1212bdcd8170SKalle Valo 121350e2740bSKalle Valo if (ar->fw_otp == NULL) 121450e2740bSKalle Valo return 0; 1215bdcd8170SKalle Valo 1216a01ac414SKalle Valo address = ar->hw.app_load_addr; 1217bdcd8170SKalle Valo 1218ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, 12196bc36431SKalle Valo ar->fw_otp_len); 12206bc36431SKalle Valo 1221bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 1222bdcd8170SKalle Valo ar->fw_otp_len); 1223bdcd8170SKalle Valo if (ret) { 1224bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 1225bdcd8170SKalle Valo return ret; 1226bdcd8170SKalle Valo } 1227bdcd8170SKalle Valo 1228639d0b89SKalle Valo /* read firmware start address */ 1229639d0b89SKalle Valo ret = ath6kl_bmi_read(ar, 1230639d0b89SKalle Valo ath6kl_get_hi_item_addr(ar, 1231639d0b89SKalle Valo HI_ITEM(hi_app_start)), 1232639d0b89SKalle Valo (u8 *) &address, sizeof(address)); 1233639d0b89SKalle Valo 1234639d0b89SKalle Valo if (ret) { 1235639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1236639d0b89SKalle Valo return ret; 1237639d0b89SKalle Valo } 1238639d0b89SKalle Valo 1239bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) { 1240639d0b89SKalle Valo ar->hw.app_start_override_addr = address; 1241bef26a7fSKalle Valo from_hw = true; 1242bef26a7fSKalle Valo } 1243639d0b89SKalle Valo 1244bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", 1245bef26a7fSKalle Valo from_hw ? " (from hw)" : "", 12466bc36431SKalle Valo ar->hw.app_start_override_addr); 12476bc36431SKalle Valo 1248bdcd8170SKalle Valo /* execute the OTP code */ 1249bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", 1250bef26a7fSKalle Valo ar->hw.app_start_override_addr); 1251bdcd8170SKalle Valo param = 0; 1252bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); 1253bdcd8170SKalle Valo 1254bdcd8170SKalle Valo return ret; 1255bdcd8170SKalle Valo } 1256bdcd8170SKalle Valo 1257bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 1258bdcd8170SKalle Valo { 1259bdcd8170SKalle Valo u32 address; 1260bdcd8170SKalle Valo int ret; 1261bdcd8170SKalle Valo 1262772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL)) 126350e2740bSKalle Valo return 0; 1264bdcd8170SKalle Valo 1265a01ac414SKalle Valo address = ar->hw.app_load_addr; 1266bdcd8170SKalle Valo 1267ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", 12686bc36431SKalle Valo address, ar->fw_len); 12696bc36431SKalle Valo 1270bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 1271bdcd8170SKalle Valo 1272bdcd8170SKalle Valo if (ret) { 1273bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 1274bdcd8170SKalle Valo return ret; 1275bdcd8170SKalle Valo } 1276bdcd8170SKalle Valo 127731024d99SKevin Fang /* 127831024d99SKevin Fang * Set starting address for firmware 127931024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 128031024d99SKevin Fang */ 128131024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1282a01ac414SKalle Valo address = ar->hw.app_start_override_addr; 1283bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 128431024d99SKevin Fang } 1285bdcd8170SKalle Valo return ret; 1286bdcd8170SKalle Valo } 1287bdcd8170SKalle Valo 1288bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 1289bdcd8170SKalle Valo { 1290bdcd8170SKalle Valo u32 address, param; 1291bdcd8170SKalle Valo int ret; 1292bdcd8170SKalle Valo 129350e2740bSKalle Valo if (ar->fw_patch == NULL) 129450e2740bSKalle Valo return 0; 1295bdcd8170SKalle Valo 1296a01ac414SKalle Valo address = ar->hw.dataset_patch_addr; 1297bdcd8170SKalle Valo 1298ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", 12996bc36431SKalle Valo address, ar->fw_patch_len); 13006bc36431SKalle Valo 1301bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 1302bdcd8170SKalle Valo if (ret) { 1303bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 1304bdcd8170SKalle Valo return ret; 1305bdcd8170SKalle Valo } 1306bdcd8170SKalle Valo 1307bdcd8170SKalle Valo param = address; 1308bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1309bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1310bdcd8170SKalle Valo HI_ITEM(hi_dset_list_head)), 1311bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 1312bdcd8170SKalle Valo 1313bdcd8170SKalle Valo return 0; 1314bdcd8170SKalle Valo } 1315bdcd8170SKalle Valo 1316cd23c1c9SAlex Yang static int ath6kl_upload_testscript(struct ath6kl *ar) 1317cd23c1c9SAlex Yang { 1318cd23c1c9SAlex Yang u32 address, param; 1319cd23c1c9SAlex Yang int ret; 1320cd23c1c9SAlex Yang 1321cd23c1c9SAlex Yang if (testmode != 2) 1322cd23c1c9SAlex Yang return 0; 1323cd23c1c9SAlex Yang 1324cd23c1c9SAlex Yang if (ar->fw_testscript == NULL) 1325cd23c1c9SAlex Yang return 0; 1326cd23c1c9SAlex Yang 1327cd23c1c9SAlex Yang address = ar->hw.testscript_addr; 1328cd23c1c9SAlex Yang 1329cd23c1c9SAlex Yang ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n", 1330cd23c1c9SAlex Yang address, ar->fw_testscript_len); 1331cd23c1c9SAlex Yang 1332cd23c1c9SAlex Yang ret = ath6kl_bmi_write(ar, address, ar->fw_testscript, 1333cd23c1c9SAlex Yang ar->fw_testscript_len); 1334cd23c1c9SAlex Yang if (ret) { 1335cd23c1c9SAlex Yang ath6kl_err("Failed to write testscript file: %d\n", ret); 1336cd23c1c9SAlex Yang return ret; 1337cd23c1c9SAlex Yang } 1338cd23c1c9SAlex Yang 1339cd23c1c9SAlex Yang param = address; 1340cd23c1c9SAlex Yang ath6kl_bmi_write(ar, 1341cd23c1c9SAlex Yang ath6kl_get_hi_item_addr(ar, 1342cd23c1c9SAlex Yang HI_ITEM(hi_ota_testscript)), 1343cd23c1c9SAlex Yang (unsigned char *) ¶m, 4); 1344cd23c1c9SAlex Yang 1345cd23c1c9SAlex Yang param = 4096; 1346cd23c1c9SAlex Yang ath6kl_bmi_write(ar, 1347cd23c1c9SAlex Yang ath6kl_get_hi_item_addr(ar, 1348cd23c1c9SAlex Yang HI_ITEM(hi_end_ram_reserve_sz)), 1349cd23c1c9SAlex Yang (unsigned char *) ¶m, 4); 1350cd23c1c9SAlex Yang 1351cd23c1c9SAlex Yang param = 1; 1352cd23c1c9SAlex Yang ath6kl_bmi_write(ar, 1353cd23c1c9SAlex Yang ath6kl_get_hi_item_addr(ar, 1354cd23c1c9SAlex Yang HI_ITEM(hi_test_apps_related)), 1355cd23c1c9SAlex Yang (unsigned char *) ¶m, 4); 1356cd23c1c9SAlex Yang 1357cd23c1c9SAlex Yang return 0; 1358cd23c1c9SAlex Yang } 1359cd23c1c9SAlex Yang 1360bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 1361bdcd8170SKalle Valo { 1362bdcd8170SKalle Valo u32 param, options, sleep, address; 1363bdcd8170SKalle Valo int status = 0; 1364bdcd8170SKalle Valo 136531024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 136631024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 1367bdcd8170SKalle Valo return -EINVAL; 1368bdcd8170SKalle Valo 1369bdcd8170SKalle Valo /* temporarily disable system sleep */ 1370bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1371bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1372bdcd8170SKalle Valo if (status) 1373bdcd8170SKalle Valo return status; 1374bdcd8170SKalle Valo 1375bdcd8170SKalle Valo options = param; 1376bdcd8170SKalle Valo 1377bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1378bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1379bdcd8170SKalle Valo if (status) 1380bdcd8170SKalle Valo return status; 1381bdcd8170SKalle Valo 1382bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1383bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1384bdcd8170SKalle Valo if (status) 1385bdcd8170SKalle Valo return status; 1386bdcd8170SKalle Valo 1387bdcd8170SKalle Valo sleep = param; 1388bdcd8170SKalle Valo 1389bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1390bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1391bdcd8170SKalle Valo if (status) 1392bdcd8170SKalle Valo return status; 1393bdcd8170SKalle Valo 1394bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1395bdcd8170SKalle Valo options, sleep); 1396bdcd8170SKalle Valo 1397bdcd8170SKalle Valo /* program analog PLL register */ 139831024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 139931024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1400bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1401bdcd8170SKalle Valo 0xF9104001); 140231024d99SKevin Fang 1403bdcd8170SKalle Valo if (status) 1404bdcd8170SKalle Valo return status; 1405bdcd8170SKalle Valo 1406bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1407bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1408bdcd8170SKalle Valo 1409bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1410bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1411bdcd8170SKalle Valo if (status) 1412bdcd8170SKalle Valo return status; 141331024d99SKevin Fang } 1414bdcd8170SKalle Valo 1415bdcd8170SKalle Valo param = 0; 1416bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1417bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1418bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1419bdcd8170SKalle Valo if (status) 1420bdcd8170SKalle Valo return status; 1421bdcd8170SKalle Valo 1422bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 14230d0192baSKalle Valo if (ar->version.target_ver == AR6003_HW_2_0_VERSION) { 1424bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1425bdcd8170SKalle Valo 1426bdcd8170SKalle Valo param = 0x20; 1427bdcd8170SKalle Valo 1428bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1429bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1430bdcd8170SKalle Valo if (status) 1431bdcd8170SKalle Valo return status; 1432bdcd8170SKalle Valo 1433bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1434bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1435bdcd8170SKalle Valo if (status) 1436bdcd8170SKalle Valo return status; 1437bdcd8170SKalle Valo 1438bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1439bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1440bdcd8170SKalle Valo if (status) 1441bdcd8170SKalle Valo return status; 1442bdcd8170SKalle Valo 1443bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1444bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1445bdcd8170SKalle Valo if (status) 1446bdcd8170SKalle Valo return status; 1447bdcd8170SKalle Valo } 1448bdcd8170SKalle Valo 1449bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1450bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1451bdcd8170SKalle Valo if (status) 1452bdcd8170SKalle Valo return status; 1453bdcd8170SKalle Valo 1454bdcd8170SKalle Valo /* transfer One time Programmable data */ 1455bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1456bdcd8170SKalle Valo if (status) 1457bdcd8170SKalle Valo return status; 1458bdcd8170SKalle Valo 1459bdcd8170SKalle Valo /* Download Target firmware */ 1460bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1461bdcd8170SKalle Valo if (status) 1462bdcd8170SKalle Valo return status; 1463bdcd8170SKalle Valo 1464bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1465bdcd8170SKalle Valo if (status) 1466bdcd8170SKalle Valo return status; 1467bdcd8170SKalle Valo 1468cd23c1c9SAlex Yang /* Download the test script */ 1469cd23c1c9SAlex Yang status = ath6kl_upload_testscript(ar); 1470cd23c1c9SAlex Yang if (status) 1471cd23c1c9SAlex Yang return status; 1472cd23c1c9SAlex Yang 1473bdcd8170SKalle Valo /* Restore system sleep */ 1474bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1475bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1476bdcd8170SKalle Valo if (status) 1477bdcd8170SKalle Valo return status; 1478bdcd8170SKalle Valo 1479bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1480bdcd8170SKalle Valo param = options | 0x20; 1481bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1482bdcd8170SKalle Valo if (status) 1483bdcd8170SKalle Valo return status; 1484bdcd8170SKalle Valo 1485bdcd8170SKalle Valo return status; 1486bdcd8170SKalle Valo } 1487bdcd8170SKalle Valo 1488a01ac414SKalle Valo static int ath6kl_init_hw_params(struct ath6kl *ar) 1489a01ac414SKalle Valo { 1490856f4b31SKalle Valo const struct ath6kl_hw *hw; 1491856f4b31SKalle Valo int i; 1492bef26a7fSKalle Valo 1493856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1494856f4b31SKalle Valo hw = &hw_list[i]; 1495bef26a7fSKalle Valo 1496856f4b31SKalle Valo if (hw->id == ar->version.target_ver) 1497a01ac414SKalle Valo break; 1498856f4b31SKalle Valo } 1499856f4b31SKalle Valo 1500856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) { 1501a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n", 1502a01ac414SKalle Valo ar->version.target_ver); 1503a01ac414SKalle Valo return -EINVAL; 1504a01ac414SKalle Valo } 1505a01ac414SKalle Valo 1506856f4b31SKalle Valo ar->hw = *hw; 1507856f4b31SKalle Valo 15086bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 15096bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", 15106bc36431SKalle Valo ar->version.target_ver, ar->target_type, 15116bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr); 15126bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 15136bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", 15146bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, 15156bc36431SKalle Valo ar->hw.reserved_ram_size); 151639586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT, 151739586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d", 151839586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin); 15196bc36431SKalle Valo 1520a01ac414SKalle Valo return 0; 1521a01ac414SKalle Valo } 1522a01ac414SKalle Valo 1523293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) 1524293badf4SKalle Valo { 1525293badf4SKalle Valo switch (type) { 1526293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO: 1527293badf4SKalle Valo return "sdio"; 1528293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB: 1529293badf4SKalle Valo return "usb"; 1530293badf4SKalle Valo } 1531293badf4SKalle Valo 1532293badf4SKalle Valo return NULL; 1533293badf4SKalle Valo } 1534293badf4SKalle Valo 15355fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar) 153620459ee2SKalle Valo { 153720459ee2SKalle Valo long timeleft; 153820459ee2SKalle Valo int ret, i; 153920459ee2SKalle Valo 15405fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); 15415fe4dffbSKalle Valo 154220459ee2SKalle Valo ret = ath6kl_hif_power_on(ar); 154320459ee2SKalle Valo if (ret) 154420459ee2SKalle Valo return ret; 154520459ee2SKalle Valo 154620459ee2SKalle Valo ret = ath6kl_configure_target(ar); 154720459ee2SKalle Valo if (ret) 154820459ee2SKalle Valo goto err_power_off; 154920459ee2SKalle Valo 155020459ee2SKalle Valo ret = ath6kl_init_upload(ar); 155120459ee2SKalle Valo if (ret) 155220459ee2SKalle Valo goto err_power_off; 155320459ee2SKalle Valo 155420459ee2SKalle Valo /* Do we need to finish the BMI phase */ 155520459ee2SKalle Valo /* FIXME: return error from ath6kl_bmi_done() */ 155620459ee2SKalle Valo if (ath6kl_bmi_done(ar)) { 155720459ee2SKalle Valo ret = -EIO; 155820459ee2SKalle Valo goto err_power_off; 155920459ee2SKalle Valo } 156020459ee2SKalle Valo 156120459ee2SKalle Valo /* 156220459ee2SKalle Valo * The reason we have to wait for the target here is that the 156320459ee2SKalle Valo * driver layer has to init BMI in order to set the host block 156420459ee2SKalle Valo * size. 156520459ee2SKalle Valo */ 156620459ee2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 156720459ee2SKalle Valo ret = -EIO; 156820459ee2SKalle Valo goto err_power_off; 156920459ee2SKalle Valo } 157020459ee2SKalle Valo 157120459ee2SKalle Valo if (ath6kl_init_service_ep(ar)) { 157220459ee2SKalle Valo ret = -EIO; 157320459ee2SKalle Valo goto err_cleanup_scatter; 157420459ee2SKalle Valo } 157520459ee2SKalle Valo 157620459ee2SKalle Valo /* setup credit distribution */ 157720459ee2SKalle Valo ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info); 157820459ee2SKalle Valo 157920459ee2SKalle Valo /* start HTC */ 158020459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target); 158120459ee2SKalle Valo if (ret) { 158220459ee2SKalle Valo /* FIXME: call this */ 158320459ee2SKalle Valo ath6kl_cookie_cleanup(ar); 158420459ee2SKalle Valo goto err_cleanup_scatter; 158520459ee2SKalle Valo } 158620459ee2SKalle Valo 158720459ee2SKalle Valo /* Wait for Wmi event to be ready */ 158820459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 158920459ee2SKalle Valo test_bit(WMI_READY, 159020459ee2SKalle Valo &ar->flag), 159120459ee2SKalle Valo WMI_TIMEOUT); 159220459ee2SKalle Valo 159320459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); 159420459ee2SKalle Valo 1595293badf4SKalle Valo 1596293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { 159765a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n", 1598293badf4SKalle Valo ar->hw.name, 1599293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type), 1600293badf4SKalle Valo ar->wiphy->fw_version, 160165a8b4ccSKalle Valo ar->fw_api, 1602293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); 1603293badf4SKalle Valo } 1604293badf4SKalle Valo 160520459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 160620459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 160720459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 160820459ee2SKalle Valo ret = -EIO; 160920459ee2SKalle Valo goto err_htc_stop; 161020459ee2SKalle Valo } 161120459ee2SKalle Valo 161220459ee2SKalle Valo if (!timeleft || signal_pending(current)) { 161320459ee2SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 161420459ee2SKalle Valo ret = -EIO; 161520459ee2SKalle Valo goto err_htc_stop; 161620459ee2SKalle Valo } 161720459ee2SKalle Valo 161820459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 161920459ee2SKalle Valo 162020459ee2SKalle Valo /* communicate the wmi protocol verision to the target */ 162120459ee2SKalle Valo /* FIXME: return error */ 162220459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 162320459ee2SKalle Valo ath6kl_err("unable to set the host app area\n"); 162420459ee2SKalle Valo 162571f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) { 162620459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i); 162720459ee2SKalle Valo if (ret) 162820459ee2SKalle Valo goto err_htc_stop; 162920459ee2SKalle Valo } 163020459ee2SKalle Valo 163176a9fbe2SKalle Valo ar->state = ATH6KL_STATE_ON; 163276a9fbe2SKalle Valo 163320459ee2SKalle Valo return 0; 163420459ee2SKalle Valo 163520459ee2SKalle Valo err_htc_stop: 163620459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target); 163720459ee2SKalle Valo err_cleanup_scatter: 163820459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar); 163920459ee2SKalle Valo err_power_off: 164020459ee2SKalle Valo ath6kl_hif_power_off(ar); 164120459ee2SKalle Valo 164220459ee2SKalle Valo return ret; 164320459ee2SKalle Valo } 164420459ee2SKalle Valo 16455fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar) 16465fe4dffbSKalle Valo { 16475fe4dffbSKalle Valo int ret; 16485fe4dffbSKalle Valo 16495fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); 16505fe4dffbSKalle Valo 16515fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target); 16525fe4dffbSKalle Valo 16535fe4dffbSKalle Valo ath6kl_hif_stop(ar); 16545fe4dffbSKalle Valo 16555fe4dffbSKalle Valo ath6kl_bmi_reset(ar); 16565fe4dffbSKalle Valo 16575fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar); 16585fe4dffbSKalle Valo if (ret) 16595fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret); 16605fe4dffbSKalle Valo 166176a9fbe2SKalle Valo ar->state = ATH6KL_STATE_OFF; 166276a9fbe2SKalle Valo 16635fe4dffbSKalle Valo return 0; 16645fe4dffbSKalle Valo } 16655fe4dffbSKalle Valo 1666bdcd8170SKalle Valo int ath6kl_core_init(struct ath6kl *ar) 1667bdcd8170SKalle Valo { 1668bdcd8170SKalle Valo struct ath6kl_bmi_target_info targ_info; 166961448a93SKalle Valo struct net_device *ndev; 167020459ee2SKalle Valo int ret = 0, i; 1671bdcd8170SKalle Valo 1672bdcd8170SKalle Valo ar->ath6kl_wq = create_singlethread_workqueue("ath6kl"); 1673bdcd8170SKalle Valo if (!ar->ath6kl_wq) 1674bdcd8170SKalle Valo return -ENOMEM; 1675bdcd8170SKalle Valo 1676bdcd8170SKalle Valo ret = ath6kl_bmi_init(ar); 1677bdcd8170SKalle Valo if (ret) 1678bdcd8170SKalle Valo goto err_wq; 1679bdcd8170SKalle Valo 168020459ee2SKalle Valo /* 168120459ee2SKalle Valo * Turn on power to get hardware (target) version and leave power 168220459ee2SKalle Valo * on delibrately as we will boot the hardware anyway within few 168320459ee2SKalle Valo * seconds. 168420459ee2SKalle Valo */ 1685b2e75698SKalle Valo ret = ath6kl_hif_power_on(ar); 1686bdcd8170SKalle Valo if (ret) 1687bdcd8170SKalle Valo goto err_bmi_cleanup; 1688bdcd8170SKalle Valo 1689b2e75698SKalle Valo ret = ath6kl_bmi_get_target_info(ar, &targ_info); 1690b2e75698SKalle Valo if (ret) 1691b2e75698SKalle Valo goto err_power_off; 1692b2e75698SKalle Valo 1693bdcd8170SKalle Valo ar->version.target_ver = le32_to_cpu(targ_info.version); 1694bdcd8170SKalle Valo ar->target_type = le32_to_cpu(targ_info.type); 1695be98e3a4SVasanthakumar Thiagarajan ar->wiphy->hw_version = le32_to_cpu(targ_info.version); 1696bdcd8170SKalle Valo 1697a01ac414SKalle Valo ret = ath6kl_init_hw_params(ar); 1698a01ac414SKalle Valo if (ret) 1699b2e75698SKalle Valo goto err_power_off; 1700a01ac414SKalle Valo 1701ad226ec2SKalle Valo ar->htc_target = ath6kl_htc_create(ar); 1702bdcd8170SKalle Valo 1703bdcd8170SKalle Valo if (!ar->htc_target) { 1704bdcd8170SKalle Valo ret = -ENOMEM; 1705b2e75698SKalle Valo goto err_power_off; 1706bdcd8170SKalle Valo } 1707bdcd8170SKalle Valo 1708772c31eeSKalle Valo ret = ath6kl_fetch_firmwares(ar); 1709772c31eeSKalle Valo if (ret) 1710772c31eeSKalle Valo goto err_htc_cleanup; 1711772c31eeSKalle Valo 171261448a93SKalle Valo /* FIXME: we should free all firmwares in the error cases below */ 171361448a93SKalle Valo 171461448a93SKalle Valo /* Indicate that WMI is enabled (although not ready yet) */ 171561448a93SKalle Valo set_bit(WMI_ENABLED, &ar->flag); 171661448a93SKalle Valo ar->wmi = ath6kl_wmi_init(ar); 171761448a93SKalle Valo if (!ar->wmi) { 171861448a93SKalle Valo ath6kl_err("failed to initialize wmi\n"); 171961448a93SKalle Valo ret = -EIO; 172061448a93SKalle Valo goto err_htc_cleanup; 172161448a93SKalle Valo } 172261448a93SKalle Valo 172361448a93SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: got wmi @ 0x%p.\n", __func__, ar->wmi); 172461448a93SKalle Valo 172546d33a21SKalle Valo ret = ath6kl_cfg80211_init(ar); 172661448a93SKalle Valo if (ret) 172761448a93SKalle Valo goto err_node_cleanup; 172861448a93SKalle Valo 172961448a93SKalle Valo ret = ath6kl_debug_init(ar); 173061448a93SKalle Valo if (ret) { 173161448a93SKalle Valo wiphy_unregister(ar->wiphy); 173261448a93SKalle Valo goto err_node_cleanup; 173361448a93SKalle Valo } 173461448a93SKalle Valo 173571f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 173661448a93SKalle Valo ar->avail_idx_map |= BIT(i); 173761448a93SKalle Valo 173861448a93SKalle Valo rtnl_lock(); 173961448a93SKalle Valo 174061448a93SKalle Valo /* Add an initial station interface */ 174161448a93SKalle Valo ndev = ath6kl_interface_add(ar, "wlan%d", NL80211_IFTYPE_STATION, 0, 174261448a93SKalle Valo INFRA_NETWORK); 174361448a93SKalle Valo 174461448a93SKalle Valo rtnl_unlock(); 174561448a93SKalle Valo 174661448a93SKalle Valo if (!ndev) { 174761448a93SKalle Valo ath6kl_err("Failed to instantiate a network device\n"); 174861448a93SKalle Valo ret = -ENOMEM; 174961448a93SKalle Valo wiphy_unregister(ar->wiphy); 175061448a93SKalle Valo goto err_debug_init; 175161448a93SKalle Valo } 175261448a93SKalle Valo 175361448a93SKalle Valo 175461448a93SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: name=%s dev=0x%p, ar=0x%p\n", 175561448a93SKalle Valo __func__, ndev->name, ndev, ar); 175661448a93SKalle Valo 175761448a93SKalle Valo /* setup access class priority mappings */ 175861448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_BK] = 0; /* lowest */ 175961448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_BE] = 1; 176061448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_VI] = 2; 176161448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_VO] = 3; /* highest */ 176261448a93SKalle Valo 176361448a93SKalle Valo /* give our connected endpoints some buffers */ 176461448a93SKalle Valo ath6kl_rx_refill(ar->htc_target, ar->ctrl_ep); 176561448a93SKalle Valo ath6kl_rx_refill(ar->htc_target, ar->ac2ep_map[WMM_AC_BE]); 176661448a93SKalle Valo 176761448a93SKalle Valo /* allocate some buffers that handle larger AMSDU frames */ 176861448a93SKalle Valo ath6kl_refill_amsdu_rxbufs(ar, ATH6KL_MAX_AMSDU_RX_BUFFERS); 176961448a93SKalle Valo 177061448a93SKalle Valo ath6kl_cookie_init(ar); 177161448a93SKalle Valo 177261448a93SKalle Valo ar->conf_flags = ATH6KL_CONF_IGNORE_ERP_BARKER | 177361448a93SKalle Valo ATH6KL_CONF_ENABLE_11N | ATH6KL_CONF_ENABLE_TX_BURST; 177461448a93SKalle Valo 17758277de15SKalle Valo if (suspend_cutpower) 17768277de15SKalle Valo ar->conf_flags |= ATH6KL_CONF_SUSPEND_CUTPOWER; 17778277de15SKalle Valo 1778*f29af978SKalle Valo if (uart_debug) 1779*f29af978SKalle Valo ar->conf_flags |= ATH6KL_CONF_UART_DEBUG; 1780*f29af978SKalle Valo 178161448a93SKalle Valo ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM | 1782fb94333aSArik Nemtsov WIPHY_FLAG_HAVE_AP_SME | 17837e95e365SKalle Valo WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL | 1784fb94333aSArik Nemtsov WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD; 1785fb94333aSArik Nemtsov 178610509f90SKalle Valo if (test_bit(ATH6KL_FW_CAPABILITY_SCHED_SCAN, ar->fw_capabilities)) 178710509f90SKalle Valo ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN; 178810509f90SKalle Valo 1789fb94333aSArik Nemtsov ar->wiphy->probe_resp_offload = 1790fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS | 1791fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2 | 1792fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P | 1793fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_80211U; 179461448a93SKalle Valo 17955fe4dffbSKalle Valo set_bit(FIRST_BOOT, &ar->flag); 17965fe4dffbSKalle Valo 1797bc48ad31SRishi Panjwani ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; 1798bc48ad31SRishi Panjwani 17995fe4dffbSKalle Valo ret = ath6kl_init_hw_start(ar); 180020459ee2SKalle Valo if (ret) { 18015fe4dffbSKalle Valo ath6kl_err("Failed to start hardware: %d\n", ret); 180220459ee2SKalle Valo goto err_rxbuf_cleanup; 180361448a93SKalle Valo } 180461448a93SKalle Valo 180561448a93SKalle Valo /* 180661448a93SKalle Valo * Set mac address which is received in ready event 180761448a93SKalle Valo * FIXME: Move to ath6kl_interface_add() 180861448a93SKalle Valo */ 180961448a93SKalle Valo memcpy(ndev->dev_addr, ar->mac_addr, ETH_ALEN); 1810bdcd8170SKalle Valo 1811bdcd8170SKalle Valo return ret; 1812bdcd8170SKalle Valo 181361448a93SKalle Valo err_rxbuf_cleanup: 181461448a93SKalle Valo ath6kl_htc_flush_rx_buf(ar->htc_target); 181561448a93SKalle Valo ath6kl_cleanup_amsdu_rxbufs(ar); 181661448a93SKalle Valo rtnl_lock(); 1817c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(netdev_priv(ndev)); 181861448a93SKalle Valo rtnl_unlock(); 181961448a93SKalle Valo wiphy_unregister(ar->wiphy); 182061448a93SKalle Valo err_debug_init: 182161448a93SKalle Valo ath6kl_debug_cleanup(ar); 182261448a93SKalle Valo err_node_cleanup: 182361448a93SKalle Valo ath6kl_wmi_shutdown(ar->wmi); 182461448a93SKalle Valo clear_bit(WMI_ENABLED, &ar->flag); 182561448a93SKalle Valo ar->wmi = NULL; 1826bdcd8170SKalle Valo err_htc_cleanup: 1827ad226ec2SKalle Valo ath6kl_htc_cleanup(ar->htc_target); 1828b2e75698SKalle Valo err_power_off: 1829b2e75698SKalle Valo ath6kl_hif_power_off(ar); 1830bdcd8170SKalle Valo err_bmi_cleanup: 1831bdcd8170SKalle Valo ath6kl_bmi_cleanup(ar); 1832bdcd8170SKalle Valo err_wq: 1833bdcd8170SKalle Valo destroy_workqueue(ar->ath6kl_wq); 18348dafb70eSVasanthakumar Thiagarajan 1835bdcd8170SKalle Valo return ret; 1836bdcd8170SKalle Valo } 1837bdcd8170SKalle Valo 1838c25889e8SKalle Valo /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */ 183955055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) 18406db8fa53SVasanthakumar Thiagarajan { 18416db8fa53SVasanthakumar Thiagarajan static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 18426db8fa53SVasanthakumar Thiagarajan bool discon_issued; 18436db8fa53SVasanthakumar Thiagarajan 18446db8fa53SVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 18456db8fa53SVasanthakumar Thiagarajan 18466db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &vif->flags); 18476db8fa53SVasanthakumar Thiagarajan 18486db8fa53SVasanthakumar Thiagarajan if (wmi_ready) { 18496db8fa53SVasanthakumar Thiagarajan discon_issued = test_bit(CONNECTED, &vif->flags) || 18506db8fa53SVasanthakumar Thiagarajan test_bit(CONNECT_PEND, &vif->flags); 18516db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect(vif); 18526db8fa53SVasanthakumar Thiagarajan del_timer(&vif->disconnect_timer); 18536db8fa53SVasanthakumar Thiagarajan 18546db8fa53SVasanthakumar Thiagarajan if (discon_issued) 18556db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect_event(vif, DISCONNECT_CMD, 18566db8fa53SVasanthakumar Thiagarajan (vif->nw_type & AP_NETWORK) ? 18576db8fa53SVasanthakumar Thiagarajan bcast_mac : vif->bssid, 18586db8fa53SVasanthakumar Thiagarajan 0, NULL, 0); 18596db8fa53SVasanthakumar Thiagarajan } 18606db8fa53SVasanthakumar Thiagarajan 18616db8fa53SVasanthakumar Thiagarajan if (vif->scan_req) { 18626db8fa53SVasanthakumar Thiagarajan cfg80211_scan_done(vif->scan_req, true); 18636db8fa53SVasanthakumar Thiagarajan vif->scan_req = NULL; 18646db8fa53SVasanthakumar Thiagarajan } 18656db8fa53SVasanthakumar Thiagarajan } 18666db8fa53SVasanthakumar Thiagarajan 1867bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1868bdcd8170SKalle Valo { 1869990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif; 1870bdcd8170SKalle Valo 1871bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1872bdcd8170SKalle Valo 1873bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1874bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1875bdcd8170SKalle Valo return; 1876bdcd8170SKalle Valo } 1877bdcd8170SKalle Valo 187811f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1879990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { 1880990bd915SVasanthakumar Thiagarajan list_del(&vif->list); 188111f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1882990bd915SVasanthakumar Thiagarajan ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); 188327929723SVasanthakumar Thiagarajan rtnl_lock(); 1884c25889e8SKalle Valo ath6kl_cfg80211_vif_cleanup(vif); 188527929723SVasanthakumar Thiagarajan rtnl_unlock(); 188611f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1887990bd915SVasanthakumar Thiagarajan } 188811f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1889bdcd8170SKalle Valo 18906db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag); 18916db8fa53SVasanthakumar Thiagarajan 18926db8fa53SVasanthakumar Thiagarajan /* 18936db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We 18946db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and 18956db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually 18966db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect 18976db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes 18986db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs 18996db8fa53SVasanthakumar Thiagarajan * are collected. 19006db8fa53SVasanthakumar Thiagarajan */ 19016db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi); 19026db8fa53SVasanthakumar Thiagarajan 19036db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag); 19046db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) { 19056db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); 19066db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target); 1907bdcd8170SKalle Valo } 1908bdcd8170SKalle Valo 1909bdcd8170SKalle Valo /* 19106db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been 19116db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session. 1912bdcd8170SKalle Valo */ 19136db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, 19146db8fa53SVasanthakumar Thiagarajan "attempting to reset target on instance destroy\n"); 19156db8fa53SVasanthakumar Thiagarajan ath6kl_reset_device(ar, ar->target_type, true, true); 1916bdcd8170SKalle Valo 19176db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &ar->flag); 1918bdcd8170SKalle Valo } 1919