1bdcd8170SKalle Valo 2bdcd8170SKalle Valo /* 3bdcd8170SKalle Valo * Copyright (c) 2011 Atheros Communications Inc. 4bdcd8170SKalle Valo * 5bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 6bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 7bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 8bdcd8170SKalle Valo * 9bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16bdcd8170SKalle Valo */ 17bdcd8170SKalle Valo 18c6efe578SStephen Rothwell #include <linux/moduleparam.h> 19f7830202SSangwook Lee #include <linux/errno.h> 2092ecbff4SSam Leffler #include <linux/of.h> 21bdcd8170SKalle Valo #include <linux/mmc/sdio_func.h> 22bdcd8170SKalle Valo #include "core.h" 23bdcd8170SKalle Valo #include "cfg80211.h" 24bdcd8170SKalle Valo #include "target.h" 25bdcd8170SKalle Valo #include "debug.h" 26bdcd8170SKalle Valo #include "hif-ops.h" 27bdcd8170SKalle Valo 28bdcd8170SKalle Valo unsigned int debug_mask; 29003353b0SKalle Valo static unsigned int testmode; 308277de15SKalle Valo static bool suspend_cutpower; 31*a10e2f2fSVasanthakumar Thiagarajan static unsigned int uart_debug; 32bdcd8170SKalle Valo 33bdcd8170SKalle Valo module_param(debug_mask, uint, 0644); 34003353b0SKalle Valo module_param(testmode, uint, 0644); 358277de15SKalle Valo module_param(suspend_cutpower, bool, 0444); 36*a10e2f2fSVasanthakumar Thiagarajan module_param(uart_debug, uint, 0644); 37bdcd8170SKalle Valo 38856f4b31SKalle Valo static const struct ath6kl_hw hw_list[] = { 39856f4b31SKalle Valo { 400d0192baSKalle Valo .id = AR6003_HW_2_0_VERSION, 41293badf4SKalle Valo .name = "ar6003 hw 2.0", 42856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 43856f4b31SKalle Valo .app_load_addr = 0x543180, 44856f4b31SKalle Valo .board_ext_data_addr = 0x57e500, 45856f4b31SKalle Valo .reserved_ram_size = 6912, 4639586bf2SRyan Hsu .refclk_hz = 26000000, 4739586bf2SRyan Hsu .uarttx_pin = 8, 48856f4b31SKalle Valo 49856f4b31SKalle Valo /* hw2.0 needs override address hardcoded */ 50856f4b31SKalle Valo .app_start_override_addr = 0x944C00, 51d1a9421dSKalle Valo 52c0038972SKalle Valo .fw = { 53c0038972SKalle Valo .dir = AR6003_HW_2_0_FW_DIR, 54c0038972SKalle Valo .otp = AR6003_HW_2_0_OTP_FILE, 55d1a9421dSKalle Valo .fw = AR6003_HW_2_0_FIRMWARE_FILE, 56c0038972SKalle Valo .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE, 57c0038972SKalle Valo .patch = AR6003_HW_2_0_PATCH_FILE, 58c0038972SKalle Valo }, 59c0038972SKalle Valo 60d1a9421dSKalle Valo .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE, 61d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE, 62856f4b31SKalle Valo }, 63856f4b31SKalle Valo { 640d0192baSKalle Valo .id = AR6003_HW_2_1_1_VERSION, 65293badf4SKalle Valo .name = "ar6003 hw 2.1.1", 66856f4b31SKalle Valo .dataset_patch_addr = 0x57ff74, 67856f4b31SKalle Valo .app_load_addr = 0x1234, 68856f4b31SKalle Valo .board_ext_data_addr = 0x542330, 69856f4b31SKalle Valo .reserved_ram_size = 512, 7039586bf2SRyan Hsu .refclk_hz = 26000000, 7139586bf2SRyan Hsu .uarttx_pin = 8, 72d1a9421dSKalle Valo 73c0038972SKalle Valo .fw = { 74c0038972SKalle Valo .dir = AR6003_HW_2_1_1_FW_DIR, 75c0038972SKalle Valo .otp = AR6003_HW_2_1_1_OTP_FILE, 76d1a9421dSKalle Valo .fw = AR6003_HW_2_1_1_FIRMWARE_FILE, 77c0038972SKalle Valo .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE, 78c0038972SKalle Valo .patch = AR6003_HW_2_1_1_PATCH_FILE, 79c0038972SKalle Valo }, 80c0038972SKalle Valo 81d1a9421dSKalle Valo .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE, 82d1a9421dSKalle Valo .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE, 83856f4b31SKalle Valo }, 84856f4b31SKalle Valo { 850d0192baSKalle Valo .id = AR6004_HW_1_0_VERSION, 86293badf4SKalle Valo .name = "ar6004 hw 1.0", 87856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 88856f4b31SKalle Valo .app_load_addr = 0x1234, 89856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 90856f4b31SKalle Valo .reserved_ram_size = 19456, 910d4d72bfSKalle Valo .board_addr = 0x433900, 9239586bf2SRyan Hsu .refclk_hz = 26000000, 9339586bf2SRyan Hsu .uarttx_pin = 11, 94d1a9421dSKalle Valo 95c0038972SKalle Valo .fw = { 96c0038972SKalle Valo .dir = AR6004_HW_1_0_FW_DIR, 97d1a9421dSKalle Valo .fw = AR6004_HW_1_0_FIRMWARE_FILE, 98c0038972SKalle Valo }, 99c0038972SKalle Valo 100d1a9421dSKalle Valo .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE, 101d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE, 102856f4b31SKalle Valo }, 103856f4b31SKalle Valo { 1040d0192baSKalle Valo .id = AR6004_HW_1_1_VERSION, 105293badf4SKalle Valo .name = "ar6004 hw 1.1", 106856f4b31SKalle Valo .dataset_patch_addr = 0x57e884, 107856f4b31SKalle Valo .app_load_addr = 0x1234, 108856f4b31SKalle Valo .board_ext_data_addr = 0x437000, 109856f4b31SKalle Valo .reserved_ram_size = 11264, 1100d4d72bfSKalle Valo .board_addr = 0x43d400, 11139586bf2SRyan Hsu .refclk_hz = 40000000, 11239586bf2SRyan Hsu .uarttx_pin = 11, 113d1a9421dSKalle Valo 114c0038972SKalle Valo .fw = { 115c0038972SKalle Valo .dir = AR6004_HW_1_1_FW_DIR, 116d1a9421dSKalle Valo .fw = AR6004_HW_1_1_FIRMWARE_FILE, 117c0038972SKalle Valo }, 118c0038972SKalle Valo 119d1a9421dSKalle Valo .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE, 120d1a9421dSKalle Valo .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE, 121856f4b31SKalle Valo }, 122856f4b31SKalle Valo }; 123856f4b31SKalle Valo 124bdcd8170SKalle Valo /* 125bdcd8170SKalle Valo * Include definitions here that can be used to tune the WLAN module 126bdcd8170SKalle Valo * behavior. Different customers can tune the behavior as per their needs, 127bdcd8170SKalle Valo * here. 128bdcd8170SKalle Valo */ 129bdcd8170SKalle Valo 130bdcd8170SKalle Valo /* 131bdcd8170SKalle Valo * This configuration item enable/disable keepalive support. 132bdcd8170SKalle Valo * Keepalive support: In the absence of any data traffic to AP, null 133bdcd8170SKalle Valo * frames will be sent to the AP at periodic interval, to keep the association 134bdcd8170SKalle Valo * active. This configuration item defines the periodic interval. 135bdcd8170SKalle Valo * Use value of zero to disable keepalive support 136bdcd8170SKalle Valo * Default: 60 seconds 137bdcd8170SKalle Valo */ 138bdcd8170SKalle Valo #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60 139bdcd8170SKalle Valo 140bdcd8170SKalle Valo /* 141bdcd8170SKalle Valo * This configuration item sets the value of disconnect timeout 142bdcd8170SKalle Valo * Firmware delays sending the disconnec event to the host for this 143bdcd8170SKalle Valo * timeout after is gets disconnected from the current AP. 144bdcd8170SKalle Valo * If the firmware successly roams within the disconnect timeout 145bdcd8170SKalle Valo * it sends a new connect event 146bdcd8170SKalle Valo */ 147bdcd8170SKalle Valo #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10 148bdcd8170SKalle Valo 149bdcd8170SKalle Valo 150bdcd8170SKalle Valo #define ATH6KL_DATA_OFFSET 64 151bdcd8170SKalle Valo struct sk_buff *ath6kl_buf_alloc(int size) 152bdcd8170SKalle Valo { 153bdcd8170SKalle Valo struct sk_buff *skb; 154bdcd8170SKalle Valo u16 reserved; 155bdcd8170SKalle Valo 156bdcd8170SKalle Valo /* Add chacheline space at front and back of buffer */ 157bdcd8170SKalle Valo reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET + 1581df94a85SVasanthakumar Thiagarajan sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES; 159bdcd8170SKalle Valo skb = dev_alloc_skb(size + reserved); 160bdcd8170SKalle Valo 161bdcd8170SKalle Valo if (skb) 162bdcd8170SKalle Valo skb_reserve(skb, reserved - L1_CACHE_BYTES); 163bdcd8170SKalle Valo return skb; 164bdcd8170SKalle Valo } 165bdcd8170SKalle Valo 166e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_profile_info(struct ath6kl_vif *vif) 167bdcd8170SKalle Valo { 1683450334fSVasanthakumar Thiagarajan vif->ssid_len = 0; 1693450334fSVasanthakumar Thiagarajan memset(vif->ssid, 0, sizeof(vif->ssid)); 1703450334fSVasanthakumar Thiagarajan 1713450334fSVasanthakumar Thiagarajan vif->dot11_auth_mode = OPEN_AUTH; 1723450334fSVasanthakumar Thiagarajan vif->auth_mode = NONE_AUTH; 1733450334fSVasanthakumar Thiagarajan vif->prwise_crypto = NONE_CRYPT; 1743450334fSVasanthakumar Thiagarajan vif->prwise_crypto_len = 0; 1753450334fSVasanthakumar Thiagarajan vif->grp_crypto = NONE_CRYPT; 1763450334fSVasanthakumar Thiagarajan vif->grp_crypto_len = 0; 1776f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 1788c8b65e3SVasanthakumar Thiagarajan memset(vif->req_bssid, 0, sizeof(vif->req_bssid)); 1798c8b65e3SVasanthakumar Thiagarajan memset(vif->bssid, 0, sizeof(vif->bssid)); 180f74bac54SVasanthakumar Thiagarajan vif->bss_ch = 0; 181bdcd8170SKalle Valo } 182bdcd8170SKalle Valo 183bdcd8170SKalle Valo static int ath6kl_set_host_app_area(struct ath6kl *ar) 184bdcd8170SKalle Valo { 185bdcd8170SKalle Valo u32 address, data; 186bdcd8170SKalle Valo struct host_app_area host_app_area; 187bdcd8170SKalle Valo 188bdcd8170SKalle Valo /* Fetch the address of the host_app_area_s 189bdcd8170SKalle Valo * instance in the host interest area */ 190bdcd8170SKalle Valo address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest)); 19131024d99SKevin Fang address = TARG_VTOP(ar->target_type, address); 192bdcd8170SKalle Valo 193addb44beSKalle Valo if (ath6kl_diag_read32(ar, address, &data)) 194bdcd8170SKalle Valo return -EIO; 195bdcd8170SKalle Valo 19631024d99SKevin Fang address = TARG_VTOP(ar->target_type, data); 197cbf49a6fSKalle Valo host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION); 198addb44beSKalle Valo if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area, 199addb44beSKalle Valo sizeof(struct host_app_area))) 200bdcd8170SKalle Valo return -EIO; 201bdcd8170SKalle Valo 202bdcd8170SKalle Valo return 0; 203bdcd8170SKalle Valo } 204bdcd8170SKalle Valo 205bdcd8170SKalle Valo static inline void set_ac2_ep_map(struct ath6kl *ar, 206bdcd8170SKalle Valo u8 ac, 207bdcd8170SKalle Valo enum htc_endpoint_id ep) 208bdcd8170SKalle Valo { 209bdcd8170SKalle Valo ar->ac2ep_map[ac] = ep; 210bdcd8170SKalle Valo ar->ep2ac_map[ep] = ac; 211bdcd8170SKalle Valo } 212bdcd8170SKalle Valo 213bdcd8170SKalle Valo /* connect to a service */ 214bdcd8170SKalle Valo static int ath6kl_connectservice(struct ath6kl *ar, 215bdcd8170SKalle Valo struct htc_service_connect_req *con_req, 216bdcd8170SKalle Valo char *desc) 217bdcd8170SKalle Valo { 218bdcd8170SKalle Valo int status; 219bdcd8170SKalle Valo struct htc_service_connect_resp response; 220bdcd8170SKalle Valo 221bdcd8170SKalle Valo memset(&response, 0, sizeof(response)); 222bdcd8170SKalle Valo 223ad226ec2SKalle Valo status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response); 224bdcd8170SKalle Valo if (status) { 225bdcd8170SKalle Valo ath6kl_err("failed to connect to %s service status:%d\n", 226bdcd8170SKalle Valo desc, status); 227bdcd8170SKalle Valo return status; 228bdcd8170SKalle Valo } 229bdcd8170SKalle Valo 230bdcd8170SKalle Valo switch (con_req->svc_id) { 231bdcd8170SKalle Valo case WMI_CONTROL_SVC: 232bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) 233bdcd8170SKalle Valo ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint); 234bdcd8170SKalle Valo ar->ctrl_ep = response.endpoint; 235bdcd8170SKalle Valo break; 236bdcd8170SKalle Valo case WMI_DATA_BE_SVC: 237bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint); 238bdcd8170SKalle Valo break; 239bdcd8170SKalle Valo case WMI_DATA_BK_SVC: 240bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint); 241bdcd8170SKalle Valo break; 242bdcd8170SKalle Valo case WMI_DATA_VI_SVC: 243bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint); 244bdcd8170SKalle Valo break; 245bdcd8170SKalle Valo case WMI_DATA_VO_SVC: 246bdcd8170SKalle Valo set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint); 247bdcd8170SKalle Valo break; 248bdcd8170SKalle Valo default: 249bdcd8170SKalle Valo ath6kl_err("service id is not mapped %d\n", con_req->svc_id); 250bdcd8170SKalle Valo return -EINVAL; 251bdcd8170SKalle Valo } 252bdcd8170SKalle Valo 253bdcd8170SKalle Valo return 0; 254bdcd8170SKalle Valo } 255bdcd8170SKalle Valo 256bdcd8170SKalle Valo static int ath6kl_init_service_ep(struct ath6kl *ar) 257bdcd8170SKalle Valo { 258bdcd8170SKalle Valo struct htc_service_connect_req connect; 259bdcd8170SKalle Valo 260bdcd8170SKalle Valo memset(&connect, 0, sizeof(connect)); 261bdcd8170SKalle Valo 262bdcd8170SKalle Valo /* these fields are the same for all service endpoints */ 263bdcd8170SKalle Valo connect.ep_cb.rx = ath6kl_rx; 264bdcd8170SKalle Valo connect.ep_cb.rx_refill = ath6kl_rx_refill; 265bdcd8170SKalle Valo connect.ep_cb.tx_full = ath6kl_tx_queue_full; 266bdcd8170SKalle Valo 267bdcd8170SKalle Valo /* 268bdcd8170SKalle Valo * Set the max queue depth so that our ath6kl_tx_queue_full handler 269bdcd8170SKalle Valo * gets called. 270bdcd8170SKalle Valo */ 271bdcd8170SKalle Valo connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH; 272bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4; 273bdcd8170SKalle Valo if (!connect.ep_cb.rx_refill_thresh) 274bdcd8170SKalle Valo connect.ep_cb.rx_refill_thresh++; 275bdcd8170SKalle Valo 276bdcd8170SKalle Valo /* connect to control service */ 277bdcd8170SKalle Valo connect.svc_id = WMI_CONTROL_SVC; 278bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI CONTROL")) 279bdcd8170SKalle Valo return -EIO; 280bdcd8170SKalle Valo 281bdcd8170SKalle Valo connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN; 282bdcd8170SKalle Valo 283bdcd8170SKalle Valo /* 284bdcd8170SKalle Valo * Limit the HTC message size on the send path, although e can 285bdcd8170SKalle Valo * receive A-MSDU frames of 4K, we will only send ethernet-sized 286bdcd8170SKalle Valo * (802.3) frames on the send path. 287bdcd8170SKalle Valo */ 288bdcd8170SKalle Valo connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH; 289bdcd8170SKalle Valo 290bdcd8170SKalle Valo /* 291bdcd8170SKalle Valo * To reduce the amount of committed memory for larger A_MSDU 292bdcd8170SKalle Valo * frames, use the recv-alloc threshold mechanism for larger 293bdcd8170SKalle Valo * packets. 294bdcd8170SKalle Valo */ 295bdcd8170SKalle Valo connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE; 296bdcd8170SKalle Valo connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf; 297bdcd8170SKalle Valo 298bdcd8170SKalle Valo /* 299bdcd8170SKalle Valo * For the remaining data services set the connection flag to 300bdcd8170SKalle Valo * reduce dribbling, if configured to do so. 301bdcd8170SKalle Valo */ 302bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB; 303bdcd8170SKalle Valo connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK; 304bdcd8170SKalle Valo connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF; 305bdcd8170SKalle Valo 306bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BE_SVC; 307bdcd8170SKalle Valo 308bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BE")) 309bdcd8170SKalle Valo return -EIO; 310bdcd8170SKalle Valo 311bdcd8170SKalle Valo /* connect to back-ground map this to WMI LOW_PRI */ 312bdcd8170SKalle Valo connect.svc_id = WMI_DATA_BK_SVC; 313bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA BK")) 314bdcd8170SKalle Valo return -EIO; 315bdcd8170SKalle Valo 316bdcd8170SKalle Valo /* connect to Video service, map this to to HI PRI */ 317bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VI_SVC; 318bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VI")) 319bdcd8170SKalle Valo return -EIO; 320bdcd8170SKalle Valo 321bdcd8170SKalle Valo /* 322bdcd8170SKalle Valo * Connect to VO service, this is currently not mapped to a WMI 323bdcd8170SKalle Valo * priority stream due to historical reasons. WMI originally 324bdcd8170SKalle Valo * defined 3 priorities over 3 mailboxes We can change this when 325bdcd8170SKalle Valo * WMI is reworked so that priorities are not dependent on 326bdcd8170SKalle Valo * mailboxes. 327bdcd8170SKalle Valo */ 328bdcd8170SKalle Valo connect.svc_id = WMI_DATA_VO_SVC; 329bdcd8170SKalle Valo if (ath6kl_connectservice(ar, &connect, "WMI DATA VO")) 330bdcd8170SKalle Valo return -EIO; 331bdcd8170SKalle Valo 332bdcd8170SKalle Valo return 0; 333bdcd8170SKalle Valo } 334bdcd8170SKalle Valo 335e29f25f5SVasanthakumar Thiagarajan void ath6kl_init_control_info(struct ath6kl_vif *vif) 336bdcd8170SKalle Valo { 337e29f25f5SVasanthakumar Thiagarajan ath6kl_init_profile_info(vif); 3383450334fSVasanthakumar Thiagarajan vif->def_txkey_index = 0; 3396f2a73f9SVasanthakumar Thiagarajan memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list)); 340f74bac54SVasanthakumar Thiagarajan vif->ch_hint = 0; 341bdcd8170SKalle Valo } 342bdcd8170SKalle Valo 343bdcd8170SKalle Valo /* 344bdcd8170SKalle Valo * Set HTC/Mbox operational parameters, this can only be called when the 345bdcd8170SKalle Valo * target is in the BMI phase. 346bdcd8170SKalle Valo */ 347bdcd8170SKalle Valo static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val, 348bdcd8170SKalle Valo u8 htc_ctrl_buf) 349bdcd8170SKalle Valo { 350bdcd8170SKalle Valo int status; 351bdcd8170SKalle Valo u32 blk_size; 352bdcd8170SKalle Valo 353bdcd8170SKalle Valo blk_size = ar->mbox_info.block_size; 354bdcd8170SKalle Valo 355bdcd8170SKalle Valo if (htc_ctrl_buf) 356bdcd8170SKalle Valo blk_size |= ((u32)htc_ctrl_buf) << 16; 357bdcd8170SKalle Valo 358bdcd8170SKalle Valo /* set the host interest area for the block size */ 359bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 360bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 361bdcd8170SKalle Valo HI_ITEM(hi_mbox_io_block_sz)), 362bdcd8170SKalle Valo (u8 *)&blk_size, 363bdcd8170SKalle Valo 4); 364bdcd8170SKalle Valo if (status) { 365bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for IO block size failed\n"); 366bdcd8170SKalle Valo goto out; 367bdcd8170SKalle Valo } 368bdcd8170SKalle Valo 369bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n", 370bdcd8170SKalle Valo blk_size, 371bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz))); 372bdcd8170SKalle Valo 373bdcd8170SKalle Valo if (mbox_isr_yield_val) { 374bdcd8170SKalle Valo /* set the host interest area for the mbox ISR yield limit */ 375bdcd8170SKalle Valo status = ath6kl_bmi_write(ar, 376bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 377bdcd8170SKalle Valo HI_ITEM(hi_mbox_isr_yield_limit)), 378bdcd8170SKalle Valo (u8 *)&mbox_isr_yield_val, 379bdcd8170SKalle Valo 4); 380bdcd8170SKalle Valo if (status) { 381bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for yield limit failed\n"); 382bdcd8170SKalle Valo goto out; 383bdcd8170SKalle Valo } 384bdcd8170SKalle Valo } 385bdcd8170SKalle Valo 386bdcd8170SKalle Valo out: 387bdcd8170SKalle Valo return status; 388bdcd8170SKalle Valo } 389bdcd8170SKalle Valo 3900ce59445SVasanthakumar Thiagarajan static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx) 391bdcd8170SKalle Valo { 392bdcd8170SKalle Valo int status = 0; 3934dea08e0SJouni Malinen int ret; 394bdcd8170SKalle Valo 395bdcd8170SKalle Valo /* 396bdcd8170SKalle Valo * Configure the device for rx dot11 header rules. "0,0" are the 397bdcd8170SKalle Valo * default values. Required if checksum offload is needed. Set 398bdcd8170SKalle Valo * RxMetaVersion to 2. 399bdcd8170SKalle Valo */ 4000ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx, 401bdcd8170SKalle Valo ar->rx_meta_ver, 0, 0)) { 402bdcd8170SKalle Valo ath6kl_err("unable to set the rx frame format\n"); 403bdcd8170SKalle Valo status = -EIO; 404bdcd8170SKalle Valo } 405bdcd8170SKalle Valo 406bdcd8170SKalle Valo if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) 4070ce59445SVasanthakumar Thiagarajan if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1, 408bdcd8170SKalle Valo IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) { 409bdcd8170SKalle Valo ath6kl_err("unable to set power save fail event policy\n"); 410bdcd8170SKalle Valo status = -EIO; 411bdcd8170SKalle Valo } 412bdcd8170SKalle Valo 413bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) 4140ce59445SVasanthakumar Thiagarajan if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0, 415bdcd8170SKalle Valo WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) { 416bdcd8170SKalle Valo ath6kl_err("unable to set barker preamble policy\n"); 417bdcd8170SKalle Valo status = -EIO; 418bdcd8170SKalle Valo } 419bdcd8170SKalle Valo 4200ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx, 421bdcd8170SKalle Valo WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) { 422bdcd8170SKalle Valo ath6kl_err("unable to set keep alive interval\n"); 423bdcd8170SKalle Valo status = -EIO; 424bdcd8170SKalle Valo } 425bdcd8170SKalle Valo 4260ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx, 427bdcd8170SKalle Valo WLAN_CONFIG_DISCONNECT_TIMEOUT)) { 428bdcd8170SKalle Valo ath6kl_err("unable to set disconnect timeout\n"); 429bdcd8170SKalle Valo status = -EIO; 430bdcd8170SKalle Valo } 431bdcd8170SKalle Valo 432bdcd8170SKalle Valo if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) 4330ce59445SVasanthakumar Thiagarajan if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) { 434bdcd8170SKalle Valo ath6kl_err("unable to set txop bursting\n"); 435bdcd8170SKalle Valo status = -EIO; 436bdcd8170SKalle Valo } 437bdcd8170SKalle Valo 438b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4390ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx, 4406bbc7c35SJouni Malinen P2P_FLAG_CAPABILITIES_REQ | 4414dea08e0SJouni Malinen P2P_FLAG_MACADDR_REQ | 4424dea08e0SJouni Malinen P2P_FLAG_HMODEL_REQ); 4434dea08e0SJouni Malinen if (ret) { 4444dea08e0SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P " 4456bbc7c35SJouni Malinen "capabilities (%d) - assuming P2P not " 4466bbc7c35SJouni Malinen "supported\n", ret); 4476bbc7c35SJouni Malinen ar->p2p = 0; 4486bbc7c35SJouni Malinen } 4496bbc7c35SJouni Malinen } 4506bbc7c35SJouni Malinen 451b64de356SVasanthakumar Thiagarajan if (ar->p2p && (ar->vif_max == 1 || idx)) { 4526bbc7c35SJouni Malinen /* Enable Probe Request reporting for P2P */ 4530ce59445SVasanthakumar Thiagarajan ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true); 4546bbc7c35SJouni Malinen if (ret) { 4556bbc7c35SJouni Malinen ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe " 4566bbc7c35SJouni Malinen "Request reporting (%d)\n", ret); 4576bbc7c35SJouni Malinen } 4584dea08e0SJouni Malinen } 4594dea08e0SJouni Malinen 460bdcd8170SKalle Valo return status; 461bdcd8170SKalle Valo } 462bdcd8170SKalle Valo 463bdcd8170SKalle Valo int ath6kl_configure_target(struct ath6kl *ar) 464bdcd8170SKalle Valo { 465bdcd8170SKalle Valo u32 param, ram_reserved_size; 4663226f68aSVasanthakumar Thiagarajan u8 fw_iftype, fw_mode = 0, fw_submode = 0; 46739586bf2SRyan Hsu int i, status; 468bdcd8170SKalle Valo 469*a10e2f2fSVasanthakumar Thiagarajan param = uart_debug; 470*a10e2f2fSVasanthakumar Thiagarajan if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 471*a10e2f2fSVasanthakumar Thiagarajan HI_ITEM(hi_serial_enable)), (u8 *)¶m, 4)) { 472*a10e2f2fSVasanthakumar Thiagarajan ath6kl_err("bmi_write_memory for uart debug failed\n"); 473*a10e2f2fSVasanthakumar Thiagarajan return -EIO; 474*a10e2f2fSVasanthakumar Thiagarajan } 475*a10e2f2fSVasanthakumar Thiagarajan 4767b85832dSVasanthakumar Thiagarajan /* 4777b85832dSVasanthakumar Thiagarajan * Note: Even though the firmware interface type is 4787b85832dSVasanthakumar Thiagarajan * chosen as BSS_STA for all three interfaces, can 4797b85832dSVasanthakumar Thiagarajan * be configured to IBSS/AP as long as the fw submode 4807b85832dSVasanthakumar Thiagarajan * remains normal mode (0 - AP, STA and IBSS). But 4817b85832dSVasanthakumar Thiagarajan * due to an target assert in firmware only one interface is 4827b85832dSVasanthakumar Thiagarajan * configured for now. 4837b85832dSVasanthakumar Thiagarajan */ 484dd3751f7SVasanthakumar Thiagarajan fw_iftype = HI_OPTION_FW_MODE_BSS_STA; 485bdcd8170SKalle Valo 48671f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 4877b85832dSVasanthakumar Thiagarajan fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS); 4887b85832dSVasanthakumar Thiagarajan 4897b85832dSVasanthakumar Thiagarajan /* 4903226f68aSVasanthakumar Thiagarajan * By default, submodes : 4913226f68aSVasanthakumar Thiagarajan * vif[0] - AP/STA/IBSS 4927b85832dSVasanthakumar Thiagarajan * vif[1] - "P2P dev"/"P2P GO"/"P2P Client" 4937b85832dSVasanthakumar Thiagarajan * vif[2] - "P2P dev"/"P2P GO"/"P2P Client" 4947b85832dSVasanthakumar Thiagarajan */ 4953226f68aSVasanthakumar Thiagarajan 4963226f68aSVasanthakumar Thiagarajan for (i = 0; i < ar->max_norm_iface; i++) 4973226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_NONE << 4983226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 4993226f68aSVasanthakumar Thiagarajan 50071f96ee6SKalle Valo for (i = ar->max_norm_iface; i < ar->vif_max; i++) 5013226f68aSVasanthakumar Thiagarajan fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV << 5023226f68aSVasanthakumar Thiagarajan (i * HI_OPTION_FW_SUBMODE_BITS); 5037b85832dSVasanthakumar Thiagarajan 504b64de356SVasanthakumar Thiagarajan if (ar->p2p && ar->vif_max == 1) 5057b85832dSVasanthakumar Thiagarajan fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV; 5067b85832dSVasanthakumar Thiagarajan 507bdcd8170SKalle Valo param = HTC_PROTOCOL_VERSION; 508bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 509bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 510bdcd8170SKalle Valo HI_ITEM(hi_app_host_interest)), 511bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 512bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for htc version failed\n"); 513bdcd8170SKalle Valo return -EIO; 514bdcd8170SKalle Valo } 515bdcd8170SKalle Valo 516bdcd8170SKalle Valo /* set the firmware mode to STA/IBSS/AP */ 517bdcd8170SKalle Valo param = 0; 518bdcd8170SKalle Valo 519bdcd8170SKalle Valo if (ath6kl_bmi_read(ar, 520bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 521bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 522bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 523bdcd8170SKalle Valo ath6kl_err("bmi_read_memory for setting fwmode failed\n"); 524bdcd8170SKalle Valo return -EIO; 525bdcd8170SKalle Valo } 526bdcd8170SKalle Valo 52771f96ee6SKalle Valo param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT); 5287b85832dSVasanthakumar Thiagarajan param |= fw_mode << HI_OPTION_FW_MODE_SHIFT; 5297b85832dSVasanthakumar Thiagarajan param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT; 5307b85832dSVasanthakumar Thiagarajan 531bdcd8170SKalle Valo param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); 532bdcd8170SKalle Valo param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); 533bdcd8170SKalle Valo 534bdcd8170SKalle Valo if (ath6kl_bmi_write(ar, 535bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 536bdcd8170SKalle Valo HI_ITEM(hi_option_flag)), 537bdcd8170SKalle Valo (u8 *)¶m, 538bdcd8170SKalle Valo 4) != 0) { 539bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for setting fwmode failed\n"); 540bdcd8170SKalle Valo return -EIO; 541bdcd8170SKalle Valo } 542bdcd8170SKalle Valo 543bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n"); 544bdcd8170SKalle Valo 545bdcd8170SKalle Valo /* 546bdcd8170SKalle Valo * Hardcode the address use for the extended board data 547bdcd8170SKalle Valo * Ideally this should be pre-allocate by the OS at boot time 548bdcd8170SKalle Valo * But since it is a new feature and board data is loaded 549bdcd8170SKalle Valo * at init time, we have to workaround this from host. 550bdcd8170SKalle Valo * It is difficult to patch the firmware boot code, 551bdcd8170SKalle Valo * but possible in theory. 552bdcd8170SKalle Valo */ 553bdcd8170SKalle Valo 554991b27eaSKalle Valo param = ar->hw.board_ext_data_addr; 555991b27eaSKalle Valo ram_reserved_size = ar->hw.reserved_ram_size; 556bdcd8170SKalle Valo 557991b27eaSKalle Valo if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 558bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 559bdcd8170SKalle Valo (u8 *)¶m, 4) != 0) { 560bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n"); 561bdcd8170SKalle Valo return -EIO; 562bdcd8170SKalle Valo } 563991b27eaSKalle Valo 564991b27eaSKalle Valo if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar, 565bdcd8170SKalle Valo HI_ITEM(hi_end_ram_reserve_sz)), 566bdcd8170SKalle Valo (u8 *)&ram_reserved_size, 4) != 0) { 567bdcd8170SKalle Valo ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n"); 568bdcd8170SKalle Valo return -EIO; 569bdcd8170SKalle Valo } 570bdcd8170SKalle Valo 571bdcd8170SKalle Valo /* set the block size for the target */ 572bdcd8170SKalle Valo if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0)) 573bdcd8170SKalle Valo /* use default number of control buffers */ 574bdcd8170SKalle Valo return -EIO; 575bdcd8170SKalle Valo 57639586bf2SRyan Hsu /* Configure GPIO AR600x UART */ 57739586bf2SRyan Hsu param = ar->hw.uarttx_pin; 57839586bf2SRyan Hsu status = ath6kl_bmi_write(ar, 57939586bf2SRyan Hsu ath6kl_get_hi_item_addr(ar, 58039586bf2SRyan Hsu HI_ITEM(hi_dbg_uart_txpin)), 58139586bf2SRyan Hsu (u8 *)¶m, 4); 58239586bf2SRyan Hsu if (status) 58339586bf2SRyan Hsu return status; 58439586bf2SRyan Hsu 58539586bf2SRyan Hsu /* Configure target refclk_hz */ 58639586bf2SRyan Hsu param = ar->hw.refclk_hz; 58739586bf2SRyan Hsu status = ath6kl_bmi_write(ar, 58839586bf2SRyan Hsu ath6kl_get_hi_item_addr(ar, 58939586bf2SRyan Hsu HI_ITEM(hi_refclk_hz)), 59039586bf2SRyan Hsu (u8 *)¶m, 4); 59139586bf2SRyan Hsu if (status) 59239586bf2SRyan Hsu return status; 59339586bf2SRyan Hsu 594bdcd8170SKalle Valo return 0; 595bdcd8170SKalle Valo } 596bdcd8170SKalle Valo 5978dafb70eSVasanthakumar Thiagarajan void ath6kl_core_free(struct ath6kl *ar) 598bdcd8170SKalle Valo { 5998dafb70eSVasanthakumar Thiagarajan wiphy_free(ar->wiphy); 600bdcd8170SKalle Valo } 601bdcd8170SKalle Valo 6026db8fa53SVasanthakumar Thiagarajan void ath6kl_core_cleanup(struct ath6kl *ar) 603bdcd8170SKalle Valo { 604b2e75698SKalle Valo ath6kl_hif_power_off(ar); 605b2e75698SKalle Valo 6066db8fa53SVasanthakumar Thiagarajan destroy_workqueue(ar->ath6kl_wq); 607bdcd8170SKalle Valo 6086db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) 6096db8fa53SVasanthakumar Thiagarajan ath6kl_htc_cleanup(ar->htc_target); 6106db8fa53SVasanthakumar Thiagarajan 6116db8fa53SVasanthakumar Thiagarajan ath6kl_cookie_cleanup(ar); 6126db8fa53SVasanthakumar Thiagarajan 6136db8fa53SVasanthakumar Thiagarajan ath6kl_cleanup_amsdu_rxbufs(ar); 6146db8fa53SVasanthakumar Thiagarajan 6156db8fa53SVasanthakumar Thiagarajan ath6kl_bmi_cleanup(ar); 6166db8fa53SVasanthakumar Thiagarajan 6176db8fa53SVasanthakumar Thiagarajan ath6kl_debug_cleanup(ar); 6186db8fa53SVasanthakumar Thiagarajan 6196db8fa53SVasanthakumar Thiagarajan kfree(ar->fw_board); 6206db8fa53SVasanthakumar Thiagarajan kfree(ar->fw_otp); 6216db8fa53SVasanthakumar Thiagarajan kfree(ar->fw); 6226db8fa53SVasanthakumar Thiagarajan kfree(ar->fw_patch); 6236db8fa53SVasanthakumar Thiagarajan 6246db8fa53SVasanthakumar Thiagarajan ath6kl_deinit_ieee80211_hw(ar); 625bdcd8170SKalle Valo } 626bdcd8170SKalle Valo 627bdcd8170SKalle Valo /* firmware upload */ 628bdcd8170SKalle Valo static int ath6kl_get_fw(struct ath6kl *ar, const char *filename, 629bdcd8170SKalle Valo u8 **fw, size_t *fw_len) 630bdcd8170SKalle Valo { 631bdcd8170SKalle Valo const struct firmware *fw_entry; 632bdcd8170SKalle Valo int ret; 633bdcd8170SKalle Valo 634bdcd8170SKalle Valo ret = request_firmware(&fw_entry, filename, ar->dev); 635bdcd8170SKalle Valo if (ret) 636bdcd8170SKalle Valo return ret; 637bdcd8170SKalle Valo 638bdcd8170SKalle Valo *fw_len = fw_entry->size; 639bdcd8170SKalle Valo *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL); 640bdcd8170SKalle Valo 641bdcd8170SKalle Valo if (*fw == NULL) 642bdcd8170SKalle Valo ret = -ENOMEM; 643bdcd8170SKalle Valo 644bdcd8170SKalle Valo release_firmware(fw_entry); 645bdcd8170SKalle Valo 646bdcd8170SKalle Valo return ret; 647bdcd8170SKalle Valo } 648bdcd8170SKalle Valo 64992ecbff4SSam Leffler #ifdef CONFIG_OF 65092ecbff4SSam Leffler /* 65192ecbff4SSam Leffler * Check the device tree for a board-id and use it to construct 65292ecbff4SSam Leffler * the pathname to the firmware file. Used (for now) to find a 65392ecbff4SSam Leffler * fallback to the "bdata.bin" file--typically a symlink to the 65492ecbff4SSam Leffler * appropriate board-specific file. 65592ecbff4SSam Leffler */ 65692ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 65792ecbff4SSam Leffler { 65892ecbff4SSam Leffler static const char *board_id_prop = "atheros,board-id"; 65992ecbff4SSam Leffler struct device_node *node; 66092ecbff4SSam Leffler char board_filename[64]; 66192ecbff4SSam Leffler const char *board_id; 66292ecbff4SSam Leffler int ret; 66392ecbff4SSam Leffler 66492ecbff4SSam Leffler for_each_compatible_node(node, NULL, "atheros,ath6kl") { 66592ecbff4SSam Leffler board_id = of_get_property(node, board_id_prop, NULL); 66692ecbff4SSam Leffler if (board_id == NULL) { 66792ecbff4SSam Leffler ath6kl_warn("No \"%s\" property on %s node.\n", 66892ecbff4SSam Leffler board_id_prop, node->name); 66992ecbff4SSam Leffler continue; 67092ecbff4SSam Leffler } 67192ecbff4SSam Leffler snprintf(board_filename, sizeof(board_filename), 672c0038972SKalle Valo "%s/bdata.%s.bin", ar->hw.fw.dir, board_id); 67392ecbff4SSam Leffler 67492ecbff4SSam Leffler ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board, 67592ecbff4SSam Leffler &ar->fw_board_len); 67692ecbff4SSam Leffler if (ret) { 67792ecbff4SSam Leffler ath6kl_err("Failed to get DT board file %s: %d\n", 67892ecbff4SSam Leffler board_filename, ret); 67992ecbff4SSam Leffler continue; 68092ecbff4SSam Leffler } 68192ecbff4SSam Leffler return true; 68292ecbff4SSam Leffler } 68392ecbff4SSam Leffler return false; 68492ecbff4SSam Leffler } 68592ecbff4SSam Leffler #else 68692ecbff4SSam Leffler static bool check_device_tree(struct ath6kl *ar) 68792ecbff4SSam Leffler { 68892ecbff4SSam Leffler return false; 68992ecbff4SSam Leffler } 69092ecbff4SSam Leffler #endif /* CONFIG_OF */ 69192ecbff4SSam Leffler 692bdcd8170SKalle Valo static int ath6kl_fetch_board_file(struct ath6kl *ar) 693bdcd8170SKalle Valo { 694bdcd8170SKalle Valo const char *filename; 695bdcd8170SKalle Valo int ret; 696bdcd8170SKalle Valo 697772c31eeSKalle Valo if (ar->fw_board != NULL) 698772c31eeSKalle Valo return 0; 699772c31eeSKalle Valo 700d1a9421dSKalle Valo if (WARN_ON(ar->hw.fw_board == NULL)) 701d1a9421dSKalle Valo return -EINVAL; 702d1a9421dSKalle Valo 703d1a9421dSKalle Valo filename = ar->hw.fw_board; 704bdcd8170SKalle Valo 705bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 706bdcd8170SKalle Valo &ar->fw_board_len); 707bdcd8170SKalle Valo if (ret == 0) { 708bdcd8170SKalle Valo /* managed to get proper board file */ 709bdcd8170SKalle Valo return 0; 710bdcd8170SKalle Valo } 711bdcd8170SKalle Valo 71292ecbff4SSam Leffler if (check_device_tree(ar)) { 71392ecbff4SSam Leffler /* got board file from device tree */ 71492ecbff4SSam Leffler return 0; 71592ecbff4SSam Leffler } 71692ecbff4SSam Leffler 717bdcd8170SKalle Valo /* there was no proper board file, try to use default instead */ 718bdcd8170SKalle Valo ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n", 719bdcd8170SKalle Valo filename, ret); 720bdcd8170SKalle Valo 721d1a9421dSKalle Valo filename = ar->hw.fw_default_board; 722bdcd8170SKalle Valo 723bdcd8170SKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_board, 724bdcd8170SKalle Valo &ar->fw_board_len); 725bdcd8170SKalle Valo if (ret) { 726bdcd8170SKalle Valo ath6kl_err("Failed to get default board file %s: %d\n", 727bdcd8170SKalle Valo filename, ret); 728bdcd8170SKalle Valo return ret; 729bdcd8170SKalle Valo } 730bdcd8170SKalle Valo 731bdcd8170SKalle Valo ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n"); 732bdcd8170SKalle Valo ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n"); 733bdcd8170SKalle Valo 734bdcd8170SKalle Valo return 0; 735bdcd8170SKalle Valo } 736bdcd8170SKalle Valo 737772c31eeSKalle Valo static int ath6kl_fetch_otp_file(struct ath6kl *ar) 738772c31eeSKalle Valo { 739c0038972SKalle Valo char filename[100]; 740772c31eeSKalle Valo int ret; 741772c31eeSKalle Valo 742772c31eeSKalle Valo if (ar->fw_otp != NULL) 743772c31eeSKalle Valo return 0; 744772c31eeSKalle Valo 745c0038972SKalle Valo if (ar->hw.fw.otp == NULL) { 746d1a9421dSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 747d1a9421dSKalle Valo "no OTP file configured for this hw\n"); 748772c31eeSKalle Valo return 0; 749772c31eeSKalle Valo } 750772c31eeSKalle Valo 751c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 752c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.otp); 753d1a9421dSKalle Valo 754772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_otp, 755772c31eeSKalle Valo &ar->fw_otp_len); 756772c31eeSKalle Valo if (ret) { 757772c31eeSKalle Valo ath6kl_err("Failed to get OTP file %s: %d\n", 758772c31eeSKalle Valo filename, ret); 759772c31eeSKalle Valo return ret; 760772c31eeSKalle Valo } 761772c31eeSKalle Valo 762772c31eeSKalle Valo return 0; 763772c31eeSKalle Valo } 764772c31eeSKalle Valo 765772c31eeSKalle Valo static int ath6kl_fetch_fw_file(struct ath6kl *ar) 766772c31eeSKalle Valo { 767c0038972SKalle Valo char filename[100]; 768772c31eeSKalle Valo int ret; 769772c31eeSKalle Valo 770772c31eeSKalle Valo if (ar->fw != NULL) 771772c31eeSKalle Valo return 0; 772772c31eeSKalle Valo 773772c31eeSKalle Valo if (testmode) { 774c0038972SKalle Valo if (ar->hw.fw.tcmd == NULL) { 775d1a9421dSKalle Valo ath6kl_warn("testmode not supported\n"); 776772c31eeSKalle Valo return -EOPNOTSUPP; 777772c31eeSKalle Valo } 778772c31eeSKalle Valo 779c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 780c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.tcmd); 781d1a9421dSKalle Valo 782772c31eeSKalle Valo set_bit(TESTMODE, &ar->flag); 783772c31eeSKalle Valo 784772c31eeSKalle Valo goto get_fw; 785772c31eeSKalle Valo } 786772c31eeSKalle Valo 787c0038972SKalle Valo /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */ 788c0038972SKalle Valo if (WARN_ON(ar->hw.fw.fw == NULL)) 789d1a9421dSKalle Valo return -EINVAL; 790d1a9421dSKalle Valo 791c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 792c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.fw); 793772c31eeSKalle Valo 794772c31eeSKalle Valo get_fw: 795772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len); 796772c31eeSKalle Valo if (ret) { 797772c31eeSKalle Valo ath6kl_err("Failed to get firmware file %s: %d\n", 798772c31eeSKalle Valo filename, ret); 799772c31eeSKalle Valo return ret; 800772c31eeSKalle Valo } 801772c31eeSKalle Valo 802772c31eeSKalle Valo return 0; 803772c31eeSKalle Valo } 804772c31eeSKalle Valo 805772c31eeSKalle Valo static int ath6kl_fetch_patch_file(struct ath6kl *ar) 806772c31eeSKalle Valo { 807c0038972SKalle Valo char filename[100]; 808772c31eeSKalle Valo int ret; 809772c31eeSKalle Valo 810d1a9421dSKalle Valo if (ar->fw_patch != NULL) 811772c31eeSKalle Valo return 0; 812772c31eeSKalle Valo 813c0038972SKalle Valo if (ar->hw.fw.patch == NULL) 814d1a9421dSKalle Valo return 0; 815d1a9421dSKalle Valo 816c0038972SKalle Valo snprintf(filename, sizeof(filename), "%s/%s", 817c0038972SKalle Valo ar->hw.fw.dir, ar->hw.fw.patch); 818d1a9421dSKalle Valo 819772c31eeSKalle Valo ret = ath6kl_get_fw(ar, filename, &ar->fw_patch, 820772c31eeSKalle Valo &ar->fw_patch_len); 821772c31eeSKalle Valo if (ret) { 822772c31eeSKalle Valo ath6kl_err("Failed to get patch file %s: %d\n", 823772c31eeSKalle Valo filename, ret); 824772c31eeSKalle Valo return ret; 825772c31eeSKalle Valo } 826772c31eeSKalle Valo 827772c31eeSKalle Valo return 0; 828772c31eeSKalle Valo } 829772c31eeSKalle Valo 83050d41234SKalle Valo static int ath6kl_fetch_fw_api1(struct ath6kl *ar) 831772c31eeSKalle Valo { 832772c31eeSKalle Valo int ret; 833772c31eeSKalle Valo 834772c31eeSKalle Valo ret = ath6kl_fetch_otp_file(ar); 835772c31eeSKalle Valo if (ret) 836772c31eeSKalle Valo return ret; 837772c31eeSKalle Valo 838772c31eeSKalle Valo ret = ath6kl_fetch_fw_file(ar); 839772c31eeSKalle Valo if (ret) 840772c31eeSKalle Valo return ret; 841772c31eeSKalle Valo 842772c31eeSKalle Valo ret = ath6kl_fetch_patch_file(ar); 843772c31eeSKalle Valo if (ret) 844772c31eeSKalle Valo return ret; 845772c31eeSKalle Valo 846772c31eeSKalle Valo return 0; 847772c31eeSKalle Valo } 848bdcd8170SKalle Valo 84965a8b4ccSKalle Valo static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name) 85050d41234SKalle Valo { 85150d41234SKalle Valo size_t magic_len, len, ie_len; 85250d41234SKalle Valo const struct firmware *fw; 85350d41234SKalle Valo struct ath6kl_fw_ie *hdr; 854c0038972SKalle Valo char filename[100]; 85550d41234SKalle Valo const u8 *data; 85697e0496dSKalle Valo int ret, ie_id, i, index, bit; 8578a137480SKalle Valo __le32 *val; 85850d41234SKalle Valo 85965a8b4ccSKalle Valo snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name); 86050d41234SKalle Valo 86150d41234SKalle Valo ret = request_firmware(&fw, filename, ar->dev); 86250d41234SKalle Valo if (ret) 86350d41234SKalle Valo return ret; 86450d41234SKalle Valo 86550d41234SKalle Valo data = fw->data; 86650d41234SKalle Valo len = fw->size; 86750d41234SKalle Valo 86850d41234SKalle Valo /* magic also includes the null byte, check that as well */ 86950d41234SKalle Valo magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1; 87050d41234SKalle Valo 87150d41234SKalle Valo if (len < magic_len) { 87250d41234SKalle Valo ret = -EINVAL; 87350d41234SKalle Valo goto out; 87450d41234SKalle Valo } 87550d41234SKalle Valo 87650d41234SKalle Valo if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) { 87750d41234SKalle Valo ret = -EINVAL; 87850d41234SKalle Valo goto out; 87950d41234SKalle Valo } 88050d41234SKalle Valo 88150d41234SKalle Valo len -= magic_len; 88250d41234SKalle Valo data += magic_len; 88350d41234SKalle Valo 88450d41234SKalle Valo /* loop elements */ 88550d41234SKalle Valo while (len > sizeof(struct ath6kl_fw_ie)) { 88650d41234SKalle Valo /* hdr is unaligned! */ 88750d41234SKalle Valo hdr = (struct ath6kl_fw_ie *) data; 88850d41234SKalle Valo 88950d41234SKalle Valo ie_id = le32_to_cpup(&hdr->id); 89050d41234SKalle Valo ie_len = le32_to_cpup(&hdr->len); 89150d41234SKalle Valo 89250d41234SKalle Valo len -= sizeof(*hdr); 89350d41234SKalle Valo data += sizeof(*hdr); 89450d41234SKalle Valo 89550d41234SKalle Valo if (len < ie_len) { 89650d41234SKalle Valo ret = -EINVAL; 89750d41234SKalle Valo goto out; 89850d41234SKalle Valo } 89950d41234SKalle Valo 90050d41234SKalle Valo switch (ie_id) { 90150d41234SKalle Valo case ATH6KL_FW_IE_OTP_IMAGE: 902ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n", 9036bc36431SKalle Valo ie_len); 9046bc36431SKalle Valo 90550d41234SKalle Valo ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL); 90650d41234SKalle Valo 90750d41234SKalle Valo if (ar->fw_otp == NULL) { 90850d41234SKalle Valo ret = -ENOMEM; 90950d41234SKalle Valo goto out; 91050d41234SKalle Valo } 91150d41234SKalle Valo 91250d41234SKalle Valo ar->fw_otp_len = ie_len; 91350d41234SKalle Valo break; 91450d41234SKalle Valo case ATH6KL_FW_IE_FW_IMAGE: 915ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n", 9166bc36431SKalle Valo ie_len); 9176bc36431SKalle Valo 91850d41234SKalle Valo ar->fw = kmemdup(data, ie_len, GFP_KERNEL); 91950d41234SKalle Valo 92050d41234SKalle Valo if (ar->fw == NULL) { 92150d41234SKalle Valo ret = -ENOMEM; 92250d41234SKalle Valo goto out; 92350d41234SKalle Valo } 92450d41234SKalle Valo 92550d41234SKalle Valo ar->fw_len = ie_len; 92650d41234SKalle Valo break; 92750d41234SKalle Valo case ATH6KL_FW_IE_PATCH_IMAGE: 928ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n", 9296bc36431SKalle Valo ie_len); 9306bc36431SKalle Valo 93150d41234SKalle Valo ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL); 93250d41234SKalle Valo 93350d41234SKalle Valo if (ar->fw_patch == NULL) { 93450d41234SKalle Valo ret = -ENOMEM; 93550d41234SKalle Valo goto out; 93650d41234SKalle Valo } 93750d41234SKalle Valo 93850d41234SKalle Valo ar->fw_patch_len = ie_len; 93950d41234SKalle Valo break; 9408a137480SKalle Valo case ATH6KL_FW_IE_RESERVED_RAM_SIZE: 9418a137480SKalle Valo val = (__le32 *) data; 9428a137480SKalle Valo ar->hw.reserved_ram_size = le32_to_cpup(val); 9436bc36431SKalle Valo 9446bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 9456bc36431SKalle Valo "found reserved ram size ie 0x%d\n", 9466bc36431SKalle Valo ar->hw.reserved_ram_size); 9478a137480SKalle Valo break; 94897e0496dSKalle Valo case ATH6KL_FW_IE_CAPABILITIES: 949277d90f4SKalle Valo if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8)) 950277d90f4SKalle Valo break; 951277d90f4SKalle Valo 9526bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 953ef548626SKalle Valo "found firmware capabilities ie (%zd B)\n", 9546bc36431SKalle Valo ie_len); 9556bc36431SKalle Valo 95697e0496dSKalle Valo for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) { 957277d90f4SKalle Valo index = i / 8; 95897e0496dSKalle Valo bit = i % 8; 95997e0496dSKalle Valo 96097e0496dSKalle Valo if (data[index] & (1 << bit)) 96197e0496dSKalle Valo __set_bit(i, ar->fw_capabilities); 96297e0496dSKalle Valo } 9636bc36431SKalle Valo 9646bc36431SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "", 9656bc36431SKalle Valo ar->fw_capabilities, 9666bc36431SKalle Valo sizeof(ar->fw_capabilities)); 96797e0496dSKalle Valo break; 9681b4304daSKalle Valo case ATH6KL_FW_IE_PATCH_ADDR: 9691b4304daSKalle Valo if (ie_len != sizeof(*val)) 9701b4304daSKalle Valo break; 9711b4304daSKalle Valo 9721b4304daSKalle Valo val = (__le32 *) data; 9731b4304daSKalle Valo ar->hw.dataset_patch_addr = le32_to_cpup(val); 9746bc36431SKalle Valo 9756bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 97603ef0250SKalle Valo "found patch address ie 0x%x\n", 9776bc36431SKalle Valo ar->hw.dataset_patch_addr); 9781b4304daSKalle Valo break; 97903ef0250SKalle Valo case ATH6KL_FW_IE_BOARD_ADDR: 98003ef0250SKalle Valo if (ie_len != sizeof(*val)) 98103ef0250SKalle Valo break; 98203ef0250SKalle Valo 98303ef0250SKalle Valo val = (__le32 *) data; 98403ef0250SKalle Valo ar->hw.board_addr = le32_to_cpup(val); 98503ef0250SKalle Valo 98603ef0250SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 98703ef0250SKalle Valo "found board address ie 0x%x\n", 98803ef0250SKalle Valo ar->hw.board_addr); 98903ef0250SKalle Valo break; 990368b1b0fSKalle Valo case ATH6KL_FW_IE_VIF_MAX: 991368b1b0fSKalle Valo if (ie_len != sizeof(*val)) 992368b1b0fSKalle Valo break; 993368b1b0fSKalle Valo 994368b1b0fSKalle Valo val = (__le32 *) data; 995368b1b0fSKalle Valo ar->vif_max = min_t(unsigned int, le32_to_cpup(val), 996368b1b0fSKalle Valo ATH6KL_VIF_MAX); 997368b1b0fSKalle Valo 998f143379dSVasanthakumar Thiagarajan if (ar->vif_max > 1 && !ar->p2p) 999f143379dSVasanthakumar Thiagarajan ar->max_norm_iface = 2; 1000f143379dSVasanthakumar Thiagarajan 1001368b1b0fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 1002368b1b0fSKalle Valo "found vif max ie %d\n", ar->vif_max); 1003368b1b0fSKalle Valo break; 100450d41234SKalle Valo default: 10056bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n", 100650d41234SKalle Valo le32_to_cpup(&hdr->id)); 100750d41234SKalle Valo break; 100850d41234SKalle Valo } 100950d41234SKalle Valo 101050d41234SKalle Valo len -= ie_len; 101150d41234SKalle Valo data += ie_len; 101250d41234SKalle Valo }; 101350d41234SKalle Valo 101450d41234SKalle Valo ret = 0; 101550d41234SKalle Valo out: 101650d41234SKalle Valo release_firmware(fw); 101750d41234SKalle Valo 101850d41234SKalle Valo return ret; 101950d41234SKalle Valo } 102050d41234SKalle Valo 102150d41234SKalle Valo static int ath6kl_fetch_firmwares(struct ath6kl *ar) 102250d41234SKalle Valo { 102350d41234SKalle Valo int ret; 102450d41234SKalle Valo 102550d41234SKalle Valo ret = ath6kl_fetch_board_file(ar); 102650d41234SKalle Valo if (ret) 102750d41234SKalle Valo return ret; 102850d41234SKalle Valo 102965a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE); 10306bc36431SKalle Valo if (ret == 0) { 103165a8b4ccSKalle Valo ar->fw_api = 3; 103265a8b4ccSKalle Valo goto out; 103365a8b4ccSKalle Valo } 103465a8b4ccSKalle Valo 103565a8b4ccSKalle Valo ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE); 103665a8b4ccSKalle Valo if (ret == 0) { 103765a8b4ccSKalle Valo ar->fw_api = 2; 103865a8b4ccSKalle Valo goto out; 10396bc36431SKalle Valo } 104050d41234SKalle Valo 104150d41234SKalle Valo ret = ath6kl_fetch_fw_api1(ar); 104250d41234SKalle Valo if (ret) 104350d41234SKalle Valo return ret; 104450d41234SKalle Valo 104565a8b4ccSKalle Valo ar->fw_api = 1; 104665a8b4ccSKalle Valo 104765a8b4ccSKalle Valo out: 104865a8b4ccSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api); 10496bc36431SKalle Valo 105050d41234SKalle Valo return 0; 105150d41234SKalle Valo } 105250d41234SKalle Valo 1053bdcd8170SKalle Valo static int ath6kl_upload_board_file(struct ath6kl *ar) 1054bdcd8170SKalle Valo { 1055bdcd8170SKalle Valo u32 board_address, board_ext_address, param; 105631024d99SKevin Fang u32 board_data_size, board_ext_data_size; 1057bdcd8170SKalle Valo int ret; 1058bdcd8170SKalle Valo 1059772c31eeSKalle Valo if (WARN_ON(ar->fw_board == NULL)) 1060772c31eeSKalle Valo return -ENOENT; 1061bdcd8170SKalle Valo 106231024d99SKevin Fang /* 106331024d99SKevin Fang * Determine where in Target RAM to write Board Data. 106431024d99SKevin Fang * For AR6004, host determine Target RAM address for 106531024d99SKevin Fang * writing board data. 106631024d99SKevin Fang */ 10670d4d72bfSKalle Valo if (ar->hw.board_addr != 0) { 10680d4d72bfSKalle Valo board_address = ar->hw.board_addr; 106931024d99SKevin Fang ath6kl_bmi_write(ar, 107031024d99SKevin Fang ath6kl_get_hi_item_addr(ar, 107131024d99SKevin Fang HI_ITEM(hi_board_data)), 107231024d99SKevin Fang (u8 *) &board_address, 4); 107331024d99SKevin Fang } else { 1074bdcd8170SKalle Valo ath6kl_bmi_read(ar, 1075bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1076bdcd8170SKalle Valo HI_ITEM(hi_board_data)), 1077bdcd8170SKalle Valo (u8 *) &board_address, 4); 107831024d99SKevin Fang } 107931024d99SKevin Fang 1080bdcd8170SKalle Valo /* determine where in target ram to write extended board data */ 1081bdcd8170SKalle Valo ath6kl_bmi_read(ar, 1082bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1083bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data)), 1084bdcd8170SKalle Valo (u8 *) &board_ext_address, 4); 1085bdcd8170SKalle Valo 108650e2740bSKalle Valo if (ar->target_type == TARGET_TYPE_AR6003 && 108750e2740bSKalle Valo board_ext_address == 0) { 1088bdcd8170SKalle Valo ath6kl_err("Failed to get board file target address.\n"); 1089bdcd8170SKalle Valo return -EINVAL; 1090bdcd8170SKalle Valo } 1091bdcd8170SKalle Valo 109231024d99SKevin Fang switch (ar->target_type) { 109331024d99SKevin Fang case TARGET_TYPE_AR6003: 109431024d99SKevin Fang board_data_size = AR6003_BOARD_DATA_SZ; 109531024d99SKevin Fang board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ; 109631024d99SKevin Fang break; 109731024d99SKevin Fang case TARGET_TYPE_AR6004: 109831024d99SKevin Fang board_data_size = AR6004_BOARD_DATA_SZ; 109931024d99SKevin Fang board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ; 110031024d99SKevin Fang break; 110131024d99SKevin Fang default: 110231024d99SKevin Fang WARN_ON(1); 110331024d99SKevin Fang return -EINVAL; 110431024d99SKevin Fang break; 110531024d99SKevin Fang } 110631024d99SKevin Fang 110750e2740bSKalle Valo if (board_ext_address && 110850e2740bSKalle Valo ar->fw_board_len == (board_data_size + board_ext_data_size)) { 110931024d99SKevin Fang 1110bdcd8170SKalle Valo /* write extended board data */ 11116bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 11126bc36431SKalle Valo "writing extended board data to 0x%x (%d B)\n", 11136bc36431SKalle Valo board_ext_address, board_ext_data_size); 11146bc36431SKalle Valo 1115bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_ext_address, 111631024d99SKevin Fang ar->fw_board + board_data_size, 111731024d99SKevin Fang board_ext_data_size); 1118bdcd8170SKalle Valo if (ret) { 1119bdcd8170SKalle Valo ath6kl_err("Failed to write extended board data: %d\n", 1120bdcd8170SKalle Valo ret); 1121bdcd8170SKalle Valo return ret; 1122bdcd8170SKalle Valo } 1123bdcd8170SKalle Valo 1124bdcd8170SKalle Valo /* record that extended board data is initialized */ 112531024d99SKevin Fang param = (board_ext_data_size << 16) | 1; 112631024d99SKevin Fang 1127bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1128bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1129bdcd8170SKalle Valo HI_ITEM(hi_board_ext_data_config)), 1130bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 1131bdcd8170SKalle Valo } 1132bdcd8170SKalle Valo 113331024d99SKevin Fang if (ar->fw_board_len < board_data_size) { 1134bdcd8170SKalle Valo ath6kl_err("Too small board file: %zu\n", ar->fw_board_len); 1135bdcd8170SKalle Valo ret = -EINVAL; 1136bdcd8170SKalle Valo return ret; 1137bdcd8170SKalle Valo } 1138bdcd8170SKalle Valo 11396bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n", 11406bc36431SKalle Valo board_address, board_data_size); 11416bc36431SKalle Valo 1142bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, board_address, ar->fw_board, 114331024d99SKevin Fang board_data_size); 1144bdcd8170SKalle Valo 1145bdcd8170SKalle Valo if (ret) { 1146bdcd8170SKalle Valo ath6kl_err("Board file bmi write failed: %d\n", ret); 1147bdcd8170SKalle Valo return ret; 1148bdcd8170SKalle Valo } 1149bdcd8170SKalle Valo 1150bdcd8170SKalle Valo /* record the fact that Board Data IS initialized */ 1151bdcd8170SKalle Valo param = 1; 1152bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1153bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1154bdcd8170SKalle Valo HI_ITEM(hi_board_data_initialized)), 1155bdcd8170SKalle Valo (u8 *)¶m, 4); 1156bdcd8170SKalle Valo 1157bdcd8170SKalle Valo return ret; 1158bdcd8170SKalle Valo } 1159bdcd8170SKalle Valo 1160bdcd8170SKalle Valo static int ath6kl_upload_otp(struct ath6kl *ar) 1161bdcd8170SKalle Valo { 1162bdcd8170SKalle Valo u32 address, param; 1163bef26a7fSKalle Valo bool from_hw = false; 1164bdcd8170SKalle Valo int ret; 1165bdcd8170SKalle Valo 116650e2740bSKalle Valo if (ar->fw_otp == NULL) 116750e2740bSKalle Valo return 0; 1168bdcd8170SKalle Valo 1169a01ac414SKalle Valo address = ar->hw.app_load_addr; 1170bdcd8170SKalle Valo 1171ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address, 11726bc36431SKalle Valo ar->fw_otp_len); 11736bc36431SKalle Valo 1174bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp, 1175bdcd8170SKalle Valo ar->fw_otp_len); 1176bdcd8170SKalle Valo if (ret) { 1177bdcd8170SKalle Valo ath6kl_err("Failed to upload OTP file: %d\n", ret); 1178bdcd8170SKalle Valo return ret; 1179bdcd8170SKalle Valo } 1180bdcd8170SKalle Valo 1181639d0b89SKalle Valo /* read firmware start address */ 1182639d0b89SKalle Valo ret = ath6kl_bmi_read(ar, 1183639d0b89SKalle Valo ath6kl_get_hi_item_addr(ar, 1184639d0b89SKalle Valo HI_ITEM(hi_app_start)), 1185639d0b89SKalle Valo (u8 *) &address, sizeof(address)); 1186639d0b89SKalle Valo 1187639d0b89SKalle Valo if (ret) { 1188639d0b89SKalle Valo ath6kl_err("Failed to read hi_app_start: %d\n", ret); 1189639d0b89SKalle Valo return ret; 1190639d0b89SKalle Valo } 1191639d0b89SKalle Valo 1192bef26a7fSKalle Valo if (ar->hw.app_start_override_addr == 0) { 1193639d0b89SKalle Valo ar->hw.app_start_override_addr = address; 1194bef26a7fSKalle Valo from_hw = true; 1195bef26a7fSKalle Valo } 1196639d0b89SKalle Valo 1197bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n", 1198bef26a7fSKalle Valo from_hw ? " (from hw)" : "", 11996bc36431SKalle Valo ar->hw.app_start_override_addr); 12006bc36431SKalle Valo 1201bdcd8170SKalle Valo /* execute the OTP code */ 1202bef26a7fSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n", 1203bef26a7fSKalle Valo ar->hw.app_start_override_addr); 1204bdcd8170SKalle Valo param = 0; 1205bef26a7fSKalle Valo ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, ¶m); 1206bdcd8170SKalle Valo 1207bdcd8170SKalle Valo return ret; 1208bdcd8170SKalle Valo } 1209bdcd8170SKalle Valo 1210bdcd8170SKalle Valo static int ath6kl_upload_firmware(struct ath6kl *ar) 1211bdcd8170SKalle Valo { 1212bdcd8170SKalle Valo u32 address; 1213bdcd8170SKalle Valo int ret; 1214bdcd8170SKalle Valo 1215772c31eeSKalle Valo if (WARN_ON(ar->fw == NULL)) 121650e2740bSKalle Valo return 0; 1217bdcd8170SKalle Valo 1218a01ac414SKalle Valo address = ar->hw.app_load_addr; 1219bdcd8170SKalle Valo 1220ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n", 12216bc36431SKalle Valo address, ar->fw_len); 12226bc36431SKalle Valo 1223bdcd8170SKalle Valo ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len); 1224bdcd8170SKalle Valo 1225bdcd8170SKalle Valo if (ret) { 1226bdcd8170SKalle Valo ath6kl_err("Failed to write firmware: %d\n", ret); 1227bdcd8170SKalle Valo return ret; 1228bdcd8170SKalle Valo } 1229bdcd8170SKalle Valo 123031024d99SKevin Fang /* 123131024d99SKevin Fang * Set starting address for firmware 123231024d99SKevin Fang * Don't need to setup app_start override addr on AR6004 123331024d99SKevin Fang */ 123431024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1235a01ac414SKalle Valo address = ar->hw.app_start_override_addr; 1236bdcd8170SKalle Valo ath6kl_bmi_set_app_start(ar, address); 123731024d99SKevin Fang } 1238bdcd8170SKalle Valo return ret; 1239bdcd8170SKalle Valo } 1240bdcd8170SKalle Valo 1241bdcd8170SKalle Valo static int ath6kl_upload_patch(struct ath6kl *ar) 1242bdcd8170SKalle Valo { 1243bdcd8170SKalle Valo u32 address, param; 1244bdcd8170SKalle Valo int ret; 1245bdcd8170SKalle Valo 124650e2740bSKalle Valo if (ar->fw_patch == NULL) 124750e2740bSKalle Valo return 0; 1248bdcd8170SKalle Valo 1249a01ac414SKalle Valo address = ar->hw.dataset_patch_addr; 1250bdcd8170SKalle Valo 1251ef548626SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n", 12526bc36431SKalle Valo address, ar->fw_patch_len); 12536bc36431SKalle Valo 1254bdcd8170SKalle Valo ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len); 1255bdcd8170SKalle Valo if (ret) { 1256bdcd8170SKalle Valo ath6kl_err("Failed to write patch file: %d\n", ret); 1257bdcd8170SKalle Valo return ret; 1258bdcd8170SKalle Valo } 1259bdcd8170SKalle Valo 1260bdcd8170SKalle Valo param = address; 1261bdcd8170SKalle Valo ath6kl_bmi_write(ar, 1262bdcd8170SKalle Valo ath6kl_get_hi_item_addr(ar, 1263bdcd8170SKalle Valo HI_ITEM(hi_dset_list_head)), 1264bdcd8170SKalle Valo (unsigned char *) ¶m, 4); 1265bdcd8170SKalle Valo 1266bdcd8170SKalle Valo return 0; 1267bdcd8170SKalle Valo } 1268bdcd8170SKalle Valo 1269bdcd8170SKalle Valo static int ath6kl_init_upload(struct ath6kl *ar) 1270bdcd8170SKalle Valo { 1271bdcd8170SKalle Valo u32 param, options, sleep, address; 1272bdcd8170SKalle Valo int status = 0; 1273bdcd8170SKalle Valo 127431024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6003 && 127531024d99SKevin Fang ar->target_type != TARGET_TYPE_AR6004) 1276bdcd8170SKalle Valo return -EINVAL; 1277bdcd8170SKalle Valo 1278bdcd8170SKalle Valo /* temporarily disable system sleep */ 1279bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1280bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1281bdcd8170SKalle Valo if (status) 1282bdcd8170SKalle Valo return status; 1283bdcd8170SKalle Valo 1284bdcd8170SKalle Valo options = param; 1285bdcd8170SKalle Valo 1286bdcd8170SKalle Valo param |= ATH6KL_OPTION_SLEEP_DISABLE; 1287bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1288bdcd8170SKalle Valo if (status) 1289bdcd8170SKalle Valo return status; 1290bdcd8170SKalle Valo 1291bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1292bdcd8170SKalle Valo status = ath6kl_bmi_reg_read(ar, address, ¶m); 1293bdcd8170SKalle Valo if (status) 1294bdcd8170SKalle Valo return status; 1295bdcd8170SKalle Valo 1296bdcd8170SKalle Valo sleep = param; 1297bdcd8170SKalle Valo 1298bdcd8170SKalle Valo param |= SM(SYSTEM_SLEEP_DISABLE, 1); 1299bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1300bdcd8170SKalle Valo if (status) 1301bdcd8170SKalle Valo return status; 1302bdcd8170SKalle Valo 1303bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n", 1304bdcd8170SKalle Valo options, sleep); 1305bdcd8170SKalle Valo 1306bdcd8170SKalle Valo /* program analog PLL register */ 130731024d99SKevin Fang /* no need to control 40/44MHz clock on AR6004 */ 130831024d99SKevin Fang if (ar->target_type != TARGET_TYPE_AR6004) { 1309bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER, 1310bdcd8170SKalle Valo 0xF9104001); 131131024d99SKevin Fang 1312bdcd8170SKalle Valo if (status) 1313bdcd8170SKalle Valo return status; 1314bdcd8170SKalle Valo 1315bdcd8170SKalle Valo /* Run at 80/88MHz by default */ 1316bdcd8170SKalle Valo param = SM(CPU_CLOCK_STANDARD, 1); 1317bdcd8170SKalle Valo 1318bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS; 1319bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1320bdcd8170SKalle Valo if (status) 1321bdcd8170SKalle Valo return status; 132231024d99SKevin Fang } 1323bdcd8170SKalle Valo 1324bdcd8170SKalle Valo param = 0; 1325bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS; 1326bdcd8170SKalle Valo param = SM(LPO_CAL_ENABLE, 1); 1327bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1328bdcd8170SKalle Valo if (status) 1329bdcd8170SKalle Valo return status; 1330bdcd8170SKalle Valo 1331bdcd8170SKalle Valo /* WAR to avoid SDIO CRC err */ 13320d0192baSKalle Valo if (ar->version.target_ver == AR6003_HW_2_0_VERSION) { 1333bdcd8170SKalle Valo ath6kl_err("temporary war to avoid sdio crc error\n"); 1334bdcd8170SKalle Valo 1335bdcd8170SKalle Valo param = 0x20; 1336bdcd8170SKalle Valo 1337bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS; 1338bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1339bdcd8170SKalle Valo if (status) 1340bdcd8170SKalle Valo return status; 1341bdcd8170SKalle Valo 1342bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS; 1343bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1344bdcd8170SKalle Valo if (status) 1345bdcd8170SKalle Valo return status; 1346bdcd8170SKalle Valo 1347bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS; 1348bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1349bdcd8170SKalle Valo if (status) 1350bdcd8170SKalle Valo return status; 1351bdcd8170SKalle Valo 1352bdcd8170SKalle Valo address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS; 1353bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1354bdcd8170SKalle Valo if (status) 1355bdcd8170SKalle Valo return status; 1356bdcd8170SKalle Valo } 1357bdcd8170SKalle Valo 1358bdcd8170SKalle Valo /* write EEPROM data to Target RAM */ 1359bdcd8170SKalle Valo status = ath6kl_upload_board_file(ar); 1360bdcd8170SKalle Valo if (status) 1361bdcd8170SKalle Valo return status; 1362bdcd8170SKalle Valo 1363bdcd8170SKalle Valo /* transfer One time Programmable data */ 1364bdcd8170SKalle Valo status = ath6kl_upload_otp(ar); 1365bdcd8170SKalle Valo if (status) 1366bdcd8170SKalle Valo return status; 1367bdcd8170SKalle Valo 1368bdcd8170SKalle Valo /* Download Target firmware */ 1369bdcd8170SKalle Valo status = ath6kl_upload_firmware(ar); 1370bdcd8170SKalle Valo if (status) 1371bdcd8170SKalle Valo return status; 1372bdcd8170SKalle Valo 1373bdcd8170SKalle Valo status = ath6kl_upload_patch(ar); 1374bdcd8170SKalle Valo if (status) 1375bdcd8170SKalle Valo return status; 1376bdcd8170SKalle Valo 1377bdcd8170SKalle Valo /* Restore system sleep */ 1378bdcd8170SKalle Valo address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS; 1379bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, sleep); 1380bdcd8170SKalle Valo if (status) 1381bdcd8170SKalle Valo return status; 1382bdcd8170SKalle Valo 1383bdcd8170SKalle Valo address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS; 1384bdcd8170SKalle Valo param = options | 0x20; 1385bdcd8170SKalle Valo status = ath6kl_bmi_reg_write(ar, address, param); 1386bdcd8170SKalle Valo if (status) 1387bdcd8170SKalle Valo return status; 1388bdcd8170SKalle Valo 1389bdcd8170SKalle Valo return status; 1390bdcd8170SKalle Valo } 1391bdcd8170SKalle Valo 1392a01ac414SKalle Valo static int ath6kl_init_hw_params(struct ath6kl *ar) 1393a01ac414SKalle Valo { 1394856f4b31SKalle Valo const struct ath6kl_hw *hw; 1395856f4b31SKalle Valo int i; 1396bef26a7fSKalle Valo 1397856f4b31SKalle Valo for (i = 0; i < ARRAY_SIZE(hw_list); i++) { 1398856f4b31SKalle Valo hw = &hw_list[i]; 1399bef26a7fSKalle Valo 1400856f4b31SKalle Valo if (hw->id == ar->version.target_ver) 1401a01ac414SKalle Valo break; 1402856f4b31SKalle Valo } 1403856f4b31SKalle Valo 1404856f4b31SKalle Valo if (i == ARRAY_SIZE(hw_list)) { 1405a01ac414SKalle Valo ath6kl_err("Unsupported hardware version: 0x%x\n", 1406a01ac414SKalle Valo ar->version.target_ver); 1407a01ac414SKalle Valo return -EINVAL; 1408a01ac414SKalle Valo } 1409a01ac414SKalle Valo 1410856f4b31SKalle Valo ar->hw = *hw; 1411856f4b31SKalle Valo 14126bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14136bc36431SKalle Valo "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n", 14146bc36431SKalle Valo ar->version.target_ver, ar->target_type, 14156bc36431SKalle Valo ar->hw.dataset_patch_addr, ar->hw.app_load_addr); 14166bc36431SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, 14176bc36431SKalle Valo "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x", 14186bc36431SKalle Valo ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr, 14196bc36431SKalle Valo ar->hw.reserved_ram_size); 142039586bf2SRyan Hsu ath6kl_dbg(ATH6KL_DBG_BOOT, 142139586bf2SRyan Hsu "refclk_hz %d uarttx_pin %d", 142239586bf2SRyan Hsu ar->hw.refclk_hz, ar->hw.uarttx_pin); 14236bc36431SKalle Valo 1424a01ac414SKalle Valo return 0; 1425a01ac414SKalle Valo } 1426a01ac414SKalle Valo 1427293badf4SKalle Valo static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type) 1428293badf4SKalle Valo { 1429293badf4SKalle Valo switch (type) { 1430293badf4SKalle Valo case ATH6KL_HIF_TYPE_SDIO: 1431293badf4SKalle Valo return "sdio"; 1432293badf4SKalle Valo case ATH6KL_HIF_TYPE_USB: 1433293badf4SKalle Valo return "usb"; 1434293badf4SKalle Valo } 1435293badf4SKalle Valo 1436293badf4SKalle Valo return NULL; 1437293badf4SKalle Valo } 1438293badf4SKalle Valo 14395fe4dffbSKalle Valo int ath6kl_init_hw_start(struct ath6kl *ar) 144020459ee2SKalle Valo { 144120459ee2SKalle Valo long timeleft; 144220459ee2SKalle Valo int ret, i; 144320459ee2SKalle Valo 14445fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n"); 14455fe4dffbSKalle Valo 144620459ee2SKalle Valo ret = ath6kl_hif_power_on(ar); 144720459ee2SKalle Valo if (ret) 144820459ee2SKalle Valo return ret; 144920459ee2SKalle Valo 145020459ee2SKalle Valo ret = ath6kl_configure_target(ar); 145120459ee2SKalle Valo if (ret) 145220459ee2SKalle Valo goto err_power_off; 145320459ee2SKalle Valo 145420459ee2SKalle Valo ret = ath6kl_init_upload(ar); 145520459ee2SKalle Valo if (ret) 145620459ee2SKalle Valo goto err_power_off; 145720459ee2SKalle Valo 145820459ee2SKalle Valo /* Do we need to finish the BMI phase */ 145920459ee2SKalle Valo /* FIXME: return error from ath6kl_bmi_done() */ 146020459ee2SKalle Valo if (ath6kl_bmi_done(ar)) { 146120459ee2SKalle Valo ret = -EIO; 146220459ee2SKalle Valo goto err_power_off; 146320459ee2SKalle Valo } 146420459ee2SKalle Valo 146520459ee2SKalle Valo /* 146620459ee2SKalle Valo * The reason we have to wait for the target here is that the 146720459ee2SKalle Valo * driver layer has to init BMI in order to set the host block 146820459ee2SKalle Valo * size. 146920459ee2SKalle Valo */ 147020459ee2SKalle Valo if (ath6kl_htc_wait_target(ar->htc_target)) { 147120459ee2SKalle Valo ret = -EIO; 147220459ee2SKalle Valo goto err_power_off; 147320459ee2SKalle Valo } 147420459ee2SKalle Valo 147520459ee2SKalle Valo if (ath6kl_init_service_ep(ar)) { 147620459ee2SKalle Valo ret = -EIO; 147720459ee2SKalle Valo goto err_cleanup_scatter; 147820459ee2SKalle Valo } 147920459ee2SKalle Valo 148020459ee2SKalle Valo /* setup credit distribution */ 148120459ee2SKalle Valo ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info); 148220459ee2SKalle Valo 148320459ee2SKalle Valo /* start HTC */ 148420459ee2SKalle Valo ret = ath6kl_htc_start(ar->htc_target); 148520459ee2SKalle Valo if (ret) { 148620459ee2SKalle Valo /* FIXME: call this */ 148720459ee2SKalle Valo ath6kl_cookie_cleanup(ar); 148820459ee2SKalle Valo goto err_cleanup_scatter; 148920459ee2SKalle Valo } 149020459ee2SKalle Valo 149120459ee2SKalle Valo /* Wait for Wmi event to be ready */ 149220459ee2SKalle Valo timeleft = wait_event_interruptible_timeout(ar->event_wq, 149320459ee2SKalle Valo test_bit(WMI_READY, 149420459ee2SKalle Valo &ar->flag), 149520459ee2SKalle Valo WMI_TIMEOUT); 149620459ee2SKalle Valo 149720459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n"); 149820459ee2SKalle Valo 1499293badf4SKalle Valo 1500293badf4SKalle Valo if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) { 150165a8b4ccSKalle Valo ath6kl_info("%s %s fw %s api %d%s\n", 1502293badf4SKalle Valo ar->hw.name, 1503293badf4SKalle Valo ath6kl_init_get_hif_name(ar->hif_type), 1504293badf4SKalle Valo ar->wiphy->fw_version, 150565a8b4ccSKalle Valo ar->fw_api, 1506293badf4SKalle Valo test_bit(TESTMODE, &ar->flag) ? " testmode" : ""); 1507293badf4SKalle Valo } 1508293badf4SKalle Valo 150920459ee2SKalle Valo if (ar->version.abi_ver != ATH6KL_ABI_VERSION) { 151020459ee2SKalle Valo ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n", 151120459ee2SKalle Valo ATH6KL_ABI_VERSION, ar->version.abi_ver); 151220459ee2SKalle Valo ret = -EIO; 151320459ee2SKalle Valo goto err_htc_stop; 151420459ee2SKalle Valo } 151520459ee2SKalle Valo 151620459ee2SKalle Valo if (!timeleft || signal_pending(current)) { 151720459ee2SKalle Valo ath6kl_err("wmi is not ready or wait was interrupted\n"); 151820459ee2SKalle Valo ret = -EIO; 151920459ee2SKalle Valo goto err_htc_stop; 152020459ee2SKalle Valo } 152120459ee2SKalle Valo 152220459ee2SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__); 152320459ee2SKalle Valo 152420459ee2SKalle Valo /* communicate the wmi protocol verision to the target */ 152520459ee2SKalle Valo /* FIXME: return error */ 152620459ee2SKalle Valo if ((ath6kl_set_host_app_area(ar)) != 0) 152720459ee2SKalle Valo ath6kl_err("unable to set the host app area\n"); 152820459ee2SKalle Valo 152971f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) { 153020459ee2SKalle Valo ret = ath6kl_target_config_wlan_params(ar, i); 153120459ee2SKalle Valo if (ret) 153220459ee2SKalle Valo goto err_htc_stop; 153320459ee2SKalle Valo } 153420459ee2SKalle Valo 153576a9fbe2SKalle Valo ar->state = ATH6KL_STATE_ON; 153676a9fbe2SKalle Valo 153720459ee2SKalle Valo return 0; 153820459ee2SKalle Valo 153920459ee2SKalle Valo err_htc_stop: 154020459ee2SKalle Valo ath6kl_htc_stop(ar->htc_target); 154120459ee2SKalle Valo err_cleanup_scatter: 154220459ee2SKalle Valo ath6kl_hif_cleanup_scatter(ar); 154320459ee2SKalle Valo err_power_off: 154420459ee2SKalle Valo ath6kl_hif_power_off(ar); 154520459ee2SKalle Valo 154620459ee2SKalle Valo return ret; 154720459ee2SKalle Valo } 154820459ee2SKalle Valo 15495fe4dffbSKalle Valo int ath6kl_init_hw_stop(struct ath6kl *ar) 15505fe4dffbSKalle Valo { 15515fe4dffbSKalle Valo int ret; 15525fe4dffbSKalle Valo 15535fe4dffbSKalle Valo ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n"); 15545fe4dffbSKalle Valo 15555fe4dffbSKalle Valo ath6kl_htc_stop(ar->htc_target); 15565fe4dffbSKalle Valo 15575fe4dffbSKalle Valo ath6kl_hif_stop(ar); 15585fe4dffbSKalle Valo 15595fe4dffbSKalle Valo ath6kl_bmi_reset(ar); 15605fe4dffbSKalle Valo 15615fe4dffbSKalle Valo ret = ath6kl_hif_power_off(ar); 15625fe4dffbSKalle Valo if (ret) 15635fe4dffbSKalle Valo ath6kl_warn("failed to power off hif: %d\n", ret); 15645fe4dffbSKalle Valo 156576a9fbe2SKalle Valo ar->state = ATH6KL_STATE_OFF; 156676a9fbe2SKalle Valo 15675fe4dffbSKalle Valo return 0; 15685fe4dffbSKalle Valo } 15695fe4dffbSKalle Valo 1570bdcd8170SKalle Valo int ath6kl_core_init(struct ath6kl *ar) 1571bdcd8170SKalle Valo { 1572bdcd8170SKalle Valo struct ath6kl_bmi_target_info targ_info; 157361448a93SKalle Valo struct net_device *ndev; 157420459ee2SKalle Valo int ret = 0, i; 1575bdcd8170SKalle Valo 1576bdcd8170SKalle Valo ar->ath6kl_wq = create_singlethread_workqueue("ath6kl"); 1577bdcd8170SKalle Valo if (!ar->ath6kl_wq) 1578bdcd8170SKalle Valo return -ENOMEM; 1579bdcd8170SKalle Valo 1580bdcd8170SKalle Valo ret = ath6kl_bmi_init(ar); 1581bdcd8170SKalle Valo if (ret) 1582bdcd8170SKalle Valo goto err_wq; 1583bdcd8170SKalle Valo 158420459ee2SKalle Valo /* 158520459ee2SKalle Valo * Turn on power to get hardware (target) version and leave power 158620459ee2SKalle Valo * on delibrately as we will boot the hardware anyway within few 158720459ee2SKalle Valo * seconds. 158820459ee2SKalle Valo */ 1589b2e75698SKalle Valo ret = ath6kl_hif_power_on(ar); 1590bdcd8170SKalle Valo if (ret) 1591bdcd8170SKalle Valo goto err_bmi_cleanup; 1592bdcd8170SKalle Valo 1593b2e75698SKalle Valo ret = ath6kl_bmi_get_target_info(ar, &targ_info); 1594b2e75698SKalle Valo if (ret) 1595b2e75698SKalle Valo goto err_power_off; 1596b2e75698SKalle Valo 1597bdcd8170SKalle Valo ar->version.target_ver = le32_to_cpu(targ_info.version); 1598bdcd8170SKalle Valo ar->target_type = le32_to_cpu(targ_info.type); 1599be98e3a4SVasanthakumar Thiagarajan ar->wiphy->hw_version = le32_to_cpu(targ_info.version); 1600bdcd8170SKalle Valo 1601a01ac414SKalle Valo ret = ath6kl_init_hw_params(ar); 1602a01ac414SKalle Valo if (ret) 1603b2e75698SKalle Valo goto err_power_off; 1604a01ac414SKalle Valo 1605ad226ec2SKalle Valo ar->htc_target = ath6kl_htc_create(ar); 1606bdcd8170SKalle Valo 1607bdcd8170SKalle Valo if (!ar->htc_target) { 1608bdcd8170SKalle Valo ret = -ENOMEM; 1609b2e75698SKalle Valo goto err_power_off; 1610bdcd8170SKalle Valo } 1611bdcd8170SKalle Valo 1612772c31eeSKalle Valo ret = ath6kl_fetch_firmwares(ar); 1613772c31eeSKalle Valo if (ret) 1614772c31eeSKalle Valo goto err_htc_cleanup; 1615772c31eeSKalle Valo 161661448a93SKalle Valo /* FIXME: we should free all firmwares in the error cases below */ 161761448a93SKalle Valo 161861448a93SKalle Valo /* Indicate that WMI is enabled (although not ready yet) */ 161961448a93SKalle Valo set_bit(WMI_ENABLED, &ar->flag); 162061448a93SKalle Valo ar->wmi = ath6kl_wmi_init(ar); 162161448a93SKalle Valo if (!ar->wmi) { 162261448a93SKalle Valo ath6kl_err("failed to initialize wmi\n"); 162361448a93SKalle Valo ret = -EIO; 162461448a93SKalle Valo goto err_htc_cleanup; 162561448a93SKalle Valo } 162661448a93SKalle Valo 162761448a93SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: got wmi @ 0x%p.\n", __func__, ar->wmi); 162861448a93SKalle Valo 162961448a93SKalle Valo ret = ath6kl_register_ieee80211_hw(ar); 163061448a93SKalle Valo if (ret) 163161448a93SKalle Valo goto err_node_cleanup; 163261448a93SKalle Valo 163361448a93SKalle Valo ret = ath6kl_debug_init(ar); 163461448a93SKalle Valo if (ret) { 163561448a93SKalle Valo wiphy_unregister(ar->wiphy); 163661448a93SKalle Valo goto err_node_cleanup; 163761448a93SKalle Valo } 163861448a93SKalle Valo 163971f96ee6SKalle Valo for (i = 0; i < ar->vif_max; i++) 164061448a93SKalle Valo ar->avail_idx_map |= BIT(i); 164161448a93SKalle Valo 164261448a93SKalle Valo rtnl_lock(); 164361448a93SKalle Valo 164461448a93SKalle Valo /* Add an initial station interface */ 164561448a93SKalle Valo ndev = ath6kl_interface_add(ar, "wlan%d", NL80211_IFTYPE_STATION, 0, 164661448a93SKalle Valo INFRA_NETWORK); 164761448a93SKalle Valo 164861448a93SKalle Valo rtnl_unlock(); 164961448a93SKalle Valo 165061448a93SKalle Valo if (!ndev) { 165161448a93SKalle Valo ath6kl_err("Failed to instantiate a network device\n"); 165261448a93SKalle Valo ret = -ENOMEM; 165361448a93SKalle Valo wiphy_unregister(ar->wiphy); 165461448a93SKalle Valo goto err_debug_init; 165561448a93SKalle Valo } 165661448a93SKalle Valo 165761448a93SKalle Valo 165861448a93SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "%s: name=%s dev=0x%p, ar=0x%p\n", 165961448a93SKalle Valo __func__, ndev->name, ndev, ar); 166061448a93SKalle Valo 166161448a93SKalle Valo /* setup access class priority mappings */ 166261448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_BK] = 0; /* lowest */ 166361448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_BE] = 1; 166461448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_VI] = 2; 166561448a93SKalle Valo ar->ac_stream_pri_map[WMM_AC_VO] = 3; /* highest */ 166661448a93SKalle Valo 166761448a93SKalle Valo /* give our connected endpoints some buffers */ 166861448a93SKalle Valo ath6kl_rx_refill(ar->htc_target, ar->ctrl_ep); 166961448a93SKalle Valo ath6kl_rx_refill(ar->htc_target, ar->ac2ep_map[WMM_AC_BE]); 167061448a93SKalle Valo 167161448a93SKalle Valo /* allocate some buffers that handle larger AMSDU frames */ 167261448a93SKalle Valo ath6kl_refill_amsdu_rxbufs(ar, ATH6KL_MAX_AMSDU_RX_BUFFERS); 167361448a93SKalle Valo 167461448a93SKalle Valo ath6kl_cookie_init(ar); 167561448a93SKalle Valo 167661448a93SKalle Valo ar->conf_flags = ATH6KL_CONF_IGNORE_ERP_BARKER | 167761448a93SKalle Valo ATH6KL_CONF_ENABLE_11N | ATH6KL_CONF_ENABLE_TX_BURST; 167861448a93SKalle Valo 16798277de15SKalle Valo if (suspend_cutpower) 16808277de15SKalle Valo ar->conf_flags |= ATH6KL_CONF_SUSPEND_CUTPOWER; 16818277de15SKalle Valo 168261448a93SKalle Valo ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM | 1683fb94333aSArik Nemtsov WIPHY_FLAG_HAVE_AP_SME | 16847e95e365SKalle Valo WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL | 1685fb94333aSArik Nemtsov WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD; 1686fb94333aSArik Nemtsov 168710509f90SKalle Valo if (test_bit(ATH6KL_FW_CAPABILITY_SCHED_SCAN, ar->fw_capabilities)) 168810509f90SKalle Valo ar->wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN; 168910509f90SKalle Valo 1690fb94333aSArik Nemtsov ar->wiphy->probe_resp_offload = 1691fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS | 1692fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_WPS2 | 1693fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_P2P | 1694fb94333aSArik Nemtsov NL80211_PROBE_RESP_OFFLOAD_SUPPORT_80211U; 169561448a93SKalle Valo 16965fe4dffbSKalle Valo set_bit(FIRST_BOOT, &ar->flag); 16975fe4dffbSKalle Valo 1698bc48ad31SRishi Panjwani ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; 1699bc48ad31SRishi Panjwani 17005fe4dffbSKalle Valo ret = ath6kl_init_hw_start(ar); 170120459ee2SKalle Valo if (ret) { 17025fe4dffbSKalle Valo ath6kl_err("Failed to start hardware: %d\n", ret); 170320459ee2SKalle Valo goto err_rxbuf_cleanup; 170461448a93SKalle Valo } 170561448a93SKalle Valo 170661448a93SKalle Valo /* 170761448a93SKalle Valo * Set mac address which is received in ready event 170861448a93SKalle Valo * FIXME: Move to ath6kl_interface_add() 170961448a93SKalle Valo */ 171061448a93SKalle Valo memcpy(ndev->dev_addr, ar->mac_addr, ETH_ALEN); 1711bdcd8170SKalle Valo 1712bdcd8170SKalle Valo return ret; 1713bdcd8170SKalle Valo 171461448a93SKalle Valo err_rxbuf_cleanup: 171561448a93SKalle Valo ath6kl_htc_flush_rx_buf(ar->htc_target); 171661448a93SKalle Valo ath6kl_cleanup_amsdu_rxbufs(ar); 171761448a93SKalle Valo rtnl_lock(); 171861448a93SKalle Valo ath6kl_deinit_if_data(netdev_priv(ndev)); 171961448a93SKalle Valo rtnl_unlock(); 172061448a93SKalle Valo wiphy_unregister(ar->wiphy); 172161448a93SKalle Valo err_debug_init: 172261448a93SKalle Valo ath6kl_debug_cleanup(ar); 172361448a93SKalle Valo err_node_cleanup: 172461448a93SKalle Valo ath6kl_wmi_shutdown(ar->wmi); 172561448a93SKalle Valo clear_bit(WMI_ENABLED, &ar->flag); 172661448a93SKalle Valo ar->wmi = NULL; 1727bdcd8170SKalle Valo err_htc_cleanup: 1728ad226ec2SKalle Valo ath6kl_htc_cleanup(ar->htc_target); 1729b2e75698SKalle Valo err_power_off: 1730b2e75698SKalle Valo ath6kl_hif_power_off(ar); 1731bdcd8170SKalle Valo err_bmi_cleanup: 1732bdcd8170SKalle Valo ath6kl_bmi_cleanup(ar); 1733bdcd8170SKalle Valo err_wq: 1734bdcd8170SKalle Valo destroy_workqueue(ar->ath6kl_wq); 17358dafb70eSVasanthakumar Thiagarajan 1736bdcd8170SKalle Valo return ret; 1737bdcd8170SKalle Valo } 1738bdcd8170SKalle Valo 173955055976SVasanthakumar Thiagarajan void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready) 17406db8fa53SVasanthakumar Thiagarajan { 17416db8fa53SVasanthakumar Thiagarajan static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 17426db8fa53SVasanthakumar Thiagarajan bool discon_issued; 17436db8fa53SVasanthakumar Thiagarajan 17446db8fa53SVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 17456db8fa53SVasanthakumar Thiagarajan 17466db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &vif->flags); 17476db8fa53SVasanthakumar Thiagarajan 17486db8fa53SVasanthakumar Thiagarajan if (wmi_ready) { 17496db8fa53SVasanthakumar Thiagarajan discon_issued = test_bit(CONNECTED, &vif->flags) || 17506db8fa53SVasanthakumar Thiagarajan test_bit(CONNECT_PEND, &vif->flags); 17516db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect(vif); 17526db8fa53SVasanthakumar Thiagarajan del_timer(&vif->disconnect_timer); 17536db8fa53SVasanthakumar Thiagarajan 17546db8fa53SVasanthakumar Thiagarajan if (discon_issued) 17556db8fa53SVasanthakumar Thiagarajan ath6kl_disconnect_event(vif, DISCONNECT_CMD, 17566db8fa53SVasanthakumar Thiagarajan (vif->nw_type & AP_NETWORK) ? 17576db8fa53SVasanthakumar Thiagarajan bcast_mac : vif->bssid, 17586db8fa53SVasanthakumar Thiagarajan 0, NULL, 0); 17596db8fa53SVasanthakumar Thiagarajan } 17606db8fa53SVasanthakumar Thiagarajan 17616db8fa53SVasanthakumar Thiagarajan if (vif->scan_req) { 17626db8fa53SVasanthakumar Thiagarajan cfg80211_scan_done(vif->scan_req, true); 17636db8fa53SVasanthakumar Thiagarajan vif->scan_req = NULL; 17646db8fa53SVasanthakumar Thiagarajan } 17656db8fa53SVasanthakumar Thiagarajan } 17666db8fa53SVasanthakumar Thiagarajan 1767bdcd8170SKalle Valo void ath6kl_stop_txrx(struct ath6kl *ar) 1768bdcd8170SKalle Valo { 1769990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif, *tmp_vif; 1770bdcd8170SKalle Valo 1771bdcd8170SKalle Valo set_bit(DESTROY_IN_PROGRESS, &ar->flag); 1772bdcd8170SKalle Valo 1773bdcd8170SKalle Valo if (down_interruptible(&ar->sem)) { 1774bdcd8170SKalle Valo ath6kl_err("down_interruptible failed\n"); 1775bdcd8170SKalle Valo return; 1776bdcd8170SKalle Valo } 1777bdcd8170SKalle Valo 177811f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1779990bd915SVasanthakumar Thiagarajan list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) { 1780990bd915SVasanthakumar Thiagarajan list_del(&vif->list); 178111f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1782990bd915SVasanthakumar Thiagarajan ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag)); 178327929723SVasanthakumar Thiagarajan rtnl_lock(); 178427929723SVasanthakumar Thiagarajan ath6kl_deinit_if_data(vif); 178527929723SVasanthakumar Thiagarajan rtnl_unlock(); 178611f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 1787990bd915SVasanthakumar Thiagarajan } 178811f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 1789bdcd8170SKalle Valo 17906db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_READY, &ar->flag); 17916db8fa53SVasanthakumar Thiagarajan 17926db8fa53SVasanthakumar Thiagarajan /* 17936db8fa53SVasanthakumar Thiagarajan * After wmi_shudown all WMI events will be dropped. We 17946db8fa53SVasanthakumar Thiagarajan * need to cleanup the buffers allocated in AP mode and 17956db8fa53SVasanthakumar Thiagarajan * give disconnect notification to stack, which usually 17966db8fa53SVasanthakumar Thiagarajan * happens in the disconnect_event. Simulate the disconnect 17976db8fa53SVasanthakumar Thiagarajan * event by calling the function directly. Sometimes 17986db8fa53SVasanthakumar Thiagarajan * disconnect_event will be received when the debug logs 17996db8fa53SVasanthakumar Thiagarajan * are collected. 18006db8fa53SVasanthakumar Thiagarajan */ 18016db8fa53SVasanthakumar Thiagarajan ath6kl_wmi_shutdown(ar->wmi); 18026db8fa53SVasanthakumar Thiagarajan 18036db8fa53SVasanthakumar Thiagarajan clear_bit(WMI_ENABLED, &ar->flag); 18046db8fa53SVasanthakumar Thiagarajan if (ar->htc_target) { 18056db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__); 18066db8fa53SVasanthakumar Thiagarajan ath6kl_htc_stop(ar->htc_target); 1807bdcd8170SKalle Valo } 1808bdcd8170SKalle Valo 1809bdcd8170SKalle Valo /* 18106db8fa53SVasanthakumar Thiagarajan * Try to reset the device if we can. The driver may have been 18116db8fa53SVasanthakumar Thiagarajan * configure NOT to reset the target during a debug session. 1812bdcd8170SKalle Valo */ 18136db8fa53SVasanthakumar Thiagarajan ath6kl_dbg(ATH6KL_DBG_TRC, 18146db8fa53SVasanthakumar Thiagarajan "attempting to reset target on instance destroy\n"); 18156db8fa53SVasanthakumar Thiagarajan ath6kl_reset_device(ar, ar->target_type, true, true); 1816bdcd8170SKalle Valo 18176db8fa53SVasanthakumar Thiagarajan clear_bit(WLAN_ENABLED, &ar->flag); 1818bdcd8170SKalle Valo } 1819