1 /* 2 * Copyright (c) 2007-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 #include "hif.h" 18 19 #include <linux/export.h> 20 21 #include "core.h" 22 #include "target.h" 23 #include "hif-ops.h" 24 #include "debug.h" 25 #include "trace.h" 26 27 #define MAILBOX_FOR_BLOCK_SIZE 1 28 29 #define ATH6KL_TIME_QUANTUM 10 /* in ms */ 30 31 static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req, 32 bool from_dma) 33 { 34 u8 *buf; 35 int i; 36 37 buf = req->virt_dma_buf; 38 39 for (i = 0; i < req->scat_entries; i++) { 40 41 if (from_dma) 42 memcpy(req->scat_list[i].buf, buf, 43 req->scat_list[i].len); 44 else 45 memcpy(buf, req->scat_list[i].buf, 46 req->scat_list[i].len); 47 48 buf += req->scat_list[i].len; 49 } 50 51 return 0; 52 } 53 54 int ath6kl_hif_rw_comp_handler(void *context, int status) 55 { 56 struct htc_packet *packet = context; 57 58 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n", 59 packet, status); 60 61 packet->status = status; 62 packet->completion(packet->context, packet); 63 64 return 0; 65 } 66 EXPORT_SYMBOL(ath6kl_hif_rw_comp_handler); 67 68 #define REG_DUMP_COUNT_AR6003 60 69 #define REGISTER_DUMP_LEN_MAX 60 70 71 static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar) 72 { 73 __le32 regdump_val[REGISTER_DUMP_LEN_MAX]; 74 u32 i, address, regdump_addr = 0; 75 int ret; 76 77 if (ar->target_type != TARGET_TYPE_AR6003) 78 return; 79 80 /* the reg dump pointer is copied to the host interest area */ 81 address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state)); 82 address = TARG_VTOP(ar->target_type, address); 83 84 /* read RAM location through diagnostic window */ 85 ret = ath6kl_diag_read32(ar, address, ®dump_addr); 86 87 if (ret || !regdump_addr) { 88 ath6kl_warn("failed to get ptr to register dump area: %d\n", 89 ret); 90 return; 91 } 92 93 ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n", 94 regdump_addr); 95 regdump_addr = TARG_VTOP(ar->target_type, regdump_addr); 96 97 /* fetch register dump data */ 98 ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0], 99 REG_DUMP_COUNT_AR6003 * (sizeof(u32))); 100 if (ret) { 101 ath6kl_warn("failed to get register dump: %d\n", ret); 102 return; 103 } 104 105 ath6kl_info("crash dump:\n"); 106 ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version, 107 ar->wiphy->fw_version); 108 109 BUILD_BUG_ON(REG_DUMP_COUNT_AR6003 % 4); 110 111 for (i = 0; i < REG_DUMP_COUNT_AR6003; i += 4) { 112 ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n", 113 i, 114 le32_to_cpu(regdump_val[i]), 115 le32_to_cpu(regdump_val[i + 1]), 116 le32_to_cpu(regdump_val[i + 2]), 117 le32_to_cpu(regdump_val[i + 3])); 118 } 119 120 } 121 122 static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev) 123 { 124 u32 dummy; 125 int ret; 126 127 ath6kl_warn("firmware crashed\n"); 128 129 /* 130 * read counter to clear the interrupt, the debug error interrupt is 131 * counter 0. 132 */ 133 ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS, 134 (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC); 135 if (ret) 136 ath6kl_warn("Failed to clear debug interrupt: %d\n", ret); 137 138 ath6kl_hif_dump_fw_crash(dev->ar); 139 ath6kl_read_fwlogs(dev->ar); 140 ath6kl_recovery_err_notify(dev->ar, ATH6KL_FW_ASSERT); 141 142 return ret; 143 } 144 145 /* mailbox recv message polling */ 146 int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd, 147 int timeout) 148 { 149 struct ath6kl_irq_proc_registers *rg; 150 int status = 0, i; 151 u8 htc_mbox = 1 << HTC_MAILBOX; 152 153 for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) { 154 /* this is the standard HIF way, load the reg table */ 155 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 156 (u8 *) &dev->irq_proc_reg, 157 sizeof(dev->irq_proc_reg), 158 HIF_RD_SYNC_BYTE_INC); 159 160 if (status) { 161 ath6kl_err("failed to read reg table\n"); 162 return status; 163 } 164 165 /* check for MBOX data and valid lookahead */ 166 if (dev->irq_proc_reg.host_int_status & htc_mbox) { 167 if (dev->irq_proc_reg.rx_lkahd_valid & 168 htc_mbox) { 169 /* 170 * Mailbox has a message and the look ahead 171 * is valid. 172 */ 173 rg = &dev->irq_proc_reg; 174 *lk_ahd = 175 le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 176 break; 177 } 178 } 179 180 /* delay a little */ 181 mdelay(ATH6KL_TIME_QUANTUM); 182 ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i); 183 } 184 185 if (i == 0) { 186 ath6kl_err("timeout waiting for recv message\n"); 187 status = -ETIME; 188 /* check if the target asserted */ 189 if (dev->irq_proc_reg.counter_int_status & 190 ATH6KL_TARGET_DEBUG_INTR_MASK) 191 /* 192 * Target failure handler will be called in case of 193 * an assert. 194 */ 195 ath6kl_hif_proc_dbg_intr(dev); 196 } 197 198 return status; 199 } 200 201 /* 202 * Disable packet reception (used in case the host runs out of buffers) 203 * using the interrupt enable registers through the host I/F 204 */ 205 int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx) 206 { 207 struct ath6kl_irq_enable_reg regs; 208 int status = 0; 209 210 ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n", 211 enable_rx ? "enable" : "disable"); 212 213 /* take the lock to protect interrupt enable shadows */ 214 spin_lock_bh(&dev->lock); 215 216 if (enable_rx) 217 dev->irq_en_reg.int_status_en |= 218 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 219 else 220 dev->irq_en_reg.int_status_en &= 221 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 222 223 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 224 225 spin_unlock_bh(&dev->lock); 226 227 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 228 ®s.int_status_en, 229 sizeof(struct ath6kl_irq_enable_reg), 230 HIF_WR_SYNC_BYTE_INC); 231 232 return status; 233 } 234 235 int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev, 236 struct hif_scatter_req *scat_req, bool read) 237 { 238 int status = 0; 239 240 if (read) { 241 scat_req->req = HIF_RD_SYNC_BLOCK_FIX; 242 scat_req->addr = dev->ar->mbox_info.htc_addr; 243 } else { 244 scat_req->req = HIF_WR_ASYNC_BLOCK_INC; 245 246 scat_req->addr = 247 (scat_req->len > HIF_MBOX_WIDTH) ? 248 dev->ar->mbox_info.htc_ext_addr : 249 dev->ar->mbox_info.htc_addr; 250 } 251 252 ath6kl_dbg(ATH6KL_DBG_HIF, 253 "hif submit scatter request entries %d len %d mbox 0x%x %s %s\n", 254 scat_req->scat_entries, scat_req->len, 255 scat_req->addr, !read ? "async" : "sync", 256 (read) ? "rd" : "wr"); 257 258 if (!read && scat_req->virt_scat) { 259 status = ath6kl_hif_cp_scat_dma_buf(scat_req, false); 260 if (status) { 261 scat_req->status = status; 262 scat_req->complete(dev->ar->htc_target, scat_req); 263 return 0; 264 } 265 } 266 267 status = ath6kl_hif_scat_req_rw(dev->ar, scat_req); 268 269 if (read) { 270 /* in sync mode, we can touch the scatter request */ 271 scat_req->status = status; 272 if (!status && scat_req->virt_scat) 273 scat_req->status = 274 ath6kl_hif_cp_scat_dma_buf(scat_req, true); 275 } 276 277 return status; 278 } 279 280 static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev) 281 { 282 u8 counter_int_status; 283 284 ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n"); 285 286 counter_int_status = dev->irq_proc_reg.counter_int_status & 287 dev->irq_en_reg.cntr_int_status_en; 288 289 ath6kl_dbg(ATH6KL_DBG_IRQ, 290 "valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", 291 counter_int_status); 292 293 /* 294 * NOTE: other modules like GMBOX may use the counter interrupt for 295 * credit flow control on other counters, we only need to check for 296 * the debug assertion counter interrupt. 297 */ 298 if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK) 299 return ath6kl_hif_proc_dbg_intr(dev); 300 301 return 0; 302 } 303 304 static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev) 305 { 306 int status; 307 u8 error_int_status; 308 u8 reg_buf[4]; 309 310 ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n"); 311 312 error_int_status = dev->irq_proc_reg.error_int_status & 0x0F; 313 if (!error_int_status) { 314 WARN_ON(1); 315 return -EIO; 316 } 317 318 ath6kl_dbg(ATH6KL_DBG_IRQ, 319 "valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", 320 error_int_status); 321 322 if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status)) 323 ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n"); 324 325 if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status)) 326 ath6kl_err("rx underflow\n"); 327 328 if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status)) 329 ath6kl_err("tx overflow\n"); 330 331 /* Clear the interrupt */ 332 dev->irq_proc_reg.error_int_status &= ~error_int_status; 333 334 /* set W1C value to clear the interrupt, this hits the register first */ 335 reg_buf[0] = error_int_status; 336 reg_buf[1] = 0; 337 reg_buf[2] = 0; 338 reg_buf[3] = 0; 339 340 status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS, 341 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 342 343 WARN_ON(status); 344 345 return status; 346 } 347 348 static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev) 349 { 350 int status; 351 u8 cpu_int_status; 352 u8 reg_buf[4]; 353 354 ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n"); 355 356 cpu_int_status = dev->irq_proc_reg.cpu_int_status & 357 dev->irq_en_reg.cpu_int_status_en; 358 if (!cpu_int_status) { 359 WARN_ON(1); 360 return -EIO; 361 } 362 363 ath6kl_dbg(ATH6KL_DBG_IRQ, 364 "valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", 365 cpu_int_status); 366 367 /* Clear the interrupt */ 368 dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status; 369 370 /* 371 * Set up the register transfer buffer to hit the register 4 times , 372 * this is done to make the access 4-byte aligned to mitigate issues 373 * with host bus interconnects that restrict bus transfer lengths to 374 * be a multiple of 4-bytes. 375 */ 376 377 /* set W1C value to clear the interrupt, this hits the register first */ 378 reg_buf[0] = cpu_int_status; 379 /* the remaining are set to zero which have no-effect */ 380 reg_buf[1] = 0; 381 reg_buf[2] = 0; 382 reg_buf[3] = 0; 383 384 status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS, 385 reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); 386 387 WARN_ON(status); 388 389 return status; 390 } 391 392 /* process pending interrupts synchronously */ 393 static int proc_pending_irqs(struct ath6kl_device *dev, bool *done) 394 { 395 struct ath6kl_irq_proc_registers *rg; 396 int status = 0; 397 u8 host_int_status = 0; 398 u32 lk_ahd = 0; 399 u8 htc_mbox = 1 << HTC_MAILBOX; 400 401 ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev); 402 403 /* 404 * NOTE: HIF implementation guarantees that the context of this 405 * call allows us to perform SYNCHRONOUS I/O, that is we can block, 406 * sleep or call any API that can block or switch thread/task 407 * contexts. This is a fully schedulable context. 408 */ 409 410 /* 411 * Process pending intr only when int_status_en is clear, it may 412 * result in unnecessary bus transaction otherwise. Target may be 413 * unresponsive at the time. 414 */ 415 if (dev->irq_en_reg.int_status_en) { 416 /* 417 * Read the first 28 bytes of the HTC register table. This 418 * will yield us the value of different int status 419 * registers and the lookahead registers. 420 * 421 * length = sizeof(int_status) + sizeof(cpu_int_status) 422 * + sizeof(error_int_status) + 423 * sizeof(counter_int_status) + 424 * sizeof(mbox_frame) + sizeof(rx_lkahd_valid) 425 * + sizeof(hole) + sizeof(rx_lkahd) + 426 * sizeof(int_status_en) + 427 * sizeof(cpu_int_status_en) + 428 * sizeof(err_int_status_en) + 429 * sizeof(cntr_int_status_en); 430 */ 431 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, 432 (u8 *) &dev->irq_proc_reg, 433 sizeof(dev->irq_proc_reg), 434 HIF_RD_SYNC_BYTE_INC); 435 if (status) 436 goto out; 437 438 ath6kl_dump_registers(dev, &dev->irq_proc_reg, 439 &dev->irq_en_reg); 440 trace_ath6kl_sdio_irq(&dev->irq_en_reg, 441 sizeof(dev->irq_en_reg)); 442 443 /* Update only those registers that are enabled */ 444 host_int_status = dev->irq_proc_reg.host_int_status & 445 dev->irq_en_reg.int_status_en; 446 447 /* Look at mbox status */ 448 if (host_int_status & htc_mbox) { 449 /* 450 * Mask out pending mbox value, we use "lookAhead as 451 * the real flag for mbox processing. 452 */ 453 host_int_status &= ~htc_mbox; 454 if (dev->irq_proc_reg.rx_lkahd_valid & 455 htc_mbox) { 456 rg = &dev->irq_proc_reg; 457 lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); 458 if (!lk_ahd) 459 ath6kl_err("lookAhead is zero!\n"); 460 } 461 } 462 } 463 464 if (!host_int_status && !lk_ahd) { 465 *done = true; 466 goto out; 467 } 468 469 if (lk_ahd) { 470 int fetched = 0; 471 472 ath6kl_dbg(ATH6KL_DBG_IRQ, 473 "pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd); 474 /* 475 * Mailbox Interrupt, the HTC layer may issue async 476 * requests to empty the mailbox. When emptying the recv 477 * mailbox we use the async handler above called from the 478 * completion routine of the callers read request. This can 479 * improve performance by reducing context switching when 480 * we rapidly pull packets. 481 */ 482 status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt, 483 lk_ahd, &fetched); 484 if (status) 485 goto out; 486 487 if (!fetched) 488 /* 489 * HTC could not pull any messages out due to lack 490 * of resources. 491 */ 492 dev->htc_cnxt->chk_irq_status_cnt = 0; 493 } 494 495 /* now handle the rest of them */ 496 ath6kl_dbg(ATH6KL_DBG_IRQ, 497 "valid interrupt source(s) for other interrupts: 0x%x\n", 498 host_int_status); 499 500 if (MS(HOST_INT_STATUS_CPU, host_int_status)) { 501 /* CPU Interrupt */ 502 status = ath6kl_hif_proc_cpu_intr(dev); 503 if (status) 504 goto out; 505 } 506 507 if (MS(HOST_INT_STATUS_ERROR, host_int_status)) { 508 /* Error Interrupt */ 509 status = ath6kl_hif_proc_err_intr(dev); 510 if (status) 511 goto out; 512 } 513 514 if (MS(HOST_INT_STATUS_COUNTER, host_int_status)) 515 /* Counter Interrupt */ 516 status = ath6kl_hif_proc_counter_intr(dev); 517 518 out: 519 /* 520 * An optimization to bypass reading the IRQ status registers 521 * unecessarily which can re-wake the target, if upper layers 522 * determine that we are in a low-throughput mode, we can rely on 523 * taking another interrupt rather than re-checking the status 524 * registers which can re-wake the target. 525 * 526 * NOTE : for host interfaces that makes use of detecting pending 527 * mbox messages at hif can not use this optimization due to 528 * possible side effects, SPI requires the host to drain all 529 * messages from the mailbox before exiting the ISR routine. 530 */ 531 532 ath6kl_dbg(ATH6KL_DBG_IRQ, 533 "bypassing irq status re-check, forcing done\n"); 534 535 if (!dev->htc_cnxt->chk_irq_status_cnt) 536 *done = true; 537 538 ath6kl_dbg(ATH6KL_DBG_IRQ, 539 "proc_pending_irqs: (done:%d, status=%d\n", *done, status); 540 541 return status; 542 } 543 544 /* interrupt handler, kicks off all interrupt processing */ 545 int ath6kl_hif_intr_bh_handler(struct ath6kl *ar) 546 { 547 struct ath6kl_device *dev = ar->htc_target->dev; 548 unsigned long timeout; 549 int status = 0; 550 bool done = false; 551 552 /* 553 * Reset counter used to flag a re-scan of IRQ status registers on 554 * the target. 555 */ 556 dev->htc_cnxt->chk_irq_status_cnt = 0; 557 558 /* 559 * IRQ processing is synchronous, interrupt status registers can be 560 * re-read. 561 */ 562 timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT); 563 while (time_before(jiffies, timeout) && !done) { 564 status = proc_pending_irqs(dev, &done); 565 if (status) 566 break; 567 } 568 569 return status; 570 } 571 EXPORT_SYMBOL(ath6kl_hif_intr_bh_handler); 572 573 static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev) 574 { 575 struct ath6kl_irq_enable_reg regs; 576 int status; 577 578 spin_lock_bh(&dev->lock); 579 580 /* Enable all but ATH6KL CPU interrupts */ 581 dev->irq_en_reg.int_status_en = 582 SM(INT_STATUS_ENABLE_ERROR, 0x01) | 583 SM(INT_STATUS_ENABLE_CPU, 0x01) | 584 SM(INT_STATUS_ENABLE_COUNTER, 0x01); 585 586 /* 587 * NOTE: There are some cases where HIF can do detection of 588 * pending mbox messages which is disabled now. 589 */ 590 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); 591 592 /* Set up the CPU Interrupt status Register */ 593 dev->irq_en_reg.cpu_int_status_en = 0; 594 595 /* Set up the Error Interrupt status Register */ 596 dev->irq_en_reg.err_int_status_en = 597 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | 598 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); 599 600 /* 601 * Enable Counter interrupt status register to get fatal errors for 602 * debugging. 603 */ 604 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, 605 ATH6KL_TARGET_DEBUG_INTR_MASK); 606 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 607 608 spin_unlock_bh(&dev->lock); 609 610 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 611 ®s.int_status_en, sizeof(regs), 612 HIF_WR_SYNC_BYTE_INC); 613 614 if (status) 615 ath6kl_err("failed to update interrupt ctl reg err: %d\n", 616 status); 617 618 return status; 619 } 620 621 int ath6kl_hif_disable_intrs(struct ath6kl_device *dev) 622 { 623 struct ath6kl_irq_enable_reg regs; 624 625 spin_lock_bh(&dev->lock); 626 /* Disable all interrupts */ 627 dev->irq_en_reg.int_status_en = 0; 628 dev->irq_en_reg.cpu_int_status_en = 0; 629 dev->irq_en_reg.err_int_status_en = 0; 630 dev->irq_en_reg.cntr_int_status_en = 0; 631 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); 632 spin_unlock_bh(&dev->lock); 633 634 return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, 635 ®s.int_status_en, sizeof(regs), 636 HIF_WR_SYNC_BYTE_INC); 637 } 638 639 /* enable device interrupts */ 640 int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev) 641 { 642 int status = 0; 643 644 /* 645 * Make sure interrupt are disabled before unmasking at the HIF 646 * layer. The rationale here is that between device insertion 647 * (where we clear the interrupts the first time) and when HTC 648 * is finally ready to handle interrupts, other software can perform 649 * target "soft" resets. The ATH6KL interrupt enables reset back to an 650 * "enabled" state when this happens. 651 */ 652 ath6kl_hif_disable_intrs(dev); 653 654 /* unmask the host controller interrupts */ 655 ath6kl_hif_irq_enable(dev->ar); 656 status = ath6kl_hif_enable_intrs(dev); 657 658 return status; 659 } 660 661 /* disable all device interrupts */ 662 int ath6kl_hif_mask_intrs(struct ath6kl_device *dev) 663 { 664 /* 665 * Mask the interrupt at the HIF layer to avoid any stray interrupt 666 * taken while we zero out our shadow registers in 667 * ath6kl_hif_disable_intrs(). 668 */ 669 ath6kl_hif_irq_disable(dev->ar); 670 671 return ath6kl_hif_disable_intrs(dev); 672 } 673 674 int ath6kl_hif_setup(struct ath6kl_device *dev) 675 { 676 int status = 0; 677 678 spin_lock_init(&dev->lock); 679 680 /* 681 * NOTE: we actually get the block size of a mailbox other than 0, 682 * for SDIO the block size on mailbox 0 is artificially set to 1. 683 * So we use the block size that is set for the other 3 mailboxes. 684 */ 685 dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size; 686 687 /* must be a power of 2 */ 688 if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) { 689 WARN_ON(1); 690 status = -EINVAL; 691 goto fail_setup; 692 } 693 694 /* assemble mask, used for padding to a block */ 695 dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1; 696 697 ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n", 698 dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr); 699 700 status = ath6kl_hif_disable_intrs(dev); 701 702 fail_setup: 703 return status; 704 705 } 706