1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 */ 21 22 /*****************************\ 23 Reset functions and helpers 24 \*****************************/ 25 26 #include <asm/unaligned.h> 27 28 #include <linux/pci.h> /* To determine if a card is pci-e */ 29 #include <linux/log2.h> 30 #include "ath5k.h" 31 #include "reg.h" 32 #include "base.h" 33 #include "debug.h" 34 35 /* 36 * Check if a register write has been completed 37 */ 38 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 39 bool is_set) 40 { 41 int i; 42 u32 data; 43 44 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 45 data = ath5k_hw_reg_read(ah, reg); 46 if (is_set && (data & flag)) 47 break; 48 else if ((data & flag) == val) 49 break; 50 udelay(15); 51 } 52 53 return (i <= 0) ? -EAGAIN : 0; 54 } 55 56 /** 57 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 58 * 59 * @ah: the &struct ath5k_hw 60 * @channel: the currently set channel upon reset 61 * 62 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 63 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset(). 64 * 65 * Since delta slope is floating point we split it on its exponent and 66 * mantissa and provide these values on hw. 67 * 68 * For more infos i think this patent is related 69 * http://www.freepatentsonline.com/7184495.html 70 */ 71 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 72 struct ieee80211_channel *channel) 73 { 74 /* Get exponent and mantissa and set it */ 75 u32 coef_scaled, coef_exp, coef_man, 76 ds_coef_exp, ds_coef_man, clock; 77 78 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 79 !(channel->hw_value & CHANNEL_OFDM)); 80 81 /* Get coefficient 82 * ALGO: coef = (5 * clock / carrier_freq) / 2 83 * we scale coef by shifting clock value by 24 for 84 * better precision since we use integers */ 85 /* TODO: Half/quarter rate */ 86 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40; 87 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 88 89 /* Get exponent 90 * ALGO: coef_exp = 14 - highest set bit position */ 91 coef_exp = ilog2(coef_scaled); 92 93 /* Doesn't make sense if it's zero*/ 94 if (!coef_scaled || !coef_exp) 95 return -EINVAL; 96 97 /* Note: we've shifted coef_scaled by 24 */ 98 coef_exp = 14 - (coef_exp - 24); 99 100 101 /* Get mantissa (significant digits) 102 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 103 coef_man = coef_scaled + 104 (1 << (24 - coef_exp - 1)); 105 106 /* Calculate delta slope coefficient exponent 107 * and mantissa (remove scaling) and set them on hw */ 108 ds_coef_man = coef_man >> (24 - coef_exp); 109 ds_coef_exp = coef_exp - 16; 110 111 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 112 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 113 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 114 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 115 116 return 0; 117 } 118 119 120 /* 121 * index into rates for control rates, we can set it up like this because 122 * this is only used for AR5212 and we know it supports G mode 123 */ 124 static const unsigned int control_rates[] = 125 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 }; 126 127 /** 128 * ath5k_hw_write_rate_duration - fill rate code to duration table 129 * 130 * @ah: the &struct ath5k_hw 131 * @mode: one of enum ath5k_driver_mode 132 * 133 * Write the rate code to duration table upon hw reset. This is a helper for 134 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on 135 * the hardware, based on current mode, for each rate. The rates which are 136 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 137 * different rate code so we write their value twice (one for long preample 138 * and one for short). 139 * 140 * Note: Band doesn't matter here, if we set the values for OFDM it works 141 * on both a and g modes. So all we have to do is set values for all g rates 142 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/ 143 * quarter rate mode, we need to use another set of bitrates (that's why we 144 * need the mode parameter) but we don't handle these proprietary modes yet. 145 */ 146 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, 147 unsigned int mode) 148 { 149 struct ath5k_softc *sc = ah->ah_sc; 150 struct ieee80211_rate *rate; 151 unsigned int i; 152 153 /* Write rate duration table */ 154 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) { 155 u32 reg; 156 u16 tx_time; 157 158 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]]; 159 160 /* Set ACK timeout */ 161 reg = AR5K_RATE_DUR(rate->hw_value); 162 163 /* An ACK frame consists of 10 bytes. If you add the FCS, 164 * which ieee80211_generic_frame_duration() adds, 165 * its 14 bytes. Note we use the control rate and not the 166 * actual rate for this rate. See mac80211 tx.c 167 * ieee80211_duration() for a brief description of 168 * what rate we should choose to TX ACKs. */ 169 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw, 170 sc->vif, 10, rate)); 171 172 ath5k_hw_reg_write(ah, tx_time, reg); 173 174 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 175 continue; 176 177 /* 178 * We're not distinguishing short preamble here, 179 * This is true, all we'll get is a longer value here 180 * which is not necessarilly bad. We could use 181 * export ieee80211_frame_duration() but that needs to be 182 * fixed first to be properly used by mac802111 drivers: 183 * 184 * - remove erp stuff and let the routine figure ofdm 185 * erp rates 186 * - remove passing argument ieee80211_local as 187 * drivers don't have access to it 188 * - move drivers using ieee80211_generic_frame_duration() 189 * to this 190 */ 191 ath5k_hw_reg_write(ah, tx_time, 192 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 193 } 194 } 195 196 /* 197 * Reset chipset 198 */ 199 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val) 200 { 201 int ret; 202 u32 mask = val ? val : ~0U; 203 204 ATH5K_TRACE(ah->ah_sc); 205 206 /* Read-and-clear RX Descriptor Pointer*/ 207 ath5k_hw_reg_read(ah, AR5K_RXDP); 208 209 /* 210 * Reset the device and wait until success 211 */ 212 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); 213 214 /* Wait at least 128 PCI clocks */ 215 udelay(15); 216 217 if (ah->ah_version == AR5K_AR5210) { 218 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 219 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 220 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA 221 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY; 222 } else { 223 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 224 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; 225 } 226 227 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false); 228 229 /* 230 * Reset configuration register (for hw byte-swap). Note that this 231 * is only set for big endian. We do the necessary magic in 232 * AR5K_INIT_CFG. 233 */ 234 if ((val & AR5K_RESET_CTL_PCU) == 0) 235 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); 236 237 return ret; 238 } 239 240 /* 241 * Sleep control 242 */ 243 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, 244 bool set_chip, u16 sleep_duration) 245 { 246 unsigned int i; 247 u32 staid, data; 248 249 ATH5K_TRACE(ah->ah_sc); 250 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); 251 252 switch (mode) { 253 case AR5K_PM_AUTO: 254 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; 255 /* fallthrough */ 256 case AR5K_PM_NETWORK_SLEEP: 257 if (set_chip) 258 ath5k_hw_reg_write(ah, 259 AR5K_SLEEP_CTL_SLE_ALLOW | 260 sleep_duration, 261 AR5K_SLEEP_CTL); 262 263 staid |= AR5K_STA_ID1_PWR_SV; 264 break; 265 266 case AR5K_PM_FULL_SLEEP: 267 if (set_chip) 268 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, 269 AR5K_SLEEP_CTL); 270 271 staid |= AR5K_STA_ID1_PWR_SV; 272 break; 273 274 case AR5K_PM_AWAKE: 275 276 staid &= ~AR5K_STA_ID1_PWR_SV; 277 278 if (!set_chip) 279 goto commit; 280 281 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL); 282 283 /* If card is down we 'll get 0xffff... so we 284 * need to clean this up before we write the register 285 */ 286 if (data & 0xffc00000) 287 data = 0; 288 else 289 /* Preserve sleep duration etc */ 290 data = data & ~AR5K_SLEEP_CTL_SLE; 291 292 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 293 AR5K_SLEEP_CTL); 294 udelay(15); 295 296 for (i = 200; i > 0; i--) { 297 /* Check if the chip did wake up */ 298 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & 299 AR5K_PCICFG_SPWR_DN) == 0) 300 break; 301 302 /* Wait a bit and retry */ 303 udelay(50); 304 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, 305 AR5K_SLEEP_CTL); 306 } 307 308 /* Fail if the chip didn't wake up */ 309 if (i == 0) 310 return -EIO; 311 312 break; 313 314 default: 315 return -EINVAL; 316 } 317 318 commit: 319 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1); 320 321 return 0; 322 } 323 324 /* 325 * Put device on hold 326 * 327 * Put MAC and Baseband on warm reset and 328 * keep that state (don't clean sleep control 329 * register). After this MAC and Baseband are 330 * disabled and a full reset is needed to come 331 * back. This way we save as much power as possible 332 * without puting the card on full sleep. 333 */ 334 int ath5k_hw_on_hold(struct ath5k_hw *ah) 335 { 336 struct pci_dev *pdev = ah->ah_sc->pdev; 337 u32 bus_flags; 338 int ret; 339 340 /* Make sure device is awake */ 341 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 342 if (ret) { 343 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 344 return ret; 345 } 346 347 /* 348 * Put chipset on warm reset... 349 * 350 * Note: puting PCI core on warm reset on PCI-E cards 351 * results card to hang and always return 0xffff... so 352 * we ingore that flag for PCI-E cards. On PCI cards 353 * this flag gets cleared after 64 PCI clocks. 354 */ 355 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 356 357 if (ah->ah_version == AR5K_AR5210) { 358 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 359 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 360 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 361 mdelay(2); 362 } else { 363 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 364 AR5K_RESET_CTL_BASEBAND | bus_flags); 365 } 366 367 if (ret) { 368 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n"); 369 return -EIO; 370 } 371 372 /* ...wakeup again!*/ 373 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 374 if (ret) { 375 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n"); 376 return ret; 377 } 378 379 return ret; 380 } 381 382 /* 383 * Bring up MAC + PHY Chips and program PLL 384 * TODO: Half/Quarter rate support 385 */ 386 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 387 { 388 struct pci_dev *pdev = ah->ah_sc->pdev; 389 u32 turbo, mode, clock, bus_flags; 390 int ret; 391 392 turbo = 0; 393 mode = 0; 394 clock = 0; 395 396 ATH5K_TRACE(ah->ah_sc); 397 398 /* Wakeup the device */ 399 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 400 if (ret) { 401 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 402 return ret; 403 } 404 405 /* 406 * Put chipset on warm reset... 407 * 408 * Note: puting PCI core on warm reset on PCI-E cards 409 * results card to hang and always return 0xffff... so 410 * we ingore that flag for PCI-E cards. On PCI cards 411 * this flag gets cleared after 64 PCI clocks. 412 */ 413 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; 414 415 if (ah->ah_version == AR5K_AR5210) { 416 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 417 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 418 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 419 mdelay(2); 420 } else { 421 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 422 AR5K_RESET_CTL_BASEBAND | bus_flags); 423 } 424 425 if (ret) { 426 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n"); 427 return -EIO; 428 } 429 430 /* ...wakeup again!...*/ 431 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 432 if (ret) { 433 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n"); 434 return ret; 435 } 436 437 /* ...clear reset control register and pull device out of 438 * warm reset */ 439 if (ath5k_hw_nic_reset(ah, 0)) { 440 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n"); 441 return -EIO; 442 } 443 444 /* On initialization skip PLL programming since we don't have 445 * a channel / mode set yet */ 446 if (initial) 447 return 0; 448 449 if (ah->ah_version != AR5K_AR5210) { 450 /* 451 * Get channel mode flags 452 */ 453 454 if (ah->ah_radio >= AR5K_RF5112) { 455 mode = AR5K_PHY_MODE_RAD_RF5112; 456 clock = AR5K_PHY_PLL_RF5112; 457 } else { 458 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ 459 clock = AR5K_PHY_PLL_RF5111; /*Zero*/ 460 } 461 462 if (flags & CHANNEL_2GHZ) { 463 mode |= AR5K_PHY_MODE_FREQ_2GHZ; 464 clock |= AR5K_PHY_PLL_44MHZ; 465 466 if (flags & CHANNEL_CCK) { 467 mode |= AR5K_PHY_MODE_MOD_CCK; 468 } else if (flags & CHANNEL_OFDM) { 469 /* XXX Dynamic OFDM/CCK is not supported by the 470 * AR5211 so we set MOD_OFDM for plain g (no 471 * CCK headers) operation. We need to test 472 * this, 5211 might support ofdm-only g after 473 * all, there are also initial register values 474 * in the code for g mode (see initvals.c). */ 475 if (ah->ah_version == AR5K_AR5211) 476 mode |= AR5K_PHY_MODE_MOD_OFDM; 477 else 478 mode |= AR5K_PHY_MODE_MOD_DYN; 479 } else { 480 ATH5K_ERR(ah->ah_sc, 481 "invalid radio modulation mode\n"); 482 return -EINVAL; 483 } 484 } else if (flags & CHANNEL_5GHZ) { 485 mode |= AR5K_PHY_MODE_FREQ_5GHZ; 486 487 if (ah->ah_radio == AR5K_RF5413) 488 clock = AR5K_PHY_PLL_40MHZ_5413; 489 else 490 clock |= AR5K_PHY_PLL_40MHZ; 491 492 if (flags & CHANNEL_OFDM) 493 mode |= AR5K_PHY_MODE_MOD_OFDM; 494 else { 495 ATH5K_ERR(ah->ah_sc, 496 "invalid radio modulation mode\n"); 497 return -EINVAL; 498 } 499 } else { 500 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n"); 501 return -EINVAL; 502 } 503 504 if (flags & CHANNEL_TURBO) 505 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; 506 } else { /* Reset the device */ 507 508 /* ...enable Atheros turbo mode if requested */ 509 if (flags & CHANNEL_TURBO) 510 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, 511 AR5K_PHY_TURBO); 512 } 513 514 if (ah->ah_version != AR5K_AR5210) { 515 516 /* ...update PLL if needed */ 517 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) { 518 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); 519 udelay(300); 520 } 521 522 /* ...set the PHY operating mode */ 523 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); 524 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); 525 } 526 527 return 0; 528 } 529 530 /* 531 * If there is an external 32KHz crystal available, use it 532 * as ref. clock instead of 32/40MHz clock and baseband clocks 533 * to save power during sleep or restore normal 32/40MHz 534 * operation. 535 * 536 * XXX: When operating on 32KHz certain PHY registers (27 - 31, 537 * 123 - 127) require delay on access. 538 */ 539 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) 540 { 541 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 542 u32 scal, spending, usec32; 543 544 /* Only set 32KHz settings if we have an external 545 * 32KHz crystal present */ 546 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) || 547 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) && 548 enable) { 549 550 /* 1 usec/cycle */ 551 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1); 552 /* Set up tsf increment on each cycle */ 553 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61); 554 555 /* Set baseband sleep control registers 556 * and sleep control rate */ 557 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 558 559 if ((ah->ah_radio == AR5K_RF5112) || 560 (ah->ah_radio == AR5K_RF5413) || 561 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 562 spending = 0x14; 563 else 564 spending = 0x18; 565 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 566 567 if ((ah->ah_radio == AR5K_RF5112) || 568 (ah->ah_radio == AR5K_RF5413) || 569 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 570 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); 571 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL); 572 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK); 573 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY); 574 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 575 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02); 576 } else { 577 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); 578 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL); 579 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK); 580 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY); 581 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 582 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03); 583 } 584 585 /* Enable sleep clock operation */ 586 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, 587 AR5K_PCICFG_SLEEP_CLOCK_EN); 588 589 } else { 590 591 /* Disable sleep clock operation and 592 * restore default parameters */ 593 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, 594 AR5K_PCICFG_SLEEP_CLOCK_EN); 595 596 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG, 597 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0); 598 599 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); 600 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); 601 602 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 603 scal = AR5K_PHY_SCAL_32MHZ_2417; 604 else if (ee->ee_is_hb63) 605 scal = AR5K_PHY_SCAL_32MHZ_HB63; 606 else 607 scal = AR5K_PHY_SCAL_32MHZ; 608 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 609 610 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); 611 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); 612 613 if ((ah->ah_radio == AR5K_RF5112) || 614 (ah->ah_radio == AR5K_RF5413) || 615 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 616 spending = 0x14; 617 else 618 spending = 0x18; 619 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); 620 621 if ((ah->ah_radio == AR5K_RF5112) || 622 (ah->ah_radio == AR5K_RF5413)) 623 usec32 = 39; 624 else 625 usec32 = 31; 626 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32); 627 628 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1); 629 } 630 } 631 632 /* TODO: Half/Quarter rate */ 633 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, 634 struct ieee80211_channel *channel) 635 { 636 if (ah->ah_version == AR5K_AR5212 && 637 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 638 639 /* Setup ADC control */ 640 ath5k_hw_reg_write(ah, 641 (AR5K_REG_SM(2, 642 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) | 643 AR5K_REG_SM(2, 644 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) | 645 AR5K_PHY_ADC_CTL_PWD_DAC_OFF | 646 AR5K_PHY_ADC_CTL_PWD_ADC_OFF), 647 AR5K_PHY_ADC_CTL); 648 649 650 651 /* Disable barker RSSI threshold */ 652 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 653 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR); 654 655 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL, 656 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2); 657 658 /* Set the mute mask */ 659 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); 660 } 661 662 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */ 663 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B) 664 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH); 665 666 /* Enable DCU double buffering */ 667 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B) 668 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 669 AR5K_TXCFG_DCU_DBL_BUF_DIS); 670 671 /* Set DAC/ADC delays */ 672 if (ah->ah_version == AR5K_AR5212) { 673 u32 scal; 674 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 675 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)) 676 scal = AR5K_PHY_SCAL_32MHZ_2417; 677 else if (ee->ee_is_hb63) 678 scal = AR5K_PHY_SCAL_32MHZ_HB63; 679 else 680 scal = AR5K_PHY_SCAL_32MHZ; 681 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); 682 } 683 684 /* Set fast ADC */ 685 if ((ah->ah_radio == AR5K_RF5413) || 686 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) { 687 u32 fast_adc = true; 688 689 if (channel->center_freq == 2462 || 690 channel->center_freq == 2467) 691 fast_adc = 0; 692 693 /* Only update if needed */ 694 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc) 695 ath5k_hw_reg_write(ah, fast_adc, 696 AR5K_PHY_FAST_ADC); 697 } 698 699 /* Fix for first revision of the RF5112 RF chipset */ 700 if (ah->ah_radio == AR5K_RF5112 && 701 ah->ah_radio_5ghz_revision < 702 AR5K_SREV_RAD_5112A) { 703 u32 data; 704 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, 705 AR5K_PHY_CCKTXCTL); 706 if (channel->hw_value & CHANNEL_5GHZ) 707 data = 0xffb81020; 708 else 709 data = 0xffb80d20; 710 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); 711 } 712 713 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 714 u32 usec_reg; 715 /* 5311 has different tx/rx latency masks 716 * from 5211, since we deal 5311 the same 717 * as 5211 when setting initvals, shift 718 * values here to their proper locations */ 719 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211); 720 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 | 721 AR5K_USEC_32 | 722 AR5K_USEC_TX_LATENCY_5211 | 723 AR5K_REG_SM(29, 724 AR5K_USEC_RX_LATENCY_5210)), 725 AR5K_USEC_5211); 726 /* Clear QCU/DCU clock gating register */ 727 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); 728 /* Set DAC/ADC delays */ 729 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL); 730 /* Enable PCU FIFO corruption ECO */ 731 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 732 AR5K_DIAG_SW_ECO_ENABLE); 733 } 734 } 735 736 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah, 737 struct ieee80211_channel *channel, u8 *ant, u8 ee_mode) 738 { 739 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 740 s16 cck_ofdm_pwr_delta; 741 742 /* Adjust power delta for channel 14 */ 743 if (channel->center_freq == 2484) 744 cck_ofdm_pwr_delta = 745 ((ee->ee_cck_ofdm_power_delta - 746 ee->ee_scaled_cck_delta) * 2) / 10; 747 else 748 cck_ofdm_pwr_delta = 749 (ee->ee_cck_ofdm_power_delta * 2) / 10; 750 751 /* Set CCK to OFDM power delta on tx power 752 * adjustment register */ 753 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 754 if (channel->hw_value == CHANNEL_G) 755 ath5k_hw_reg_write(ah, 756 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1), 757 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) | 758 AR5K_REG_SM((cck_ofdm_pwr_delta * -1), 759 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX), 760 AR5K_PHY_TX_PWR_ADJ); 761 else 762 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ); 763 } else { 764 /* For older revs we scale power on sw during tx power 765 * setup */ 766 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta; 767 ah->ah_txpower.txp_cck_ofdm_gainf_delta = 768 ee->ee_cck_ofdm_gain_delta; 769 } 770 771 /* Set antenna idle switch table */ 772 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 773 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 774 (ah->ah_ant_ctl[ee_mode][0] | 775 AR5K_PHY_ANT_CTL_TXRX_EN)); 776 777 /* Set antenna switch tables */ 778 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[0]], 779 AR5K_PHY_ANT_SWITCH_TABLE_0); 780 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[1]], 781 AR5K_PHY_ANT_SWITCH_TABLE_1); 782 783 /* Noise floor threshold */ 784 ath5k_hw_reg_write(ah, 785 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), 786 AR5K_PHY_NFTHRES); 787 788 if ((channel->hw_value & CHANNEL_TURBO) && 789 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) { 790 /* Switch settling time (Turbo) */ 791 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 792 AR5K_PHY_SETTLING_SWITCH, 793 ee->ee_switch_settling_turbo[ee_mode]); 794 795 /* Tx/Rx attenuation (Turbo) */ 796 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 797 AR5K_PHY_GAIN_TXRX_ATTEN, 798 ee->ee_atn_tx_rx_turbo[ee_mode]); 799 800 /* ADC/PGA desired size (Turbo) */ 801 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 802 AR5K_PHY_DESIRED_SIZE_ADC, 803 ee->ee_adc_desired_size_turbo[ee_mode]); 804 805 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 806 AR5K_PHY_DESIRED_SIZE_PGA, 807 ee->ee_pga_desired_size_turbo[ee_mode]); 808 809 /* Tx/Rx margin (Turbo) */ 810 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 811 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 812 ee->ee_margin_tx_rx_turbo[ee_mode]); 813 814 } else { 815 /* Switch settling time */ 816 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING, 817 AR5K_PHY_SETTLING_SWITCH, 818 ee->ee_switch_settling[ee_mode]); 819 820 /* Tx/Rx attenuation */ 821 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN, 822 AR5K_PHY_GAIN_TXRX_ATTEN, 823 ee->ee_atn_tx_rx[ee_mode]); 824 825 /* ADC/PGA desired size */ 826 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 827 AR5K_PHY_DESIRED_SIZE_ADC, 828 ee->ee_adc_desired_size[ee_mode]); 829 830 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 831 AR5K_PHY_DESIRED_SIZE_PGA, 832 ee->ee_pga_desired_size[ee_mode]); 833 834 /* Tx/Rx margin */ 835 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) 836 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ, 837 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, 838 ee->ee_margin_tx_rx[ee_mode]); 839 } 840 841 /* XPA delays */ 842 ath5k_hw_reg_write(ah, 843 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | 844 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | 845 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | 846 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4); 847 848 /* XLNA delay */ 849 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3, 850 AR5K_PHY_RF_CTL3_TXE2XLNA_ON, 851 ee->ee_tx_end2xlna_enable[ee_mode]); 852 853 /* Thresh64 (ANI) */ 854 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF, 855 AR5K_PHY_NF_THRESH62, 856 ee->ee_thr_62[ee_mode]); 857 858 859 /* False detect backoff for channels 860 * that have spur noise. Write the new 861 * cyclic power RSSI threshold. */ 862 if (ath5k_hw_chan_has_spur_noise(ah, channel)) 863 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 864 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 865 AR5K_INIT_CYCRSSI_THR1 + 866 ee->ee_false_detect[ee_mode]); 867 else 868 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 869 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, 870 AR5K_INIT_CYCRSSI_THR1); 871 872 /* I/Q correction (set enable bit last to match HAL sources) */ 873 /* TODO: Per channel i/q infos ? */ 874 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 875 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, 876 ee->ee_i_cal[ee_mode]); 877 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, 878 ee->ee_q_cal[ee_mode]); 879 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 880 } 881 882 /* Heavy clipping -disable for now */ 883 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1) 884 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE); 885 } 886 887 /* 888 * Main reset function 889 */ 890 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 891 struct ieee80211_channel *channel, bool change_channel) 892 { 893 struct ath_common *common = ath5k_hw_common(ah); 894 u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo; 895 u32 phy_tst1; 896 u8 mode, freq, ee_mode, ant[2]; 897 int i, ret; 898 899 ATH5K_TRACE(ah->ah_sc); 900 901 s_ant = 0; 902 ee_mode = 0; 903 staid1_flags = 0; 904 tsf_up = 0; 905 tsf_lo = 0; 906 freq = 0; 907 mode = 0; 908 909 /* 910 * Save some registers before a reset 911 */ 912 /*DCU/Antenna selection not available on 5210*/ 913 if (ah->ah_version != AR5K_AR5210) { 914 915 switch (channel->hw_value & CHANNEL_MODES) { 916 case CHANNEL_A: 917 mode = AR5K_MODE_11A; 918 freq = AR5K_INI_RFGAIN_5GHZ; 919 ee_mode = AR5K_EEPROM_MODE_11A; 920 break; 921 case CHANNEL_G: 922 mode = AR5K_MODE_11G; 923 freq = AR5K_INI_RFGAIN_2GHZ; 924 ee_mode = AR5K_EEPROM_MODE_11G; 925 break; 926 case CHANNEL_B: 927 mode = AR5K_MODE_11B; 928 freq = AR5K_INI_RFGAIN_2GHZ; 929 ee_mode = AR5K_EEPROM_MODE_11B; 930 break; 931 case CHANNEL_T: 932 mode = AR5K_MODE_11A_TURBO; 933 freq = AR5K_INI_RFGAIN_5GHZ; 934 ee_mode = AR5K_EEPROM_MODE_11A; 935 break; 936 case CHANNEL_TG: 937 if (ah->ah_version == AR5K_AR5211) { 938 ATH5K_ERR(ah->ah_sc, 939 "TurboG mode not available on 5211"); 940 return -EINVAL; 941 } 942 mode = AR5K_MODE_11G_TURBO; 943 freq = AR5K_INI_RFGAIN_2GHZ; 944 ee_mode = AR5K_EEPROM_MODE_11G; 945 break; 946 case CHANNEL_XR: 947 if (ah->ah_version == AR5K_AR5211) { 948 ATH5K_ERR(ah->ah_sc, 949 "XR mode not available on 5211"); 950 return -EINVAL; 951 } 952 mode = AR5K_MODE_XR; 953 freq = AR5K_INI_RFGAIN_5GHZ; 954 ee_mode = AR5K_EEPROM_MODE_11A; 955 break; 956 default: 957 ATH5K_ERR(ah->ah_sc, 958 "invalid channel: %d\n", channel->center_freq); 959 return -EINVAL; 960 } 961 962 if (change_channel) { 963 /* 964 * Save frame sequence count 965 * For revs. after Oahu, only save 966 * seq num for DCU 0 (Global seq num) 967 */ 968 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 969 970 for (i = 0; i < 10; i++) 971 s_seq[i] = ath5k_hw_reg_read(ah, 972 AR5K_QUEUE_DCU_SEQNUM(i)); 973 974 } else { 975 s_seq[0] = ath5k_hw_reg_read(ah, 976 AR5K_QUEUE_DCU_SEQNUM(0)); 977 } 978 979 /* TSF accelerates on AR5211 durring reset 980 * As a workaround save it here and restore 981 * it later so that it's back in time after 982 * reset. This way it'll get re-synced on the 983 * next beacon without breaking ad-hoc. 984 * 985 * On AR5212 TSF is almost preserved across a 986 * reset so it stays back in time anyway and 987 * we don't have to save/restore it. 988 * 989 * XXX: Since this breaks power saving we have 990 * to disable power saving until we receive the 991 * next beacon, so we can resync beacon timers */ 992 if (ah->ah_version == AR5K_AR5211) { 993 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 994 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 995 } 996 } 997 998 /* Save default antenna */ 999 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); 1000 1001 if (ah->ah_version == AR5K_AR5212) { 1002 /* Restore normal 32/40MHz clock operation 1003 * to avoid register access delay on certain 1004 * PHY registers */ 1005 ath5k_hw_set_sleep_clock(ah, false); 1006 1007 /* Since we are going to write rf buffer 1008 * check if we have any pending gain_F 1009 * optimization settings */ 1010 if (change_channel && ah->ah_rf_banks != NULL) 1011 ath5k_hw_gainf_calibrate(ah); 1012 } 1013 } 1014 1015 /*GPIOs*/ 1016 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & 1017 AR5K_PCICFG_LEDSTATE; 1018 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 1019 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 1020 1021 /* AR5K_STA_ID1 flags, only preserve antenna 1022 * settings and ack/cts rate mode */ 1023 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 1024 (AR5K_STA_ID1_DEFAULT_ANTENNA | 1025 AR5K_STA_ID1_DESC_ANTENNA | 1026 AR5K_STA_ID1_RTS_DEF_ANTENNA | 1027 AR5K_STA_ID1_ACKCTS_6MB | 1028 AR5K_STA_ID1_BASE_RATE_11B | 1029 AR5K_STA_ID1_SELFGEN_DEF_ANT); 1030 1031 /* Wakeup the device */ 1032 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false); 1033 if (ret) 1034 return ret; 1035 1036 /* PHY access enable */ 1037 if (ah->ah_mac_srev >= AR5K_SREV_AR5211) 1038 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 1039 else 1040 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40, 1041 AR5K_PHY(0)); 1042 1043 /* Write initial settings */ 1044 ret = ath5k_hw_write_initvals(ah, mode, change_channel); 1045 if (ret) 1046 return ret; 1047 1048 /* 1049 * 5211/5212 Specific 1050 */ 1051 if (ah->ah_version != AR5K_AR5210) { 1052 1053 /* 1054 * Write initial RF gain settings 1055 * This should work for both 5111/5112 1056 */ 1057 ret = ath5k_hw_rfgain_init(ah, freq); 1058 if (ret) 1059 return ret; 1060 1061 mdelay(1); 1062 1063 /* 1064 * Tweak initval settings for revised 1065 * chipsets and add some more config 1066 * bits 1067 */ 1068 ath5k_hw_tweak_initval_settings(ah, channel); 1069 1070 /* 1071 * Set TX power 1072 */ 1073 ret = ath5k_hw_txpower(ah, channel, ee_mode, 1074 ah->ah_txpower.txp_max_pwr / 2); 1075 if (ret) 1076 return ret; 1077 1078 /* Write rate duration table only on AR5212 and if 1079 * virtual interface has already been brought up 1080 * XXX: rethink this after new mode changes to 1081 * mac80211 are integrated */ 1082 if (ah->ah_version == AR5K_AR5212 && 1083 ah->ah_sc->vif != NULL) 1084 ath5k_hw_write_rate_duration(ah, mode); 1085 1086 /* 1087 * Write RF buffer 1088 */ 1089 ret = ath5k_hw_rfregs_init(ah, channel, mode); 1090 if (ret) 1091 return ret; 1092 1093 1094 /* Write OFDM timings on 5212*/ 1095 if (ah->ah_version == AR5K_AR5212 && 1096 channel->hw_value & CHANNEL_OFDM) { 1097 struct ath5k_eeprom_info *ee = 1098 &ah->ah_capabilities.cap_eeprom; 1099 1100 ret = ath5k_hw_write_ofdm_timings(ah, channel); 1101 if (ret) 1102 return ret; 1103 1104 /* Note: According to docs we can have a newer 1105 * EEPROM on old hardware, so we need to verify 1106 * that our hardware is new enough to have spur 1107 * mitigation registers (delta phase etc) */ 1108 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 || 1109 (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1110 ee->ee_version >= AR5K_EEPROM_VERSION_5_3)) 1111 ath5k_hw_set_spur_mitigation_filter(ah, 1112 channel); 1113 } 1114 1115 /*Enable/disable 802.11b mode on 5111 1116 (enable 2111 frequency converter + CCK)*/ 1117 if (ah->ah_radio == AR5K_RF5111) { 1118 if (mode == AR5K_MODE_11B) 1119 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 1120 AR5K_TXCFG_B_MODE); 1121 else 1122 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 1123 AR5K_TXCFG_B_MODE); 1124 } 1125 1126 /* 1127 * In case a fixed antenna was set as default 1128 * use the same switch table twice. 1129 */ 1130 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1131 ant[0] = ant[1] = AR5K_ANT_SWTABLE_A; 1132 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1133 ant[0] = ant[1] = AR5K_ANT_SWTABLE_B; 1134 else { 1135 ant[0] = AR5K_ANT_SWTABLE_A; 1136 ant[1] = AR5K_ANT_SWTABLE_B; 1137 } 1138 1139 /* Commit values from EEPROM */ 1140 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode); 1141 1142 } else { 1143 /* 1144 * For 5210 we do all initialization using 1145 * initvals, so we don't have to modify 1146 * any settings (5210 also only supports 1147 * a/aturbo modes) 1148 */ 1149 mdelay(1); 1150 /* Disable phy and wait */ 1151 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 1152 mdelay(1); 1153 } 1154 1155 /* 1156 * Restore saved values 1157 */ 1158 1159 /*DCU/Antenna selection not available on 5210*/ 1160 if (ah->ah_version != AR5K_AR5210) { 1161 1162 if (change_channel) { 1163 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 1164 for (i = 0; i < 10; i++) 1165 ath5k_hw_reg_write(ah, s_seq[i], 1166 AR5K_QUEUE_DCU_SEQNUM(i)); 1167 } else { 1168 ath5k_hw_reg_write(ah, s_seq[0], 1169 AR5K_QUEUE_DCU_SEQNUM(0)); 1170 } 1171 1172 1173 if (ah->ah_version == AR5K_AR5211) { 1174 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32); 1175 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32); 1176 } 1177 } 1178 1179 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA); 1180 } 1181 1182 /* Ledstate */ 1183 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]); 1184 1185 /* Gpio settings */ 1186 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); 1187 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); 1188 1189 /* Restore sta_id flags and preserve our mac address*/ 1190 ath5k_hw_reg_write(ah, 1191 get_unaligned_le32(common->macaddr), 1192 AR5K_STA_ID0); 1193 ath5k_hw_reg_write(ah, 1194 staid1_flags | get_unaligned_le16(common->macaddr + 4), 1195 AR5K_STA_ID1); 1196 1197 1198 /* 1199 * Configure PCU 1200 */ 1201 1202 /* Restore bssid and bssid mask */ 1203 ath5k_hw_set_associd(ah); 1204 1205 /* Set PCU config */ 1206 ath5k_hw_set_opmode(ah, op_mode); 1207 1208 /* Clear any pending interrupts 1209 * PISR/SISR Not available on 5210 */ 1210 if (ah->ah_version != AR5K_AR5210) 1211 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); 1212 1213 /* Set RSSI/BRSSI thresholds 1214 * 1215 * Note: If we decide to set this value 1216 * dynamicaly, have in mind that when AR5K_RSSI_THR 1217 * register is read it might return 0x40 if we haven't 1218 * wrote anything to it plus BMISS RSSI threshold is zeroed. 1219 * So doing a save/restore procedure here isn't the right 1220 * choice. Instead store it on ath5k_hw */ 1221 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 1222 AR5K_TUNE_BMISS_THRES << 1223 AR5K_RSSI_THR_BMISS_S), 1224 AR5K_RSSI_THR); 1225 1226 /* MIC QoS support */ 1227 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 1228 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 1229 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 1230 } 1231 1232 /* QoS NOACK Policy */ 1233 if (ah->ah_version == AR5K_AR5212) { 1234 ath5k_hw_reg_write(ah, 1235 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 1236 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 1237 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 1238 AR5K_QOS_NOACK); 1239 } 1240 1241 1242 /* 1243 * Configure PHY 1244 */ 1245 1246 /* Set channel on PHY */ 1247 ret = ath5k_hw_channel(ah, channel); 1248 if (ret) 1249 return ret; 1250 1251 /* 1252 * Enable the PHY and wait until completion 1253 * This includes BaseBand and Synthesizer 1254 * activation. 1255 */ 1256 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1257 1258 /* 1259 * On 5211+ read activation -> rx delay 1260 * and use it. 1261 * 1262 * TODO: Half/quarter rate support 1263 */ 1264 if (ah->ah_version != AR5K_AR5210) { 1265 u32 delay; 1266 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 1267 AR5K_PHY_RX_DELAY_M; 1268 delay = (channel->hw_value & CHANNEL_CCK) ? 1269 ((delay << 2) / 22) : (delay / 10); 1270 1271 udelay(100 + (2 * delay)); 1272 } else { 1273 mdelay(1); 1274 } 1275 1276 /* 1277 * Perform ADC test to see if baseband is ready 1278 * Set tx hold and check adc test register 1279 */ 1280 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 1281 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 1282 for (i = 0; i <= 20; i++) { 1283 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 1284 break; 1285 udelay(200); 1286 } 1287 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 1288 1289 /* 1290 * Start automatic gain control calibration 1291 * 1292 * During AGC calibration RX path is re-routed to 1293 * a power detector so we don't receive anything. 1294 * 1295 * This method is used to calibrate some static offsets 1296 * used together with on-the fly I/Q calibration (the 1297 * one performed via ath5k_hw_phy_calibrate), that doesn't 1298 * interrupt rx path. 1299 * 1300 * While rx path is re-routed to the power detector we also 1301 * start a noise floor calibration, to measure the 1302 * card's noise floor (the noise we measure when we are not 1303 * transmiting or receiving anything). 1304 * 1305 * If we are in a noisy environment AGC calibration may time 1306 * out and/or noise floor calibration might timeout. 1307 */ 1308 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1309 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 1310 1311 /* At the same time start I/Q calibration for QAM constellation 1312 * -no need for CCK- */ 1313 ah->ah_calibration = false; 1314 if (!(mode == AR5K_MODE_11B)) { 1315 ah->ah_calibration = true; 1316 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1317 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1318 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1319 AR5K_PHY_IQ_RUN); 1320 } 1321 1322 /* Wait for gain calibration to finish (we check for I/Q calibration 1323 * during ath5k_phy_calibrate) */ 1324 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1325 AR5K_PHY_AGCCTL_CAL, 0, false)) { 1326 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 1327 channel->center_freq); 1328 } 1329 1330 /* Restore antenna mode */ 1331 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 1332 1333 /* Restore slot time and ACK timeouts */ 1334 if (ah->ah_coverage_class > 0) 1335 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 1336 1337 /* 1338 * Configure QCUs/DCUs 1339 */ 1340 1341 /* TODO: HW Compression support for data queues */ 1342 /* TODO: Burst prefetch for data queues */ 1343 1344 /* 1345 * Reset queues and start beacon timers at the end of the reset routine 1346 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping 1347 * Note: If we want we can assign multiple qcus on one dcu. 1348 */ 1349 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) { 1350 ret = ath5k_hw_reset_tx_queue(ah, i); 1351 if (ret) { 1352 ATH5K_ERR(ah->ah_sc, 1353 "failed to reset TX queue #%d\n", i); 1354 return ret; 1355 } 1356 } 1357 1358 1359 /* 1360 * Configure DMA/Interrupts 1361 */ 1362 1363 /* 1364 * Set Rx/Tx DMA Configuration 1365 * 1366 * Set standard DMA size (128). Note that 1367 * a DMA size of 512 causes rx overruns and tx errors 1368 * on pci-e cards (tested on 5424 but since rx overruns 1369 * also occur on 5416/5418 with madwifi we set 128 1370 * for all PCI-E cards to be safe). 1371 * 1372 * XXX: need to check 5210 for this 1373 * TODO: Check out tx triger level, it's always 64 on dumps but I 1374 * guess we can tweak it and see how it goes ;-) 1375 */ 1376 if (ah->ah_version != AR5K_AR5210) { 1377 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 1378 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); 1379 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, 1380 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); 1381 } 1382 1383 /* Pre-enable interrupts on 5211/5212*/ 1384 if (ah->ah_version != AR5K_AR5210) 1385 ath5k_hw_set_imr(ah, ah->ah_imr); 1386 1387 /* Enable 32KHz clock function for AR5212+ chips 1388 * Set clocks to 32KHz operation and use an 1389 * external 32KHz crystal when sleeping if one 1390 * exists */ 1391 if (ah->ah_version == AR5K_AR5212 && 1392 op_mode != NL80211_IFTYPE_AP) 1393 ath5k_hw_set_sleep_clock(ah, true); 1394 1395 /* 1396 * Disable beacons and reset the TSF 1397 */ 1398 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE); 1399 ath5k_hw_reset_tsf(ah); 1400 return 0; 1401 } 1402