1 /* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/slab.h> 25 #include <asm/unaligned.h> 26 27 #include "ath5k.h" 28 #include "reg.h" 29 #include "rfbuffer.h" 30 #include "rfgain.h" 31 #include "../regd.h" 32 33 34 /******************\ 35 * Helper functions * 36 \******************/ 37 38 /* 39 * Get the PHY Chip revision 40 */ 41 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) 42 { 43 unsigned int i; 44 u32 srev; 45 u16 ret; 46 47 /* 48 * Set the radio chip access register 49 */ 50 switch (band) { 51 case IEEE80211_BAND_2GHZ: 52 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 53 break; 54 case IEEE80211_BAND_5GHZ: 55 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 56 break; 57 default: 58 return 0; 59 } 60 61 mdelay(2); 62 63 /* ...wait until PHY is ready and read the selected radio revision */ 64 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 65 66 for (i = 0; i < 8; i++) 67 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 68 69 if (ah->ah_version == AR5K_AR5210) { 70 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 71 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 72 } else { 73 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 74 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 75 ((srev & 0x0f) << 4), 8); 76 } 77 78 /* Reset to the 5GHz mode */ 79 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 80 81 return ret; 82 } 83 84 /* 85 * Check if a channel is supported 86 */ 87 bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) 88 { 89 u16 freq = channel->center_freq; 90 91 /* Check if the channel is in our supported range */ 92 if (channel->band == IEEE80211_BAND_2GHZ) { 93 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 94 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 95 return true; 96 } else if (channel->band == IEEE80211_BAND_5GHZ) 97 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 98 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 99 return true; 100 101 return false; 102 } 103 104 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 105 struct ieee80211_channel *channel) 106 { 107 u8 refclk_freq; 108 109 if ((ah->ah_radio == AR5K_RF5112) || 110 (ah->ah_radio == AR5K_RF5413) || 111 (ah->ah_radio == AR5K_RF2413) || 112 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 113 refclk_freq = 40; 114 else 115 refclk_freq = 32; 116 117 if ((channel->center_freq % refclk_freq != 0) && 118 ((channel->center_freq % refclk_freq < 10) || 119 (channel->center_freq % refclk_freq > 22))) 120 return true; 121 else 122 return false; 123 } 124 125 /* 126 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 127 */ 128 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 129 const struct ath5k_rf_reg *rf_regs, 130 u32 val, u8 reg_id, bool set) 131 { 132 const struct ath5k_rf_reg *rfreg = NULL; 133 u8 offset, bank, num_bits, col, position; 134 u16 entry; 135 u32 mask, data, last_bit, bits_shifted, first_bit; 136 u32 *rfb; 137 s32 bits_left; 138 int i; 139 140 data = 0; 141 rfb = ah->ah_rf_banks; 142 143 for (i = 0; i < ah->ah_rf_regs_count; i++) { 144 if (rf_regs[i].index == reg_id) { 145 rfreg = &rf_regs[i]; 146 break; 147 } 148 } 149 150 if (rfb == NULL || rfreg == NULL) { 151 ATH5K_PRINTF("Rf register not found!\n"); 152 /* should not happen */ 153 return 0; 154 } 155 156 bank = rfreg->bank; 157 num_bits = rfreg->field.len; 158 first_bit = rfreg->field.pos; 159 col = rfreg->field.col; 160 161 /* first_bit is an offset from bank's 162 * start. Since we have all banks on 163 * the same array, we use this offset 164 * to mark each bank's start */ 165 offset = ah->ah_offset[bank]; 166 167 /* Boundary check */ 168 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 169 ATH5K_PRINTF("invalid values at offset %u\n", offset); 170 return 0; 171 } 172 173 entry = ((first_bit - 1) / 8) + offset; 174 position = (first_bit - 1) % 8; 175 176 if (set) 177 data = ath5k_hw_bitswap(val, num_bits); 178 179 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 180 position = 0, entry++) { 181 182 last_bit = (position + bits_left > 8) ? 8 : 183 position + bits_left; 184 185 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 186 (col * 8); 187 188 if (set) { 189 rfb[entry] &= ~mask; 190 rfb[entry] |= ((data << position) << (col * 8)) & mask; 191 data >>= (8 - position); 192 } else { 193 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 194 << bits_shifted; 195 bits_shifted += last_bit - position; 196 } 197 198 bits_left -= 8 - position; 199 } 200 201 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 202 203 return data; 204 } 205 206 /** 207 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 208 * 209 * @ah: the &struct ath5k_hw 210 * @channel: the currently set channel upon reset 211 * 212 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 213 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 214 * 215 * Since delta slope is floating point we split it on its exponent and 216 * mantissa and provide these values on hw. 217 * 218 * For more infos i think this patent is related 219 * http://www.freepatentsonline.com/7184495.html 220 */ 221 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 222 struct ieee80211_channel *channel) 223 { 224 /* Get exponent and mantissa and set it */ 225 u32 coef_scaled, coef_exp, coef_man, 226 ds_coef_exp, ds_coef_man, clock; 227 228 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 229 (channel->hw_value == AR5K_MODE_11B)); 230 231 /* Get coefficient 232 * ALGO: coef = (5 * clock / carrier_freq) / 2 233 * we scale coef by shifting clock value by 24 for 234 * better precision since we use integers */ 235 switch (ah->ah_bwmode) { 236 case AR5K_BWMODE_40MHZ: 237 clock = 40 * 2; 238 break; 239 case AR5K_BWMODE_10MHZ: 240 clock = 40 / 2; 241 break; 242 case AR5K_BWMODE_5MHZ: 243 clock = 40 / 4; 244 break; 245 default: 246 clock = 40; 247 break; 248 } 249 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 250 251 /* Get exponent 252 * ALGO: coef_exp = 14 - highest set bit position */ 253 coef_exp = ilog2(coef_scaled); 254 255 /* Doesn't make sense if it's zero*/ 256 if (!coef_scaled || !coef_exp) 257 return -EINVAL; 258 259 /* Note: we've shifted coef_scaled by 24 */ 260 coef_exp = 14 - (coef_exp - 24); 261 262 263 /* Get mantissa (significant digits) 264 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 265 coef_man = coef_scaled + 266 (1 << (24 - coef_exp - 1)); 267 268 /* Calculate delta slope coefficient exponent 269 * and mantissa (remove scaling) and set them on hw */ 270 ds_coef_man = coef_man >> (24 - coef_exp); 271 ds_coef_exp = coef_exp - 16; 272 273 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 274 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 275 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 276 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 277 278 return 0; 279 } 280 281 int ath5k_hw_phy_disable(struct ath5k_hw *ah) 282 { 283 /*Just a try M.F.*/ 284 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 285 286 return 0; 287 } 288 289 /* 290 * Wait for synth to settle 291 */ 292 static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah, 293 struct ieee80211_channel *channel) 294 { 295 /* 296 * On 5211+ read activation -> rx delay 297 * and use it (100ns steps). 298 */ 299 if (ah->ah_version != AR5K_AR5210) { 300 u32 delay; 301 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 302 AR5K_PHY_RX_DELAY_M; 303 delay = (channel->hw_value == AR5K_MODE_11B) ? 304 ((delay << 2) / 22) : (delay / 10); 305 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) 306 delay = delay << 1; 307 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) 308 delay = delay << 2; 309 /* XXX: /2 on turbo ? Let's be safe 310 * for now */ 311 udelay(100 + delay); 312 } else { 313 mdelay(1); 314 } 315 } 316 317 318 /**********************\ 319 * RF Gain optimization * 320 \**********************/ 321 322 /* 323 * This code is used to optimize RF gain on different environments 324 * (temperature mostly) based on feedback from a power detector. 325 * 326 * It's only used on RF5111 and RF5112, later RF chips seem to have 327 * auto adjustment on hw -notice they have a much smaller BANK 7 and 328 * no gain optimization ladder-. 329 * 330 * For more infos check out this patent doc 331 * http://www.freepatentsonline.com/7400691.html 332 * 333 * This paper describes power drops as seen on the receiver due to 334 * probe packets 335 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 336 * %20of%20Power%20Control.pdf 337 * 338 * And this is the MadWiFi bug entry related to the above 339 * http://madwifi-project.org/ticket/1659 340 * with various measurements and diagrams 341 * 342 * TODO: Deal with power drops due to probes by setting an appropriate 343 * tx power on the probe packets ! Make this part of the calibration process. 344 */ 345 346 /* Initialize ah_gain during attach */ 347 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 348 { 349 /* Initialize the gain optimization values */ 350 switch (ah->ah_radio) { 351 case AR5K_RF5111: 352 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 353 ah->ah_gain.g_low = 20; 354 ah->ah_gain.g_high = 35; 355 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 356 break; 357 case AR5K_RF5112: 358 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 359 ah->ah_gain.g_low = 20; 360 ah->ah_gain.g_high = 85; 361 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 362 break; 363 default: 364 return -EINVAL; 365 } 366 367 return 0; 368 } 369 370 /* Schedule a gain probe check on the next transmitted packet. 371 * That means our next packet is going to be sent with lower 372 * tx power and a Peak to Average Power Detector (PAPD) will try 373 * to measure the gain. 374 * 375 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc) 376 * just after we enable the probe so that we don't mess with 377 * standard traffic ? Maybe it's time to use sw interrupts and 378 * a probe tasklet !!! 379 */ 380 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 381 { 382 383 /* Skip if gain calibration is inactive or 384 * we already handle a probe request */ 385 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 386 return; 387 388 /* Send the packet with 2dB below max power as 389 * patent doc suggest */ 390 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 391 AR5K_PHY_PAPD_PROBE_TXPOWER) | 392 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 393 394 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 395 396 } 397 398 /* Calculate gain_F measurement correction 399 * based on the current step for RF5112 rev. 2 */ 400 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 401 { 402 u32 mix, step; 403 u32 *rf; 404 const struct ath5k_gain_opt *go; 405 const struct ath5k_gain_opt_step *g_step; 406 const struct ath5k_rf_reg *rf_regs; 407 408 /* Only RF5112 Rev. 2 supports it */ 409 if ((ah->ah_radio != AR5K_RF5112) || 410 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 411 return 0; 412 413 go = &rfgain_opt_5112; 414 rf_regs = rf_regs_5112a; 415 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 416 417 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 418 419 if (ah->ah_rf_banks == NULL) 420 return 0; 421 422 rf = ah->ah_rf_banks; 423 ah->ah_gain.g_f_corr = 0; 424 425 /* No VGA (Variable Gain Amplifier) override, skip */ 426 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 427 return 0; 428 429 /* Mix gain stepping */ 430 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 431 432 /* Mix gain override */ 433 mix = g_step->gos_param[0]; 434 435 switch (mix) { 436 case 3: 437 ah->ah_gain.g_f_corr = step * 2; 438 break; 439 case 2: 440 ah->ah_gain.g_f_corr = (step - 5) * 2; 441 break; 442 case 1: 443 ah->ah_gain.g_f_corr = step; 444 break; 445 default: 446 ah->ah_gain.g_f_corr = 0; 447 break; 448 } 449 450 return ah->ah_gain.g_f_corr; 451 } 452 453 /* Check if current gain_F measurement is in the range of our 454 * power detector windows. If we get a measurement outside range 455 * we know it's not accurate (detectors can't measure anything outside 456 * their detection window) so we must ignore it */ 457 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 458 { 459 const struct ath5k_rf_reg *rf_regs; 460 u32 step, mix_ovr, level[4]; 461 u32 *rf; 462 463 if (ah->ah_rf_banks == NULL) 464 return false; 465 466 rf = ah->ah_rf_banks; 467 468 if (ah->ah_radio == AR5K_RF5111) { 469 470 rf_regs = rf_regs_5111; 471 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 472 473 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 474 false); 475 476 level[0] = 0; 477 level[1] = (step == 63) ? 50 : step + 4; 478 level[2] = (step != 63) ? 64 : level[0]; 479 level[3] = level[2] + 50; 480 481 ah->ah_gain.g_high = level[3] - 482 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 483 ah->ah_gain.g_low = level[0] + 484 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 485 } else { 486 487 rf_regs = rf_regs_5112; 488 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 489 490 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 491 false); 492 493 level[0] = level[2] = 0; 494 495 if (mix_ovr == 1) { 496 level[1] = level[3] = 83; 497 } else { 498 level[1] = level[3] = 107; 499 ah->ah_gain.g_high = 55; 500 } 501 } 502 503 return (ah->ah_gain.g_current >= level[0] && 504 ah->ah_gain.g_current <= level[1]) || 505 (ah->ah_gain.g_current >= level[2] && 506 ah->ah_gain.g_current <= level[3]); 507 } 508 509 /* Perform gain_F adjustment by choosing the right set 510 * of parameters from RF gain optimization ladder */ 511 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 512 { 513 const struct ath5k_gain_opt *go; 514 const struct ath5k_gain_opt_step *g_step; 515 int ret = 0; 516 517 switch (ah->ah_radio) { 518 case AR5K_RF5111: 519 go = &rfgain_opt_5111; 520 break; 521 case AR5K_RF5112: 522 go = &rfgain_opt_5112; 523 break; 524 default: 525 return 0; 526 } 527 528 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 529 530 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 531 532 /* Reached maximum */ 533 if (ah->ah_gain.g_step_idx == 0) 534 return -1; 535 536 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 537 ah->ah_gain.g_target >= ah->ah_gain.g_high && 538 ah->ah_gain.g_step_idx > 0; 539 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 540 ah->ah_gain.g_target -= 2 * 541 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 542 g_step->gos_gain); 543 544 ret = 1; 545 goto done; 546 } 547 548 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 549 550 /* Reached minimum */ 551 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 552 return -2; 553 554 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 555 ah->ah_gain.g_target <= ah->ah_gain.g_low && 556 ah->ah_gain.g_step_idx < go->go_steps_count - 1; 557 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 558 ah->ah_gain.g_target -= 2 * 559 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 560 g_step->gos_gain); 561 562 ret = 2; 563 goto done; 564 } 565 566 done: 567 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 568 "ret %d, gain step %u, current gain %u, target gain %u\n", 569 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 570 ah->ah_gain.g_target); 571 572 return ret; 573 } 574 575 /* Main callback for thermal RF gain calibration engine 576 * Check for a new gain reading and schedule an adjustment 577 * if needed. 578 * 579 * TODO: Use sw interrupt to schedule reset if gain_F needs 580 * adjustment */ 581 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 582 { 583 u32 data, type; 584 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 585 586 if (ah->ah_rf_banks == NULL || 587 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 588 return AR5K_RFGAIN_INACTIVE; 589 590 /* No check requested, either engine is inactive 591 * or an adjustment is already requested */ 592 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 593 goto done; 594 595 /* Read the PAPD (Peak to Average Power Detector) 596 * register */ 597 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 598 599 /* No probe is scheduled, read gain_F measurement */ 600 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 601 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 602 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 603 604 /* If tx packet is CCK correct the gain_F measurement 605 * by cck ofdm gain delta */ 606 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 607 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 608 ah->ah_gain.g_current += 609 ee->ee_cck_ofdm_gain_delta; 610 else 611 ah->ah_gain.g_current += 612 AR5K_GAIN_CCK_PROBE_CORR; 613 } 614 615 /* Further correct gain_F measurement for 616 * RF5112A radios */ 617 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 618 ath5k_hw_rf_gainf_corr(ah); 619 ah->ah_gain.g_current = 620 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 621 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : 622 0; 623 } 624 625 /* Check if measurement is ok and if we need 626 * to adjust gain, schedule a gain adjustment, 627 * else switch back to the active state */ 628 if (ath5k_hw_rf_check_gainf_readback(ah) && 629 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 630 ath5k_hw_rf_gainf_adjust(ah)) { 631 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 632 } else { 633 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 634 } 635 } 636 637 done: 638 return ah->ah_gain.g_state; 639 } 640 641 /* Write initial RF gain table to set the RF sensitivity 642 * this one works on all RF chips and has nothing to do 643 * with gain_F calibration */ 644 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) 645 { 646 const struct ath5k_ini_rfgain *ath5k_rfg; 647 unsigned int i, size, index; 648 649 switch (ah->ah_radio) { 650 case AR5K_RF5111: 651 ath5k_rfg = rfgain_5111; 652 size = ARRAY_SIZE(rfgain_5111); 653 break; 654 case AR5K_RF5112: 655 ath5k_rfg = rfgain_5112; 656 size = ARRAY_SIZE(rfgain_5112); 657 break; 658 case AR5K_RF2413: 659 ath5k_rfg = rfgain_2413; 660 size = ARRAY_SIZE(rfgain_2413); 661 break; 662 case AR5K_RF2316: 663 ath5k_rfg = rfgain_2316; 664 size = ARRAY_SIZE(rfgain_2316); 665 break; 666 case AR5K_RF5413: 667 ath5k_rfg = rfgain_5413; 668 size = ARRAY_SIZE(rfgain_5413); 669 break; 670 case AR5K_RF2317: 671 case AR5K_RF2425: 672 ath5k_rfg = rfgain_2425; 673 size = ARRAY_SIZE(rfgain_2425); 674 break; 675 default: 676 return -EINVAL; 677 } 678 679 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0; 680 681 for (i = 0; i < size; i++) { 682 AR5K_REG_WAIT(i); 683 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], 684 (u32)ath5k_rfg[i].rfg_register); 685 } 686 687 return 0; 688 } 689 690 691 692 /********************\ 693 * RF Registers setup * 694 \********************/ 695 696 /* 697 * Setup RF registers by writing RF buffer on hw 698 */ 699 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 700 struct ieee80211_channel *channel, unsigned int mode) 701 { 702 const struct ath5k_rf_reg *rf_regs; 703 const struct ath5k_ini_rfbuffer *ini_rfb; 704 const struct ath5k_gain_opt *go = NULL; 705 const struct ath5k_gain_opt_step *g_step; 706 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 707 u8 ee_mode = 0; 708 u32 *rfb; 709 int i, obdb = -1, bank = -1; 710 711 switch (ah->ah_radio) { 712 case AR5K_RF5111: 713 rf_regs = rf_regs_5111; 714 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 715 ini_rfb = rfb_5111; 716 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 717 go = &rfgain_opt_5111; 718 break; 719 case AR5K_RF5112: 720 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 721 rf_regs = rf_regs_5112a; 722 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 723 ini_rfb = rfb_5112a; 724 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 725 } else { 726 rf_regs = rf_regs_5112; 727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 728 ini_rfb = rfb_5112; 729 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 730 } 731 go = &rfgain_opt_5112; 732 break; 733 case AR5K_RF2413: 734 rf_regs = rf_regs_2413; 735 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 736 ini_rfb = rfb_2413; 737 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 738 break; 739 case AR5K_RF2316: 740 rf_regs = rf_regs_2316; 741 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 742 ini_rfb = rfb_2316; 743 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 744 break; 745 case AR5K_RF5413: 746 rf_regs = rf_regs_5413; 747 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 748 ini_rfb = rfb_5413; 749 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 750 break; 751 case AR5K_RF2317: 752 rf_regs = rf_regs_2425; 753 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 754 ini_rfb = rfb_2317; 755 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 756 break; 757 case AR5K_RF2425: 758 rf_regs = rf_regs_2425; 759 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 760 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 761 ini_rfb = rfb_2425; 762 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 763 } else { 764 ini_rfb = rfb_2417; 765 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 766 } 767 break; 768 default: 769 return -EINVAL; 770 } 771 772 /* If it's the first time we set RF buffer, allocate 773 * ah->ah_rf_banks based on ah->ah_rf_banks_size 774 * we set above */ 775 if (ah->ah_rf_banks == NULL) { 776 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 777 GFP_KERNEL); 778 if (ah->ah_rf_banks == NULL) { 779 ATH5K_ERR(ah, "out of memory\n"); 780 return -ENOMEM; 781 } 782 } 783 784 /* Copy values to modify them */ 785 rfb = ah->ah_rf_banks; 786 787 for (i = 0; i < ah->ah_rf_banks_size; i++) { 788 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 789 ATH5K_ERR(ah, "invalid bank\n"); 790 return -EINVAL; 791 } 792 793 /* Bank changed, write down the offset */ 794 if (bank != ini_rfb[i].rfb_bank) { 795 bank = ini_rfb[i].rfb_bank; 796 ah->ah_offset[bank] = i; 797 } 798 799 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 800 } 801 802 /* Set Output and Driver bias current (OB/DB) */ 803 if (channel->band == IEEE80211_BAND_2GHZ) { 804 805 if (channel->hw_value == AR5K_MODE_11B) 806 ee_mode = AR5K_EEPROM_MODE_11B; 807 else 808 ee_mode = AR5K_EEPROM_MODE_11G; 809 810 /* For RF511X/RF211X combination we 811 * use b_OB and b_DB parameters stored 812 * in eeprom on ee->ee_ob[ee_mode][0] 813 * 814 * For all other chips we use OB/DB for 2GHz 815 * stored in the b/g modal section just like 816 * 802.11a on ee->ee_ob[ee_mode][1] */ 817 if ((ah->ah_radio == AR5K_RF5111) || 818 (ah->ah_radio == AR5K_RF5112)) 819 obdb = 0; 820 else 821 obdb = 1; 822 823 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 824 AR5K_RF_OB_2GHZ, true); 825 826 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 827 AR5K_RF_DB_2GHZ, true); 828 829 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 830 } else if ((channel->band == IEEE80211_BAND_5GHZ) || 831 (ah->ah_radio == AR5K_RF5111)) { 832 833 /* For 11a, Turbo and XR we need to choose 834 * OB/DB based on frequency range */ 835 ee_mode = AR5K_EEPROM_MODE_11A; 836 obdb = channel->center_freq >= 5725 ? 3 : 837 (channel->center_freq >= 5500 ? 2 : 838 (channel->center_freq >= 5260 ? 1 : 839 (channel->center_freq > 4000 ? 0 : -1))); 840 841 if (obdb < 0) 842 return -EINVAL; 843 844 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 845 AR5K_RF_OB_5GHZ, true); 846 847 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 848 AR5K_RF_DB_5GHZ, true); 849 } 850 851 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 852 853 /* Set turbo mode (N/A on RF5413) */ 854 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && 855 (ah->ah_radio != AR5K_RF5413)) 856 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); 857 858 /* Bank Modifications (chip-specific) */ 859 if (ah->ah_radio == AR5K_RF5111) { 860 861 /* Set gain_F settings according to current step */ 862 if (channel->hw_value != AR5K_MODE_11B) { 863 864 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 865 AR5K_PHY_FRAME_CTL_TX_CLIP, 866 g_step->gos_param[0]); 867 868 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 869 AR5K_RF_PWD_90, true); 870 871 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 872 AR5K_RF_PWD_84, true); 873 874 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 875 AR5K_RF_RFGAIN_SEL, true); 876 877 /* We programmed gain_F parameters, switch back 878 * to active state */ 879 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 880 881 } 882 883 /* Bank 6/7 setup */ 884 885 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 886 AR5K_RF_PWD_XPD, true); 887 888 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 889 AR5K_RF_XPD_GAIN, true); 890 891 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 892 AR5K_RF_GAIN_I, true); 893 894 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 895 AR5K_RF_PLO_SEL, true); 896 897 /* Tweak power detectors for half/quarter rate support */ 898 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 899 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 900 u8 wait_i; 901 902 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 903 AR5K_RF_WAIT_S, true); 904 905 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 906 0x1f : 0x10; 907 908 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 909 AR5K_RF_WAIT_I, true); 910 ath5k_hw_rfb_op(ah, rf_regs, 3, 911 AR5K_RF_MAX_TIME, true); 912 913 } 914 } 915 916 if (ah->ah_radio == AR5K_RF5112) { 917 918 /* Set gain_F settings according to current step */ 919 if (channel->hw_value != AR5K_MODE_11B) { 920 921 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 922 AR5K_RF_MIXGAIN_OVR, true); 923 924 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 925 AR5K_RF_PWD_138, true); 926 927 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 928 AR5K_RF_PWD_137, true); 929 930 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 931 AR5K_RF_PWD_136, true); 932 933 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 934 AR5K_RF_PWD_132, true); 935 936 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 937 AR5K_RF_PWD_131, true); 938 939 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 940 AR5K_RF_PWD_130, true); 941 942 /* We programmed gain_F parameters, switch back 943 * to active state */ 944 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 945 } 946 947 /* Bank 6/7 setup */ 948 949 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 950 AR5K_RF_XPD_SEL, true); 951 952 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 953 /* Rev. 1 supports only one xpd */ 954 ath5k_hw_rfb_op(ah, rf_regs, 955 ee->ee_x_gain[ee_mode], 956 AR5K_RF_XPD_GAIN, true); 957 958 } else { 959 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 960 if (ee->ee_pd_gains[ee_mode] > 1) { 961 ath5k_hw_rfb_op(ah, rf_regs, 962 pdg_curve_to_idx[0], 963 AR5K_RF_PD_GAIN_LO, true); 964 ath5k_hw_rfb_op(ah, rf_regs, 965 pdg_curve_to_idx[1], 966 AR5K_RF_PD_GAIN_HI, true); 967 } else { 968 ath5k_hw_rfb_op(ah, rf_regs, 969 pdg_curve_to_idx[0], 970 AR5K_RF_PD_GAIN_LO, true); 971 ath5k_hw_rfb_op(ah, rf_regs, 972 pdg_curve_to_idx[0], 973 AR5K_RF_PD_GAIN_HI, true); 974 } 975 976 /* Lower synth voltage on Rev 2 */ 977 if (ah->ah_radio == AR5K_RF5112 && 978 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { 979 ath5k_hw_rfb_op(ah, rf_regs, 2, 980 AR5K_RF_HIGH_VC_CP, true); 981 982 ath5k_hw_rfb_op(ah, rf_regs, 2, 983 AR5K_RF_MID_VC_CP, true); 984 985 ath5k_hw_rfb_op(ah, rf_regs, 2, 986 AR5K_RF_LOW_VC_CP, true); 987 988 ath5k_hw_rfb_op(ah, rf_regs, 2, 989 AR5K_RF_PUSH_UP, true); 990 } 991 992 /* Decrease power consumption on 5213+ BaseBand */ 993 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 994 ath5k_hw_rfb_op(ah, rf_regs, 1, 995 AR5K_RF_PAD2GND, true); 996 997 ath5k_hw_rfb_op(ah, rf_regs, 1, 998 AR5K_RF_XB2_LVL, true); 999 1000 ath5k_hw_rfb_op(ah, rf_regs, 1, 1001 AR5K_RF_XB5_LVL, true); 1002 1003 ath5k_hw_rfb_op(ah, rf_regs, 1, 1004 AR5K_RF_PWD_167, true); 1005 1006 ath5k_hw_rfb_op(ah, rf_regs, 1, 1007 AR5K_RF_PWD_166, true); 1008 } 1009 } 1010 1011 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 1012 AR5K_RF_GAIN_I, true); 1013 1014 /* Tweak power detector for half/quarter rates */ 1015 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 1016 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 1017 u8 pd_delay; 1018 1019 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 1020 0xf : 0x8; 1021 1022 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 1023 AR5K_RF_PD_PERIOD_A, true); 1024 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 1025 AR5K_RF_PD_DELAY_A, true); 1026 1027 } 1028 } 1029 1030 if (ah->ah_radio == AR5K_RF5413 && 1031 channel->band == IEEE80211_BAND_2GHZ) { 1032 1033 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 1034 true); 1035 1036 /* Set optimum value for early revisions (on pci-e chips) */ 1037 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1038 ah->ah_mac_srev < AR5K_SREV_AR5413) 1039 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 1040 AR5K_RF_PWD_ICLOBUF_2G, true); 1041 1042 } 1043 1044 /* Write RF banks on hw */ 1045 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1046 AR5K_REG_WAIT(i); 1047 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1048 } 1049 1050 return 0; 1051 } 1052 1053 1054 /**************************\ 1055 PHY/RF channel functions 1056 \**************************/ 1057 1058 /* 1059 * Conversion needed for RF5110 1060 */ 1061 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1062 { 1063 u32 athchan; 1064 1065 /* 1066 * Convert IEEE channel/MHz to an internal channel value used 1067 * by the AR5210 chipset. This has not been verified with 1068 * newer chipsets like the AR5212A who have a completely 1069 * different RF/PHY part. 1070 */ 1071 athchan = (ath5k_hw_bitswap( 1072 (ieee80211_frequency_to_channel( 1073 channel->center_freq) - 24) / 2, 5) 1074 << 1) | (1 << 6) | 0x1; 1075 return athchan; 1076 } 1077 1078 /* 1079 * Set channel on RF5110 1080 */ 1081 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1082 struct ieee80211_channel *channel) 1083 { 1084 u32 data; 1085 1086 /* 1087 * Set the channel and wait 1088 */ 1089 data = ath5k_hw_rf5110_chan2athchan(channel); 1090 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1091 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1092 mdelay(1); 1093 1094 return 0; 1095 } 1096 1097 /* 1098 * Conversion needed for 5111 1099 */ 1100 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1101 struct ath5k_athchan_2ghz *athchan) 1102 { 1103 int channel; 1104 1105 /* Cast this value to catch negative channel numbers (>= -19) */ 1106 channel = (int)ieee; 1107 1108 /* 1109 * Map 2GHz IEEE channel to 5GHz Atheros channel 1110 */ 1111 if (channel <= 13) { 1112 athchan->a2_athchan = 115 + channel; 1113 athchan->a2_flags = 0x46; 1114 } else if (channel == 14) { 1115 athchan->a2_athchan = 124; 1116 athchan->a2_flags = 0x44; 1117 } else if (channel >= 15 && channel <= 26) { 1118 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1119 athchan->a2_flags = 0x46; 1120 } else 1121 return -EINVAL; 1122 1123 return 0; 1124 } 1125 1126 /* 1127 * Set channel on 5111 1128 */ 1129 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1130 struct ieee80211_channel *channel) 1131 { 1132 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1133 unsigned int ath5k_channel = 1134 ieee80211_frequency_to_channel(channel->center_freq); 1135 u32 data0, data1, clock; 1136 int ret; 1137 1138 /* 1139 * Set the channel on the RF5111 radio 1140 */ 1141 data0 = data1 = 0; 1142 1143 if (channel->band == IEEE80211_BAND_2GHZ) { 1144 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1145 ret = ath5k_hw_rf5111_chan2athchan( 1146 ieee80211_frequency_to_channel(channel->center_freq), 1147 &ath5k_channel_2ghz); 1148 if (ret) 1149 return ret; 1150 1151 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1152 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1153 << 5) | (1 << 4); 1154 } 1155 1156 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1157 clock = 1; 1158 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1159 (clock << 1) | (1 << 10) | 1; 1160 } else { 1161 clock = 0; 1162 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1163 << 2) | (clock << 1) | (1 << 10) | 1; 1164 } 1165 1166 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1167 AR5K_RF_BUFFER); 1168 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1169 AR5K_RF_BUFFER_CONTROL_3); 1170 1171 return 0; 1172 } 1173 1174 /* 1175 * Set channel on 5112 and newer 1176 */ 1177 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1178 struct ieee80211_channel *channel) 1179 { 1180 u32 data, data0, data1, data2; 1181 u16 c; 1182 1183 data = data0 = data1 = data2 = 0; 1184 c = channel->center_freq; 1185 1186 if (c < 4800) { 1187 if (!((c - 2224) % 5)) { 1188 data0 = ((2 * (c - 704)) - 3040) / 10; 1189 data1 = 1; 1190 } else if (!((c - 2192) % 5)) { 1191 data0 = ((2 * (c - 672)) - 3040) / 10; 1192 data1 = 0; 1193 } else 1194 return -EINVAL; 1195 1196 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1197 } else if ((c % 5) != 2 || c > 5435) { 1198 if (!(c % 20) && c >= 5120) { 1199 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1200 data2 = ath5k_hw_bitswap(3, 2); 1201 } else if (!(c % 10)) { 1202 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1203 data2 = ath5k_hw_bitswap(2, 2); 1204 } else if (!(c % 5)) { 1205 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1206 data2 = ath5k_hw_bitswap(1, 2); 1207 } else 1208 return -EINVAL; 1209 } else { 1210 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1211 data2 = ath5k_hw_bitswap(0, 2); 1212 } 1213 1214 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1215 1216 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1217 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1218 1219 return 0; 1220 } 1221 1222 /* 1223 * Set the channel on the RF2425 1224 */ 1225 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1226 struct ieee80211_channel *channel) 1227 { 1228 u32 data, data0, data2; 1229 u16 c; 1230 1231 data = data0 = data2 = 0; 1232 c = channel->center_freq; 1233 1234 if (c < 4800) { 1235 data0 = ath5k_hw_bitswap((c - 2272), 8); 1236 data2 = 0; 1237 /* ? 5GHz ? */ 1238 } else if ((c % 5) != 2 || c > 5435) { 1239 if (!(c % 20) && c < 5120) 1240 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1241 else if (!(c % 10)) 1242 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1243 else if (!(c % 5)) 1244 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1245 else 1246 return -EINVAL; 1247 data2 = ath5k_hw_bitswap(1, 2); 1248 } else { 1249 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1250 data2 = ath5k_hw_bitswap(0, 2); 1251 } 1252 1253 data = (data0 << 4) | data2 << 2 | 0x1001; 1254 1255 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1256 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1257 1258 return 0; 1259 } 1260 1261 /* 1262 * Set a channel on the radio chip 1263 */ 1264 static int ath5k_hw_channel(struct ath5k_hw *ah, 1265 struct ieee80211_channel *channel) 1266 { 1267 int ret; 1268 /* 1269 * Check bounds supported by the PHY (we don't care about regulatory 1270 * restrictions at this point). 1271 */ 1272 if (!ath5k_channel_ok(ah, channel)) { 1273 ATH5K_ERR(ah, 1274 "channel frequency (%u MHz) out of supported " 1275 "band range\n", 1276 channel->center_freq); 1277 return -EINVAL; 1278 } 1279 1280 /* 1281 * Set the channel and wait 1282 */ 1283 switch (ah->ah_radio) { 1284 case AR5K_RF5110: 1285 ret = ath5k_hw_rf5110_channel(ah, channel); 1286 break; 1287 case AR5K_RF5111: 1288 ret = ath5k_hw_rf5111_channel(ah, channel); 1289 break; 1290 case AR5K_RF2317: 1291 case AR5K_RF2425: 1292 ret = ath5k_hw_rf2425_channel(ah, channel); 1293 break; 1294 default: 1295 ret = ath5k_hw_rf5112_channel(ah, channel); 1296 break; 1297 } 1298 1299 if (ret) 1300 return ret; 1301 1302 /* Set JAPAN setting for channel 14 */ 1303 if (channel->center_freq == 2484) { 1304 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1305 AR5K_PHY_CCKTXCTL_JAPAN); 1306 } else { 1307 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1308 AR5K_PHY_CCKTXCTL_WORLD); 1309 } 1310 1311 ah->ah_current_channel = channel; 1312 1313 return 0; 1314 } 1315 1316 /*****************\ 1317 PHY calibration 1318 \*****************/ 1319 1320 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1321 { 1322 s32 val; 1323 1324 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1325 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1326 } 1327 1328 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1329 { 1330 int i; 1331 1332 ah->ah_nfcal_hist.index = 0; 1333 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1334 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1335 } 1336 1337 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1338 { 1339 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1340 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1); 1341 hist->nfval[hist->index] = noise_floor; 1342 } 1343 1344 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1345 { 1346 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1347 s16 tmp; 1348 int i, j; 1349 1350 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1351 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1352 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1353 if (sort[j] > sort[j - 1]) { 1354 tmp = sort[j]; 1355 sort[j] = sort[j - 1]; 1356 sort[j - 1] = tmp; 1357 } 1358 } 1359 } 1360 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1361 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1362 "cal %d:%d\n", i, sort[i]); 1363 } 1364 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; 1365 } 1366 1367 /* 1368 * When we tell the hardware to perform a noise floor calibration 1369 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1370 * sample-and-hold the minimum noise level seen at the antennas. 1371 * This value is then stored in a ring buffer of recently measured 1372 * noise floor values so we have a moving window of the last few 1373 * samples. 1374 * 1375 * The median of the values in the history is then loaded into the 1376 * hardware for its own use for RSSI and CCA measurements. 1377 */ 1378 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1379 { 1380 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1381 u32 val; 1382 s16 nf, threshold; 1383 u8 ee_mode; 1384 1385 /* keep last value if calibration hasn't completed */ 1386 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1387 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1388 "NF did not complete in calibration window\n"); 1389 1390 return; 1391 } 1392 1393 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel); 1394 1395 /* completed NF calibration, test threshold */ 1396 nf = ath5k_hw_read_measured_noise_floor(ah); 1397 threshold = ee->ee_noise_floor_thr[ee_mode]; 1398 1399 if (nf > threshold) { 1400 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1401 "noise floor failure detected; " 1402 "read %d, threshold %d\n", 1403 nf, threshold); 1404 1405 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1406 } 1407 1408 ath5k_hw_update_nfcal_hist(ah, nf); 1409 nf = ath5k_hw_get_median_noise_floor(ah); 1410 1411 /* load noise floor (in .5 dBm) so the hardware will use it */ 1412 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1413 val |= (nf * 2) & AR5K_PHY_NF_M; 1414 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1415 1416 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1417 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1418 1419 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1420 0, false); 1421 1422 /* 1423 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1424 * so that we're not capped by the median we just loaded. 1425 * This will be used as the initial value for the next noise 1426 * floor calibration. 1427 */ 1428 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1429 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1430 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1431 AR5K_PHY_AGCCTL_NF_EN | 1432 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1433 AR5K_PHY_AGCCTL_NF); 1434 1435 ah->ah_noise_floor = nf; 1436 1437 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1438 "noise floor calibrated: %d\n", nf); 1439 } 1440 1441 /* 1442 * Perform a PHY calibration on RF5110 1443 * -Fix BPSK/QAM Constellation (I/Q correction) 1444 */ 1445 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1446 struct ieee80211_channel *channel) 1447 { 1448 u32 phy_sig, phy_agc, phy_sat, beacon; 1449 int ret; 1450 1451 /* 1452 * Disable beacons and RX/TX queues, wait 1453 */ 1454 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1455 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1456 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1457 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1458 1459 mdelay(2); 1460 1461 /* 1462 * Set the channel (with AGC turned off) 1463 */ 1464 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1465 udelay(10); 1466 ret = ath5k_hw_channel(ah, channel); 1467 1468 /* 1469 * Activate PHY and wait 1470 */ 1471 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1472 mdelay(1); 1473 1474 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1475 1476 if (ret) 1477 return ret; 1478 1479 /* 1480 * Calibrate the radio chip 1481 */ 1482 1483 /* Remember normal state */ 1484 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1485 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1486 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1487 1488 /* Update radio registers */ 1489 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1490 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1491 1492 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1493 AR5K_PHY_AGCCOARSE_LO)) | 1494 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1495 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1496 1497 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1498 AR5K_PHY_ADCSAT_THR)) | 1499 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1500 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1501 1502 udelay(20); 1503 1504 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1505 udelay(10); 1506 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1507 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1508 1509 mdelay(1); 1510 1511 /* 1512 * Enable calibration and wait until completion 1513 */ 1514 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1515 1516 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1517 AR5K_PHY_AGCCTL_CAL, 0, false); 1518 1519 /* Reset to normal state */ 1520 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1521 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1522 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1523 1524 if (ret) { 1525 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", 1526 channel->center_freq); 1527 return ret; 1528 } 1529 1530 /* 1531 * Re-enable RX/TX and beacons 1532 */ 1533 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1534 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1535 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1536 1537 return 0; 1538 } 1539 1540 /* 1541 * Perform I/Q calibration on RF5111/5112 and newer chips 1542 */ 1543 static int 1544 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1545 { 1546 u32 i_pwr, q_pwr; 1547 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1548 int i; 1549 1550 if (!ah->ah_calibration || 1551 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1552 return 0; 1553 1554 /* Calibration has finished, get the results and re-run */ 1555 /* work around empty results which can apparently happen on 5212 */ 1556 for (i = 0; i <= 10; i++) { 1557 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1558 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1559 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1560 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1561 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1562 if (i_pwr && q_pwr) 1563 break; 1564 } 1565 1566 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1567 1568 if (ah->ah_version == AR5K_AR5211) 1569 q_coffd = q_pwr >> 6; 1570 else 1571 q_coffd = q_pwr >> 7; 1572 1573 /* protect against divide by 0 and loss of sign bits */ 1574 if (i_coffd == 0 || q_coffd < 2) 1575 return 0; 1576 1577 i_coff = (-iq_corr) / i_coffd; 1578 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1579 1580 if (ah->ah_version == AR5K_AR5211) 1581 q_coff = (i_pwr / q_coffd) - 64; 1582 else 1583 q_coff = (i_pwr / q_coffd) - 128; 1584 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1585 1586 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1587 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1588 i_coff, q_coff, i_coffd, q_coffd); 1589 1590 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1591 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1592 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1593 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1594 1595 /* Re-enable calibration -if we don't we'll commit 1596 * the same values again and again */ 1597 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1598 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1599 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1600 1601 return 0; 1602 } 1603 1604 /* 1605 * Perform a PHY calibration 1606 */ 1607 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1608 struct ieee80211_channel *channel) 1609 { 1610 int ret; 1611 1612 if (ah->ah_radio == AR5K_RF5110) 1613 return ath5k_hw_rf5110_calibrate(ah, channel); 1614 1615 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1616 1617 if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) && 1618 (channel->hw_value != AR5K_MODE_11B)) 1619 ath5k_hw_request_rfgain_probe(ah); 1620 1621 return ret; 1622 } 1623 1624 1625 /***************************\ 1626 * Spur mitigation functions * 1627 \***************************/ 1628 1629 static void 1630 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1631 struct ieee80211_channel *channel) 1632 { 1633 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1634 u32 mag_mask[4] = {0, 0, 0, 0}; 1635 u32 pilot_mask[2] = {0, 0}; 1636 /* Note: fbin values are scaled up by 2 */ 1637 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1638 s32 spur_delta_phase, spur_freq_sigma_delta; 1639 s32 spur_offset, num_symbols_x16; 1640 u8 num_symbol_offsets, i, freq_band; 1641 1642 /* Convert current frequency to fbin value (the same way channels 1643 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1644 * up by 2 so we can compare it later */ 1645 if (channel->band == IEEE80211_BAND_2GHZ) { 1646 chan_fbin = (channel->center_freq - 2300) * 10; 1647 freq_band = AR5K_EEPROM_BAND_2GHZ; 1648 } else { 1649 chan_fbin = (channel->center_freq - 4900) * 10; 1650 freq_band = AR5K_EEPROM_BAND_5GHZ; 1651 } 1652 1653 /* Check if any spur_chan_fbin from EEPROM is 1654 * within our current channel's spur detection range */ 1655 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1656 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1657 /* XXX: Half/Quarter channels ?*/ 1658 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 1659 spur_detection_window *= 2; 1660 1661 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1662 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1663 1664 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1665 * so it's zero if we got nothing from EEPROM */ 1666 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1667 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1668 break; 1669 } 1670 1671 if ((chan_fbin - spur_detection_window <= 1672 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1673 (chan_fbin + spur_detection_window >= 1674 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1675 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1676 break; 1677 } 1678 } 1679 1680 /* We need to enable spur filter for this channel */ 1681 if (spur_chan_fbin) { 1682 spur_offset = spur_chan_fbin - chan_fbin; 1683 /* 1684 * Calculate deltas: 1685 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1686 * spur_delta_phase -> spur_offset / chip_freq << 11 1687 * Note: Both values have 100Hz resolution 1688 */ 1689 switch (ah->ah_bwmode) { 1690 case AR5K_BWMODE_40MHZ: 1691 /* Both sample_freq and chip_freq are 80MHz */ 1692 spur_delta_phase = (spur_offset << 16) / 25; 1693 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1694 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2; 1695 break; 1696 case AR5K_BWMODE_10MHZ: 1697 /* Both sample_freq and chip_freq are 20MHz (?) */ 1698 spur_delta_phase = (spur_offset << 18) / 25; 1699 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1700 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2; 1701 case AR5K_BWMODE_5MHZ: 1702 /* Both sample_freq and chip_freq are 10MHz (?) */ 1703 spur_delta_phase = (spur_offset << 19) / 25; 1704 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1705 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4; 1706 default: 1707 if (channel->band == IEEE80211_BAND_5GHZ) { 1708 /* Both sample_freq and chip_freq are 40MHz */ 1709 spur_delta_phase = (spur_offset << 17) / 25; 1710 spur_freq_sigma_delta = 1711 (spur_delta_phase >> 10); 1712 symbol_width = 1713 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1714 } else { 1715 /* sample_freq -> 40MHz chip_freq -> 44MHz 1716 * (for b compatibility) */ 1717 spur_delta_phase = (spur_offset << 17) / 25; 1718 spur_freq_sigma_delta = 1719 (spur_offset << 8) / 55; 1720 symbol_width = 1721 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1722 } 1723 break; 1724 } 1725 1726 /* Calculate pilot and magnitude masks */ 1727 1728 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1729 * and divide by symbol_width to find how many symbols we have 1730 * Note: number of symbols is scaled up by 16 */ 1731 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1732 1733 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1734 if (!(num_symbols_x16 & 0xF)) 1735 /* _X_ */ 1736 num_symbol_offsets = 3; 1737 else 1738 /* _xx_ */ 1739 num_symbol_offsets = 4; 1740 1741 for (i = 0; i < num_symbol_offsets; i++) { 1742 1743 /* Calculate pilot mask */ 1744 s32 curr_sym_off = 1745 (num_symbols_x16 / 16) + i + 25; 1746 1747 /* Pilot magnitude mask seems to be a way to 1748 * declare the boundaries for our detection 1749 * window or something, it's 2 for the middle 1750 * value(s) where the symbol is expected to be 1751 * and 1 on the boundary values */ 1752 u8 plt_mag_map = 1753 (i == 0 || i == (num_symbol_offsets - 1)) 1754 ? 1 : 2; 1755 1756 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1757 if (curr_sym_off <= 25) 1758 pilot_mask[0] |= 1 << curr_sym_off; 1759 else if (curr_sym_off >= 27) 1760 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1761 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1762 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1763 1764 /* Calculate magnitude mask (for viterbi decoder) */ 1765 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1766 mag_mask[0] |= 1767 plt_mag_map << (curr_sym_off + 1) * 2; 1768 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1769 mag_mask[1] |= 1770 plt_mag_map << (curr_sym_off - 15) * 2; 1771 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1772 mag_mask[2] |= 1773 plt_mag_map << (curr_sym_off - 31) * 2; 1774 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1775 mag_mask[3] |= 1776 plt_mag_map << (curr_sym_off - 47) * 2; 1777 1778 } 1779 1780 /* Write settings on hw to enable spur filter */ 1781 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1782 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1783 /* XXX: Self correlator also ? */ 1784 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1785 AR5K_PHY_IQ_PILOT_MASK_EN | 1786 AR5K_PHY_IQ_CHAN_MASK_EN | 1787 AR5K_PHY_IQ_SPUR_FILT_EN); 1788 1789 /* Set delta phase and freq sigma delta */ 1790 ath5k_hw_reg_write(ah, 1791 AR5K_REG_SM(spur_delta_phase, 1792 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1793 AR5K_REG_SM(spur_freq_sigma_delta, 1794 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1795 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1796 AR5K_PHY_TIMING_11); 1797 1798 /* Write pilot masks */ 1799 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1800 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1801 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1802 pilot_mask[1]); 1803 1804 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1805 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1806 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1807 pilot_mask[1]); 1808 1809 /* Write magnitude masks */ 1810 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1811 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1812 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1813 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1814 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1815 mag_mask[3]); 1816 1817 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1818 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1819 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1820 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1821 AR5K_PHY_BIN_MASK2_4_MASK_4, 1822 mag_mask[3]); 1823 1824 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1825 AR5K_PHY_IQ_SPUR_FILT_EN) { 1826 /* Clean up spur mitigation settings and disable filter */ 1827 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1828 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1829 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1830 AR5K_PHY_IQ_PILOT_MASK_EN | 1831 AR5K_PHY_IQ_CHAN_MASK_EN | 1832 AR5K_PHY_IQ_SPUR_FILT_EN); 1833 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1834 1835 /* Clear pilot masks */ 1836 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1837 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1838 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1839 0); 1840 1841 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1842 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1843 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1844 0); 1845 1846 /* Clear magnitude masks */ 1847 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1848 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1849 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1850 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1851 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1852 0); 1853 1854 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1855 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1856 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1857 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1858 AR5K_PHY_BIN_MASK2_4_MASK_4, 1859 0); 1860 } 1861 } 1862 1863 1864 /*****************\ 1865 * Antenna control * 1866 \*****************/ 1867 1868 static void /*TODO:Boundary check*/ 1869 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1870 { 1871 if (ah->ah_version != AR5K_AR5210) 1872 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1873 } 1874 1875 /* 1876 * Enable/disable fast rx antenna diversity 1877 */ 1878 static void 1879 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1880 { 1881 switch (ee_mode) { 1882 case AR5K_EEPROM_MODE_11G: 1883 /* XXX: This is set to 1884 * disabled on initvals !!! */ 1885 case AR5K_EEPROM_MODE_11A: 1886 if (enable) 1887 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1888 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1889 else 1890 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1891 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1892 break; 1893 case AR5K_EEPROM_MODE_11B: 1894 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1895 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1896 break; 1897 default: 1898 return; 1899 } 1900 1901 if (enable) { 1902 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1903 AR5K_PHY_RESTART_DIV_GC, 4); 1904 1905 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1906 AR5K_PHY_FAST_ANT_DIV_EN); 1907 } else { 1908 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1909 AR5K_PHY_RESTART_DIV_GC, 0); 1910 1911 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1912 AR5K_PHY_FAST_ANT_DIV_EN); 1913 } 1914 } 1915 1916 void 1917 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1918 { 1919 u8 ant0, ant1; 1920 1921 /* 1922 * In case a fixed antenna was set as default 1923 * use the same switch table twice. 1924 */ 1925 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1926 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1927 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1928 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1929 else { 1930 ant0 = AR5K_ANT_SWTABLE_A; 1931 ant1 = AR5K_ANT_SWTABLE_B; 1932 } 1933 1934 /* Set antenna idle switch table */ 1935 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1936 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1937 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1938 AR5K_PHY_ANT_CTL_TXRX_EN)); 1939 1940 /* Set antenna switch tables */ 1941 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1942 AR5K_PHY_ANT_SWITCH_TABLE_0); 1943 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1944 AR5K_PHY_ANT_SWITCH_TABLE_1); 1945 } 1946 1947 /* 1948 * Set antenna operating mode 1949 */ 1950 void 1951 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1952 { 1953 struct ieee80211_channel *channel = ah->ah_current_channel; 1954 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1955 bool use_def_for_sg; 1956 int ee_mode; 1957 u8 def_ant, tx_ant; 1958 u32 sta_id1 = 0; 1959 1960 /* if channel is not initialized yet we can't set the antennas 1961 * so just store the mode. it will be set on the next reset */ 1962 if (channel == NULL) { 1963 ah->ah_ant_mode = ant_mode; 1964 return; 1965 } 1966 1967 def_ant = ah->ah_def_ant; 1968 1969 ee_mode = ath5k_eeprom_mode_from_channel(channel); 1970 if (ee_mode < 0) { 1971 ATH5K_ERR(ah, 1972 "invalid channel: %d\n", channel->center_freq); 1973 return; 1974 } 1975 1976 switch (ant_mode) { 1977 case AR5K_ANTMODE_DEFAULT: 1978 tx_ant = 0; 1979 use_def_for_tx = false; 1980 update_def_on_tx = false; 1981 use_def_for_rts = false; 1982 use_def_for_sg = false; 1983 fast_div = true; 1984 break; 1985 case AR5K_ANTMODE_FIXED_A: 1986 def_ant = 1; 1987 tx_ant = 1; 1988 use_def_for_tx = true; 1989 update_def_on_tx = false; 1990 use_def_for_rts = true; 1991 use_def_for_sg = true; 1992 fast_div = false; 1993 break; 1994 case AR5K_ANTMODE_FIXED_B: 1995 def_ant = 2; 1996 tx_ant = 2; 1997 use_def_for_tx = true; 1998 update_def_on_tx = false; 1999 use_def_for_rts = true; 2000 use_def_for_sg = true; 2001 fast_div = false; 2002 break; 2003 case AR5K_ANTMODE_SINGLE_AP: 2004 def_ant = 1; /* updated on tx */ 2005 tx_ant = 0; 2006 use_def_for_tx = true; 2007 update_def_on_tx = true; 2008 use_def_for_rts = true; 2009 use_def_for_sg = true; 2010 fast_div = true; 2011 break; 2012 case AR5K_ANTMODE_SECTOR_AP: 2013 tx_ant = 1; /* variable */ 2014 use_def_for_tx = false; 2015 update_def_on_tx = false; 2016 use_def_for_rts = true; 2017 use_def_for_sg = false; 2018 fast_div = false; 2019 break; 2020 case AR5K_ANTMODE_SECTOR_STA: 2021 tx_ant = 1; /* variable */ 2022 use_def_for_tx = true; 2023 update_def_on_tx = false; 2024 use_def_for_rts = true; 2025 use_def_for_sg = false; 2026 fast_div = true; 2027 break; 2028 case AR5K_ANTMODE_DEBUG: 2029 def_ant = 1; 2030 tx_ant = 2; 2031 use_def_for_tx = false; 2032 update_def_on_tx = false; 2033 use_def_for_rts = false; 2034 use_def_for_sg = false; 2035 fast_div = false; 2036 break; 2037 default: 2038 return; 2039 } 2040 2041 ah->ah_tx_ant = tx_ant; 2042 ah->ah_ant_mode = ant_mode; 2043 ah->ah_def_ant = def_ant; 2044 2045 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2046 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2047 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2048 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2049 2050 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2051 2052 if (sta_id1) 2053 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2054 2055 ath5k_hw_set_antenna_switch(ah, ee_mode); 2056 /* Note: set diversity before default antenna 2057 * because it won't work correctly */ 2058 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2059 ath5k_hw_set_def_antenna(ah, def_ant); 2060 } 2061 2062 2063 /****************\ 2064 * TX power setup * 2065 \****************/ 2066 2067 /* 2068 * Helper functions 2069 */ 2070 2071 /* 2072 * Do linear interpolation between two given (x, y) points 2073 */ 2074 static s16 2075 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2076 s16 y_left, s16 y_right) 2077 { 2078 s16 ratio, result; 2079 2080 /* Avoid divide by zero and skip interpolation 2081 * if we have the same point */ 2082 if ((x_left == x_right) || (y_left == y_right)) 2083 return y_left; 2084 2085 /* 2086 * Since we use ints and not fps, we need to scale up in 2087 * order to get a sane ratio value (or else we 'll eg. get 2088 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2089 * to have some accuracy both for 0.5 and 0.25 steps. 2090 */ 2091 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left)); 2092 2093 /* Now scale down to be in range */ 2094 result = y_left + (ratio * (target - x_left) / 100); 2095 2096 return result; 2097 } 2098 2099 /* 2100 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2101 * 2102 * Since we have the top of the curve and we draw the line below 2103 * until we reach 1 (1 pcdac step) we need to know which point 2104 * (x value) that is so that we don't go below y axis and have negative 2105 * pcdac values when creating the curve, or fill the table with zeroes. 2106 */ 2107 static s16 2108 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2109 const s16 *pwrL, const s16 *pwrR) 2110 { 2111 s8 tmp; 2112 s16 min_pwrL, min_pwrR; 2113 s16 pwr_i; 2114 2115 /* Some vendors write the same pcdac value twice !!! */ 2116 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2117 return max(pwrL[0], pwrR[0]); 2118 2119 if (pwrL[0] == pwrL[1]) 2120 min_pwrL = pwrL[0]; 2121 else { 2122 pwr_i = pwrL[0]; 2123 do { 2124 pwr_i--; 2125 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2126 pwrL[0], pwrL[1], 2127 stepL[0], stepL[1]); 2128 } while (tmp > 1); 2129 2130 min_pwrL = pwr_i; 2131 } 2132 2133 if (pwrR[0] == pwrR[1]) 2134 min_pwrR = pwrR[0]; 2135 else { 2136 pwr_i = pwrR[0]; 2137 do { 2138 pwr_i--; 2139 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2140 pwrR[0], pwrR[1], 2141 stepR[0], stepR[1]); 2142 } while (tmp > 1); 2143 2144 min_pwrR = pwr_i; 2145 } 2146 2147 /* Keep the right boundary so that it works for both curves */ 2148 return max(min_pwrL, min_pwrR); 2149 } 2150 2151 /* 2152 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2153 * Power to PCDAC curve. 2154 * 2155 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2156 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2157 * PCDAC/PDADC step for each curve is 64 but we can write more than 2158 * one curves on hw so we can go up to 128 (which is the max step we 2159 * can write on the final table). 2160 * 2161 * We write y values (PCDAC/PDADC steps) on hw. 2162 */ 2163 static void 2164 ath5k_create_power_curve(s16 pmin, s16 pmax, 2165 const s16 *pwr, const u8 *vpd, 2166 u8 num_points, 2167 u8 *vpd_table, u8 type) 2168 { 2169 u8 idx[2] = { 0, 1 }; 2170 s16 pwr_i = 2 * pmin; 2171 int i; 2172 2173 if (num_points < 2) 2174 return; 2175 2176 /* We want the whole line, so adjust boundaries 2177 * to cover the entire power range. Note that 2178 * power values are already 0.25dB so no need 2179 * to multiply pwr_i by 2 */ 2180 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2181 pwr_i = pmin; 2182 pmin = 0; 2183 pmax = 63; 2184 } 2185 2186 /* Find surrounding turning points (TPs) 2187 * and interpolate between them */ 2188 for (i = 0; (i <= (u16) (pmax - pmin)) && 2189 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2190 2191 /* We passed the right TP, move to the next set of TPs 2192 * if we pass the last TP, extrapolate above using the last 2193 * two TPs for ratio */ 2194 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2195 idx[0]++; 2196 idx[1]++; 2197 } 2198 2199 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2200 pwr[idx[0]], pwr[idx[1]], 2201 vpd[idx[0]], vpd[idx[1]]); 2202 2203 /* Increase by 0.5dB 2204 * (0.25 dB units) */ 2205 pwr_i += 2; 2206 } 2207 } 2208 2209 /* 2210 * Get the surrounding per-channel power calibration piers 2211 * for a given frequency so that we can interpolate between 2212 * them and come up with an appropriate dataset for our current 2213 * channel. 2214 */ 2215 static void 2216 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2217 struct ieee80211_channel *channel, 2218 struct ath5k_chan_pcal_info **pcinfo_l, 2219 struct ath5k_chan_pcal_info **pcinfo_r) 2220 { 2221 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2222 struct ath5k_chan_pcal_info *pcinfo; 2223 u8 idx_l, idx_r; 2224 u8 mode, max, i; 2225 u32 target = channel->center_freq; 2226 2227 idx_l = 0; 2228 idx_r = 0; 2229 2230 switch (channel->hw_value) { 2231 case AR5K_EEPROM_MODE_11A: 2232 pcinfo = ee->ee_pwr_cal_a; 2233 mode = AR5K_EEPROM_MODE_11A; 2234 break; 2235 case AR5K_EEPROM_MODE_11B: 2236 pcinfo = ee->ee_pwr_cal_b; 2237 mode = AR5K_EEPROM_MODE_11B; 2238 break; 2239 case AR5K_EEPROM_MODE_11G: 2240 default: 2241 pcinfo = ee->ee_pwr_cal_g; 2242 mode = AR5K_EEPROM_MODE_11G; 2243 break; 2244 } 2245 max = ee->ee_n_piers[mode] - 1; 2246 2247 /* Frequency is below our calibrated 2248 * range. Use the lowest power curve 2249 * we have */ 2250 if (target < pcinfo[0].freq) { 2251 idx_l = idx_r = 0; 2252 goto done; 2253 } 2254 2255 /* Frequency is above our calibrated 2256 * range. Use the highest power curve 2257 * we have */ 2258 if (target > pcinfo[max].freq) { 2259 idx_l = idx_r = max; 2260 goto done; 2261 } 2262 2263 /* Frequency is inside our calibrated 2264 * channel range. Pick the surrounding 2265 * calibration piers so that we can 2266 * interpolate */ 2267 for (i = 0; i <= max; i++) { 2268 2269 /* Frequency matches one of our calibration 2270 * piers, no need to interpolate, just use 2271 * that calibration pier */ 2272 if (pcinfo[i].freq == target) { 2273 idx_l = idx_r = i; 2274 goto done; 2275 } 2276 2277 /* We found a calibration pier that's above 2278 * frequency, use this pier and the previous 2279 * one to interpolate */ 2280 if (target < pcinfo[i].freq) { 2281 idx_r = i; 2282 idx_l = idx_r - 1; 2283 goto done; 2284 } 2285 } 2286 2287 done: 2288 *pcinfo_l = &pcinfo[idx_l]; 2289 *pcinfo_r = &pcinfo[idx_r]; 2290 } 2291 2292 /* 2293 * Get the surrounding per-rate power calibration data 2294 * for a given frequency and interpolate between power 2295 * values to set max target power supported by hw for 2296 * each rate. 2297 */ 2298 static void 2299 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2300 struct ieee80211_channel *channel, 2301 struct ath5k_rate_pcal_info *rates) 2302 { 2303 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2304 struct ath5k_rate_pcal_info *rpinfo; 2305 u8 idx_l, idx_r; 2306 u8 mode, max, i; 2307 u32 target = channel->center_freq; 2308 2309 idx_l = 0; 2310 idx_r = 0; 2311 2312 switch (channel->hw_value) { 2313 case AR5K_MODE_11A: 2314 rpinfo = ee->ee_rate_tpwr_a; 2315 mode = AR5K_EEPROM_MODE_11A; 2316 break; 2317 case AR5K_MODE_11B: 2318 rpinfo = ee->ee_rate_tpwr_b; 2319 mode = AR5K_EEPROM_MODE_11B; 2320 break; 2321 case AR5K_MODE_11G: 2322 default: 2323 rpinfo = ee->ee_rate_tpwr_g; 2324 mode = AR5K_EEPROM_MODE_11G; 2325 break; 2326 } 2327 max = ee->ee_rate_target_pwr_num[mode] - 1; 2328 2329 /* Get the surrounding calibration 2330 * piers - same as above */ 2331 if (target < rpinfo[0].freq) { 2332 idx_l = idx_r = 0; 2333 goto done; 2334 } 2335 2336 if (target > rpinfo[max].freq) { 2337 idx_l = idx_r = max; 2338 goto done; 2339 } 2340 2341 for (i = 0; i <= max; i++) { 2342 2343 if (rpinfo[i].freq == target) { 2344 idx_l = idx_r = i; 2345 goto done; 2346 } 2347 2348 if (target < rpinfo[i].freq) { 2349 idx_r = i; 2350 idx_l = idx_r - 1; 2351 goto done; 2352 } 2353 } 2354 2355 done: 2356 /* Now interpolate power value, based on the frequency */ 2357 rates->freq = target; 2358 2359 rates->target_power_6to24 = 2360 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2361 rpinfo[idx_r].freq, 2362 rpinfo[idx_l].target_power_6to24, 2363 rpinfo[idx_r].target_power_6to24); 2364 2365 rates->target_power_36 = 2366 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2367 rpinfo[idx_r].freq, 2368 rpinfo[idx_l].target_power_36, 2369 rpinfo[idx_r].target_power_36); 2370 2371 rates->target_power_48 = 2372 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2373 rpinfo[idx_r].freq, 2374 rpinfo[idx_l].target_power_48, 2375 rpinfo[idx_r].target_power_48); 2376 2377 rates->target_power_54 = 2378 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2379 rpinfo[idx_r].freq, 2380 rpinfo[idx_l].target_power_54, 2381 rpinfo[idx_r].target_power_54); 2382 } 2383 2384 /* 2385 * Get the max edge power for this channel if 2386 * we have such data from EEPROM's Conformance Test 2387 * Limits (CTL), and limit max power if needed. 2388 */ 2389 static void 2390 ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2391 struct ieee80211_channel *channel) 2392 { 2393 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2394 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2395 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2396 u8 *ctl_val = ee->ee_ctl; 2397 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2398 s16 edge_pwr = 0; 2399 u8 rep_idx; 2400 u8 i, ctl_mode; 2401 u8 ctl_idx = 0xFF; 2402 u32 target = channel->center_freq; 2403 2404 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2405 2406 switch (channel->hw_value) { 2407 case AR5K_MODE_11A: 2408 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2409 ctl_mode |= AR5K_CTL_TURBO; 2410 else 2411 ctl_mode |= AR5K_CTL_11A; 2412 break; 2413 case AR5K_MODE_11G: 2414 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2415 ctl_mode |= AR5K_CTL_TURBOG; 2416 else 2417 ctl_mode |= AR5K_CTL_11G; 2418 break; 2419 case AR5K_MODE_11B: 2420 ctl_mode |= AR5K_CTL_11B; 2421 break; 2422 default: 2423 return; 2424 } 2425 2426 for (i = 0; i < ee->ee_ctls; i++) { 2427 if (ctl_val[i] == ctl_mode) { 2428 ctl_idx = i; 2429 break; 2430 } 2431 } 2432 2433 /* If we have a CTL dataset available grab it and find the 2434 * edge power for our frequency */ 2435 if (ctl_idx == 0xFF) 2436 return; 2437 2438 /* Edge powers are sorted by frequency from lower 2439 * to higher. Each CTL corresponds to 8 edge power 2440 * measurements. */ 2441 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2442 2443 /* Don't do boundaries check because we 2444 * might have more that one bands defined 2445 * for this mode */ 2446 2447 /* Get the edge power that's closer to our 2448 * frequency */ 2449 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2450 rep_idx += i; 2451 if (target <= rep[rep_idx].freq) 2452 edge_pwr = (s16) rep[rep_idx].edge; 2453 } 2454 2455 if (edge_pwr) 2456 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); 2457 } 2458 2459 2460 /* 2461 * Power to PCDAC table functions 2462 */ 2463 2464 /* 2465 * Fill Power to PCDAC table on RF5111 2466 * 2467 * No further processing is needed for RF5111, the only thing we have to 2468 * do is fill the values below and above calibration range since eeprom data 2469 * may not cover the entire PCDAC table. 2470 */ 2471 static void 2472 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2473 s16 *table_max) 2474 { 2475 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2476 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2477 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2478 s16 min_pwr, max_pwr; 2479 2480 /* Get table boundaries */ 2481 min_pwr = table_min[0]; 2482 pcdac_0 = pcdac_tmp[0]; 2483 2484 max_pwr = table_max[0]; 2485 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2486 2487 /* Extrapolate below minimum using pcdac_0 */ 2488 pcdac_i = 0; 2489 for (i = 0; i < min_pwr; i++) 2490 pcdac_out[pcdac_i++] = pcdac_0; 2491 2492 /* Copy values from pcdac_tmp */ 2493 pwr_idx = min_pwr; 2494 for (i = 0; pwr_idx <= max_pwr && 2495 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2496 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2497 pwr_idx++; 2498 } 2499 2500 /* Extrapolate above maximum */ 2501 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2502 pcdac_out[pcdac_i++] = pcdac_n; 2503 2504 } 2505 2506 /* 2507 * Combine available XPD Curves and fill Linear Power to PCDAC table 2508 * on RF5112 2509 * 2510 * RFX112 can have up to 2 curves (one for low txpower range and one for 2511 * higher txpower range). We need to put them both on pcdac_out and place 2512 * them in the correct location. In case we only have one curve available 2513 * just fit it on pcdac_out (it's supposed to cover the entire range of 2514 * available pwr levels since it's always the higher power curve). Extrapolate 2515 * below and above final table if needed. 2516 */ 2517 static void 2518 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2519 s16 *table_max, u8 pdcurves) 2520 { 2521 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2522 u8 *pcdac_low_pwr; 2523 u8 *pcdac_high_pwr; 2524 u8 *pcdac_tmp; 2525 u8 pwr; 2526 s16 max_pwr_idx; 2527 s16 min_pwr_idx; 2528 s16 mid_pwr_idx = 0; 2529 /* Edge flag turns on the 7nth bit on the PCDAC 2530 * to declare the higher power curve (force values 2531 * to be greater than 64). If we only have one curve 2532 * we don't need to set this, if we have 2 curves and 2533 * fill the table backwards this can also be used to 2534 * switch from higher power curve to lower power curve */ 2535 u8 edge_flag; 2536 int i; 2537 2538 /* When we have only one curve available 2539 * that's the higher power curve. If we have 2540 * two curves the first is the high power curve 2541 * and the next is the low power curve. */ 2542 if (pdcurves > 1) { 2543 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2544 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2545 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2546 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2547 2548 /* If table size goes beyond 31.5dB, keep the 2549 * upper 31.5dB range when setting tx power. 2550 * Note: 126 = 31.5 dB in quarter dB steps */ 2551 if (table_max[0] - table_min[1] > 126) 2552 min_pwr_idx = table_max[0] - 126; 2553 else 2554 min_pwr_idx = table_min[1]; 2555 2556 /* Since we fill table backwards 2557 * start from high power curve */ 2558 pcdac_tmp = pcdac_high_pwr; 2559 2560 edge_flag = 0x40; 2561 } else { 2562 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2563 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2564 min_pwr_idx = table_min[0]; 2565 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2566 pcdac_tmp = pcdac_high_pwr; 2567 edge_flag = 0; 2568 } 2569 2570 /* This is used when setting tx power*/ 2571 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; 2572 2573 /* Fill Power to PCDAC table backwards */ 2574 pwr = max_pwr_idx; 2575 for (i = 63; i >= 0; i--) { 2576 /* Entering lower power range, reset 2577 * edge flag and set pcdac_tmp to lower 2578 * power curve.*/ 2579 if (edge_flag == 0x40 && 2580 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2581 edge_flag = 0x00; 2582 pcdac_tmp = pcdac_low_pwr; 2583 pwr = mid_pwr_idx / 2; 2584 } 2585 2586 /* Don't go below 1, extrapolate below if we have 2587 * already switched to the lower power curve -or 2588 * we only have one curve and edge_flag is zero 2589 * anyway */ 2590 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2591 while (i >= 0) { 2592 pcdac_out[i] = pcdac_out[i + 1]; 2593 i--; 2594 } 2595 break; 2596 } 2597 2598 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2599 2600 /* Extrapolate above if pcdac is greater than 2601 * 126 -this can happen because we OR pcdac_out 2602 * value with edge_flag on high power curve */ 2603 if (pcdac_out[i] > 126) 2604 pcdac_out[i] = 126; 2605 2606 /* Decrease by a 0.5dB step */ 2607 pwr--; 2608 } 2609 } 2610 2611 /* Write PCDAC values on hw */ 2612 static void 2613 ath5k_write_pcdac_table(struct ath5k_hw *ah) 2614 { 2615 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2616 int i; 2617 2618 /* 2619 * Write TX power values 2620 */ 2621 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2622 ath5k_hw_reg_write(ah, 2623 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) | 2624 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16), 2625 AR5K_PHY_PCDAC_TXPOWER(i)); 2626 } 2627 } 2628 2629 2630 /* 2631 * Power to PDADC table functions 2632 */ 2633 2634 /* 2635 * Set the gain boundaries and create final Power to PDADC table 2636 * 2637 * We can have up to 4 pd curves, we need to do a similar process 2638 * as we do for RF5112. This time we don't have an edge_flag but we 2639 * set the gain boundaries on a separate register. 2640 */ 2641 static void 2642 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2643 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2644 { 2645 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2646 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2647 u8 *pdadc_tmp; 2648 s16 pdadc_0; 2649 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2650 u8 pd_gain_overlap; 2651 2652 /* Note: Register value is initialized on initvals 2653 * there is no feedback from hw. 2654 * XXX: What about pd_gain_overlap from EEPROM ? */ 2655 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2656 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2657 2658 /* Create final PDADC table */ 2659 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2660 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2661 2662 if (pdg == pdcurves - 1) 2663 /* 2 dB boundary stretch for last 2664 * (higher power) curve */ 2665 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2666 else 2667 /* Set gain boundary in the middle 2668 * between this curve and the next one */ 2669 gain_boundaries[pdg] = 2670 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2671 2672 /* Sanity check in case our 2 db stretch got out of 2673 * range. */ 2674 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2675 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2676 2677 /* For the first curve (lower power) 2678 * start from 0 dB */ 2679 if (pdg == 0) 2680 pdadc_0 = 0; 2681 else 2682 /* For the other curves use the gain overlap */ 2683 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2684 pd_gain_overlap; 2685 2686 /* Force each power step to be at least 0.5 dB */ 2687 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2688 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2689 else 2690 pwr_step = 1; 2691 2692 /* If pdadc_0 is negative, we need to extrapolate 2693 * below this pdgain by a number of pwr_steps */ 2694 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2695 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2696 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2697 pdadc_0++; 2698 } 2699 2700 /* Set last pwr level, using gain boundaries */ 2701 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2702 /* Limit it to be inside pwr range */ 2703 table_size = pwr_max[pdg] - pwr_min[pdg]; 2704 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2705 2706 /* Fill pdadc_out table */ 2707 while (pdadc_0 < max_idx && pdadc_i < 128) 2708 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2709 2710 /* Need to extrapolate above this pdgain? */ 2711 if (pdadc_n <= max_idx) 2712 continue; 2713 2714 /* Force each power step to be at least 0.5 dB */ 2715 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2716 pwr_step = pdadc_tmp[table_size - 1] - 2717 pdadc_tmp[table_size - 2]; 2718 else 2719 pwr_step = 1; 2720 2721 /* Extrapolate above */ 2722 while ((pdadc_0 < (s16) pdadc_n) && 2723 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2724 s16 tmp = pdadc_tmp[table_size - 1] + 2725 (pdadc_0 - max_idx) * pwr_step; 2726 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2727 pdadc_0++; 2728 } 2729 } 2730 2731 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2732 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2733 pdg++; 2734 } 2735 2736 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2737 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2738 pdadc_i++; 2739 } 2740 2741 /* Set gain boundaries */ 2742 ath5k_hw_reg_write(ah, 2743 AR5K_REG_SM(pd_gain_overlap, 2744 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2745 AR5K_REG_SM(gain_boundaries[0], 2746 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2747 AR5K_REG_SM(gain_boundaries[1], 2748 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2749 AR5K_REG_SM(gain_boundaries[2], 2750 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2751 AR5K_REG_SM(gain_boundaries[3], 2752 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2753 AR5K_PHY_TPC_RG5); 2754 2755 /* Used for setting rate power table */ 2756 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2757 2758 } 2759 2760 /* Write PDADC values on hw */ 2761 static void 2762 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) 2763 { 2764 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2765 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2766 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2767 u8 pdcurves = ee->ee_pd_gains[ee_mode]; 2768 u32 reg; 2769 u8 i; 2770 2771 /* Select the right pdgain curves */ 2772 2773 /* Clear current settings */ 2774 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2775 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2776 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2777 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2778 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2779 2780 /* 2781 * Use pd_gains curve from eeprom 2782 * 2783 * This overrides the default setting from initvals 2784 * in case some vendors (e.g. Zcomax) don't use the default 2785 * curves. If we don't honor their settings we 'll get a 2786 * 5dB (1 * gain overlap ?) drop. 2787 */ 2788 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2789 2790 switch (pdcurves) { 2791 case 3: 2792 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2793 /* Fall through */ 2794 case 2: 2795 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2796 /* Fall through */ 2797 case 1: 2798 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2799 break; 2800 } 2801 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2802 2803 /* 2804 * Write TX power values 2805 */ 2806 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2807 u32 val = get_unaligned_le32(&pdadc_out[4 * i]); 2808 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); 2809 } 2810 } 2811 2812 2813 /* 2814 * Common code for PCDAC/PDADC tables 2815 */ 2816 2817 /* 2818 * This is the main function that uses all of the above 2819 * to set PCDAC/PDADC table on hw for the current channel. 2820 * This table is used for tx power calibration on the baseband, 2821 * without it we get weird tx power levels and in some cases 2822 * distorted spectral mask 2823 */ 2824 static int 2825 ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2826 struct ieee80211_channel *channel, 2827 u8 ee_mode, u8 type) 2828 { 2829 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2830 struct ath5k_chan_pcal_info *pcinfo_L; 2831 struct ath5k_chan_pcal_info *pcinfo_R; 2832 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2833 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2834 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2835 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2836 u8 *tmpL; 2837 u8 *tmpR; 2838 u32 target = channel->center_freq; 2839 int pdg, i; 2840 2841 /* Get surrounding freq piers for this channel */ 2842 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2843 &pcinfo_L, 2844 &pcinfo_R); 2845 2846 /* Loop over pd gain curves on 2847 * surrounding freq piers by index */ 2848 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2849 2850 /* Fill curves in reverse order 2851 * from lower power (max gain) 2852 * to higher power. Use curve -> idx 2853 * backmapping we did on eeprom init */ 2854 u8 idx = pdg_curve_to_idx[pdg]; 2855 2856 /* Grab the needed curves by index */ 2857 pdg_L = &pcinfo_L->pd_curves[idx]; 2858 pdg_R = &pcinfo_R->pd_curves[idx]; 2859 2860 /* Initialize the temp tables */ 2861 tmpL = ah->ah_txpower.tmpL[pdg]; 2862 tmpR = ah->ah_txpower.tmpR[pdg]; 2863 2864 /* Set curve's x boundaries and create 2865 * curves so that they cover the same 2866 * range (if we don't do that one table 2867 * will have values on some range and the 2868 * other one won't have any so interpolation 2869 * will fail) */ 2870 table_min[pdg] = min(pdg_L->pd_pwr[0], 2871 pdg_R->pd_pwr[0]) / 2; 2872 2873 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2874 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2875 2876 /* Now create the curves on surrounding channels 2877 * and interpolate if needed to get the final 2878 * curve for this gain on this channel */ 2879 switch (type) { 2880 case AR5K_PWRTABLE_LINEAR_PCDAC: 2881 /* Override min/max so that we don't loose 2882 * accuracy (don't divide by 2) */ 2883 table_min[pdg] = min(pdg_L->pd_pwr[0], 2884 pdg_R->pd_pwr[0]); 2885 2886 table_max[pdg] = 2887 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2888 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2889 2890 /* Override minimum so that we don't get 2891 * out of bounds while extrapolating 2892 * below. Don't do this when we have 2 2893 * curves and we are on the high power curve 2894 * because table_min is ok in this case */ 2895 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2896 2897 table_min[pdg] = 2898 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2899 pdg_R->pd_step, 2900 pdg_L->pd_pwr, 2901 pdg_R->pd_pwr); 2902 2903 /* Don't go too low because we will 2904 * miss the upper part of the curve. 2905 * Note: 126 = 31.5dB (max power supported) 2906 * in 0.25dB units */ 2907 if (table_max[pdg] - table_min[pdg] > 126) 2908 table_min[pdg] = table_max[pdg] - 126; 2909 } 2910 2911 /* Fall through */ 2912 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2913 case AR5K_PWRTABLE_PWR_TO_PDADC: 2914 2915 ath5k_create_power_curve(table_min[pdg], 2916 table_max[pdg], 2917 pdg_L->pd_pwr, 2918 pdg_L->pd_step, 2919 pdg_L->pd_points, tmpL, type); 2920 2921 /* We are in a calibration 2922 * pier, no need to interpolate 2923 * between freq piers */ 2924 if (pcinfo_L == pcinfo_R) 2925 continue; 2926 2927 ath5k_create_power_curve(table_min[pdg], 2928 table_max[pdg], 2929 pdg_R->pd_pwr, 2930 pdg_R->pd_step, 2931 pdg_R->pd_points, tmpR, type); 2932 break; 2933 default: 2934 return -EINVAL; 2935 } 2936 2937 /* Interpolate between curves 2938 * of surrounding freq piers to 2939 * get the final curve for this 2940 * pd gain. Re-use tmpL for interpolation 2941 * output */ 2942 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2943 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2944 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2945 (s16) pcinfo_L->freq, 2946 (s16) pcinfo_R->freq, 2947 (s16) tmpL[i], 2948 (s16) tmpR[i]); 2949 } 2950 } 2951 2952 /* Now we have a set of curves for this 2953 * channel on tmpL (x range is table_max - table_min 2954 * and y values are tmpL[pdg][]) sorted in the same 2955 * order as EEPROM (because we've used the backmapping). 2956 * So for RF5112 it's from higher power to lower power 2957 * and for RF2413 it's from lower power to higher power. 2958 * For RF5111 we only have one curve. */ 2959 2960 /* Fill min and max power levels for this 2961 * channel by interpolating the values on 2962 * surrounding channels to complete the dataset */ 2963 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 2964 (s16) pcinfo_L->freq, 2965 (s16) pcinfo_R->freq, 2966 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 2967 2968 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 2969 (s16) pcinfo_L->freq, 2970 (s16) pcinfo_R->freq, 2971 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 2972 2973 /* Fill PCDAC/PDADC table */ 2974 switch (type) { 2975 case AR5K_PWRTABLE_LINEAR_PCDAC: 2976 /* For RF5112 we can have one or two curves 2977 * and each curve covers a certain power lvl 2978 * range so we need to do some more processing */ 2979 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 2980 ee->ee_pd_gains[ee_mode]); 2981 2982 /* Set txp.offset so that we can 2983 * match max power value with max 2984 * table index */ 2985 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 2986 break; 2987 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2988 /* We are done for RF5111 since it has only 2989 * one curve, just fit the curve on the table */ 2990 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 2991 2992 /* No rate powertable adjustment for RF5111 */ 2993 ah->ah_txpower.txp_min_idx = 0; 2994 ah->ah_txpower.txp_offset = 0; 2995 break; 2996 case AR5K_PWRTABLE_PWR_TO_PDADC: 2997 /* Set PDADC boundaries and fill 2998 * final PDADC table */ 2999 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 3000 ee->ee_pd_gains[ee_mode]); 3001 3002 /* Set txp.offset, note that table_min 3003 * can be negative */ 3004 ah->ah_txpower.txp_offset = table_min[0]; 3005 break; 3006 default: 3007 return -EINVAL; 3008 } 3009 3010 ah->ah_txpower.txp_setup = true; 3011 3012 return 0; 3013 } 3014 3015 /* Write power table for current channel to hw */ 3016 static void 3017 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) 3018 { 3019 if (type == AR5K_PWRTABLE_PWR_TO_PDADC) 3020 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); 3021 else 3022 ath5k_write_pcdac_table(ah); 3023 } 3024 3025 /* 3026 * Per-rate tx power setting 3027 * 3028 * This is the code that sets the desired tx power (below 3029 * maximum) on hw for each rate (we also have TPC that sets 3030 * power per packet). We do that by providing an index on the 3031 * PCDAC/PDADC table we set up. 3032 */ 3033 3034 /* 3035 * Set rate power table 3036 * 3037 * For now we only limit txpower based on maximum tx power 3038 * supported by hw (what's inside rate_info). We need to limit 3039 * this even more, based on regulatory domain etc. 3040 * 3041 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3042 * and is indexed as follows: 3043 * rates[0] - rates[7] -> OFDM rates 3044 * rates[8] - rates[14] -> CCK rates 3045 * rates[15] -> XR rates (they all have the same power) 3046 */ 3047 static void 3048 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3049 struct ath5k_rate_pcal_info *rate_info, 3050 u8 ee_mode) 3051 { 3052 unsigned int i; 3053 u16 *rates; 3054 3055 /* max_pwr is power level we got from driver/user in 0.5dB 3056 * units, switch to 0.25dB units so we can compare */ 3057 max_pwr *= 2; 3058 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3059 3060 /* apply rate limits */ 3061 rates = ah->ah_txpower.txp_rates_power_table; 3062 3063 /* OFDM rates 6 to 24Mb/s */ 3064 for (i = 0; i < 5; i++) 3065 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3066 3067 /* Rest OFDM rates */ 3068 rates[5] = min(rates[0], rate_info->target_power_36); 3069 rates[6] = min(rates[0], rate_info->target_power_48); 3070 rates[7] = min(rates[0], rate_info->target_power_54); 3071 3072 /* CCK rates */ 3073 /* 1L */ 3074 rates[8] = min(rates[0], rate_info->target_power_6to24); 3075 /* 2L */ 3076 rates[9] = min(rates[0], rate_info->target_power_36); 3077 /* 2S */ 3078 rates[10] = min(rates[0], rate_info->target_power_36); 3079 /* 5L */ 3080 rates[11] = min(rates[0], rate_info->target_power_48); 3081 /* 5S */ 3082 rates[12] = min(rates[0], rate_info->target_power_48); 3083 /* 11L */ 3084 rates[13] = min(rates[0], rate_info->target_power_54); 3085 /* 11S */ 3086 rates[14] = min(rates[0], rate_info->target_power_54); 3087 3088 /* XR rates */ 3089 rates[15] = min(rates[0], rate_info->target_power_6to24); 3090 3091 /* CCK rates have different peak to average ratio 3092 * so we have to tweak their power so that gainf 3093 * correction works ok. For this we use OFDM to 3094 * CCK delta from eeprom */ 3095 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3096 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3097 for (i = 8; i <= 15; i++) 3098 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3099 3100 /* Now that we have all rates setup use table offset to 3101 * match the power range set by user with the power indices 3102 * on PCDAC/PDADC table */ 3103 for (i = 0; i < 16; i++) { 3104 rates[i] += ah->ah_txpower.txp_offset; 3105 /* Don't get out of bounds */ 3106 if (rates[i] > 63) 3107 rates[i] = 63; 3108 } 3109 3110 /* Min/max in 0.25dB units */ 3111 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3112 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; 3113 ah->ah_txpower.txp_ofdm = rates[7]; 3114 } 3115 3116 3117 /* 3118 * Set transmission power 3119 */ 3120 static int 3121 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3122 u8 txpower) 3123 { 3124 struct ath5k_rate_pcal_info rate_info; 3125 struct ieee80211_channel *curr_channel = ah->ah_current_channel; 3126 int ee_mode; 3127 u8 type; 3128 int ret; 3129 3130 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3131 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); 3132 return -EINVAL; 3133 } 3134 3135 ee_mode = ath5k_eeprom_mode_from_channel(channel); 3136 if (ee_mode < 0) { 3137 ATH5K_ERR(ah, 3138 "invalid channel: %d\n", channel->center_freq); 3139 return -EINVAL; 3140 } 3141 3142 /* Initialize TX power table */ 3143 switch (ah->ah_radio) { 3144 case AR5K_RF5110: 3145 /* TODO */ 3146 return 0; 3147 case AR5K_RF5111: 3148 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3149 break; 3150 case AR5K_RF5112: 3151 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3152 break; 3153 case AR5K_RF2413: 3154 case AR5K_RF5413: 3155 case AR5K_RF2316: 3156 case AR5K_RF2317: 3157 case AR5K_RF2425: 3158 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3159 break; 3160 default: 3161 return -EINVAL; 3162 } 3163 3164 /* 3165 * If we don't change channel/mode skip tx powertable calculation 3166 * and use the cached one. 3167 */ 3168 if (!ah->ah_txpower.txp_setup || 3169 (channel->hw_value != curr_channel->hw_value) || 3170 (channel->center_freq != curr_channel->center_freq)) { 3171 /* Reset TX power values */ 3172 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3173 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3174 3175 /* Calculate the powertable */ 3176 ret = ath5k_setup_channel_powertable(ah, channel, 3177 ee_mode, type); 3178 if (ret) 3179 return ret; 3180 } 3181 3182 /* Write table on hw */ 3183 ath5k_write_channel_powertable(ah, ee_mode, type); 3184 3185 /* Limit max power if we have a CTL available */ 3186 ath5k_get_max_ctl_power(ah, channel); 3187 3188 /* FIXME: Antenna reduction stuff */ 3189 3190 /* FIXME: Limit power on turbo modes */ 3191 3192 /* FIXME: TPC scale reduction */ 3193 3194 /* Get surrounding channels for per-rate power table 3195 * calibration */ 3196 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3197 3198 /* Setup rate power table */ 3199 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3200 3201 /* Write rate power table on hw */ 3202 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3203 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3204 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3205 3206 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3207 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3208 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3209 3210 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3211 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3212 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3213 3214 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3215 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3216 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3217 3218 /* FIXME: TPC support */ 3219 if (ah->ah_txpower.txp_tpc) { 3220 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3221 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3222 3223 ath5k_hw_reg_write(ah, 3224 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3225 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3226 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3227 AR5K_TPC); 3228 } else { 3229 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3230 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3231 } 3232 3233 return 0; 3234 } 3235 3236 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3237 { 3238 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, 3239 "changing txpower to %d\n", txpower); 3240 3241 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3242 } 3243 3244 /*************\ 3245 Init function 3246 \*************/ 3247 3248 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3249 u8 mode, bool fast) 3250 { 3251 struct ieee80211_channel *curr_channel; 3252 int ret, i; 3253 u32 phy_tst1; 3254 ret = 0; 3255 3256 /* 3257 * Sanity check for fast flag 3258 * Don't try fast channel change when changing modulation 3259 * mode/band. We check for chip compatibility on 3260 * ath5k_hw_reset. 3261 */ 3262 curr_channel = ah->ah_current_channel; 3263 if (fast && (channel->hw_value != curr_channel->hw_value)) 3264 return -EINVAL; 3265 3266 /* 3267 * On fast channel change we only set the synth parameters 3268 * while PHY is running, enable calibration and skip the rest. 3269 */ 3270 if (fast) { 3271 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3272 AR5K_PHY_RFBUS_REQ_REQUEST); 3273 for (i = 0; i < 100; i++) { 3274 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) 3275 break; 3276 udelay(5); 3277 } 3278 /* Failed */ 3279 if (i >= 100) 3280 return -EIO; 3281 3282 /* Set channel and wait for synth */ 3283 ret = ath5k_hw_channel(ah, channel); 3284 if (ret) 3285 return ret; 3286 3287 ath5k_hw_wait_for_synth(ah, channel); 3288 } 3289 3290 /* 3291 * Set TX power 3292 * 3293 * Note: We need to do that before we set 3294 * RF buffer settings on 5211/5212+ so that we 3295 * properly set curve indices. 3296 */ 3297 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ? 3298 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER); 3299 if (ret) 3300 return ret; 3301 3302 /* Write OFDM timings on 5212*/ 3303 if (ah->ah_version == AR5K_AR5212 && 3304 channel->hw_value != AR5K_MODE_11B) { 3305 3306 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3307 if (ret) 3308 return ret; 3309 3310 /* Spur info is available only from EEPROM versions 3311 * greater than 5.3, but the EEPROM routines will use 3312 * static values for older versions */ 3313 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3314 ath5k_hw_set_spur_mitigation_filter(ah, 3315 channel); 3316 } 3317 3318 /* If we used fast channel switching 3319 * we are done, release RF bus and 3320 * fire up NF calibration. 3321 * 3322 * Note: Only NF calibration due to 3323 * channel change, not AGC calibration 3324 * since AGC is still running ! 3325 */ 3326 if (fast) { 3327 /* 3328 * Release RF Bus grant 3329 */ 3330 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3331 AR5K_PHY_RFBUS_REQ_REQUEST); 3332 3333 /* 3334 * Start NF calibration 3335 */ 3336 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3337 AR5K_PHY_AGCCTL_NF); 3338 3339 return ret; 3340 } 3341 3342 /* 3343 * For 5210 we do all initialization using 3344 * initvals, so we don't have to modify 3345 * any settings (5210 also only supports 3346 * a/aturbo modes) 3347 */ 3348 if (ah->ah_version != AR5K_AR5210) { 3349 3350 /* 3351 * Write initial RF gain settings 3352 * This should work for both 5111/5112 3353 */ 3354 ret = ath5k_hw_rfgain_init(ah, channel->band); 3355 if (ret) 3356 return ret; 3357 3358 mdelay(1); 3359 3360 /* 3361 * Write RF buffer 3362 */ 3363 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3364 if (ret) 3365 return ret; 3366 3367 /*Enable/disable 802.11b mode on 5111 3368 (enable 2111 frequency converter + CCK)*/ 3369 if (ah->ah_radio == AR5K_RF5111) { 3370 if (mode == AR5K_MODE_11B) 3371 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3372 AR5K_TXCFG_B_MODE); 3373 else 3374 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3375 AR5K_TXCFG_B_MODE); 3376 } 3377 3378 } else if (ah->ah_version == AR5K_AR5210) { 3379 mdelay(1); 3380 /* Disable phy and wait */ 3381 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3382 mdelay(1); 3383 } 3384 3385 /* Set channel on PHY */ 3386 ret = ath5k_hw_channel(ah, channel); 3387 if (ret) 3388 return ret; 3389 3390 /* 3391 * Enable the PHY and wait until completion 3392 * This includes BaseBand and Synthesizer 3393 * activation. 3394 */ 3395 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3396 3397 ath5k_hw_wait_for_synth(ah, channel); 3398 3399 /* 3400 * Perform ADC test to see if baseband is ready 3401 * Set tx hold and check adc test register 3402 */ 3403 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3404 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3405 for (i = 0; i <= 20; i++) { 3406 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3407 break; 3408 udelay(200); 3409 } 3410 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3411 3412 /* 3413 * Start automatic gain control calibration 3414 * 3415 * During AGC calibration RX path is re-routed to 3416 * a power detector so we don't receive anything. 3417 * 3418 * This method is used to calibrate some static offsets 3419 * used together with on-the fly I/Q calibration (the 3420 * one performed via ath5k_hw_phy_calibrate), which doesn't 3421 * interrupt rx path. 3422 * 3423 * While rx path is re-routed to the power detector we also 3424 * start a noise floor calibration to measure the 3425 * card's noise floor (the noise we measure when we are not 3426 * transmitting or receiving anything). 3427 * 3428 * If we are in a noisy environment, AGC calibration may time 3429 * out and/or noise floor calibration might timeout. 3430 */ 3431 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3432 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3433 3434 /* At the same time start I/Q calibration for QAM constellation 3435 * -no need for CCK- */ 3436 ah->ah_calibration = false; 3437 if (!(mode == AR5K_MODE_11B)) { 3438 ah->ah_calibration = true; 3439 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3440 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3441 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3442 AR5K_PHY_IQ_RUN); 3443 } 3444 3445 /* Wait for gain calibration to finish (we check for I/Q calibration 3446 * during ath5k_phy_calibrate) */ 3447 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3448 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3449 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", 3450 channel->center_freq); 3451 } 3452 3453 /* Restore antenna mode */ 3454 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3455 3456 return ret; 3457 } 3458