1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 /*********************************\ 24 * Protocol Control Unit Functions * 25 \*********************************/ 26 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "debug.h" 32 33 /** 34 * DOC: Protocol Control Unit (PCU) functions 35 * 36 * Protocol control unit is responsible to maintain various protocol 37 * properties before a frame is send and after a frame is received to/from 38 * baseband. To be more specific, PCU handles: 39 * 40 * - Buffering of RX and TX frames (after QCU/DCUs) 41 * 42 * - Encrypting and decrypting (using the built-in engine) 43 * 44 * - Generating ACKs, RTS/CTS frames 45 * 46 * - Maintaining TSF 47 * 48 * - FCS 49 * 50 * - Updating beacon data (with TSF etc) 51 * 52 * - Generating virtual CCA 53 * 54 * - RX/Multicast filtering 55 * 56 * - BSSID filtering 57 * 58 * - Various statistics 59 * 60 * -Different operating modes: AP, STA, IBSS 61 * 62 * Note: Most of these functions can be tweaked/bypassed so you can do 63 * them on sw above for debugging or research. For more infos check out PCU 64 * registers on reg.h. 65 */ 66 67 /** 68 * DOC: ACK rates 69 * 70 * AR5212+ can use higher rates for ack transmission 71 * based on current tx rate instead of the base rate. 72 * It does this to better utilize channel usage. 73 * There is a mapping between G rates (that cover both 74 * CCK and OFDM) and ack rates that we use when setting 75 * rate -> duration table. This mapping is hw-based so 76 * don't change anything. 77 * 78 * To enable this functionality we must set 79 * ah->ah_ack_bitrate_high to true else base rate is 80 * used (1Mb for CCK, 6Mb for OFDM). 81 */ 82 static const unsigned int ack_rates_high[] = 83 /* Tx -> ACK */ 84 /* 1Mb -> 1Mb */ { 0, 85 /* 2MB -> 2Mb */ 1, 86 /* 5.5Mb -> 2Mb */ 1, 87 /* 11Mb -> 2Mb */ 1, 88 /* 6Mb -> 6Mb */ 4, 89 /* 9Mb -> 6Mb */ 4, 90 /* 12Mb -> 12Mb */ 6, 91 /* 18Mb -> 12Mb */ 6, 92 /* 24Mb -> 24Mb */ 8, 93 /* 36Mb -> 24Mb */ 8, 94 /* 48Mb -> 24Mb */ 8, 95 /* 54Mb -> 24Mb */ 8 }; 96 97 /*******************\ 98 * Helper functions * 99 \*******************/ 100 101 /** 102 * ath5k_hw_get_frame_duration() - Get tx time of a frame 103 * @ah: The &struct ath5k_hw 104 * @len: Frame's length in bytes 105 * @rate: The @struct ieee80211_rate 106 * @shortpre: Indicate short preample 107 * 108 * Calculate tx duration of a frame given it's rate and length 109 * It extends ieee80211_generic_frame_duration for non standard 110 * bwmodes. 111 */ 112 int 113 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum ieee80211_band band, 114 int len, struct ieee80211_rate *rate, bool shortpre) 115 { 116 int sifs, preamble, plcp_bits, sym_time; 117 int bitrate, bits, symbols, symbol_bits; 118 int dur; 119 120 /* Fallback */ 121 if (!ah->ah_bwmode) { 122 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, 123 NULL, band, len, rate); 124 125 /* subtract difference between long and short preamble */ 126 dur = le16_to_cpu(raw_dur); 127 if (shortpre) 128 dur -= 96; 129 130 return dur; 131 } 132 133 bitrate = rate->bitrate; 134 preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; 135 plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; 136 sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; 137 138 switch (ah->ah_bwmode) { 139 case AR5K_BWMODE_40MHZ: 140 sifs = AR5K_INIT_SIFS_TURBO; 141 preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; 142 break; 143 case AR5K_BWMODE_10MHZ: 144 sifs = AR5K_INIT_SIFS_HALF_RATE; 145 preamble *= 2; 146 sym_time *= 2; 147 break; 148 case AR5K_BWMODE_5MHZ: 149 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 150 preamble *= 4; 151 sym_time *= 4; 152 break; 153 default: 154 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 155 break; 156 } 157 158 bits = plcp_bits + (len << 3); 159 /* Bit rate is in 100Kbits */ 160 symbol_bits = bitrate * sym_time; 161 symbols = DIV_ROUND_UP(bits * 10, symbol_bits); 162 163 dur = sifs + preamble + (sym_time * symbols); 164 165 return dur; 166 } 167 168 /** 169 * ath5k_hw_get_default_slottime() - Get the default slot time for current mode 170 * @ah: The &struct ath5k_hw 171 */ 172 unsigned int 173 ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 174 { 175 struct ieee80211_channel *channel = ah->ah_current_channel; 176 unsigned int slot_time; 177 178 switch (ah->ah_bwmode) { 179 case AR5K_BWMODE_40MHZ: 180 slot_time = AR5K_INIT_SLOT_TIME_TURBO; 181 break; 182 case AR5K_BWMODE_10MHZ: 183 slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; 184 break; 185 case AR5K_BWMODE_5MHZ: 186 slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; 187 break; 188 case AR5K_BWMODE_DEFAULT: 189 default: 190 slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; 191 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) 192 slot_time = AR5K_INIT_SLOT_TIME_B; 193 break; 194 } 195 196 return slot_time; 197 } 198 199 /** 200 * ath5k_hw_get_default_sifs() - Get the default SIFS for current mode 201 * @ah: The &struct ath5k_hw 202 */ 203 unsigned int 204 ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 205 { 206 struct ieee80211_channel *channel = ah->ah_current_channel; 207 unsigned int sifs; 208 209 switch (ah->ah_bwmode) { 210 case AR5K_BWMODE_40MHZ: 211 sifs = AR5K_INIT_SIFS_TURBO; 212 break; 213 case AR5K_BWMODE_10MHZ: 214 sifs = AR5K_INIT_SIFS_HALF_RATE; 215 break; 216 case AR5K_BWMODE_5MHZ: 217 sifs = AR5K_INIT_SIFS_QUARTER_RATE; 218 break; 219 case AR5K_BWMODE_DEFAULT: 220 sifs = AR5K_INIT_SIFS_DEFAULT_BG; 221 default: 222 if (channel->band == IEEE80211_BAND_5GHZ) 223 sifs = AR5K_INIT_SIFS_DEFAULT_A; 224 break; 225 } 226 227 return sifs; 228 } 229 230 /** 231 * ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics) 232 * @ah: The &struct ath5k_hw 233 * 234 * Reads MIB counters from PCU and updates sw statistics. Is called after a 235 * MIB interrupt, because one of these counters might have reached their maximum 236 * and triggered the MIB interrupt, to let us read and clear the counter. 237 * 238 * NOTE: Is called in interrupt context! 239 */ 240 void 241 ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 242 { 243 struct ath5k_statistics *stats = &ah->stats; 244 245 /* Read-And-Clear */ 246 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 247 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 248 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 249 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 250 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 251 } 252 253 254 /******************\ 255 * ACK/CTS Timeouts * 256 \******************/ 257 258 /** 259 * ath5k_hw_write_rate_duration() - Fill rate code to duration table 260 * @ah: The &struct ath5k_hw 261 * 262 * Write the rate code to duration table upon hw reset. This is a helper for 263 * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on 264 * the hardware, based on current mode, for each rate. The rates which are 265 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have 266 * different rate code so we write their value twice (one for long preamble 267 * and one for short). 268 * 269 * Note: Band doesn't matter here, if we set the values for OFDM it works 270 * on both a and g modes. So all we have to do is set values for all g rates 271 * that include all OFDM and CCK rates. 272 * 273 */ 274 static inline void 275 ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 276 { 277 struct ieee80211_rate *rate; 278 unsigned int i; 279 /* 802.11g covers both OFDM and CCK */ 280 u8 band = IEEE80211_BAND_2GHZ; 281 282 /* Write rate duration table */ 283 for (i = 0; i < ah->sbands[band].n_bitrates; i++) { 284 u32 reg; 285 u16 tx_time; 286 287 if (ah->ah_ack_bitrate_high) 288 rate = &ah->sbands[band].bitrates[ack_rates_high[i]]; 289 /* CCK -> 1Mb */ 290 else if (i < 4) 291 rate = &ah->sbands[band].bitrates[0]; 292 /* OFDM -> 6Mb */ 293 else 294 rate = &ah->sbands[band].bitrates[4]; 295 296 /* Set ACK timeout */ 297 reg = AR5K_RATE_DUR(rate->hw_value); 298 299 /* An ACK frame consists of 10 bytes. If you add the FCS, 300 * which ieee80211_generic_frame_duration() adds, 301 * its 14 bytes. Note we use the control rate and not the 302 * actual rate for this rate. See mac80211 tx.c 303 * ieee80211_duration() for a brief description of 304 * what rate we should choose to TX ACKs. */ 305 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, 306 rate, false); 307 308 ath5k_hw_reg_write(ah, tx_time, reg); 309 310 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) 311 continue; 312 313 tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true); 314 ath5k_hw_reg_write(ah, tx_time, 315 reg + (AR5K_SET_SHORT_PREAMBLE << 2)); 316 } 317 } 318 319 /** 320 * ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU 321 * @ah: The &struct ath5k_hw 322 * @timeout: Timeout in usec 323 */ 324 static int 325 ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 326 { 327 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 328 <= timeout) 329 return -EINVAL; 330 331 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 332 ath5k_hw_htoclock(ah, timeout)); 333 334 return 0; 335 } 336 337 /** 338 * ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU 339 * @ah: The &struct ath5k_hw 340 * @timeout: Timeout in usec 341 */ 342 static int 343 ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 344 { 345 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 346 <= timeout) 347 return -EINVAL; 348 349 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 350 ath5k_hw_htoclock(ah, timeout)); 351 352 return 0; 353 } 354 355 356 /*******************\ 357 * RX filter Control * 358 \*******************/ 359 360 /** 361 * ath5k_hw_set_lladdr() - Set station id 362 * @ah: The &struct ath5k_hw 363 * @mac: The card's mac address (array of octets) 364 * 365 * Set station id on hw using the provided mac address 366 */ 367 int 368 ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 369 { 370 struct ath_common *common = ath5k_hw_common(ah); 371 u32 low_id, high_id; 372 u32 pcu_reg; 373 374 /* Set new station ID */ 375 memcpy(common->macaddr, mac, ETH_ALEN); 376 377 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 378 379 low_id = get_unaligned_le32(mac); 380 high_id = get_unaligned_le16(mac + 4); 381 382 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 383 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 384 385 return 0; 386 } 387 388 /** 389 * ath5k_hw_set_bssid() - Set current BSSID on hw 390 * @ah: The &struct ath5k_hw 391 * 392 * Sets the current BSSID and BSSID mask we have from the 393 * common struct into the hardware 394 */ 395 void 396 ath5k_hw_set_bssid(struct ath5k_hw *ah) 397 { 398 struct ath_common *common = ath5k_hw_common(ah); 399 u16 tim_offset = 0; 400 401 /* 402 * Set BSSID mask on 5212 403 */ 404 if (ah->ah_version == AR5K_AR5212) 405 ath_hw_setbssidmask(common); 406 407 /* 408 * Set BSSID 409 */ 410 ath5k_hw_reg_write(ah, 411 get_unaligned_le32(common->curbssid), 412 AR5K_BSS_ID0); 413 ath5k_hw_reg_write(ah, 414 get_unaligned_le16(common->curbssid + 4) | 415 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 416 AR5K_BSS_ID1); 417 418 if (common->curaid == 0) { 419 ath5k_hw_disable_pspoll(ah); 420 return; 421 } 422 423 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 424 tim_offset ? tim_offset + 4 : 0); 425 426 ath5k_hw_enable_pspoll(ah, NULL, 0); 427 } 428 429 /** 430 * ath5k_hw_set_bssid_mask() - Filter out bssids we listen 431 * @ah: The &struct ath5k_hw 432 * @mask: The BSSID mask to set (array of octets) 433 * 434 * BSSID masking is a method used by AR5212 and newer hardware to inform PCU 435 * which bits of the interface's MAC address should be looked at when trying 436 * to decide which packets to ACK. In station mode and AP mode with a single 437 * BSS every bit matters since we lock to only one BSS. In AP mode with 438 * multiple BSSes (virtual interfaces) not every bit matters because hw must 439 * accept frames for all BSSes and so we tweak some bits of our mac address 440 * in order to have multiple BSSes. 441 * 442 * For more information check out ../hw.c of the common ath module. 443 */ 444 void 445 ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 446 { 447 struct ath_common *common = ath5k_hw_common(ah); 448 449 /* Cache bssid mask so that we can restore it 450 * on reset */ 451 memcpy(common->bssidmask, mask, ETH_ALEN); 452 if (ah->ah_version == AR5K_AR5212) 453 ath_hw_setbssidmask(common); 454 } 455 456 /** 457 * ath5k_hw_set_mcast_filter() - Set multicast filter 458 * @ah: The &struct ath5k_hw 459 * @filter0: Lower 32bits of muticast filter 460 * @filter1: Higher 16bits of multicast filter 461 */ 462 void 463 ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 464 { 465 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 466 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 467 } 468 469 /** 470 * ath5k_hw_get_rx_filter() - Get current rx filter 471 * @ah: The &struct ath5k_hw 472 * 473 * Returns the RX filter by reading rx filter and 474 * phy error filter registers. RX filter is used 475 * to set the allowed frame types that PCU will accept 476 * and pass to the driver. For a list of frame types 477 * check out reg.h. 478 */ 479 u32 480 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 481 { 482 u32 data, filter = 0; 483 484 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 485 486 /*Radar detection for 5212*/ 487 if (ah->ah_version == AR5K_AR5212) { 488 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 489 490 if (data & AR5K_PHY_ERR_FIL_RADAR) 491 filter |= AR5K_RX_FILTER_RADARERR; 492 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 493 filter |= AR5K_RX_FILTER_PHYERR; 494 } 495 496 return filter; 497 } 498 499 /** 500 * ath5k_hw_set_rx_filter() - Set rx filter 501 * @ah: The &struct ath5k_hw 502 * @filter: RX filter mask (see reg.h) 503 * 504 * Sets RX filter register and also handles PHY error filter 505 * register on 5212 and newer chips so that we have proper PHY 506 * error reporting. 507 */ 508 void 509 ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 510 { 511 u32 data = 0; 512 513 /* Set PHY error filter register on 5212*/ 514 if (ah->ah_version == AR5K_AR5212) { 515 if (filter & AR5K_RX_FILTER_RADARERR) 516 data |= AR5K_PHY_ERR_FIL_RADAR; 517 if (filter & AR5K_RX_FILTER_PHYERR) 518 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 519 } 520 521 /* 522 * The AR5210 uses promiscuous mode to detect radar activity 523 */ 524 if (ah->ah_version == AR5K_AR5210 && 525 (filter & AR5K_RX_FILTER_RADARERR)) { 526 filter &= ~AR5K_RX_FILTER_RADARERR; 527 filter |= AR5K_RX_FILTER_PROM; 528 } 529 530 /*Zero length DMA (phy error reporting) */ 531 if (data) 532 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 533 else 534 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 535 536 /*Write RX Filter register*/ 537 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 538 539 /*Write PHY error filter register on 5212*/ 540 if (ah->ah_version == AR5K_AR5212) 541 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 542 543 } 544 545 546 /****************\ 547 * Beacon control * 548 \****************/ 549 550 #define ATH5K_MAX_TSF_READ 10 551 552 /** 553 * ath5k_hw_get_tsf64() - Get the full 64bit TSF 554 * @ah: The &struct ath5k_hw 555 * 556 * Returns the current TSF 557 */ 558 u64 559 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 560 { 561 u32 tsf_lower, tsf_upper1, tsf_upper2; 562 int i; 563 unsigned long flags; 564 565 /* This code is time critical - we don't want to be interrupted here */ 566 local_irq_save(flags); 567 568 /* 569 * While reading TSF upper and then lower part, the clock is still 570 * counting (or jumping in case of IBSS merge) so we might get 571 * inconsistent values. To avoid this, we read the upper part again 572 * and check it has not been changed. We make the hypothesis that a 573 * maximum of 3 changes can happens in a row (we use 10 as a safe 574 * value). 575 * 576 * Impact on performance is pretty small, since in most cases, only 577 * 3 register reads are needed. 578 */ 579 580 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 581 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { 582 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); 583 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 584 if (tsf_upper2 == tsf_upper1) 585 break; 586 tsf_upper1 = tsf_upper2; 587 } 588 589 local_irq_restore(flags); 590 591 WARN_ON(i == ATH5K_MAX_TSF_READ); 592 593 return ((u64)tsf_upper1 << 32) | tsf_lower; 594 } 595 596 #undef ATH5K_MAX_TSF_READ 597 598 /** 599 * ath5k_hw_set_tsf64() - Set a new 64bit TSF 600 * @ah: The &struct ath5k_hw 601 * @tsf64: The new 64bit TSF 602 * 603 * Sets the new TSF 604 */ 605 void 606 ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 607 { 608 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 609 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 610 } 611 612 /** 613 * ath5k_hw_reset_tsf() - Force a TSF reset 614 * @ah: The &struct ath5k_hw 615 * 616 * Forces a TSF reset on PCU 617 */ 618 void 619 ath5k_hw_reset_tsf(struct ath5k_hw *ah) 620 { 621 u32 val; 622 623 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 624 625 /* 626 * Each write to the RESET_TSF bit toggles a hardware internal 627 * signal to reset TSF, but if left high it will cause a TSF reset 628 * on the next chip reset as well. Thus we always write the value 629 * twice to clear the signal. 630 */ 631 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 632 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 633 } 634 635 /** 636 * ath5k_hw_init_beacon_timers() - Initialize beacon timers 637 * @ah: The &struct ath5k_hw 638 * @next_beacon: Next TBTT 639 * @interval: Current beacon interval 640 * 641 * This function is used to initialize beacon timers based on current 642 * operation mode and settings. 643 */ 644 void 645 ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 646 { 647 u32 timer1, timer2, timer3; 648 649 /* 650 * Set the additional timers by mode 651 */ 652 switch (ah->opmode) { 653 case NL80211_IFTYPE_MONITOR: 654 case NL80211_IFTYPE_STATION: 655 /* In STA mode timer1 is used as next wakeup 656 * timer and timer2 as next CFP duration start 657 * timer. Both in 1/8TUs. */ 658 /* TODO: PCF handling */ 659 if (ah->ah_version == AR5K_AR5210) { 660 timer1 = 0xffffffff; 661 timer2 = 0xffffffff; 662 } else { 663 timer1 = 0x0000ffff; 664 timer2 = 0x0007ffff; 665 } 666 /* Mark associated AP as PCF incapable for now */ 667 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 668 break; 669 case NL80211_IFTYPE_ADHOC: 670 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 671 default: 672 /* On non-STA modes timer1 is used as next DMA 673 * beacon alert (DBA) timer and timer2 as next 674 * software beacon alert. Both in 1/8TUs. */ 675 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 676 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 677 break; 678 } 679 680 /* Timer3 marks the end of our ATIM window 681 * a zero length window is not allowed because 682 * we 'll get no beacons */ 683 timer3 = next_beacon + 1; 684 685 /* 686 * Set the beacon register and enable all timers. 687 */ 688 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 689 if (ah->opmode == NL80211_IFTYPE_AP || 690 ah->opmode == NL80211_IFTYPE_MESH_POINT) 691 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 692 693 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 694 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 695 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 696 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 697 698 /* Force a TSF reset if requested and enable beacons */ 699 if (interval & AR5K_BEACON_RESET_TSF) 700 ath5k_hw_reset_tsf(ah); 701 702 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 703 AR5K_BEACON_ENABLE), 704 AR5K_BEACON); 705 706 /* Flush any pending BMISS interrupts on ISR by 707 * performing a clear-on-write operation on PISR 708 * register for the BMISS bit (writing a bit on 709 * ISR toggles a reset for that bit and leaves 710 * the remaining bits intact) */ 711 if (ah->ah_version == AR5K_AR5210) 712 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 713 else 714 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 715 716 /* TODO: Set enhanced sleep registers on AR5212 717 * based on vif->bss_conf params, until then 718 * disable power save reporting.*/ 719 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 720 721 } 722 723 /** 724 * ath5k_check_timer_win() - Check if timer B is timer A + window 725 * @a: timer a (before b) 726 * @b: timer b (after a) 727 * @window: difference between a and b 728 * @intval: timers are increased by this interval 729 * 730 * This helper function checks if timer B is timer A + window and covers 731 * cases where timer A or B might have already been updated or wrapped 732 * around (Timers are 16 bit). 733 * 734 * Returns true if O.K. 735 */ 736 static inline bool 737 ath5k_check_timer_win(int a, int b, int window, int intval) 738 { 739 /* 740 * 1.) usually B should be A + window 741 * 2.) A already updated, B not updated yet 742 * 3.) A already updated and has wrapped around 743 * 4.) B has wrapped around 744 */ 745 if ((b - a == window) || /* 1.) */ 746 (a - b == intval - window) || /* 2.) */ 747 ((a | 0x10000) - b == intval - window) || /* 3.) */ 748 ((b | 0x10000) - a == window)) /* 4.) */ 749 return true; /* O.K. */ 750 return false; 751 } 752 753 /** 754 * ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct 755 * @ah: The &struct ath5k_hw 756 * @intval: beacon interval 757 * 758 * This is a workaround for IBSS mode 759 * 760 * The need for this function arises from the fact that we have 4 separate 761 * HW timer registers (TIMER0 - TIMER3), which are closely related to the 762 * next beacon target time (NBTT), and that the HW updates these timers 763 * separately based on the current TSF value. The hardware increments each 764 * timer by the beacon interval, when the local TSF converted to TU is equal 765 * to the value stored in the timer. 766 * 767 * The reception of a beacon with the same BSSID can update the local HW TSF 768 * at any time - this is something we can't avoid. If the TSF jumps to a 769 * time which is later than the time stored in a timer, this timer will not 770 * be updated until the TSF in TU wraps around at 16 bit (the size of the 771 * timers) and reaches the time which is stored in the timer. 772 * 773 * The problem is that these timers are closely related to TIMER0 (NBTT) and 774 * that they define a time "window". When the TSF jumps between two timers 775 * (e.g. ATIM and NBTT), the one in the past will be left behind (not 776 * updated), while the one in the future will be updated every beacon 777 * interval. This causes the window to get larger, until the TSF wraps 778 * around as described above and the timer which was left behind gets 779 * updated again. But - because the beacon interval is usually not an exact 780 * divisor of the size of the timers (16 bit), an unwanted "window" between 781 * these timers has developed! 782 * 783 * This is especially important with the ATIM window, because during 784 * the ATIM window only ATIM frames and no data frames are allowed to be 785 * sent, which creates transmission pauses after each beacon. This symptom 786 * has been described as "ramping ping" because ping times increase linearly 787 * for some time and then drop down again. A wrong window on the DMA beacon 788 * timer has the same effect, so we check for these two conditions. 789 * 790 * Returns true if O.K. 791 */ 792 bool 793 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) 794 { 795 unsigned int nbtt, atim, dma; 796 797 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); 798 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); 799 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; 800 801 /* NOTE: SWBA is different. Having a wrong window there does not 802 * stop us from sending data and this condition is caught by 803 * other means (SWBA interrupt) */ 804 805 if (ath5k_check_timer_win(nbtt, atim, 1, intval) && 806 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, 807 intval)) 808 return true; /* O.K. */ 809 return false; 810 } 811 812 /** 813 * ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class 814 * @ah: The &struct ath5k_hw 815 * @coverage_class: IEEE 802.11 coverage class number 816 * 817 * Sets IFS intervals and ACK/CTS timeouts for given coverage class. 818 */ 819 void 820 ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 821 { 822 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 823 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 824 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; 825 int cts_timeout = ack_timeout; 826 827 ath5k_hw_set_ifs_intervals(ah, slot_time); 828 ath5k_hw_set_ack_timeout(ah, ack_timeout); 829 ath5k_hw_set_cts_timeout(ah, cts_timeout); 830 831 ah->ah_coverage_class = coverage_class; 832 } 833 834 /***************************\ 835 * Init/Start/Stop functions * 836 \***************************/ 837 838 /** 839 * ath5k_hw_start_rx_pcu() - Start RX engine 840 * @ah: The &struct ath5k_hw 841 * 842 * Starts RX engine on PCU so that hw can process RXed frames 843 * (ACK etc). 844 * 845 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 846 */ 847 void 848 ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 849 { 850 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 851 } 852 853 /** 854 * at5k_hw_stop_rx_pcu() - Stop RX engine 855 * @ah: The &struct ath5k_hw 856 * 857 * Stops RX engine on PCU 858 */ 859 void 860 ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 861 { 862 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 863 } 864 865 /** 866 * ath5k_hw_set_opmode() - Set PCU operating mode 867 * @ah: The &struct ath5k_hw 868 * @op_mode: One of enum nl80211_iftype 869 * 870 * Configure PCU for the various operating modes (AP/STA etc) 871 */ 872 int 873 ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 874 { 875 struct ath_common *common = ath5k_hw_common(ah); 876 u32 pcu_reg, beacon_reg, low_id, high_id; 877 878 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); 879 880 /* Preserve rest settings */ 881 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 882 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 883 | AR5K_STA_ID1_KEYSRCH_MODE 884 | (ah->ah_version == AR5K_AR5210 ? 885 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 886 887 beacon_reg = 0; 888 889 switch (op_mode) { 890 case NL80211_IFTYPE_ADHOC: 891 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 892 beacon_reg |= AR5K_BCR_ADHOC; 893 if (ah->ah_version == AR5K_AR5210) 894 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 895 else 896 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 897 break; 898 899 case NL80211_IFTYPE_AP: 900 case NL80211_IFTYPE_MESH_POINT: 901 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 902 beacon_reg |= AR5K_BCR_AP; 903 if (ah->ah_version == AR5K_AR5210) 904 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 905 else 906 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 907 break; 908 909 case NL80211_IFTYPE_STATION: 910 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 911 | (ah->ah_version == AR5K_AR5210 ? 912 AR5K_STA_ID1_PWR_SV : 0); 913 case NL80211_IFTYPE_MONITOR: 914 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 915 | (ah->ah_version == AR5K_AR5210 ? 916 AR5K_STA_ID1_NO_PSPOLL : 0); 917 break; 918 919 default: 920 return -EINVAL; 921 } 922 923 /* 924 * Set PCU registers 925 */ 926 low_id = get_unaligned_le32(common->macaddr); 927 high_id = get_unaligned_le16(common->macaddr + 4); 928 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 929 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 930 931 /* 932 * Set Beacon Control Register on 5210 933 */ 934 if (ah->ah_version == AR5K_AR5210) 935 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 936 937 return 0; 938 } 939 940 /** 941 * ath5k_hw_pcu_init() - Initialize PCU 942 * @ah: The &struct ath5k_hw 943 * @op_mode: One of enum nl80211_iftype 944 * @mode: One of enum ath5k_driver_mode 945 * 946 * This function is used to initialize PCU by setting current 947 * operation mode and various other settings. 948 */ 949 void 950 ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode) 951 { 952 /* Set bssid and bssid mask */ 953 ath5k_hw_set_bssid(ah); 954 955 /* Set PCU config */ 956 ath5k_hw_set_opmode(ah, op_mode); 957 958 /* Write rate duration table only on AR5212 and if 959 * virtual interface has already been brought up 960 * XXX: rethink this after new mode changes to 961 * mac80211 are integrated */ 962 if (ah->ah_version == AR5K_AR5212 && 963 ah->nvifs) 964 ath5k_hw_write_rate_duration(ah); 965 966 /* Set RSSI/BRSSI thresholds 967 * 968 * Note: If we decide to set this value 969 * dynamically, have in mind that when AR5K_RSSI_THR 970 * register is read it might return 0x40 if we haven't 971 * wrote anything to it plus BMISS RSSI threshold is zeroed. 972 * So doing a save/restore procedure here isn't the right 973 * choice. Instead store it on ath5k_hw */ 974 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 975 AR5K_TUNE_BMISS_THRES << 976 AR5K_RSSI_THR_BMISS_S), 977 AR5K_RSSI_THR); 978 979 /* MIC QoS support */ 980 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 981 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 982 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 983 } 984 985 /* QoS NOACK Policy */ 986 if (ah->ah_version == AR5K_AR5212) { 987 ath5k_hw_reg_write(ah, 988 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 989 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 990 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 991 AR5K_QOS_NOACK); 992 } 993 994 /* Restore slot time and ACK timeouts */ 995 if (ah->ah_coverage_class > 0) 996 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); 997 998 /* Set ACK bitrate mode (see ack_rates_high) */ 999 if (ah->ah_version == AR5K_AR5212) { 1000 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 1001 if (ah->ah_ack_bitrate_high) 1002 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 1003 else 1004 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 1005 } 1006 return; 1007 } 1008