1 /* 2 * Initial register settings functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 * 20 */ 21 22 #include "ath5k.h" 23 #include "reg.h" 24 #include "debug.h" 25 26 /* 27 * Mode-independent initial register writes 28 */ 29 30 struct ath5k_ini { 31 u16 ini_register; 32 u32 ini_value; 33 34 enum { 35 AR5K_INI_WRITE = 0, /* Default */ 36 AR5K_INI_READ = 1, /* Cleared on read */ 37 } ini_mode; 38 }; 39 40 /* 41 * Mode specific initial register values 42 */ 43 44 struct ath5k_ini_mode { 45 u16 mode_register; 46 u32 mode_value[3]; 47 }; 48 49 /* Initial register settings for AR5210 */ 50 static const struct ath5k_ini ar5210_ini[] = { 51 /* PCU and MAC registers */ 52 { AR5K_NOQCU_TXDP0, 0 }, 53 { AR5K_NOQCU_TXDP1, 0 }, 54 { AR5K_RXDP, 0 }, 55 { AR5K_CR, 0 }, 56 { AR5K_ISR, 0, AR5K_INI_READ }, 57 { AR5K_IMR, 0 }, 58 { AR5K_IER, AR5K_IER_DISABLE }, 59 { AR5K_BSR, 0, AR5K_INI_READ }, 60 { AR5K_TXCFG, AR5K_DMASIZE_128B }, 61 { AR5K_RXCFG, AR5K_DMASIZE_128B }, 62 { AR5K_CFG, AR5K_INIT_CFG }, 63 { AR5K_TOPS, 8 }, 64 { AR5K_RXNOFRM, 8 }, 65 { AR5K_RPGTO, 0 }, 66 { AR5K_TXNOFRM, 0 }, 67 { AR5K_SFR, 0 }, 68 { AR5K_MIBC, 0 }, 69 { AR5K_MISC, 0 }, 70 { AR5K_RX_FILTER_5210, 0 }, 71 { AR5K_MCAST_FILTER0_5210, 0 }, 72 { AR5K_MCAST_FILTER1_5210, 0 }, 73 { AR5K_TX_MASK0, 0 }, 74 { AR5K_TX_MASK1, 0 }, 75 { AR5K_CLR_TMASK, 0 }, 76 { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, 77 { AR5K_DIAG_SW_5210, 0 }, 78 { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, 79 { AR5K_TSF_L32_5210, 0 }, 80 { AR5K_TIMER0_5210, 0 }, 81 { AR5K_TIMER1_5210, 0xffffffff }, 82 { AR5K_TIMER2_5210, 0xffffffff }, 83 { AR5K_TIMER3_5210, 1 }, 84 { AR5K_CFP_DUR_5210, 0 }, 85 { AR5K_CFP_PERIOD_5210, 0 }, 86 /* PHY registers */ 87 { AR5K_PHY(0), 0x00000047 }, 88 { AR5K_PHY_AGC, 0x00000000 }, 89 { AR5K_PHY(3), 0x09848ea6 }, 90 { AR5K_PHY(4), 0x3d32e000 }, 91 { AR5K_PHY(5), 0x0000076b }, 92 { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, 93 { AR5K_PHY(8), 0x02020200 }, 94 { AR5K_PHY(9), 0x00000e0e }, 95 { AR5K_PHY(10), 0x0a020201 }, 96 { AR5K_PHY(11), 0x00036ffc }, 97 { AR5K_PHY(12), 0x00000000 }, 98 { AR5K_PHY(13), 0x00000e0e }, 99 { AR5K_PHY(14), 0x00000007 }, 100 { AR5K_PHY(15), 0x00020100 }, 101 { AR5K_PHY(16), 0x89630000 }, 102 { AR5K_PHY(17), 0x1372169c }, 103 { AR5K_PHY(18), 0x0018b633 }, 104 { AR5K_PHY(19), 0x1284613c }, 105 { AR5K_PHY(20), 0x0de8b8e0 }, 106 { AR5K_PHY(21), 0x00074859 }, 107 { AR5K_PHY(22), 0x7e80beba }, 108 { AR5K_PHY(23), 0x313a665e }, 109 { AR5K_PHY_AGCCTL, 0x00001d08 }, 110 { AR5K_PHY(25), 0x0001ce00 }, 111 { AR5K_PHY(26), 0x409a4190 }, 112 { AR5K_PHY(28), 0x0000000f }, 113 { AR5K_PHY(29), 0x00000080 }, 114 { AR5K_PHY(30), 0x00000004 }, 115 { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ 116 { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ 117 { AR5K_PHY(65), 0x00000000 }, 118 { AR5K_PHY(66), 0x00000000 }, 119 { AR5K_PHY(67), 0x00800000 }, 120 { AR5K_PHY(68), 0x00000003 }, 121 /* BB gain table (64bytes) */ 122 { AR5K_BB_GAIN(0), 0x00000000 }, 123 { AR5K_BB_GAIN(1), 0x00000020 }, 124 { AR5K_BB_GAIN(2), 0x00000010 }, 125 { AR5K_BB_GAIN(3), 0x00000030 }, 126 { AR5K_BB_GAIN(4), 0x00000008 }, 127 { AR5K_BB_GAIN(5), 0x00000028 }, 128 { AR5K_BB_GAIN(6), 0x00000028 }, 129 { AR5K_BB_GAIN(7), 0x00000004 }, 130 { AR5K_BB_GAIN(8), 0x00000024 }, 131 { AR5K_BB_GAIN(9), 0x00000014 }, 132 { AR5K_BB_GAIN(10), 0x00000034 }, 133 { AR5K_BB_GAIN(11), 0x0000000c }, 134 { AR5K_BB_GAIN(12), 0x0000002c }, 135 { AR5K_BB_GAIN(13), 0x00000002 }, 136 { AR5K_BB_GAIN(14), 0x00000022 }, 137 { AR5K_BB_GAIN(15), 0x00000012 }, 138 { AR5K_BB_GAIN(16), 0x00000032 }, 139 { AR5K_BB_GAIN(17), 0x0000000a }, 140 { AR5K_BB_GAIN(18), 0x0000002a }, 141 { AR5K_BB_GAIN(19), 0x00000001 }, 142 { AR5K_BB_GAIN(20), 0x00000021 }, 143 { AR5K_BB_GAIN(21), 0x00000011 }, 144 { AR5K_BB_GAIN(22), 0x00000031 }, 145 { AR5K_BB_GAIN(23), 0x00000009 }, 146 { AR5K_BB_GAIN(24), 0x00000029 }, 147 { AR5K_BB_GAIN(25), 0x00000005 }, 148 { AR5K_BB_GAIN(26), 0x00000025 }, 149 { AR5K_BB_GAIN(27), 0x00000015 }, 150 { AR5K_BB_GAIN(28), 0x00000035 }, 151 { AR5K_BB_GAIN(29), 0x0000000d }, 152 { AR5K_BB_GAIN(30), 0x0000002d }, 153 { AR5K_BB_GAIN(31), 0x00000003 }, 154 { AR5K_BB_GAIN(32), 0x00000023 }, 155 { AR5K_BB_GAIN(33), 0x00000013 }, 156 { AR5K_BB_GAIN(34), 0x00000033 }, 157 { AR5K_BB_GAIN(35), 0x0000000b }, 158 { AR5K_BB_GAIN(36), 0x0000002b }, 159 { AR5K_BB_GAIN(37), 0x00000007 }, 160 { AR5K_BB_GAIN(38), 0x00000027 }, 161 { AR5K_BB_GAIN(39), 0x00000017 }, 162 { AR5K_BB_GAIN(40), 0x00000037 }, 163 { AR5K_BB_GAIN(41), 0x0000000f }, 164 { AR5K_BB_GAIN(42), 0x0000002f }, 165 { AR5K_BB_GAIN(43), 0x0000002f }, 166 { AR5K_BB_GAIN(44), 0x0000002f }, 167 { AR5K_BB_GAIN(45), 0x0000002f }, 168 { AR5K_BB_GAIN(46), 0x0000002f }, 169 { AR5K_BB_GAIN(47), 0x0000002f }, 170 { AR5K_BB_GAIN(48), 0x0000002f }, 171 { AR5K_BB_GAIN(49), 0x0000002f }, 172 { AR5K_BB_GAIN(50), 0x0000002f }, 173 { AR5K_BB_GAIN(51), 0x0000002f }, 174 { AR5K_BB_GAIN(52), 0x0000002f }, 175 { AR5K_BB_GAIN(53), 0x0000002f }, 176 { AR5K_BB_GAIN(54), 0x0000002f }, 177 { AR5K_BB_GAIN(55), 0x0000002f }, 178 { AR5K_BB_GAIN(56), 0x0000002f }, 179 { AR5K_BB_GAIN(57), 0x0000002f }, 180 { AR5K_BB_GAIN(58), 0x0000002f }, 181 { AR5K_BB_GAIN(59), 0x0000002f }, 182 { AR5K_BB_GAIN(60), 0x0000002f }, 183 { AR5K_BB_GAIN(61), 0x0000002f }, 184 { AR5K_BB_GAIN(62), 0x0000002f }, 185 { AR5K_BB_GAIN(63), 0x0000002f }, 186 /* 5110 RF gain table (64btes) */ 187 { AR5K_RF_GAIN(0), 0x0000001d }, 188 { AR5K_RF_GAIN(1), 0x0000005d }, 189 { AR5K_RF_GAIN(2), 0x0000009d }, 190 { AR5K_RF_GAIN(3), 0x000000dd }, 191 { AR5K_RF_GAIN(4), 0x0000011d }, 192 { AR5K_RF_GAIN(5), 0x00000021 }, 193 { AR5K_RF_GAIN(6), 0x00000061 }, 194 { AR5K_RF_GAIN(7), 0x000000a1 }, 195 { AR5K_RF_GAIN(8), 0x000000e1 }, 196 { AR5K_RF_GAIN(9), 0x00000031 }, 197 { AR5K_RF_GAIN(10), 0x00000071 }, 198 { AR5K_RF_GAIN(11), 0x000000b1 }, 199 { AR5K_RF_GAIN(12), 0x0000001c }, 200 { AR5K_RF_GAIN(13), 0x0000005c }, 201 { AR5K_RF_GAIN(14), 0x00000029 }, 202 { AR5K_RF_GAIN(15), 0x00000069 }, 203 { AR5K_RF_GAIN(16), 0x000000a9 }, 204 { AR5K_RF_GAIN(17), 0x00000020 }, 205 { AR5K_RF_GAIN(18), 0x00000019 }, 206 { AR5K_RF_GAIN(19), 0x00000059 }, 207 { AR5K_RF_GAIN(20), 0x00000099 }, 208 { AR5K_RF_GAIN(21), 0x00000030 }, 209 { AR5K_RF_GAIN(22), 0x00000005 }, 210 { AR5K_RF_GAIN(23), 0x00000025 }, 211 { AR5K_RF_GAIN(24), 0x00000065 }, 212 { AR5K_RF_GAIN(25), 0x000000a5 }, 213 { AR5K_RF_GAIN(26), 0x00000028 }, 214 { AR5K_RF_GAIN(27), 0x00000068 }, 215 { AR5K_RF_GAIN(28), 0x0000001f }, 216 { AR5K_RF_GAIN(29), 0x0000001e }, 217 { AR5K_RF_GAIN(30), 0x00000018 }, 218 { AR5K_RF_GAIN(31), 0x00000058 }, 219 { AR5K_RF_GAIN(32), 0x00000098 }, 220 { AR5K_RF_GAIN(33), 0x00000003 }, 221 { AR5K_RF_GAIN(34), 0x00000004 }, 222 { AR5K_RF_GAIN(35), 0x00000044 }, 223 { AR5K_RF_GAIN(36), 0x00000084 }, 224 { AR5K_RF_GAIN(37), 0x00000013 }, 225 { AR5K_RF_GAIN(38), 0x00000012 }, 226 { AR5K_RF_GAIN(39), 0x00000052 }, 227 { AR5K_RF_GAIN(40), 0x00000092 }, 228 { AR5K_RF_GAIN(41), 0x000000d2 }, 229 { AR5K_RF_GAIN(42), 0x0000002b }, 230 { AR5K_RF_GAIN(43), 0x0000002a }, 231 { AR5K_RF_GAIN(44), 0x0000006a }, 232 { AR5K_RF_GAIN(45), 0x000000aa }, 233 { AR5K_RF_GAIN(46), 0x0000001b }, 234 { AR5K_RF_GAIN(47), 0x0000001a }, 235 { AR5K_RF_GAIN(48), 0x0000005a }, 236 { AR5K_RF_GAIN(49), 0x0000009a }, 237 { AR5K_RF_GAIN(50), 0x000000da }, 238 { AR5K_RF_GAIN(51), 0x00000006 }, 239 { AR5K_RF_GAIN(52), 0x00000006 }, 240 { AR5K_RF_GAIN(53), 0x00000006 }, 241 { AR5K_RF_GAIN(54), 0x00000006 }, 242 { AR5K_RF_GAIN(55), 0x00000006 }, 243 { AR5K_RF_GAIN(56), 0x00000006 }, 244 { AR5K_RF_GAIN(57), 0x00000006 }, 245 { AR5K_RF_GAIN(58), 0x00000006 }, 246 { AR5K_RF_GAIN(59), 0x00000006 }, 247 { AR5K_RF_GAIN(60), 0x00000006 }, 248 { AR5K_RF_GAIN(61), 0x00000006 }, 249 { AR5K_RF_GAIN(62), 0x00000006 }, 250 { AR5K_RF_GAIN(63), 0x00000006 }, 251 /* PHY activation */ 252 { AR5K_PHY(53), 0x00000020 }, 253 { AR5K_PHY(51), 0x00000004 }, 254 { AR5K_PHY(50), 0x00060106 }, 255 { AR5K_PHY(39), 0x0000006d }, 256 { AR5K_PHY(48), 0x00000000 }, 257 { AR5K_PHY(52), 0x00000014 }, 258 { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, 259 }; 260 261 /* Initial register settings for AR5211 */ 262 static const struct ath5k_ini ar5211_ini[] = { 263 { AR5K_RXDP, 0x00000000 }, 264 { AR5K_RTSD0, 0x84849c9c }, 265 { AR5K_RTSD1, 0x7c7c7c7c }, 266 { AR5K_RXCFG, 0x00000005 }, 267 { AR5K_MIBC, 0x00000000 }, 268 { AR5K_TOPS, 0x00000008 }, 269 { AR5K_RXNOFRM, 0x00000008 }, 270 { AR5K_TXNOFRM, 0x00000010 }, 271 { AR5K_RPGTO, 0x00000000 }, 272 { AR5K_RFCNT, 0x0000001f }, 273 { AR5K_QUEUE_TXDP(0), 0x00000000 }, 274 { AR5K_QUEUE_TXDP(1), 0x00000000 }, 275 { AR5K_QUEUE_TXDP(2), 0x00000000 }, 276 { AR5K_QUEUE_TXDP(3), 0x00000000 }, 277 { AR5K_QUEUE_TXDP(4), 0x00000000 }, 278 { AR5K_QUEUE_TXDP(5), 0x00000000 }, 279 { AR5K_QUEUE_TXDP(6), 0x00000000 }, 280 { AR5K_QUEUE_TXDP(7), 0x00000000 }, 281 { AR5K_QUEUE_TXDP(8), 0x00000000 }, 282 { AR5K_QUEUE_TXDP(9), 0x00000000 }, 283 { AR5K_DCU_FP, 0x00000000 }, 284 { AR5K_STA_ID1, 0x00000000 }, 285 { AR5K_BSS_ID0, 0x00000000 }, 286 { AR5K_BSS_ID1, 0x00000000 }, 287 { AR5K_RSSI_THR, 0x00000000 }, 288 { AR5K_CFP_PERIOD_5211, 0x00000000 }, 289 { AR5K_TIMER0_5211, 0x00000030 }, 290 { AR5K_TIMER1_5211, 0x0007ffff }, 291 { AR5K_TIMER2_5211, 0x01ffffff }, 292 { AR5K_TIMER3_5211, 0x00000031 }, 293 { AR5K_CFP_DUR_5211, 0x00000000 }, 294 { AR5K_RX_FILTER_5211, 0x00000000 }, 295 { AR5K_MCAST_FILTER0_5211, 0x00000000 }, 296 { AR5K_MCAST_FILTER1_5211, 0x00000002 }, 297 { AR5K_DIAG_SW_5211, 0x00000000 }, 298 { AR5K_ADDAC_TEST, 0x00000000 }, 299 { AR5K_DEFAULT_ANTENNA, 0x00000000 }, 300 /* PHY registers */ 301 { AR5K_PHY_AGC, 0x00000000 }, 302 { AR5K_PHY(3), 0x2d849093 }, 303 { AR5K_PHY(4), 0x7d32e000 }, 304 { AR5K_PHY(5), 0x00000f6b }, 305 { AR5K_PHY_ACT, 0x00000000 }, 306 { AR5K_PHY(11), 0x00026ffe }, 307 { AR5K_PHY(12), 0x00000000 }, 308 { AR5K_PHY(15), 0x00020100 }, 309 { AR5K_PHY(16), 0x206a017a }, 310 { AR5K_PHY(19), 0x1284613c }, 311 { AR5K_PHY(21), 0x00000859 }, 312 { AR5K_PHY(26), 0x409a4190 }, /* 0x9868 */ 313 { AR5K_PHY(27), 0x050cb081 }, 314 { AR5K_PHY(28), 0x0000000f }, 315 { AR5K_PHY(29), 0x00000080 }, 316 { AR5K_PHY(30), 0x0000000c }, 317 { AR5K_PHY(64), 0x00000000 }, 318 { AR5K_PHY(65), 0x00000000 }, 319 { AR5K_PHY(66), 0x00000000 }, 320 { AR5K_PHY(67), 0x00800000 }, 321 { AR5K_PHY(68), 0x00000001 }, 322 { AR5K_PHY(71), 0x0000092a }, 323 { AR5K_PHY_IQ, 0x00000000 }, 324 { AR5K_PHY(73), 0x00058a05 }, 325 { AR5K_PHY(74), 0x00000001 }, 326 { AR5K_PHY(75), 0x00000000 }, 327 { AR5K_PHY_PAPD_PROBE, 0x00000000 }, 328 { AR5K_PHY(77), 0x00000000 }, /* 0x9934 */ 329 { AR5K_PHY(78), 0x00000000 }, /* 0x9938 */ 330 { AR5K_PHY(79), 0x0000003f }, /* 0x993c */ 331 { AR5K_PHY(80), 0x00000004 }, 332 { AR5K_PHY(82), 0x00000000 }, 333 { AR5K_PHY(83), 0x00000000 }, 334 { AR5K_PHY(84), 0x00000000 }, 335 { AR5K_PHY_RADAR, 0x5d50f14c }, 336 { AR5K_PHY(86), 0x00000018 }, 337 { AR5K_PHY(87), 0x004b6a8e }, 338 /* Initial Power table (32bytes) 339 * common on all cards/modes. 340 * Note: Table is rewritten during 341 * txpower setup later using calibration 342 * data etc. so next write is non-common */ 343 { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff }, 344 { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff }, 345 { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff }, 346 { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff }, 347 { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff }, 348 { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff }, 349 { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff }, 350 { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff }, 351 { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff }, 352 { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff }, 353 { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff }, 354 { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff }, 355 { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff }, 356 { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff }, 357 { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff }, 358 { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff }, 359 { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff }, 360 { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff }, 361 { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff }, 362 { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff }, 363 { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff }, 364 { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff }, 365 { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff }, 366 { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff }, 367 { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff }, 368 { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff }, 369 { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff }, 370 { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff }, 371 { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff }, 372 { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff }, 373 { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff }, 374 { AR5K_PHY_CCKTXCTL, 0x00000000 }, 375 { AR5K_PHY(642), 0x503e4646 }, 376 { AR5K_PHY_GAIN_2GHZ, 0x6480416c }, 377 { AR5K_PHY(644), 0x0199a003 }, 378 { AR5K_PHY(645), 0x044cd610 }, 379 { AR5K_PHY(646), 0x13800040 }, 380 { AR5K_PHY(647), 0x1be00060 }, 381 { AR5K_PHY(648), 0x0c53800a }, 382 { AR5K_PHY(649), 0x0014df3b }, 383 { AR5K_PHY(650), 0x000001b5 }, 384 { AR5K_PHY(651), 0x00000020 }, 385 }; 386 387 /* Initial mode-specific settings for AR5211 388 * 5211 supports OFDM-only g (draft g) but we 389 * need to test it ! 390 */ 391 static const struct ath5k_ini_mode ar5211_ini_mode[] = { 392 { AR5K_TXCFG, 393 /* A/XR B G */ 394 { 0x00000015, 0x0000001d, 0x00000015 } }, 395 { AR5K_QUEUE_DFS_LOCAL_IFS(0), 396 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 397 { AR5K_QUEUE_DFS_LOCAL_IFS(1), 398 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 399 { AR5K_QUEUE_DFS_LOCAL_IFS(2), 400 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 401 { AR5K_QUEUE_DFS_LOCAL_IFS(3), 402 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 403 { AR5K_QUEUE_DFS_LOCAL_IFS(4), 404 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 405 { AR5K_QUEUE_DFS_LOCAL_IFS(5), 406 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 407 { AR5K_QUEUE_DFS_LOCAL_IFS(6), 408 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 409 { AR5K_QUEUE_DFS_LOCAL_IFS(7), 410 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 411 { AR5K_QUEUE_DFS_LOCAL_IFS(8), 412 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 413 { AR5K_QUEUE_DFS_LOCAL_IFS(9), 414 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 415 { AR5K_DCU_GBL_IFS_SLOT, 416 { 0x00000168, 0x000001b8, 0x00000168 } }, 417 { AR5K_DCU_GBL_IFS_SIFS, 418 { 0x00000230, 0x000000b0, 0x00000230 } }, 419 { AR5K_DCU_GBL_IFS_EIFS, 420 { 0x00000d98, 0x00001f48, 0x00000d98 } }, 421 { AR5K_DCU_GBL_IFS_MISC, 422 { 0x0000a0e0, 0x00005880, 0x0000a0e0 } }, 423 { AR5K_TIME_OUT, 424 { 0x04000400, 0x20003000, 0x04000400 } }, 425 { AR5K_USEC_5211, 426 { 0x0e8d8fa7, 0x01608f95, 0x0e8d8fa7 } }, 427 { AR5K_PHY(8), 428 { 0x02020200, 0x02010200, 0x02020200 } }, 429 { AR5K_PHY_RF_CTL2, 430 { 0x00000e0e, 0x00000707, 0x00000e0e } }, 431 { AR5K_PHY_RF_CTL3, 432 { 0x0a020001, 0x05010000, 0x0a020001 } }, 433 { AR5K_PHY_RF_CTL4, 434 { 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 435 { AR5K_PHY_PA_CTL, 436 { 0x00000007, 0x0000000b, 0x0000000b } }, 437 { AR5K_PHY_SETTLING, 438 { 0x1372169c, 0x137216a8, 0x1372169c } }, 439 { AR5K_PHY_GAIN, 440 { 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, 441 { AR5K_PHY_DESIRED_SIZE, 442 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, 443 { AR5K_PHY_SIG, 444 { 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, 445 { AR5K_PHY_AGCCOARSE, 446 { 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, 447 { AR5K_PHY_AGCCTL, 448 { 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, 449 { AR5K_PHY_NF, 450 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, 451 { AR5K_PHY_RX_DELAY, 452 { 0x00002710, 0x0000157c, 0x00002710 } }, 453 { AR5K_PHY(70), 454 { 0x00000190, 0x00000084, 0x00000190 } }, 455 { AR5K_PHY_FRAME_CTL_5211, 456 { 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, 457 { AR5K_PHY_PCDAC_TXPOWER_BASE, 458 { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, 459 { AR5K_RF_BUFFER_CONTROL_4, 460 { 0x00000010, 0x00000010, 0x00000010 } }, 461 }; 462 463 /* Initial register settings for AR5212 */ 464 static const struct ath5k_ini ar5212_ini_common_start[] = { 465 { AR5K_RXDP, 0x00000000 }, 466 { AR5K_RXCFG, 0x00000005 }, 467 { AR5K_MIBC, 0x00000000 }, 468 { AR5K_TOPS, 0x00000008 }, 469 { AR5K_RXNOFRM, 0x00000008 }, 470 { AR5K_TXNOFRM, 0x00000010 }, 471 { AR5K_RPGTO, 0x00000000 }, 472 { AR5K_RFCNT, 0x0000001f }, 473 { AR5K_QUEUE_TXDP(0), 0x00000000 }, 474 { AR5K_QUEUE_TXDP(1), 0x00000000 }, 475 { AR5K_QUEUE_TXDP(2), 0x00000000 }, 476 { AR5K_QUEUE_TXDP(3), 0x00000000 }, 477 { AR5K_QUEUE_TXDP(4), 0x00000000 }, 478 { AR5K_QUEUE_TXDP(5), 0x00000000 }, 479 { AR5K_QUEUE_TXDP(6), 0x00000000 }, 480 { AR5K_QUEUE_TXDP(7), 0x00000000 }, 481 { AR5K_QUEUE_TXDP(8), 0x00000000 }, 482 { AR5K_QUEUE_TXDP(9), 0x00000000 }, 483 { AR5K_DCU_FP, 0x00000000 }, 484 { AR5K_DCU_TXP, 0x00000000 }, 485 /* Tx filter table 0 (32 entries) */ 486 { AR5K_DCU_TX_FILTER_0(0), 0x00000000 }, /* DCU 0 */ 487 { AR5K_DCU_TX_FILTER_0(1), 0x00000000 }, 488 { AR5K_DCU_TX_FILTER_0(2), 0x00000000 }, 489 { AR5K_DCU_TX_FILTER_0(3), 0x00000000 }, 490 { AR5K_DCU_TX_FILTER_0(4), 0x00000000 }, /* DCU 1 */ 491 { AR5K_DCU_TX_FILTER_0(5), 0x00000000 }, 492 { AR5K_DCU_TX_FILTER_0(6), 0x00000000 }, 493 { AR5K_DCU_TX_FILTER_0(7), 0x00000000 }, 494 { AR5K_DCU_TX_FILTER_0(8), 0x00000000 }, /* DCU 2 */ 495 { AR5K_DCU_TX_FILTER_0(9), 0x00000000 }, 496 { AR5K_DCU_TX_FILTER_0(10), 0x00000000 }, 497 { AR5K_DCU_TX_FILTER_0(11), 0x00000000 }, 498 { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */ 499 { AR5K_DCU_TX_FILTER_0(13), 0x00000000 }, 500 { AR5K_DCU_TX_FILTER_0(14), 0x00000000 }, 501 { AR5K_DCU_TX_FILTER_0(15), 0x00000000 }, 502 { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */ 503 { AR5K_DCU_TX_FILTER_0(17), 0x00000000 }, 504 { AR5K_DCU_TX_FILTER_0(18), 0x00000000 }, 505 { AR5K_DCU_TX_FILTER_0(19), 0x00000000 }, 506 { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */ 507 { AR5K_DCU_TX_FILTER_0(21), 0x00000000 }, 508 { AR5K_DCU_TX_FILTER_0(22), 0x00000000 }, 509 { AR5K_DCU_TX_FILTER_0(23), 0x00000000 }, 510 { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */ 511 { AR5K_DCU_TX_FILTER_0(25), 0x00000000 }, 512 { AR5K_DCU_TX_FILTER_0(26), 0x00000000 }, 513 { AR5K_DCU_TX_FILTER_0(27), 0x00000000 }, 514 { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */ 515 { AR5K_DCU_TX_FILTER_0(29), 0x00000000 }, 516 { AR5K_DCU_TX_FILTER_0(30), 0x00000000 }, 517 { AR5K_DCU_TX_FILTER_0(31), 0x00000000 }, 518 /* Tx filter table 1 (16 entries) */ 519 { AR5K_DCU_TX_FILTER_1(0), 0x00000000 }, 520 { AR5K_DCU_TX_FILTER_1(1), 0x00000000 }, 521 { AR5K_DCU_TX_FILTER_1(2), 0x00000000 }, 522 { AR5K_DCU_TX_FILTER_1(3), 0x00000000 }, 523 { AR5K_DCU_TX_FILTER_1(4), 0x00000000 }, 524 { AR5K_DCU_TX_FILTER_1(5), 0x00000000 }, 525 { AR5K_DCU_TX_FILTER_1(6), 0x00000000 }, 526 { AR5K_DCU_TX_FILTER_1(7), 0x00000000 }, 527 { AR5K_DCU_TX_FILTER_1(8), 0x00000000 }, 528 { AR5K_DCU_TX_FILTER_1(9), 0x00000000 }, 529 { AR5K_DCU_TX_FILTER_1(10), 0x00000000 }, 530 { AR5K_DCU_TX_FILTER_1(11), 0x00000000 }, 531 { AR5K_DCU_TX_FILTER_1(12), 0x00000000 }, 532 { AR5K_DCU_TX_FILTER_1(13), 0x00000000 }, 533 { AR5K_DCU_TX_FILTER_1(14), 0x00000000 }, 534 { AR5K_DCU_TX_FILTER_1(15), 0x00000000 }, 535 { AR5K_DCU_TX_FILTER_CLR, 0x00000000 }, 536 { AR5K_DCU_TX_FILTER_SET, 0x00000000 }, 537 { AR5K_STA_ID1, 0x00000000 }, 538 { AR5K_BSS_ID0, 0x00000000 }, 539 { AR5K_BSS_ID1, 0x00000000 }, 540 { AR5K_BEACON_5211, 0x00000000 }, 541 { AR5K_CFP_PERIOD_5211, 0x00000000 }, 542 { AR5K_TIMER0_5211, 0x00000030 }, 543 { AR5K_TIMER1_5211, 0x0007ffff }, 544 { AR5K_TIMER2_5211, 0x01ffffff }, 545 { AR5K_TIMER3_5211, 0x00000031 }, 546 { AR5K_CFP_DUR_5211, 0x00000000 }, 547 { AR5K_RX_FILTER_5211, 0x00000000 }, 548 { AR5K_DIAG_SW_5211, 0x00000000 }, 549 { AR5K_ADDAC_TEST, 0x00000000 }, 550 { AR5K_DEFAULT_ANTENNA, 0x00000000 }, 551 { AR5K_FRAME_CTL_QOSM, 0x000fc78f }, 552 { AR5K_XRMODE, 0x2a82301a }, 553 { AR5K_XRDELAY, 0x05dc01e0 }, 554 { AR5K_XRTIMEOUT, 0x1f402710 }, 555 { AR5K_XRCHIRP, 0x01f40000 }, 556 { AR5K_XRSTOMP, 0x00001e1c }, 557 { AR5K_SLEEP0, 0x0002aaaa }, 558 { AR5K_SLEEP1, 0x02005555 }, 559 { AR5K_SLEEP2, 0x00000000 }, 560 { AR_BSSMSKL, 0xffffffff }, 561 { AR_BSSMSKU, 0x0000ffff }, 562 { AR5K_TXPC, 0x00000000 }, 563 { AR5K_PROFCNT_TX, 0x00000000 }, 564 { AR5K_PROFCNT_RX, 0x00000000 }, 565 { AR5K_PROFCNT_RXCLR, 0x00000000 }, 566 { AR5K_PROFCNT_CYCLE, 0x00000000 }, 567 { AR5K_QUIET_CTL1, 0x00000088 }, 568 /* Initial rate duration table (32 entries )*/ 569 { AR5K_RATE_DUR(0), 0x00000000 }, 570 { AR5K_RATE_DUR(1), 0x0000008c }, 571 { AR5K_RATE_DUR(2), 0x000000e4 }, 572 { AR5K_RATE_DUR(3), 0x000002d5 }, 573 { AR5K_RATE_DUR(4), 0x00000000 }, 574 { AR5K_RATE_DUR(5), 0x00000000 }, 575 { AR5K_RATE_DUR(6), 0x000000a0 }, 576 { AR5K_RATE_DUR(7), 0x000001c9 }, 577 { AR5K_RATE_DUR(8), 0x0000002c }, 578 { AR5K_RATE_DUR(9), 0x0000002c }, 579 { AR5K_RATE_DUR(10), 0x00000030 }, 580 { AR5K_RATE_DUR(11), 0x0000003c }, 581 { AR5K_RATE_DUR(12), 0x0000002c }, 582 { AR5K_RATE_DUR(13), 0x0000002c }, 583 { AR5K_RATE_DUR(14), 0x00000030 }, 584 { AR5K_RATE_DUR(15), 0x0000003c }, 585 { AR5K_RATE_DUR(16), 0x00000000 }, 586 { AR5K_RATE_DUR(17), 0x00000000 }, 587 { AR5K_RATE_DUR(18), 0x00000000 }, 588 { AR5K_RATE_DUR(19), 0x00000000 }, 589 { AR5K_RATE_DUR(20), 0x00000000 }, 590 { AR5K_RATE_DUR(21), 0x00000000 }, 591 { AR5K_RATE_DUR(22), 0x00000000 }, 592 { AR5K_RATE_DUR(23), 0x00000000 }, 593 { AR5K_RATE_DUR(24), 0x000000d5 }, 594 { AR5K_RATE_DUR(25), 0x000000df }, 595 { AR5K_RATE_DUR(26), 0x00000102 }, 596 { AR5K_RATE_DUR(27), 0x0000013a }, 597 { AR5K_RATE_DUR(28), 0x00000075 }, 598 { AR5K_RATE_DUR(29), 0x0000007f }, 599 { AR5K_RATE_DUR(30), 0x000000a2 }, 600 { AR5K_RATE_DUR(31), 0x00000000 }, 601 { AR5K_QUIET_CTL2, 0x00010002 }, 602 { AR5K_TSF_PARM, 0x00000001 }, 603 { AR5K_QOS_NOACK, 0x000000c0 }, 604 { AR5K_PHY_ERR_FIL, 0x00000000 }, 605 { AR5K_XRLAT_TX, 0x00000168 }, 606 { AR5K_ACKSIFS, 0x00000000 }, 607 /* Rate -> db table 608 * notice ...03<-02<-01<-00 ! */ 609 { AR5K_RATE2DB(0), 0x03020100 }, 610 { AR5K_RATE2DB(1), 0x07060504 }, 611 { AR5K_RATE2DB(2), 0x0b0a0908 }, 612 { AR5K_RATE2DB(3), 0x0f0e0d0c }, 613 { AR5K_RATE2DB(4), 0x13121110 }, 614 { AR5K_RATE2DB(5), 0x17161514 }, 615 { AR5K_RATE2DB(6), 0x1b1a1918 }, 616 { AR5K_RATE2DB(7), 0x1f1e1d1c }, 617 /* Db -> Rate table */ 618 { AR5K_DB2RATE(0), 0x03020100 }, 619 { AR5K_DB2RATE(1), 0x07060504 }, 620 { AR5K_DB2RATE(2), 0x0b0a0908 }, 621 { AR5K_DB2RATE(3), 0x0f0e0d0c }, 622 { AR5K_DB2RATE(4), 0x13121110 }, 623 { AR5K_DB2RATE(5), 0x17161514 }, 624 { AR5K_DB2RATE(6), 0x1b1a1918 }, 625 { AR5K_DB2RATE(7), 0x1f1e1d1c }, 626 /* PHY registers (Common settings 627 * for all chips/modes) */ 628 { AR5K_PHY(3), 0xad848e19 }, 629 { AR5K_PHY(4), 0x7d28e000 }, 630 { AR5K_PHY_TIMING_3, 0x9c0a9f6b }, 631 { AR5K_PHY_ACT, 0x00000000 }, 632 { AR5K_PHY(16), 0x206a017a }, 633 { AR5K_PHY(21), 0x00000859 }, 634 { AR5K_PHY_BIN_MASK_1, 0x00000000 }, 635 { AR5K_PHY_BIN_MASK_2, 0x00000000 }, 636 { AR5K_PHY_BIN_MASK_3, 0x00000000 }, 637 { AR5K_PHY_BIN_MASK_CTL, 0x00800000 }, 638 { AR5K_PHY_ANT_CTL, 0x00000001 }, 639 /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */ 640 { AR5K_PHY_MAX_RX_LEN, 0x00000c80 }, 641 { AR5K_PHY_IQ, 0x05100000 }, 642 { AR5K_PHY_WARM_RESET, 0x00000001 }, 643 { AR5K_PHY_CTL, 0x00000004 }, 644 { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 }, 645 { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d }, 646 { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f }, 647 { AR5K_PHY(82), 0x9280b212 }, 648 { AR5K_PHY_RADAR, 0x5d50e188 }, 649 /*{ AR5K_PHY(86), 0x000000ff },*/ 650 { AR5K_PHY(87), 0x004b6a8e }, 651 { AR5K_PHY_NFTHRES, 0x000003ce }, 652 { AR5K_PHY_RESTART, 0x192fb515 }, 653 { AR5K_PHY(94), 0x00000001 }, 654 { AR5K_PHY_RFBUS_REQ, 0x00000000 }, 655 /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */ 656 /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */ 657 { AR5K_PHY(644), 0x00806333 }, 658 { AR5K_PHY(645), 0x00106c10 }, 659 { AR5K_PHY(646), 0x009c4060 }, 660 /* { AR5K_PHY(647), 0x1483800a }, */ 661 /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */ 662 { AR5K_PHY(648), 0x018830c6 }, 663 { AR5K_PHY(649), 0x00000400 }, 664 /*{ AR5K_PHY(650), 0x000001b5 },*/ 665 { AR5K_PHY(651), 0x00000000 }, 666 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, 667 { AR5K_PHY_TXPOWER_RATE4, 0x20202020 }, 668 /*{ AR5K_PHY(655), 0x13c889af },*/ 669 { AR5K_PHY(656), 0x38490a20 }, 670 { AR5K_PHY(657), 0x00007bb6 }, 671 { AR5K_PHY(658), 0x0fff3ffc }, 672 }; 673 674 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */ 675 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = { 676 { AR5K_QUEUE_DFS_LOCAL_IFS(0), 677 /* A/XR B G */ 678 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 679 { AR5K_QUEUE_DFS_LOCAL_IFS(1), 680 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 681 { AR5K_QUEUE_DFS_LOCAL_IFS(2), 682 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 683 { AR5K_QUEUE_DFS_LOCAL_IFS(3), 684 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 685 { AR5K_QUEUE_DFS_LOCAL_IFS(4), 686 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 687 { AR5K_QUEUE_DFS_LOCAL_IFS(5), 688 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 689 { AR5K_QUEUE_DFS_LOCAL_IFS(6), 690 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 691 { AR5K_QUEUE_DFS_LOCAL_IFS(7), 692 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 693 { AR5K_QUEUE_DFS_LOCAL_IFS(8), 694 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 695 { AR5K_QUEUE_DFS_LOCAL_IFS(9), 696 { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, 697 { AR5K_DCU_GBL_IFS_SIFS, 698 { 0x00000230, 0x000000b0, 0x00000160 } }, 699 { AR5K_DCU_GBL_IFS_SLOT, 700 { 0x00000168, 0x000001b8, 0x0000018c } }, 701 { AR5K_DCU_GBL_IFS_EIFS, 702 { 0x00000e60, 0x00001f1c, 0x00003e38 } }, 703 { AR5K_DCU_GBL_IFS_MISC, 704 { 0x0000a0e0, 0x00005880, 0x0000b0e0 } }, 705 { AR5K_TIME_OUT, 706 { 0x03e803e8, 0x04200420, 0x08400840 } }, 707 { AR5K_PHY(8), 708 { 0x02020200, 0x02010200, 0x02020200 } }, 709 { AR5K_PHY_RF_CTL2, 710 { 0x00000e0e, 0x00000707, 0x00000e0e } }, 711 { AR5K_PHY_SETTLING, 712 { 0x1372161c, 0x13721722, 0x137216a2 } }, 713 { AR5K_PHY_AGCCTL, 714 { 0x00009d10, 0x00009d18, 0x00009d18 } }, 715 { AR5K_PHY_NF, 716 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, 717 { AR5K_PHY_WEAK_OFDM_HIGH_THR, 718 { 0x409a4190, 0x409a4190, 0x409a4190 } }, 719 { AR5K_PHY(70), 720 { 0x000001b8, 0x00000084, 0x00000108 } }, 721 { AR5K_PHY_OFDM_SELFCORR, 722 { 0x10058a05, 0x10058a05, 0x10058a05 } }, 723 { 0xa230, 724 { 0x00000000, 0x00000000, 0x00000108 } }, 725 }; 726 727 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */ 728 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = { 729 { AR5K_TXCFG, 730 /* A/XR B G */ 731 { 0x00008015, 0x00008015, 0x00008015 } }, 732 { AR5K_USEC_5211, 733 { 0x128d8fa7, 0x04e00f95, 0x12e00fab } }, 734 { AR5K_PHY_RF_CTL3, 735 { 0x0a020001, 0x05010100, 0x0a020001 } }, 736 { AR5K_PHY_RF_CTL4, 737 { 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 738 { AR5K_PHY_PA_CTL, 739 { 0x00000007, 0x0000000b, 0x0000000b } }, 740 { AR5K_PHY_GAIN, 741 { 0x0018da5a, 0x0018ca69, 0x0018ca69 } }, 742 { AR5K_PHY_DESIRED_SIZE, 743 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, 744 { AR5K_PHY_SIG, 745 { 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e } }, 746 { AR5K_PHY_AGCCOARSE, 747 { 0x3137665e, 0x3137665e, 0x3137665e } }, 748 { AR5K_PHY_WEAK_OFDM_LOW_THR, 749 { 0x050cb081, 0x050cb081, 0x050cb080 } }, 750 { AR5K_PHY_RX_DELAY, 751 { 0x00002710, 0x0000157c, 0x00002af8 } }, 752 { AR5K_PHY_FRAME_CTL_5211, 753 { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } }, 754 { AR5K_PHY_GAIN_2GHZ, 755 { 0x642c416a, 0x6440416a, 0x6440416a } }, 756 { AR5K_PHY_CCK_RX_CTL_4, 757 { 0x1883800a, 0x1873800a, 0x1883800a } }, 758 }; 759 760 static const struct ath5k_ini rf5111_ini_common_end[] = { 761 { AR5K_DCU_FP, 0x00000000 }, 762 { AR5K_PHY_AGC, 0x00000000 }, 763 { AR5K_PHY_ADC_CTL, 0x00022ffe }, 764 { 0x983c, 0x00020100 }, 765 { AR5K_PHY_GAIN_OFFSET, 0x1284613c }, 766 { AR5K_PHY_PAPD_PROBE, 0x00004883 }, 767 { 0x9940, 0x00000004 }, 768 { 0x9958, 0x000000ff }, 769 { 0x9974, 0x00000000 }, 770 { AR5K_PHY_SPENDING, 0x00000018 }, 771 { AR5K_PHY_CCKTXCTL, 0x00000000 }, 772 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 }, 773 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 }, 774 { 0xa23c, 0x13c889af }, 775 }; 776 777 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */ 778 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = { 779 { AR5K_TXCFG, 780 /* A/XR B G */ 781 { 0x00008015, 0x00008015, 0x00008015 } }, 782 { AR5K_USEC_5211, 783 { 0x128d93a7, 0x04e01395, 0x12e013ab } }, 784 { AR5K_PHY_RF_CTL3, 785 { 0x0a020001, 0x05020100, 0x0a020001 } }, 786 { AR5K_PHY_RF_CTL4, 787 { 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 788 { AR5K_PHY_PA_CTL, 789 { 0x00000007, 0x0000000b, 0x0000000b } }, 790 { AR5K_PHY_GAIN, 791 { 0x0018da6d, 0x0018ca75, 0x0018ca75 } }, 792 { AR5K_PHY_DESIRED_SIZE, 793 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, 794 { AR5K_PHY_SIG, 795 { 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e } }, 796 { AR5K_PHY_AGCCOARSE, 797 { 0x3137665e, 0x3137665e, 0x3137665e } }, 798 { AR5K_PHY_WEAK_OFDM_LOW_THR, 799 { 0x050cb081, 0x050cb081, 0x050cb081 } }, 800 { AR5K_PHY_RX_DELAY, 801 { 0x000007d0, 0x0000044c, 0x00000898 } }, 802 { AR5K_PHY_FRAME_CTL_5211, 803 { 0xf7b81020, 0xf7b80d10, 0xf7b81010 } }, 804 { AR5K_PHY_CCKTXCTL, 805 { 0x00000000, 0x00000008, 0x00000008 } }, 806 { AR5K_PHY_CCK_CROSSCORR, 807 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } }, 808 { AR5K_PHY_GAIN_2GHZ, 809 { 0x642c0140, 0x6442c160, 0x6442c160 } }, 810 { AR5K_PHY_CCK_RX_CTL_4, 811 { 0x1883800a, 0x1873800a, 0x1883800a } }, 812 }; 813 814 static const struct ath5k_ini rf5112_ini_common_end[] = { 815 { AR5K_DCU_FP, 0x00000000 }, 816 { AR5K_PHY_AGC, 0x00000000 }, 817 { AR5K_PHY_ADC_CTL, 0x00022ffe }, 818 { 0x983c, 0x00020100 }, 819 { AR5K_PHY_GAIN_OFFSET, 0x1284613c }, 820 { AR5K_PHY_PAPD_PROBE, 0x00004882 }, 821 { 0x9940, 0x00000004 }, 822 { 0x9958, 0x000000ff }, 823 { 0x9974, 0x00000000 }, 824 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 }, 825 { 0xa23c, 0x13c889af }, 826 }; 827 828 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */ 829 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = { 830 { AR5K_TXCFG, 831 /* A/XR B G */ 832 { 0x00000015, 0x00000015, 0x00000015 } }, 833 { AR5K_USEC_5211, 834 { 0x128d93a7, 0x04e01395, 0x12e013ab } }, 835 { AR5K_PHY_RF_CTL3, 836 { 0x0a020001, 0x05020100, 0x0a020001 } }, 837 { AR5K_PHY_RF_CTL4, 838 { 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 839 { AR5K_PHY_PA_CTL, 840 { 0x00000007, 0x0000000b, 0x0000000b } }, 841 { AR5K_PHY_GAIN, 842 { 0x0018fa61, 0x001a1a63, 0x001a1a63 } }, 843 { AR5K_PHY_DESIRED_SIZE, 844 { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } }, 845 { AR5K_PHY_SIG, 846 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, 847 { AR5K_PHY_AGCCOARSE, 848 { 0x3139605e, 0x3139605e, 0x3139605e } }, 849 { AR5K_PHY_WEAK_OFDM_LOW_THR, 850 { 0x050cb081, 0x050cb081, 0x050cb081 } }, 851 { AR5K_PHY_RX_DELAY, 852 { 0x000007d0, 0x0000044c, 0x00000898 } }, 853 { AR5K_PHY_FRAME_CTL_5211, 854 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } }, 855 { AR5K_PHY_CCKTXCTL, 856 { 0x00000000, 0x00000000, 0x00000000 } }, 857 { AR5K_PHY_CCK_CROSSCORR, 858 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } }, 859 { AR5K_PHY_GAIN_2GHZ, 860 { 0x002ec1e0, 0x002ac120, 0x002ac120 } }, 861 { AR5K_PHY_CCK_RX_CTL_4, 862 { 0x1883800a, 0x1863800a, 0x1883800a } }, 863 { 0xa300, 864 { 0x18010000, 0x18010000, 0x18010000 } }, 865 { 0xa304, 866 { 0x30032602, 0x30032602, 0x30032602 } }, 867 { 0xa308, 868 { 0x48073e06, 0x48073e06, 0x48073e06 } }, 869 { 0xa30c, 870 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } }, 871 { 0xa310, 872 { 0x641a600f, 0x641a600f, 0x641a600f } }, 873 { 0xa314, 874 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } }, 875 { 0xa318, 876 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } }, 877 { 0xa31c, 878 { 0x90cf865b, 0x8ecf865b, 0x8ecf865b } }, 879 { 0xa320, 880 { 0x9d4f970f, 0x9b4f970f, 0x9b4f970f } }, 881 { 0xa324, 882 { 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f } }, 883 { 0xa328, 884 { 0xb55faf1f, 0xb35faf1f, 0xb35faf1f } }, 885 { 0xa32c, 886 { 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f } }, 887 { 0xa330, 888 { 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f } }, 889 { 0xa334, 890 { 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } }, 891 }; 892 893 static const struct ath5k_ini rf5413_ini_common_end[] = { 894 { AR5K_DCU_FP, 0x000003e0 }, 895 { AR5K_5414_CBCFG, 0x00000010 }, 896 { AR5K_SEQ_MASK, 0x0000000f }, 897 { 0x809c, 0x00000000 }, 898 { 0x80a0, 0x00000000 }, 899 { AR5K_MIC_QOS_CTL, 0x00000000 }, 900 { AR5K_MIC_QOS_SEL, 0x00000000 }, 901 { AR5K_MISC_MODE, 0x00000000 }, 902 { AR5K_OFDM_FIL_CNT, 0x00000000 }, 903 { AR5K_CCK_FIL_CNT, 0x00000000 }, 904 { AR5K_PHYERR_CNT1, 0x00000000 }, 905 { AR5K_PHYERR_CNT1_MASK, 0x00000000 }, 906 { AR5K_PHYERR_CNT2, 0x00000000 }, 907 { AR5K_PHYERR_CNT2_MASK, 0x00000000 }, 908 { AR5K_TSF_THRES, 0x00000000 }, 909 { 0x8140, 0x800003f9 }, 910 { 0x8144, 0x00000000 }, 911 { AR5K_PHY_AGC, 0x00000000 }, 912 { AR5K_PHY_ADC_CTL, 0x0000a000 }, 913 { 0x983c, 0x00200400 }, 914 { AR5K_PHY_GAIN_OFFSET, 0x1284233c }, 915 { AR5K_PHY_SCR, 0x0000001f }, 916 { AR5K_PHY_SLMT, 0x00000080 }, 917 { AR5K_PHY_SCAL, 0x0000000e }, 918 { 0x9958, 0x00081fff }, 919 { AR5K_PHY_TIMING_7, 0x00000000 }, 920 { AR5K_PHY_TIMING_8, 0x02800000 }, 921 { AR5K_PHY_TIMING_11, 0x00000000 }, 922 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 }, 923 { 0x99e4, 0xaaaaaaaa }, 924 { 0x99e8, 0x3c466478 }, 925 { 0x99ec, 0x000000aa }, 926 { AR5K_PHY_SCLOCK, 0x0000000c }, 927 { AR5K_PHY_SDELAY, 0x000000ff }, 928 { AR5K_PHY_SPENDING, 0x00000014 }, 929 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 }, 930 { 0xa23c, 0x93c889af }, 931 { AR5K_PHY_FAST_ADC, 0x00000001 }, 932 { 0xa250, 0x0000a000 }, 933 { AR5K_PHY_BLUETOOTH, 0x00000000 }, 934 { AR5K_PHY_TPC_RG1, 0x0cc75380 }, 935 { 0xa25c, 0x0f0f0f01 }, 936 { 0xa260, 0x5f690f01 }, 937 { 0xa264, 0x00418a11 }, 938 { 0xa268, 0x00000000 }, 939 { AR5K_PHY_TPC_RG5, 0x0c30c16a }, 940 { 0xa270, 0x00820820 }, 941 { 0xa274, 0x081b7caa }, 942 { 0xa278, 0x1ce739ce }, 943 { 0xa27c, 0x051701ce }, 944 { 0xa338, 0x00000000 }, 945 { 0xa33c, 0x00000000 }, 946 { 0xa340, 0x00000000 }, 947 { 0xa344, 0x00000000 }, 948 { 0xa348, 0x3fffffff }, 949 { 0xa34c, 0x3fffffff }, 950 { 0xa350, 0x3fffffff }, 951 { 0xa354, 0x0003ffff }, 952 { 0xa358, 0x79a8aa1f }, 953 { 0xa35c, 0x066c420f }, 954 { 0xa360, 0x0f282207 }, 955 { 0xa364, 0x17601685 }, 956 { 0xa368, 0x1f801104 }, 957 { 0xa36c, 0x37a00c03 }, 958 { 0xa370, 0x3fc40883 }, 959 { 0xa374, 0x57c00803 }, 960 { 0xa378, 0x5fd80682 }, 961 { 0xa37c, 0x7fe00482 }, 962 { 0xa380, 0x7f3c7bba }, 963 { 0xa384, 0xf3307ff0 }, 964 }; 965 966 /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */ 967 /* XXX: a mode ? */ 968 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = { 969 { AR5K_TXCFG, 970 /* A/XR B G */ 971 { 0x00000015, 0x00000015, 0x00000015 } }, 972 { AR5K_USEC_5211, 973 { 0x128d93a7, 0x04e01395, 0x12e013ab } }, 974 { AR5K_PHY_RF_CTL3, 975 { 0x0a020001, 0x05020000, 0x0a020001 } }, 976 { AR5K_PHY_RF_CTL4, 977 { 0x00000e00, 0x00000e00, 0x00000e00 } }, 978 { AR5K_PHY_PA_CTL, 979 { 0x00000002, 0x0000000a, 0x0000000a } }, 980 { AR5K_PHY_GAIN, 981 { 0x0018da6d, 0x001a6a64, 0x001a6a64 } }, 982 { AR5K_PHY_DESIRED_SIZE, 983 { 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da } }, 984 { AR5K_PHY_SIG, 985 { 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e } }, 986 { AR5K_PHY_AGCCOARSE, 987 { 0x3137665e, 0x3137665e, 0x3139605e } }, 988 { AR5K_PHY_WEAK_OFDM_LOW_THR, 989 { 0x050cb081, 0x050cb081, 0x050cb081 } }, 990 { AR5K_PHY_RX_DELAY, 991 { 0x000007d0, 0x0000044c, 0x00000898 } }, 992 { AR5K_PHY_FRAME_CTL_5211, 993 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } }, 994 { AR5K_PHY_CCKTXCTL, 995 { 0x00000000, 0x00000000, 0x00000000 } }, 996 { AR5K_PHY_CCK_CROSSCORR, 997 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } }, 998 { AR5K_PHY_GAIN_2GHZ, 999 { 0x002c0140, 0x0042c140, 0x0042c140 } }, 1000 { AR5K_PHY_CCK_RX_CTL_4, 1001 { 0x1883800a, 0x1863800a, 0x1883800a } }, 1002 }; 1003 1004 static const struct ath5k_ini rf2413_ini_common_end[] = { 1005 { AR5K_DCU_FP, 0x000003e0 }, 1006 { AR5K_SEQ_MASK, 0x0000000f }, 1007 { AR5K_MIC_QOS_CTL, 0x00000000 }, 1008 { AR5K_MIC_QOS_SEL, 0x00000000 }, 1009 { AR5K_MISC_MODE, 0x00000000 }, 1010 { AR5K_OFDM_FIL_CNT, 0x00000000 }, 1011 { AR5K_CCK_FIL_CNT, 0x00000000 }, 1012 { AR5K_PHYERR_CNT1, 0x00000000 }, 1013 { AR5K_PHYERR_CNT1_MASK, 0x00000000 }, 1014 { AR5K_PHYERR_CNT2, 0x00000000 }, 1015 { AR5K_PHYERR_CNT2_MASK, 0x00000000 }, 1016 { AR5K_TSF_THRES, 0x00000000 }, 1017 { 0x8140, 0x800000a8 }, 1018 { 0x8144, 0x00000000 }, 1019 { AR5K_PHY_AGC, 0x00000000 }, 1020 { AR5K_PHY_ADC_CTL, 0x0000a000 }, 1021 { 0x983c, 0x00200400 }, 1022 { AR5K_PHY_GAIN_OFFSET, 0x1284233c }, 1023 { AR5K_PHY_SCR, 0x0000001f }, 1024 { AR5K_PHY_SLMT, 0x00000080 }, 1025 { AR5K_PHY_SCAL, 0x0000000e }, 1026 { 0x9958, 0x000000ff }, 1027 { AR5K_PHY_TIMING_7, 0x00000000 }, 1028 { AR5K_PHY_TIMING_8, 0x02800000 }, 1029 { AR5K_PHY_TIMING_11, 0x00000000 }, 1030 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 }, 1031 { 0x99e4, 0xaaaaaaaa }, 1032 { 0x99e8, 0x3c466478 }, 1033 { 0x99ec, 0x000000aa }, 1034 { AR5K_PHY_SCLOCK, 0x0000000c }, 1035 { AR5K_PHY_SDELAY, 0x000000ff }, 1036 { AR5K_PHY_SPENDING, 0x00000014 }, 1037 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 }, 1038 { 0xa23c, 0x93c889af }, 1039 { AR5K_PHY_FAST_ADC, 0x00000001 }, 1040 { 0xa250, 0x0000a000 }, 1041 { AR5K_PHY_BLUETOOTH, 0x00000000 }, 1042 { AR5K_PHY_TPC_RG1, 0x0cc75380 }, 1043 { 0xa25c, 0x0f0f0f01 }, 1044 { 0xa260, 0x5f690f01 }, 1045 { 0xa264, 0x00418a11 }, 1046 { 0xa268, 0x00000000 }, 1047 { AR5K_PHY_TPC_RG5, 0x0c30c16a }, 1048 { 0xa270, 0x00820820 }, 1049 { 0xa274, 0x001b7caa }, 1050 { 0xa278, 0x1ce739ce }, 1051 { 0xa27c, 0x051701ce }, 1052 { 0xa300, 0x18010000 }, 1053 { 0xa304, 0x30032602 }, 1054 { 0xa308, 0x48073e06 }, 1055 { 0xa30c, 0x560b4c0a }, 1056 { 0xa310, 0x641a600f }, 1057 { 0xa314, 0x784f6e1b }, 1058 { 0xa318, 0x868f7c5a }, 1059 { 0xa31c, 0x8ecf865b }, 1060 { 0xa320, 0x9d4f970f }, 1061 { 0xa324, 0xa5cfa18f }, 1062 { 0xa328, 0xb55faf1f }, 1063 { 0xa32c, 0xbddfb99f }, 1064 { 0xa330, 0xcd7fc73f }, 1065 { 0xa334, 0xd5ffd1bf }, 1066 { 0xa338, 0x00000000 }, 1067 { 0xa33c, 0x00000000 }, 1068 { 0xa340, 0x00000000 }, 1069 { 0xa344, 0x00000000 }, 1070 { 0xa348, 0x3fffffff }, 1071 { 0xa34c, 0x3fffffff }, 1072 { 0xa350, 0x3fffffff }, 1073 { 0xa354, 0x0003ffff }, 1074 { 0xa358, 0x79a8aa1f }, 1075 { 0xa35c, 0x066c420f }, 1076 { 0xa360, 0x0f282207 }, 1077 { 0xa364, 0x17601685 }, 1078 { 0xa368, 0x1f801104 }, 1079 { 0xa36c, 0x37a00c03 }, 1080 { 0xa370, 0x3fc40883 }, 1081 { 0xa374, 0x57c00803 }, 1082 { 0xa378, 0x5fd80682 }, 1083 { 0xa37c, 0x7fe00482 }, 1084 { 0xa380, 0x7f3c7bba }, 1085 { 0xa384, 0xf3307ff0 }, 1086 }; 1087 1088 /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */ 1089 /* XXX: a mode ? */ 1090 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = { 1091 { AR5K_TXCFG, 1092 /* A/XR B G */ 1093 { 0x00000015, 0x00000015, 0x00000015 } }, 1094 { AR5K_USEC_5211, 1095 { 0x128d93a7, 0x04e01395, 0x12e013ab } }, 1096 { AR5K_PHY_RF_CTL3, 1097 { 0x0a020001, 0x05020100, 0x0a020001 } }, 1098 { AR5K_PHY_RF_CTL4, 1099 { 0x00000e0e, 0x00000e0e, 0x00000e0e } }, 1100 { AR5K_PHY_PA_CTL, 1101 { 0x00000003, 0x0000000b, 0x0000000b } }, 1102 { AR5K_PHY_SETTLING, 1103 { 0x1372161c, 0x13721722, 0x13721422 } }, 1104 { AR5K_PHY_GAIN, 1105 { 0x0018fa61, 0x00199a65, 0x00199a65 } }, 1106 { AR5K_PHY_DESIRED_SIZE, 1107 { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } }, 1108 { AR5K_PHY_SIG, 1109 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, 1110 { AR5K_PHY_AGCCOARSE, 1111 { 0x3139605e, 0x3139605e, 0x3139605e } }, 1112 { AR5K_PHY_WEAK_OFDM_LOW_THR, 1113 { 0x050cb081, 0x050cb081, 0x050cb081 } }, 1114 { AR5K_PHY_RX_DELAY, 1115 { 0x000007d0, 0x0000044c, 0x00000898 } }, 1116 { AR5K_PHY_FRAME_CTL_5211, 1117 { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } }, 1118 { AR5K_PHY_CCKTXCTL, 1119 { 0x00000000, 0x00000000, 0x00000000 } }, 1120 { AR5K_PHY_CCK_CROSSCORR, 1121 { 0xd6be6788, 0xd03e6788, 0xd03e6788 } }, 1122 { AR5K_PHY_GAIN_2GHZ, 1123 { 0x00000140, 0x0052c140, 0x0052c140 } }, 1124 { AR5K_PHY_CCK_RX_CTL_4, 1125 { 0x1883800a, 0x1863800a, 0x1883800a } }, 1126 { 0xa324, 1127 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, 1128 { 0xa328, 1129 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, 1130 { 0xa32c, 1131 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, 1132 { 0xa330, 1133 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, 1134 { 0xa334, 1135 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, 1136 }; 1137 1138 static const struct ath5k_ini rf2425_ini_common_end[] = { 1139 { AR5K_DCU_FP, 0x000003e0 }, 1140 { AR5K_SEQ_MASK, 0x0000000f }, 1141 { 0x809c, 0x00000000 }, 1142 { 0x80a0, 0x00000000 }, 1143 { AR5K_MIC_QOS_CTL, 0x00000000 }, 1144 { AR5K_MIC_QOS_SEL, 0x00000000 }, 1145 { AR5K_MISC_MODE, 0x00000000 }, 1146 { AR5K_OFDM_FIL_CNT, 0x00000000 }, 1147 { AR5K_CCK_FIL_CNT, 0x00000000 }, 1148 { AR5K_PHYERR_CNT1, 0x00000000 }, 1149 { AR5K_PHYERR_CNT1_MASK, 0x00000000 }, 1150 { AR5K_PHYERR_CNT2, 0x00000000 }, 1151 { AR5K_PHYERR_CNT2_MASK, 0x00000000 }, 1152 { AR5K_TSF_THRES, 0x00000000 }, 1153 { 0x8140, 0x800003f9 }, 1154 { 0x8144, 0x00000000 }, 1155 { AR5K_PHY_AGC, 0x00000000 }, 1156 { AR5K_PHY_ADC_CTL, 0x0000a000 }, 1157 { 0x983c, 0x00200400 }, 1158 { AR5K_PHY_GAIN_OFFSET, 0x1284233c }, 1159 { AR5K_PHY_SCR, 0x0000001f }, 1160 { AR5K_PHY_SLMT, 0x00000080 }, 1161 { AR5K_PHY_SCAL, 0x0000000e }, 1162 { 0x9958, 0x00081fff }, 1163 { AR5K_PHY_TIMING_7, 0x00000000 }, 1164 { AR5K_PHY_TIMING_8, 0x02800000 }, 1165 { AR5K_PHY_TIMING_11, 0x00000000 }, 1166 { 0x99dc, 0xfebadbe8 }, 1167 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 }, 1168 { 0x99e4, 0xaaaaaaaa }, 1169 { 0x99e8, 0x3c466478 }, 1170 { 0x99ec, 0x000000aa }, 1171 { AR5K_PHY_SCLOCK, 0x0000000c }, 1172 { AR5K_PHY_SDELAY, 0x000000ff }, 1173 { AR5K_PHY_SPENDING, 0x00000014 }, 1174 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 }, 1175 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, 1176 { AR5K_PHY_TXPOWER_RATE4, 0x20202020 }, 1177 { 0xa23c, 0x93c889af }, 1178 { AR5K_PHY_FAST_ADC, 0x00000001 }, 1179 { 0xa250, 0x0000a000 }, 1180 { AR5K_PHY_BLUETOOTH, 0x00000000 }, 1181 { AR5K_PHY_TPC_RG1, 0x0cc75380 }, 1182 { 0xa25c, 0x0f0f0f01 }, 1183 { 0xa260, 0x5f690f01 }, 1184 { 0xa264, 0x00418a11 }, 1185 { 0xa268, 0x00000000 }, 1186 { AR5K_PHY_TPC_RG5, 0x0c30c166 }, 1187 { 0xa270, 0x00820820 }, 1188 { 0xa274, 0x081a3caa }, 1189 { 0xa278, 0x1ce739ce }, 1190 { 0xa27c, 0x051701ce }, 1191 { 0xa300, 0x16010000 }, 1192 { 0xa304, 0x2c032402 }, 1193 { 0xa308, 0x48433e42 }, 1194 { 0xa30c, 0x5a0f500b }, 1195 { 0xa310, 0x6c4b624a }, 1196 { 0xa314, 0x7e8b748a }, 1197 { 0xa318, 0x96cf8ccb }, 1198 { 0xa31c, 0xa34f9d0f }, 1199 { 0xa320, 0xa7cfa58f }, 1200 { 0xa348, 0x3fffffff }, 1201 { 0xa34c, 0x3fffffff }, 1202 { 0xa350, 0x3fffffff }, 1203 { 0xa354, 0x0003ffff }, 1204 { 0xa358, 0x79a8aa1f }, 1205 { 0xa35c, 0x066c420f }, 1206 { 0xa360, 0x0f282207 }, 1207 { 0xa364, 0x17601685 }, 1208 { 0xa368, 0x1f801104 }, 1209 { 0xa36c, 0x37a00c03 }, 1210 { 0xa370, 0x3fc40883 }, 1211 { 0xa374, 0x57c00803 }, 1212 { 0xa378, 0x5fd80682 }, 1213 { 0xa37c, 0x7fe00482 }, 1214 { 0xa380, 0x7f3c7bba }, 1215 { 0xa384, 0xf3307ff0 }, 1216 }; 1217 1218 /* 1219 * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with 1220 * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI) 1221 */ 1222 1223 /* RF5111 Initial BaseBand Gain settings */ 1224 static const struct ath5k_ini rf5111_ini_bbgain[] = { 1225 { AR5K_BB_GAIN(0), 0x00000000 }, 1226 { AR5K_BB_GAIN(1), 0x00000020 }, 1227 { AR5K_BB_GAIN(2), 0x00000010 }, 1228 { AR5K_BB_GAIN(3), 0x00000030 }, 1229 { AR5K_BB_GAIN(4), 0x00000008 }, 1230 { AR5K_BB_GAIN(5), 0x00000028 }, 1231 { AR5K_BB_GAIN(6), 0x00000004 }, 1232 { AR5K_BB_GAIN(7), 0x00000024 }, 1233 { AR5K_BB_GAIN(8), 0x00000014 }, 1234 { AR5K_BB_GAIN(9), 0x00000034 }, 1235 { AR5K_BB_GAIN(10), 0x0000000c }, 1236 { AR5K_BB_GAIN(11), 0x0000002c }, 1237 { AR5K_BB_GAIN(12), 0x00000002 }, 1238 { AR5K_BB_GAIN(13), 0x00000022 }, 1239 { AR5K_BB_GAIN(14), 0x00000012 }, 1240 { AR5K_BB_GAIN(15), 0x00000032 }, 1241 { AR5K_BB_GAIN(16), 0x0000000a }, 1242 { AR5K_BB_GAIN(17), 0x0000002a }, 1243 { AR5K_BB_GAIN(18), 0x00000006 }, 1244 { AR5K_BB_GAIN(19), 0x00000026 }, 1245 { AR5K_BB_GAIN(20), 0x00000016 }, 1246 { AR5K_BB_GAIN(21), 0x00000036 }, 1247 { AR5K_BB_GAIN(22), 0x0000000e }, 1248 { AR5K_BB_GAIN(23), 0x0000002e }, 1249 { AR5K_BB_GAIN(24), 0x00000001 }, 1250 { AR5K_BB_GAIN(25), 0x00000021 }, 1251 { AR5K_BB_GAIN(26), 0x00000011 }, 1252 { AR5K_BB_GAIN(27), 0x00000031 }, 1253 { AR5K_BB_GAIN(28), 0x00000009 }, 1254 { AR5K_BB_GAIN(29), 0x00000029 }, 1255 { AR5K_BB_GAIN(30), 0x00000005 }, 1256 { AR5K_BB_GAIN(31), 0x00000025 }, 1257 { AR5K_BB_GAIN(32), 0x00000015 }, 1258 { AR5K_BB_GAIN(33), 0x00000035 }, 1259 { AR5K_BB_GAIN(34), 0x0000000d }, 1260 { AR5K_BB_GAIN(35), 0x0000002d }, 1261 { AR5K_BB_GAIN(36), 0x00000003 }, 1262 { AR5K_BB_GAIN(37), 0x00000023 }, 1263 { AR5K_BB_GAIN(38), 0x00000013 }, 1264 { AR5K_BB_GAIN(39), 0x00000033 }, 1265 { AR5K_BB_GAIN(40), 0x0000000b }, 1266 { AR5K_BB_GAIN(41), 0x0000002b }, 1267 { AR5K_BB_GAIN(42), 0x0000002b }, 1268 { AR5K_BB_GAIN(43), 0x0000002b }, 1269 { AR5K_BB_GAIN(44), 0x0000002b }, 1270 { AR5K_BB_GAIN(45), 0x0000002b }, 1271 { AR5K_BB_GAIN(46), 0x0000002b }, 1272 { AR5K_BB_GAIN(47), 0x0000002b }, 1273 { AR5K_BB_GAIN(48), 0x0000002b }, 1274 { AR5K_BB_GAIN(49), 0x0000002b }, 1275 { AR5K_BB_GAIN(50), 0x0000002b }, 1276 { AR5K_BB_GAIN(51), 0x0000002b }, 1277 { AR5K_BB_GAIN(52), 0x0000002b }, 1278 { AR5K_BB_GAIN(53), 0x0000002b }, 1279 { AR5K_BB_GAIN(54), 0x0000002b }, 1280 { AR5K_BB_GAIN(55), 0x0000002b }, 1281 { AR5K_BB_GAIN(56), 0x0000002b }, 1282 { AR5K_BB_GAIN(57), 0x0000002b }, 1283 { AR5K_BB_GAIN(58), 0x0000002b }, 1284 { AR5K_BB_GAIN(59), 0x0000002b }, 1285 { AR5K_BB_GAIN(60), 0x0000002b }, 1286 { AR5K_BB_GAIN(61), 0x0000002b }, 1287 { AR5K_BB_GAIN(62), 0x00000002 }, 1288 { AR5K_BB_GAIN(63), 0x00000016 }, 1289 }; 1290 1291 /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */ 1292 static const struct ath5k_ini rf5112_ini_bbgain[] = { 1293 { AR5K_BB_GAIN(0), 0x00000000 }, 1294 { AR5K_BB_GAIN(1), 0x00000001 }, 1295 { AR5K_BB_GAIN(2), 0x00000002 }, 1296 { AR5K_BB_GAIN(3), 0x00000003 }, 1297 { AR5K_BB_GAIN(4), 0x00000004 }, 1298 { AR5K_BB_GAIN(5), 0x00000005 }, 1299 { AR5K_BB_GAIN(6), 0x00000008 }, 1300 { AR5K_BB_GAIN(7), 0x00000009 }, 1301 { AR5K_BB_GAIN(8), 0x0000000a }, 1302 { AR5K_BB_GAIN(9), 0x0000000b }, 1303 { AR5K_BB_GAIN(10), 0x0000000c }, 1304 { AR5K_BB_GAIN(11), 0x0000000d }, 1305 { AR5K_BB_GAIN(12), 0x00000010 }, 1306 { AR5K_BB_GAIN(13), 0x00000011 }, 1307 { AR5K_BB_GAIN(14), 0x00000012 }, 1308 { AR5K_BB_GAIN(15), 0x00000013 }, 1309 { AR5K_BB_GAIN(16), 0x00000014 }, 1310 { AR5K_BB_GAIN(17), 0x00000015 }, 1311 { AR5K_BB_GAIN(18), 0x00000018 }, 1312 { AR5K_BB_GAIN(19), 0x00000019 }, 1313 { AR5K_BB_GAIN(20), 0x0000001a }, 1314 { AR5K_BB_GAIN(21), 0x0000001b }, 1315 { AR5K_BB_GAIN(22), 0x0000001c }, 1316 { AR5K_BB_GAIN(23), 0x0000001d }, 1317 { AR5K_BB_GAIN(24), 0x00000020 }, 1318 { AR5K_BB_GAIN(25), 0x00000021 }, 1319 { AR5K_BB_GAIN(26), 0x00000022 }, 1320 { AR5K_BB_GAIN(27), 0x00000023 }, 1321 { AR5K_BB_GAIN(28), 0x00000024 }, 1322 { AR5K_BB_GAIN(29), 0x00000025 }, 1323 { AR5K_BB_GAIN(30), 0x00000028 }, 1324 { AR5K_BB_GAIN(31), 0x00000029 }, 1325 { AR5K_BB_GAIN(32), 0x0000002a }, 1326 { AR5K_BB_GAIN(33), 0x0000002b }, 1327 { AR5K_BB_GAIN(34), 0x0000002c }, 1328 { AR5K_BB_GAIN(35), 0x0000002d }, 1329 { AR5K_BB_GAIN(36), 0x00000030 }, 1330 { AR5K_BB_GAIN(37), 0x00000031 }, 1331 { AR5K_BB_GAIN(38), 0x00000032 }, 1332 { AR5K_BB_GAIN(39), 0x00000033 }, 1333 { AR5K_BB_GAIN(40), 0x00000034 }, 1334 { AR5K_BB_GAIN(41), 0x00000035 }, 1335 { AR5K_BB_GAIN(42), 0x00000035 }, 1336 { AR5K_BB_GAIN(43), 0x00000035 }, 1337 { AR5K_BB_GAIN(44), 0x00000035 }, 1338 { AR5K_BB_GAIN(45), 0x00000035 }, 1339 { AR5K_BB_GAIN(46), 0x00000035 }, 1340 { AR5K_BB_GAIN(47), 0x00000035 }, 1341 { AR5K_BB_GAIN(48), 0x00000035 }, 1342 { AR5K_BB_GAIN(49), 0x00000035 }, 1343 { AR5K_BB_GAIN(50), 0x00000035 }, 1344 { AR5K_BB_GAIN(51), 0x00000035 }, 1345 { AR5K_BB_GAIN(52), 0x00000035 }, 1346 { AR5K_BB_GAIN(53), 0x00000035 }, 1347 { AR5K_BB_GAIN(54), 0x00000035 }, 1348 { AR5K_BB_GAIN(55), 0x00000035 }, 1349 { AR5K_BB_GAIN(56), 0x00000035 }, 1350 { AR5K_BB_GAIN(57), 0x00000035 }, 1351 { AR5K_BB_GAIN(58), 0x00000035 }, 1352 { AR5K_BB_GAIN(59), 0x00000035 }, 1353 { AR5K_BB_GAIN(60), 0x00000035 }, 1354 { AR5K_BB_GAIN(61), 0x00000035 }, 1355 { AR5K_BB_GAIN(62), 0x00000010 }, 1356 { AR5K_BB_GAIN(63), 0x0000001a }, 1357 }; 1358 1359 1360 /* 1361 * Write initial register dump 1362 */ 1363 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size, 1364 const struct ath5k_ini *ini_regs, bool skip_pcu) 1365 { 1366 unsigned int i; 1367 1368 /* Write initial registers */ 1369 for (i = 0; i < size; i++) { 1370 /* Skip PCU registers if 1371 * requested */ 1372 if (skip_pcu && 1373 ini_regs[i].ini_register >= AR5K_PCU_MIN && 1374 ini_regs[i].ini_register <= AR5K_PCU_MAX) 1375 continue; 1376 1377 switch (ini_regs[i].ini_mode) { 1378 case AR5K_INI_READ: 1379 /* Cleared on read */ 1380 ath5k_hw_reg_read(ah, ini_regs[i].ini_register); 1381 break; 1382 case AR5K_INI_WRITE: 1383 default: 1384 AR5K_REG_WAIT(i); 1385 ath5k_hw_reg_write(ah, ini_regs[i].ini_value, 1386 ini_regs[i].ini_register); 1387 } 1388 } 1389 } 1390 1391 static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah, 1392 unsigned int size, const struct ath5k_ini_mode *ini_mode, 1393 u8 mode) 1394 { 1395 unsigned int i; 1396 1397 for (i = 0; i < size; i++) { 1398 AR5K_REG_WAIT(i); 1399 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode], 1400 (u32)ini_mode[i].mode_register); 1401 } 1402 1403 } 1404 1405 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu) 1406 { 1407 /* 1408 * Write initial register settings 1409 */ 1410 1411 /* For AR5212 and compatible */ 1412 if (ah->ah_version == AR5K_AR5212) { 1413 1414 /* First set of mode-specific settings */ 1415 ath5k_hw_ini_mode_registers(ah, 1416 ARRAY_SIZE(ar5212_ini_mode_start), 1417 ar5212_ini_mode_start, mode); 1418 1419 /* 1420 * Write initial settings common for all modes 1421 */ 1422 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start), 1423 ar5212_ini_common_start, skip_pcu); 1424 1425 /* Second set of mode-specific settings */ 1426 switch (ah->ah_radio) { 1427 case AR5K_RF5111: 1428 1429 ath5k_hw_ini_mode_registers(ah, 1430 ARRAY_SIZE(rf5111_ini_mode_end), 1431 rf5111_ini_mode_end, mode); 1432 1433 ath5k_hw_ini_registers(ah, 1434 ARRAY_SIZE(rf5111_ini_common_end), 1435 rf5111_ini_common_end, skip_pcu); 1436 1437 /* Baseband gain table */ 1438 ath5k_hw_ini_registers(ah, 1439 ARRAY_SIZE(rf5111_ini_bbgain), 1440 rf5111_ini_bbgain, skip_pcu); 1441 1442 break; 1443 case AR5K_RF5112: 1444 1445 ath5k_hw_ini_mode_registers(ah, 1446 ARRAY_SIZE(rf5112_ini_mode_end), 1447 rf5112_ini_mode_end, mode); 1448 1449 ath5k_hw_ini_registers(ah, 1450 ARRAY_SIZE(rf5112_ini_common_end), 1451 rf5112_ini_common_end, skip_pcu); 1452 1453 ath5k_hw_ini_registers(ah, 1454 ARRAY_SIZE(rf5112_ini_bbgain), 1455 rf5112_ini_bbgain, skip_pcu); 1456 1457 break; 1458 case AR5K_RF5413: 1459 1460 ath5k_hw_ini_mode_registers(ah, 1461 ARRAY_SIZE(rf5413_ini_mode_end), 1462 rf5413_ini_mode_end, mode); 1463 1464 ath5k_hw_ini_registers(ah, 1465 ARRAY_SIZE(rf5413_ini_common_end), 1466 rf5413_ini_common_end, skip_pcu); 1467 1468 ath5k_hw_ini_registers(ah, 1469 ARRAY_SIZE(rf5112_ini_bbgain), 1470 rf5112_ini_bbgain, skip_pcu); 1471 1472 break; 1473 case AR5K_RF2316: 1474 case AR5K_RF2413: 1475 1476 ath5k_hw_ini_mode_registers(ah, 1477 ARRAY_SIZE(rf2413_ini_mode_end), 1478 rf2413_ini_mode_end, mode); 1479 1480 ath5k_hw_ini_registers(ah, 1481 ARRAY_SIZE(rf2413_ini_common_end), 1482 rf2413_ini_common_end, skip_pcu); 1483 1484 /* Override settings from rf2413_ini_common_end */ 1485 if (ah->ah_radio == AR5K_RF2316) { 1486 ath5k_hw_reg_write(ah, 0x00004000, 1487 AR5K_PHY_AGC); 1488 ath5k_hw_reg_write(ah, 0x081b7caa, 1489 0xa274); 1490 } 1491 1492 ath5k_hw_ini_registers(ah, 1493 ARRAY_SIZE(rf5112_ini_bbgain), 1494 rf5112_ini_bbgain, skip_pcu); 1495 break; 1496 case AR5K_RF2317: 1497 1498 ath5k_hw_ini_mode_registers(ah, 1499 ARRAY_SIZE(rf2413_ini_mode_end), 1500 rf2413_ini_mode_end, mode); 1501 1502 ath5k_hw_ini_registers(ah, 1503 ARRAY_SIZE(rf2425_ini_common_end), 1504 rf2425_ini_common_end, skip_pcu); 1505 1506 /* Override settings from rf2413_ini_mode_end */ 1507 ath5k_hw_reg_write(ah, 0x00180a65, AR5K_PHY_GAIN); 1508 1509 /* Override settings from rf2413_ini_common_end */ 1510 ath5k_hw_reg_write(ah, 0x00004000, AR5K_PHY_AGC); 1511 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TPC_RG5, 1512 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP, 0xa); 1513 ath5k_hw_reg_write(ah, 0x800000a8, 0x8140); 1514 ath5k_hw_reg_write(ah, 0x000000ff, 0x9958); 1515 1516 ath5k_hw_ini_registers(ah, 1517 ARRAY_SIZE(rf5112_ini_bbgain), 1518 rf5112_ini_bbgain, skip_pcu); 1519 break; 1520 case AR5K_RF2425: 1521 1522 ath5k_hw_ini_mode_registers(ah, 1523 ARRAY_SIZE(rf2425_ini_mode_end), 1524 rf2425_ini_mode_end, mode); 1525 1526 ath5k_hw_ini_registers(ah, 1527 ARRAY_SIZE(rf2425_ini_common_end), 1528 rf2425_ini_common_end, skip_pcu); 1529 1530 ath5k_hw_ini_registers(ah, 1531 ARRAY_SIZE(rf5112_ini_bbgain), 1532 rf5112_ini_bbgain, skip_pcu); 1533 break; 1534 default: 1535 return -EINVAL; 1536 1537 } 1538 1539 /* For AR5211 */ 1540 } else if (ah->ah_version == AR5K_AR5211) { 1541 1542 /* AR5K_MODE_11B */ 1543 if (mode > 2) { 1544 ATH5K_ERR(ah, 1545 "unsupported channel mode: %d\n", mode); 1546 return -EINVAL; 1547 } 1548 1549 /* Mode-specific settings */ 1550 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode), 1551 ar5211_ini_mode, mode); 1552 1553 /* 1554 * Write initial settings common for all modes 1555 */ 1556 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini), 1557 ar5211_ini, skip_pcu); 1558 1559 /* AR5211 only comes with 5111 */ 1560 1561 /* Baseband gain table */ 1562 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain), 1563 rf5111_ini_bbgain, skip_pcu); 1564 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */ 1565 } else if (ah->ah_version == AR5K_AR5210) { 1566 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini), 1567 ar5210_ini, skip_pcu); 1568 } 1569 1570 return 0; 1571 } 1572