1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 */ 19 20 /*************************************\ 21 * EEPROM access functions and helpers * 22 \*************************************/ 23 24 #include "ath5k.h" 25 #include "reg.h" 26 #include "debug.h" 27 #include "base.h" 28 29 /* 30 * Read from eeprom 31 */ 32 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data) 33 { 34 u32 status, timeout; 35 36 ATH5K_TRACE(ah->ah_sc); 37 /* 38 * Initialize EEPROM access 39 */ 40 if (ah->ah_version == AR5K_AR5210) { 41 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); 42 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); 43 } else { 44 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); 45 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, 46 AR5K_EEPROM_CMD_READ); 47 } 48 49 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { 50 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); 51 if (status & AR5K_EEPROM_STAT_RDDONE) { 52 if (status & AR5K_EEPROM_STAT_RDERR) 53 return -EIO; 54 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & 55 0xffff); 56 return 0; 57 } 58 udelay(15); 59 } 60 61 return -ETIMEDOUT; 62 } 63 64 /* 65 * Translate binary channel representation in EEPROM to frequency 66 */ 67 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin, 68 unsigned int mode) 69 { 70 u16 val; 71 72 if (bin == AR5K_EEPROM_CHANNEL_DIS) 73 return bin; 74 75 if (mode == AR5K_EEPROM_MODE_11A) { 76 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) 77 val = (5 * bin) + 4800; 78 else 79 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : 80 (bin * 10) + 5100; 81 } else { 82 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) 83 val = bin + 2300; 84 else 85 val = bin + 2400; 86 } 87 88 return val; 89 } 90 91 /* 92 * Initialize eeprom & capabilities structs 93 */ 94 static int 95 ath5k_eeprom_init_header(struct ath5k_hw *ah) 96 { 97 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 98 int ret; 99 u16 val; 100 101 /* 102 * Read values from EEPROM and store them in the capability structure 103 */ 104 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic); 105 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect); 106 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain); 107 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version); 108 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header); 109 110 /* Return if we have an old EEPROM */ 111 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0) 112 return 0; 113 114 #ifdef notyet 115 /* 116 * Validate the checksum of the EEPROM date. There are some 117 * devices with invalid EEPROMs. 118 */ 119 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) { 120 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); 121 cksum ^= val; 122 } 123 if (cksum != AR5K_EEPROM_INFO_CKSUM) { 124 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum); 125 return -EIO; 126 } 127 #endif 128 129 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version), 130 ee_ant_gain); 131 132 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { 133 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0); 134 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1); 135 136 /* XXX: Don't know which versions include these two */ 137 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2); 138 139 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) 140 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3); 141 142 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) { 143 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4); 144 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5); 145 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6); 146 } 147 } 148 149 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { 150 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val); 151 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; 152 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; 153 154 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val); 155 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; 156 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; 157 } 158 159 AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val); 160 161 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val) 162 ee->ee_is_hb63 = true; 163 else 164 ee->ee_is_hb63 = false; 165 166 AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val); 167 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL); 168 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false; 169 170 /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION 171 * and enable serdes programming if needed. 172 * 173 * XXX: Serdes values seem to be fixed so 174 * no need to read them here, we write them 175 * during ath5k_hw_attach */ 176 AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val); 177 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ? 178 true : false; 179 180 return 0; 181 } 182 183 184 /* 185 * Read antenna infos from eeprom 186 */ 187 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset, 188 unsigned int mode) 189 { 190 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 191 u32 o = *offset; 192 u16 val; 193 int ret, i = 0; 194 195 AR5K_EEPROM_READ(o++, val); 196 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; 197 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; 198 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 199 200 AR5K_EEPROM_READ(o++, val); 201 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 202 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 203 ee->ee_ant_control[mode][i++] = val & 0x3f; 204 205 AR5K_EEPROM_READ(o++, val); 206 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; 207 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; 208 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; 209 210 AR5K_EEPROM_READ(o++, val); 211 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; 212 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; 213 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; 214 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; 215 216 AR5K_EEPROM_READ(o++, val); 217 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; 218 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; 219 ee->ee_ant_control[mode][i++] = val & 0x3f; 220 221 /* Get antenna switch tables */ 222 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] = 223 (ee->ee_ant_control[mode][0] << 4); 224 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] = 225 ee->ee_ant_control[mode][1] | 226 (ee->ee_ant_control[mode][2] << 6) | 227 (ee->ee_ant_control[mode][3] << 12) | 228 (ee->ee_ant_control[mode][4] << 18) | 229 (ee->ee_ant_control[mode][5] << 24); 230 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] = 231 ee->ee_ant_control[mode][6] | 232 (ee->ee_ant_control[mode][7] << 6) | 233 (ee->ee_ant_control[mode][8] << 12) | 234 (ee->ee_ant_control[mode][9] << 18) | 235 (ee->ee_ant_control[mode][10] << 24); 236 237 /* return new offset */ 238 *offset = o; 239 240 return 0; 241 } 242 243 /* 244 * Read supported modes and some mode-specific calibration data 245 * from eeprom 246 */ 247 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, 248 unsigned int mode) 249 { 250 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 251 u32 o = *offset; 252 u16 val; 253 int ret; 254 255 ee->ee_n_piers[mode] = 0; 256 AR5K_EEPROM_READ(o++, val); 257 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); 258 switch(mode) { 259 case AR5K_EEPROM_MODE_11A: 260 ee->ee_ob[mode][3] = (val >> 5) & 0x7; 261 ee->ee_db[mode][3] = (val >> 2) & 0x7; 262 ee->ee_ob[mode][2] = (val << 1) & 0x7; 263 264 AR5K_EEPROM_READ(o++, val); 265 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; 266 ee->ee_db[mode][2] = (val >> 12) & 0x7; 267 ee->ee_ob[mode][1] = (val >> 9) & 0x7; 268 ee->ee_db[mode][1] = (val >> 6) & 0x7; 269 ee->ee_ob[mode][0] = (val >> 3) & 0x7; 270 ee->ee_db[mode][0] = val & 0x7; 271 break; 272 case AR5K_EEPROM_MODE_11G: 273 case AR5K_EEPROM_MODE_11B: 274 ee->ee_ob[mode][1] = (val >> 4) & 0x7; 275 ee->ee_db[mode][1] = val & 0x7; 276 break; 277 } 278 279 AR5K_EEPROM_READ(o++, val); 280 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; 281 ee->ee_thr_62[mode] = val & 0xff; 282 283 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 284 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; 285 286 AR5K_EEPROM_READ(o++, val); 287 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; 288 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; 289 290 AR5K_EEPROM_READ(o++, val); 291 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; 292 293 if ((val & 0xff) & 0x80) 294 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); 295 else 296 ee->ee_noise_floor_thr[mode] = val & 0xff; 297 298 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) 299 ee->ee_noise_floor_thr[mode] = 300 mode == AR5K_EEPROM_MODE_11A ? -54 : -1; 301 302 AR5K_EEPROM_READ(o++, val); 303 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; 304 ee->ee_x_gain[mode] = (val >> 1) & 0xf; 305 ee->ee_xpd[mode] = val & 0x1; 306 307 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) 308 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; 309 310 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { 311 AR5K_EEPROM_READ(o++, val); 312 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; 313 314 if (mode == AR5K_EEPROM_MODE_11A) 315 ee->ee_xr_power[mode] = val & 0x3f; 316 else { 317 ee->ee_ob[mode][0] = val & 0x7; 318 ee->ee_db[mode][0] = (val >> 3) & 0x7; 319 } 320 } 321 322 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { 323 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; 324 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; 325 } else { 326 ee->ee_i_gain[mode] = (val >> 13) & 0x7; 327 328 AR5K_EEPROM_READ(o++, val); 329 ee->ee_i_gain[mode] |= (val << 3) & 0x38; 330 331 if (mode == AR5K_EEPROM_MODE_11G) { 332 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; 333 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6) 334 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; 335 } 336 } 337 338 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && 339 mode == AR5K_EEPROM_MODE_11A) { 340 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 341 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 342 } 343 344 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0) 345 goto done; 346 347 /* Note: >= v5 have bg freq piers on another location 348 * so these freq piers are ignored for >= v5 (should be 0xff 349 * anyway) */ 350 switch(mode) { 351 case AR5K_EEPROM_MODE_11A: 352 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1) 353 break; 354 355 AR5K_EEPROM_READ(o++, val); 356 ee->ee_margin_tx_rx[mode] = val & 0x3f; 357 break; 358 case AR5K_EEPROM_MODE_11B: 359 AR5K_EEPROM_READ(o++, val); 360 361 ee->ee_pwr_cal_b[0].freq = 362 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); 363 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS) 364 ee->ee_n_piers[mode]++; 365 366 ee->ee_pwr_cal_b[1].freq = 367 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); 368 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS) 369 ee->ee_n_piers[mode]++; 370 371 AR5K_EEPROM_READ(o++, val); 372 ee->ee_pwr_cal_b[2].freq = 373 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); 374 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS) 375 ee->ee_n_piers[mode]++; 376 377 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) 378 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 379 break; 380 case AR5K_EEPROM_MODE_11G: 381 AR5K_EEPROM_READ(o++, val); 382 383 ee->ee_pwr_cal_g[0].freq = 384 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); 385 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS) 386 ee->ee_n_piers[mode]++; 387 388 ee->ee_pwr_cal_g[1].freq = 389 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); 390 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS) 391 ee->ee_n_piers[mode]++; 392 393 AR5K_EEPROM_READ(o++, val); 394 ee->ee_turbo_max_power[mode] = val & 0x7f; 395 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; 396 397 AR5K_EEPROM_READ(o++, val); 398 ee->ee_pwr_cal_g[2].freq = 399 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); 400 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS) 401 ee->ee_n_piers[mode]++; 402 403 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) 404 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; 405 406 AR5K_EEPROM_READ(o++, val); 407 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; 408 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; 409 410 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { 411 AR5K_EEPROM_READ(o++, val); 412 ee->ee_cck_ofdm_gain_delta = val & 0xff; 413 } 414 break; 415 } 416 417 /* 418 * Read turbo mode information on newer EEPROM versions 419 */ 420 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0) 421 goto done; 422 423 switch (mode){ 424 case AR5K_EEPROM_MODE_11A: 425 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; 426 427 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7; 428 AR5K_EEPROM_READ(o++, val); 429 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3; 430 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f; 431 432 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f; 433 AR5K_EEPROM_READ(o++, val); 434 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; 435 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; 436 437 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2) 438 ee->ee_pd_gain_overlap = (val >> 9) & 0xf; 439 break; 440 case AR5K_EEPROM_MODE_11G: 441 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f; 442 443 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7; 444 AR5K_EEPROM_READ(o++, val); 445 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1; 446 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f; 447 448 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f; 449 AR5K_EEPROM_READ(o++, val); 450 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5; 451 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff; 452 break; 453 } 454 455 done: 456 /* return new offset */ 457 *offset = o; 458 459 return 0; 460 } 461 462 /* Read mode-specific data (except power calibration data) */ 463 static int 464 ath5k_eeprom_init_modes(struct ath5k_hw *ah) 465 { 466 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 467 u32 mode_offset[3]; 468 unsigned int mode; 469 u32 offset; 470 int ret; 471 472 /* 473 * Get values for all modes 474 */ 475 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version); 476 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version); 477 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version); 478 479 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] = 480 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); 481 482 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) { 483 offset = mode_offset[mode]; 484 485 ret = ath5k_eeprom_read_ants(ah, &offset, mode); 486 if (ret) 487 return ret; 488 489 ret = ath5k_eeprom_read_modes(ah, &offset, mode); 490 if (ret) 491 return ret; 492 } 493 494 /* override for older eeprom versions for better performance */ 495 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) { 496 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15; 497 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28; 498 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28; 499 } 500 501 return 0; 502 } 503 504 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff 505 * frequency mask) */ 506 static inline int 507 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max, 508 struct ath5k_chan_pcal_info *pc, unsigned int mode) 509 { 510 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 511 int o = *offset; 512 int i = 0; 513 u8 freq1, freq2; 514 int ret; 515 u16 val; 516 517 ee->ee_n_piers[mode] = 0; 518 while(i < max) { 519 AR5K_EEPROM_READ(o++, val); 520 521 freq1 = val & 0xff; 522 if (!freq1) 523 break; 524 525 pc[i++].freq = ath5k_eeprom_bin2freq(ee, 526 freq1, mode); 527 ee->ee_n_piers[mode]++; 528 529 freq2 = (val >> 8) & 0xff; 530 if (!freq2) 531 break; 532 533 pc[i++].freq = ath5k_eeprom_bin2freq(ee, 534 freq2, mode); 535 ee->ee_n_piers[mode]++; 536 } 537 538 /* return new offset */ 539 *offset = o; 540 541 return 0; 542 } 543 544 /* Read frequency piers for 802.11a */ 545 static int 546 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset) 547 { 548 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 549 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a; 550 int i, ret; 551 u16 val; 552 u8 mask; 553 554 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { 555 ath5k_eeprom_read_freq_list(ah, &offset, 556 AR5K_EEPROM_N_5GHZ_CHAN, pcal, 557 AR5K_EEPROM_MODE_11A); 558 } else { 559 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version); 560 561 AR5K_EEPROM_READ(offset++, val); 562 pcal[0].freq = (val >> 9) & mask; 563 pcal[1].freq = (val >> 2) & mask; 564 pcal[2].freq = (val << 5) & mask; 565 566 AR5K_EEPROM_READ(offset++, val); 567 pcal[2].freq |= (val >> 11) & 0x1f; 568 pcal[3].freq = (val >> 4) & mask; 569 pcal[4].freq = (val << 3) & mask; 570 571 AR5K_EEPROM_READ(offset++, val); 572 pcal[4].freq |= (val >> 13) & 0x7; 573 pcal[5].freq = (val >> 6) & mask; 574 pcal[6].freq = (val << 1) & mask; 575 576 AR5K_EEPROM_READ(offset++, val); 577 pcal[6].freq |= (val >> 15) & 0x1; 578 pcal[7].freq = (val >> 8) & mask; 579 pcal[8].freq = (val >> 1) & mask; 580 pcal[9].freq = (val << 6) & mask; 581 582 AR5K_EEPROM_READ(offset++, val); 583 pcal[9].freq |= (val >> 10) & 0x3f; 584 585 /* Fixed number of piers */ 586 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10; 587 588 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) { 589 pcal[i].freq = ath5k_eeprom_bin2freq(ee, 590 pcal[i].freq, AR5K_EEPROM_MODE_11A); 591 } 592 } 593 594 return 0; 595 } 596 597 /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */ 598 static inline int 599 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset) 600 { 601 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 602 struct ath5k_chan_pcal_info *pcal; 603 604 switch(mode) { 605 case AR5K_EEPROM_MODE_11B: 606 pcal = ee->ee_pwr_cal_b; 607 break; 608 case AR5K_EEPROM_MODE_11G: 609 pcal = ee->ee_pwr_cal_g; 610 break; 611 default: 612 return -EINVAL; 613 } 614 615 ath5k_eeprom_read_freq_list(ah, &offset, 616 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal, 617 mode); 618 619 return 0; 620 } 621 622 /* 623 * Read power calibration for RF5111 chips 624 * 625 * For RF5111 we have an XPD -eXternal Power Detector- curve 626 * for each calibrated channel. Each curve has 0,5dB Power steps 627 * on x axis and PCDAC steps (offsets) on y axis and looks like an 628 * exponential function. To recreate the curve we read 11 points 629 * here and interpolate later. 630 */ 631 632 /* Used to match PCDAC steps with power values on RF5111 chips 633 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC 634 * steps that match with the power values we read from eeprom. On 635 * older eeprom versions (< 3.2) these steps are equaly spaced at 636 * 10% of the pcdac curve -until the curve reaches it's maximum- 637 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2) 638 * these 11 steps are spaced in a different way. This function returns 639 * the pcdac steps based on eeprom version and curve min/max so that we 640 * can have pcdac/pwr points. 641 */ 642 static inline void 643 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp) 644 { 645 static const u16 intercepts3[] = 646 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 }; 647 static const u16 intercepts3_2[] = 648 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 }; 649 const u16 *ip; 650 int i; 651 652 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2) 653 ip = intercepts3_2; 654 else 655 ip = intercepts3; 656 657 for (i = 0; i < ARRAY_SIZE(intercepts3); i++) 658 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100; 659 } 660 661 /* Convert RF5111 specific data to generic raw data 662 * used by interpolation code */ 663 static int 664 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode, 665 struct ath5k_chan_pcal_info *chinfo) 666 { 667 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 668 struct ath5k_chan_pcal_info_rf5111 *pcinfo; 669 struct ath5k_pdgain_info *pd; 670 u8 pier, point, idx; 671 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; 672 673 /* Fill raw data for each calibration pier */ 674 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { 675 676 pcinfo = &chinfo[pier].rf5111_info; 677 678 /* Allocate pd_curves for this cal pier */ 679 chinfo[pier].pd_curves = 680 kcalloc(AR5K_EEPROM_N_PD_CURVES, 681 sizeof(struct ath5k_pdgain_info), 682 GFP_KERNEL); 683 684 if (!chinfo[pier].pd_curves) 685 return -ENOMEM; 686 687 /* Only one curve for RF5111 688 * find out which one and place 689 * in in pd_curves. 690 * Note: ee_x_gain is reversed here */ 691 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) { 692 693 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) { 694 pdgain_idx[0] = idx; 695 break; 696 } 697 } 698 699 ee->ee_pd_gains[mode] = 1; 700 701 pd = &chinfo[pier].pd_curves[idx]; 702 703 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111; 704 705 /* Allocate pd points for this curve */ 706 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111, 707 sizeof(u8), GFP_KERNEL); 708 if (!pd->pd_step) 709 return -ENOMEM; 710 711 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111, 712 sizeof(s16), GFP_KERNEL); 713 if (!pd->pd_pwr) 714 return -ENOMEM; 715 716 /* Fill raw dataset 717 * (convert power to 0.25dB units 718 * for RF5112 combatibility) */ 719 for (point = 0; point < pd->pd_points; point++) { 720 721 /* Absolute values */ 722 pd->pd_pwr[point] = 2 * pcinfo->pwr[point]; 723 724 /* Already sorted */ 725 pd->pd_step[point] = pcinfo->pcdac[point]; 726 } 727 728 /* Set min/max pwr */ 729 chinfo[pier].min_pwr = pd->pd_pwr[0]; 730 chinfo[pier].max_pwr = pd->pd_pwr[10]; 731 732 } 733 734 return 0; 735 } 736 737 /* Parse EEPROM data */ 738 static int 739 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode) 740 { 741 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 742 struct ath5k_chan_pcal_info *pcal; 743 int offset, ret; 744 int i; 745 u16 val; 746 747 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); 748 switch(mode) { 749 case AR5K_EEPROM_MODE_11A: 750 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) 751 return 0; 752 753 ret = ath5k_eeprom_init_11a_pcal_freq(ah, 754 offset + AR5K_EEPROM_GROUP1_OFFSET); 755 if (ret < 0) 756 return ret; 757 758 offset += AR5K_EEPROM_GROUP2_OFFSET; 759 pcal = ee->ee_pwr_cal_a; 760 break; 761 case AR5K_EEPROM_MODE_11B: 762 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) && 763 !AR5K_EEPROM_HDR_11G(ee->ee_header)) 764 return 0; 765 766 pcal = ee->ee_pwr_cal_b; 767 offset += AR5K_EEPROM_GROUP3_OFFSET; 768 769 /* fixed piers */ 770 pcal[0].freq = 2412; 771 pcal[1].freq = 2447; 772 pcal[2].freq = 2484; 773 ee->ee_n_piers[mode] = 3; 774 break; 775 case AR5K_EEPROM_MODE_11G: 776 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) 777 return 0; 778 779 pcal = ee->ee_pwr_cal_g; 780 offset += AR5K_EEPROM_GROUP4_OFFSET; 781 782 /* fixed piers */ 783 pcal[0].freq = 2312; 784 pcal[1].freq = 2412; 785 pcal[2].freq = 2484; 786 ee->ee_n_piers[mode] = 3; 787 break; 788 default: 789 return -EINVAL; 790 } 791 792 for (i = 0; i < ee->ee_n_piers[mode]; i++) { 793 struct ath5k_chan_pcal_info_rf5111 *cdata = 794 &pcal[i].rf5111_info; 795 796 AR5K_EEPROM_READ(offset++, val); 797 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M); 798 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M); 799 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M); 800 801 AR5K_EEPROM_READ(offset++, val); 802 cdata->pwr[0] |= ((val >> 14) & 0x3); 803 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M); 804 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M); 805 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M); 806 807 AR5K_EEPROM_READ(offset++, val); 808 cdata->pwr[3] |= ((val >> 12) & 0xf); 809 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M); 810 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M); 811 812 AR5K_EEPROM_READ(offset++, val); 813 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M); 814 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M); 815 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M); 816 817 AR5K_EEPROM_READ(offset++, val); 818 cdata->pwr[8] |= ((val >> 14) & 0x3); 819 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M); 820 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M); 821 822 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min, 823 cdata->pcdac_max, cdata->pcdac); 824 } 825 826 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal); 827 } 828 829 830 /* 831 * Read power calibration for RF5112 chips 832 * 833 * For RF5112 we have 4 XPD -eXternal Power Detector- curves 834 * for each calibrated channel on 0, -6, -12 and -18dbm but we only 835 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB 836 * power steps on x axis and PCDAC steps on y axis and looks like a 837 * linear function. To recreate the curve and pass the power values 838 * on hw, we read 4 points for xpd 0 (lower gain -> max power) 839 * and 3 points for xpd 3 (higher gain -> lower power) here and 840 * interpolate later. 841 * 842 * Note: Many vendors just use xpd 0 so xpd 3 is zeroed. 843 */ 844 845 /* Convert RF5112 specific data to generic raw data 846 * used by interpolation code */ 847 static int 848 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode, 849 struct ath5k_chan_pcal_info *chinfo) 850 { 851 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 852 struct ath5k_chan_pcal_info_rf5112 *pcinfo; 853 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; 854 unsigned int pier, pdg, point; 855 856 /* Fill raw data for each calibration pier */ 857 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { 858 859 pcinfo = &chinfo[pier].rf5112_info; 860 861 /* Allocate pd_curves for this cal pier */ 862 chinfo[pier].pd_curves = 863 kcalloc(AR5K_EEPROM_N_PD_CURVES, 864 sizeof(struct ath5k_pdgain_info), 865 GFP_KERNEL); 866 867 if (!chinfo[pier].pd_curves) 868 return -ENOMEM; 869 870 /* Fill pd_curves */ 871 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { 872 873 u8 idx = pdgain_idx[pdg]; 874 struct ath5k_pdgain_info *pd = 875 &chinfo[pier].pd_curves[idx]; 876 877 /* Lowest gain curve (max power) */ 878 if (pdg == 0) { 879 /* One more point for better accuracy */ 880 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS; 881 882 /* Allocate pd points for this curve */ 883 pd->pd_step = kcalloc(pd->pd_points, 884 sizeof(u8), GFP_KERNEL); 885 886 if (!pd->pd_step) 887 return -ENOMEM; 888 889 pd->pd_pwr = kcalloc(pd->pd_points, 890 sizeof(s16), GFP_KERNEL); 891 892 if (!pd->pd_pwr) 893 return -ENOMEM; 894 895 896 /* Fill raw dataset 897 * (all power levels are in 0.25dB units) */ 898 pd->pd_step[0] = pcinfo->pcdac_x0[0]; 899 pd->pd_pwr[0] = pcinfo->pwr_x0[0]; 900 901 for (point = 1; point < pd->pd_points; 902 point++) { 903 /* Absolute values */ 904 pd->pd_pwr[point] = 905 pcinfo->pwr_x0[point]; 906 907 /* Deltas */ 908 pd->pd_step[point] = 909 pd->pd_step[point - 1] + 910 pcinfo->pcdac_x0[point]; 911 } 912 913 /* Set min power for this frequency */ 914 chinfo[pier].min_pwr = pd->pd_pwr[0]; 915 916 /* Highest gain curve (min power) */ 917 } else if (pdg == 1) { 918 919 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS; 920 921 /* Allocate pd points for this curve */ 922 pd->pd_step = kcalloc(pd->pd_points, 923 sizeof(u8), GFP_KERNEL); 924 925 if (!pd->pd_step) 926 return -ENOMEM; 927 928 pd->pd_pwr = kcalloc(pd->pd_points, 929 sizeof(s16), GFP_KERNEL); 930 931 if (!pd->pd_pwr) 932 return -ENOMEM; 933 934 /* Fill raw dataset 935 * (all power levels are in 0.25dB units) */ 936 for (point = 0; point < pd->pd_points; 937 point++) { 938 /* Absolute values */ 939 pd->pd_pwr[point] = 940 pcinfo->pwr_x3[point]; 941 942 /* Fixed points */ 943 pd->pd_step[point] = 944 pcinfo->pcdac_x3[point]; 945 } 946 947 /* Since we have a higher gain curve 948 * override min power */ 949 chinfo[pier].min_pwr = pd->pd_pwr[0]; 950 } 951 } 952 } 953 954 return 0; 955 } 956 957 /* Parse EEPROM data */ 958 static int 959 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode) 960 { 961 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 962 struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info; 963 struct ath5k_chan_pcal_info *gen_chan_info; 964 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; 965 u32 offset; 966 u8 i, c; 967 u16 val; 968 int ret; 969 u8 pd_gains = 0; 970 971 /* Count how many curves we have and 972 * identify them (which one of the 4 973 * available curves we have on each count). 974 * Curves are stored from lower (x0) to 975 * higher (x3) gain */ 976 for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) { 977 /* ee_x_gain[mode] is x gain mask */ 978 if ((ee->ee_x_gain[mode] >> i) & 0x1) 979 pdgain_idx[pd_gains++] = i; 980 } 981 ee->ee_pd_gains[mode] = pd_gains; 982 983 if (pd_gains == 0 || pd_gains > 2) 984 return -EINVAL; 985 986 switch (mode) { 987 case AR5K_EEPROM_MODE_11A: 988 /* 989 * Read 5GHz EEPROM channels 990 */ 991 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); 992 ath5k_eeprom_init_11a_pcal_freq(ah, offset); 993 994 offset += AR5K_EEPROM_GROUP2_OFFSET; 995 gen_chan_info = ee->ee_pwr_cal_a; 996 break; 997 case AR5K_EEPROM_MODE_11B: 998 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); 999 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) 1000 offset += AR5K_EEPROM_GROUP3_OFFSET; 1001 1002 /* NB: frequency piers parsed during mode init */ 1003 gen_chan_info = ee->ee_pwr_cal_b; 1004 break; 1005 case AR5K_EEPROM_MODE_11G: 1006 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); 1007 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) 1008 offset += AR5K_EEPROM_GROUP4_OFFSET; 1009 else if (AR5K_EEPROM_HDR_11B(ee->ee_header)) 1010 offset += AR5K_EEPROM_GROUP2_OFFSET; 1011 1012 /* NB: frequency piers parsed during mode init */ 1013 gen_chan_info = ee->ee_pwr_cal_g; 1014 break; 1015 default: 1016 return -EINVAL; 1017 } 1018 1019 for (i = 0; i < ee->ee_n_piers[mode]; i++) { 1020 chan_pcal_info = &gen_chan_info[i].rf5112_info; 1021 1022 /* Power values in quarter dB 1023 * for the lower xpd gain curve 1024 * (0 dBm -> higher output power) */ 1025 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) { 1026 AR5K_EEPROM_READ(offset++, val); 1027 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff); 1028 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff); 1029 } 1030 1031 /* PCDAC steps 1032 * corresponding to the above power 1033 * measurements */ 1034 AR5K_EEPROM_READ(offset++, val); 1035 chan_pcal_info->pcdac_x0[1] = (val & 0x1f); 1036 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f); 1037 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f); 1038 1039 /* Power values in quarter dB 1040 * for the higher xpd gain curve 1041 * (18 dBm -> lower output power) */ 1042 AR5K_EEPROM_READ(offset++, val); 1043 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff); 1044 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff); 1045 1046 AR5K_EEPROM_READ(offset++, val); 1047 chan_pcal_info->pwr_x3[2] = (val & 0xff); 1048 1049 /* PCDAC steps 1050 * corresponding to the above power 1051 * measurements (fixed) */ 1052 chan_pcal_info->pcdac_x3[0] = 20; 1053 chan_pcal_info->pcdac_x3[1] = 35; 1054 chan_pcal_info->pcdac_x3[2] = 63; 1055 1056 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) { 1057 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f); 1058 1059 /* Last xpd0 power level is also channel maximum */ 1060 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3]; 1061 } else { 1062 chan_pcal_info->pcdac_x0[0] = 1; 1063 gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff); 1064 } 1065 1066 } 1067 1068 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info); 1069 } 1070 1071 1072 /* 1073 * Read power calibration for RF2413 chips 1074 * 1075 * For RF2413 we have a Power to PDDAC table (Power Detector) 1076 * instead of a PCDAC and 4 pd gain curves for each calibrated channel. 1077 * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y 1078 * axis and looks like an exponential function like the RF5111 curve. 1079 * 1080 * To recreate the curves we read here the points and interpolate 1081 * later. Note that in most cases only 2 (higher and lower) curves are 1082 * used (like RF5112) but vendors have the oportunity to include all 1083 * 4 curves on eeprom. The final curve (higher power) has an extra 1084 * point for better accuracy like RF5112. 1085 */ 1086 1087 /* For RF2413 power calibration data doesn't start on a fixed location and 1088 * if a mode is not supported, it's section is missing -not zeroed-. 1089 * So we need to calculate the starting offset for each section by using 1090 * these two functions */ 1091 1092 /* Return the size of each section based on the mode and the number of pd 1093 * gains available (maximum 4). */ 1094 static inline unsigned int 1095 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode) 1096 { 1097 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 }; 1098 unsigned int sz; 1099 1100 sz = pdgains_size[ee->ee_pd_gains[mode] - 1]; 1101 sz *= ee->ee_n_piers[mode]; 1102 1103 return sz; 1104 } 1105 1106 /* Return the starting offset for a section based on the modes supported 1107 * and each section's size. */ 1108 static unsigned int 1109 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode) 1110 { 1111 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4); 1112 1113 switch(mode) { 1114 case AR5K_EEPROM_MODE_11G: 1115 if (AR5K_EEPROM_HDR_11B(ee->ee_header)) 1116 offset += ath5k_pdgains_size_2413(ee, 1117 AR5K_EEPROM_MODE_11B) + 1118 AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; 1119 /* fall through */ 1120 case AR5K_EEPROM_MODE_11B: 1121 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) 1122 offset += ath5k_pdgains_size_2413(ee, 1123 AR5K_EEPROM_MODE_11A) + 1124 AR5K_EEPROM_N_5GHZ_CHAN / 2; 1125 /* fall through */ 1126 case AR5K_EEPROM_MODE_11A: 1127 break; 1128 default: 1129 break; 1130 } 1131 1132 return offset; 1133 } 1134 1135 /* Convert RF2413 specific data to generic raw data 1136 * used by interpolation code */ 1137 static int 1138 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode, 1139 struct ath5k_chan_pcal_info *chinfo) 1140 { 1141 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1142 struct ath5k_chan_pcal_info_rf2413 *pcinfo; 1143 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; 1144 unsigned int pier, pdg, point; 1145 1146 /* Fill raw data for each calibration pier */ 1147 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { 1148 1149 pcinfo = &chinfo[pier].rf2413_info; 1150 1151 /* Allocate pd_curves for this cal pier */ 1152 chinfo[pier].pd_curves = 1153 kcalloc(AR5K_EEPROM_N_PD_CURVES, 1154 sizeof(struct ath5k_pdgain_info), 1155 GFP_KERNEL); 1156 1157 if (!chinfo[pier].pd_curves) 1158 return -ENOMEM; 1159 1160 /* Fill pd_curves */ 1161 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { 1162 1163 u8 idx = pdgain_idx[pdg]; 1164 struct ath5k_pdgain_info *pd = 1165 &chinfo[pier].pd_curves[idx]; 1166 1167 /* One more point for the highest power 1168 * curve (lowest gain) */ 1169 if (pdg == ee->ee_pd_gains[mode] - 1) 1170 pd->pd_points = AR5K_EEPROM_N_PD_POINTS; 1171 else 1172 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1; 1173 1174 /* Allocate pd points for this curve */ 1175 pd->pd_step = kcalloc(pd->pd_points, 1176 sizeof(u8), GFP_KERNEL); 1177 1178 if (!pd->pd_step) 1179 return -ENOMEM; 1180 1181 pd->pd_pwr = kcalloc(pd->pd_points, 1182 sizeof(s16), GFP_KERNEL); 1183 1184 if (!pd->pd_pwr) 1185 return -ENOMEM; 1186 1187 /* Fill raw dataset 1188 * convert all pwr levels to 1189 * quarter dB for RF5112 combatibility */ 1190 pd->pd_step[0] = pcinfo->pddac_i[pdg]; 1191 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg]; 1192 1193 for (point = 1; point < pd->pd_points; point++) { 1194 1195 pd->pd_pwr[point] = pd->pd_pwr[point - 1] + 1196 2 * pcinfo->pwr[pdg][point - 1]; 1197 1198 pd->pd_step[point] = pd->pd_step[point - 1] + 1199 pcinfo->pddac[pdg][point - 1]; 1200 1201 } 1202 1203 /* Highest gain curve -> min power */ 1204 if (pdg == 0) 1205 chinfo[pier].min_pwr = pd->pd_pwr[0]; 1206 1207 /* Lowest gain curve -> max power */ 1208 if (pdg == ee->ee_pd_gains[mode] - 1) 1209 chinfo[pier].max_pwr = 1210 pd->pd_pwr[pd->pd_points - 1]; 1211 } 1212 } 1213 1214 return 0; 1215 } 1216 1217 /* Parse EEPROM data */ 1218 static int 1219 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode) 1220 { 1221 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1222 struct ath5k_chan_pcal_info_rf2413 *pcinfo; 1223 struct ath5k_chan_pcal_info *chinfo; 1224 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; 1225 u32 offset; 1226 int idx, i, ret; 1227 u16 val; 1228 u8 pd_gains = 0; 1229 1230 /* Count how many curves we have and 1231 * identify them (which one of the 4 1232 * available curves we have on each count). 1233 * Curves are stored from higher to 1234 * lower gain so we go backwards */ 1235 for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) { 1236 /* ee_x_gain[mode] is x gain mask */ 1237 if ((ee->ee_x_gain[mode] >> idx) & 0x1) 1238 pdgain_idx[pd_gains++] = idx; 1239 1240 } 1241 ee->ee_pd_gains[mode] = pd_gains; 1242 1243 if (pd_gains == 0) 1244 return -EINVAL; 1245 1246 offset = ath5k_cal_data_offset_2413(ee, mode); 1247 switch (mode) { 1248 case AR5K_EEPROM_MODE_11A: 1249 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) 1250 return 0; 1251 1252 ath5k_eeprom_init_11a_pcal_freq(ah, offset); 1253 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2; 1254 chinfo = ee->ee_pwr_cal_a; 1255 break; 1256 case AR5K_EEPROM_MODE_11B: 1257 if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) 1258 return 0; 1259 1260 ath5k_eeprom_init_11bg_2413(ah, mode, offset); 1261 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; 1262 chinfo = ee->ee_pwr_cal_b; 1263 break; 1264 case AR5K_EEPROM_MODE_11G: 1265 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) 1266 return 0; 1267 1268 ath5k_eeprom_init_11bg_2413(ah, mode, offset); 1269 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; 1270 chinfo = ee->ee_pwr_cal_g; 1271 break; 1272 default: 1273 return -EINVAL; 1274 } 1275 1276 for (i = 0; i < ee->ee_n_piers[mode]; i++) { 1277 pcinfo = &chinfo[i].rf2413_info; 1278 1279 /* 1280 * Read pwr_i, pddac_i and the first 1281 * 2 pd points (pwr, pddac) 1282 */ 1283 AR5K_EEPROM_READ(offset++, val); 1284 pcinfo->pwr_i[0] = val & 0x1f; 1285 pcinfo->pddac_i[0] = (val >> 5) & 0x7f; 1286 pcinfo->pwr[0][0] = (val >> 12) & 0xf; 1287 1288 AR5K_EEPROM_READ(offset++, val); 1289 pcinfo->pddac[0][0] = val & 0x3f; 1290 pcinfo->pwr[0][1] = (val >> 6) & 0xf; 1291 pcinfo->pddac[0][1] = (val >> 10) & 0x3f; 1292 1293 AR5K_EEPROM_READ(offset++, val); 1294 pcinfo->pwr[0][2] = val & 0xf; 1295 pcinfo->pddac[0][2] = (val >> 4) & 0x3f; 1296 1297 pcinfo->pwr[0][3] = 0; 1298 pcinfo->pddac[0][3] = 0; 1299 1300 if (pd_gains > 1) { 1301 /* 1302 * Pd gain 0 is not the last pd gain 1303 * so it only has 2 pd points. 1304 * Continue wih pd gain 1. 1305 */ 1306 pcinfo->pwr_i[1] = (val >> 10) & 0x1f; 1307 1308 pcinfo->pddac_i[1] = (val >> 15) & 0x1; 1309 AR5K_EEPROM_READ(offset++, val); 1310 pcinfo->pddac_i[1] |= (val & 0x3F) << 1; 1311 1312 pcinfo->pwr[1][0] = (val >> 6) & 0xf; 1313 pcinfo->pddac[1][0] = (val >> 10) & 0x3f; 1314 1315 AR5K_EEPROM_READ(offset++, val); 1316 pcinfo->pwr[1][1] = val & 0xf; 1317 pcinfo->pddac[1][1] = (val >> 4) & 0x3f; 1318 pcinfo->pwr[1][2] = (val >> 10) & 0xf; 1319 1320 pcinfo->pddac[1][2] = (val >> 14) & 0x3; 1321 AR5K_EEPROM_READ(offset++, val); 1322 pcinfo->pddac[1][2] |= (val & 0xF) << 2; 1323 1324 pcinfo->pwr[1][3] = 0; 1325 pcinfo->pddac[1][3] = 0; 1326 } else if (pd_gains == 1) { 1327 /* 1328 * Pd gain 0 is the last one so 1329 * read the extra point. 1330 */ 1331 pcinfo->pwr[0][3] = (val >> 10) & 0xf; 1332 1333 pcinfo->pddac[0][3] = (val >> 14) & 0x3; 1334 AR5K_EEPROM_READ(offset++, val); 1335 pcinfo->pddac[0][3] |= (val & 0xF) << 2; 1336 } 1337 1338 /* 1339 * Proceed with the other pd_gains 1340 * as above. 1341 */ 1342 if (pd_gains > 2) { 1343 pcinfo->pwr_i[2] = (val >> 4) & 0x1f; 1344 pcinfo->pddac_i[2] = (val >> 9) & 0x7f; 1345 1346 AR5K_EEPROM_READ(offset++, val); 1347 pcinfo->pwr[2][0] = (val >> 0) & 0xf; 1348 pcinfo->pddac[2][0] = (val >> 4) & 0x3f; 1349 pcinfo->pwr[2][1] = (val >> 10) & 0xf; 1350 1351 pcinfo->pddac[2][1] = (val >> 14) & 0x3; 1352 AR5K_EEPROM_READ(offset++, val); 1353 pcinfo->pddac[2][1] |= (val & 0xF) << 2; 1354 1355 pcinfo->pwr[2][2] = (val >> 4) & 0xf; 1356 pcinfo->pddac[2][2] = (val >> 8) & 0x3f; 1357 1358 pcinfo->pwr[2][3] = 0; 1359 pcinfo->pddac[2][3] = 0; 1360 } else if (pd_gains == 2) { 1361 pcinfo->pwr[1][3] = (val >> 4) & 0xf; 1362 pcinfo->pddac[1][3] = (val >> 8) & 0x3f; 1363 } 1364 1365 if (pd_gains > 3) { 1366 pcinfo->pwr_i[3] = (val >> 14) & 0x3; 1367 AR5K_EEPROM_READ(offset++, val); 1368 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2; 1369 1370 pcinfo->pddac_i[3] = (val >> 3) & 0x7f; 1371 pcinfo->pwr[3][0] = (val >> 10) & 0xf; 1372 pcinfo->pddac[3][0] = (val >> 14) & 0x3; 1373 1374 AR5K_EEPROM_READ(offset++, val); 1375 pcinfo->pddac[3][0] |= (val & 0xF) << 2; 1376 pcinfo->pwr[3][1] = (val >> 4) & 0xf; 1377 pcinfo->pddac[3][1] = (val >> 8) & 0x3f; 1378 1379 pcinfo->pwr[3][2] = (val >> 14) & 0x3; 1380 AR5K_EEPROM_READ(offset++, val); 1381 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2; 1382 1383 pcinfo->pddac[3][2] = (val >> 2) & 0x3f; 1384 pcinfo->pwr[3][3] = (val >> 8) & 0xf; 1385 1386 pcinfo->pddac[3][3] = (val >> 12) & 0xF; 1387 AR5K_EEPROM_READ(offset++, val); 1388 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4; 1389 } else if (pd_gains == 3) { 1390 pcinfo->pwr[2][3] = (val >> 14) & 0x3; 1391 AR5K_EEPROM_READ(offset++, val); 1392 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2; 1393 1394 pcinfo->pddac[2][3] = (val >> 2) & 0x3f; 1395 } 1396 } 1397 1398 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo); 1399 } 1400 1401 1402 /* 1403 * Read per rate target power (this is the maximum tx power 1404 * supported by the card). This info is used when setting 1405 * tx power, no matter the channel. 1406 * 1407 * This also works for v5 EEPROMs. 1408 */ 1409 static int 1410 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode) 1411 { 1412 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1413 struct ath5k_rate_pcal_info *rate_pcal_info; 1414 u8 *rate_target_pwr_num; 1415 u32 offset; 1416 u16 val; 1417 int ret, i; 1418 1419 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1); 1420 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode]; 1421 switch (mode) { 1422 case AR5K_EEPROM_MODE_11A: 1423 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version); 1424 rate_pcal_info = ee->ee_rate_tpwr_a; 1425 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN; 1426 break; 1427 case AR5K_EEPROM_MODE_11B: 1428 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version); 1429 rate_pcal_info = ee->ee_rate_tpwr_b; 1430 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */ 1431 break; 1432 case AR5K_EEPROM_MODE_11G: 1433 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version); 1434 rate_pcal_info = ee->ee_rate_tpwr_g; 1435 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN; 1436 break; 1437 default: 1438 return -EINVAL; 1439 } 1440 1441 /* Different freq mask for older eeproms (<= v3.2) */ 1442 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) { 1443 for (i = 0; i < (*rate_target_pwr_num); i++) { 1444 AR5K_EEPROM_READ(offset++, val); 1445 rate_pcal_info[i].freq = 1446 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode); 1447 1448 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f); 1449 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f; 1450 1451 AR5K_EEPROM_READ(offset++, val); 1452 1453 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS || 1454 val == 0) { 1455 (*rate_target_pwr_num) = i; 1456 break; 1457 } 1458 1459 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7); 1460 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f); 1461 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f); 1462 } 1463 } else { 1464 for (i = 0; i < (*rate_target_pwr_num); i++) { 1465 AR5K_EEPROM_READ(offset++, val); 1466 rate_pcal_info[i].freq = 1467 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); 1468 1469 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f); 1470 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f; 1471 1472 AR5K_EEPROM_READ(offset++, val); 1473 1474 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS || 1475 val == 0) { 1476 (*rate_target_pwr_num) = i; 1477 break; 1478 } 1479 1480 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf; 1481 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f); 1482 rate_pcal_info[i].target_power_54 = (val & 0x3f); 1483 } 1484 } 1485 1486 return 0; 1487 } 1488 1489 /* 1490 * Read per channel calibration info from EEPROM 1491 * 1492 * This info is used to calibrate the baseband power table. Imagine 1493 * that for each channel there is a power curve that's hw specific 1494 * (depends on amplifier etc) and we try to "correct" this curve using 1495 * offests we pass on to phy chip (baseband -> before amplifier) so that 1496 * it can use accurate power values when setting tx power (takes amplifier's 1497 * performance on each channel into account). 1498 * 1499 * EEPROM provides us with the offsets for some pre-calibrated channels 1500 * and we have to interpolate to create the full table for these channels and 1501 * also the table for any channel. 1502 */ 1503 static int 1504 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah) 1505 { 1506 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1507 int (*read_pcal)(struct ath5k_hw *hw, int mode); 1508 int mode; 1509 int err; 1510 1511 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) && 1512 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1)) 1513 read_pcal = ath5k_eeprom_read_pcal_info_5112; 1514 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) && 1515 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2)) 1516 read_pcal = ath5k_eeprom_read_pcal_info_2413; 1517 else 1518 read_pcal = ath5k_eeprom_read_pcal_info_5111; 1519 1520 1521 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; 1522 mode++) { 1523 err = read_pcal(ah, mode); 1524 if (err) 1525 return err; 1526 1527 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode); 1528 if (err < 0) 1529 return err; 1530 } 1531 1532 return 0; 1533 } 1534 1535 static int 1536 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode) 1537 { 1538 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1539 struct ath5k_chan_pcal_info *chinfo; 1540 u8 pier, pdg; 1541 1542 switch (mode) { 1543 case AR5K_EEPROM_MODE_11A: 1544 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) 1545 return 0; 1546 chinfo = ee->ee_pwr_cal_a; 1547 break; 1548 case AR5K_EEPROM_MODE_11B: 1549 if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) 1550 return 0; 1551 chinfo = ee->ee_pwr_cal_b; 1552 break; 1553 case AR5K_EEPROM_MODE_11G: 1554 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) 1555 return 0; 1556 chinfo = ee->ee_pwr_cal_g; 1557 break; 1558 default: 1559 return -EINVAL; 1560 } 1561 1562 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { 1563 if (!chinfo[pier].pd_curves) 1564 continue; 1565 1566 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { 1567 struct ath5k_pdgain_info *pd = 1568 &chinfo[pier].pd_curves[pdg]; 1569 1570 if (pd != NULL) { 1571 kfree(pd->pd_step); 1572 kfree(pd->pd_pwr); 1573 } 1574 } 1575 1576 kfree(chinfo[pier].pd_curves); 1577 } 1578 1579 return 0; 1580 } 1581 1582 void 1583 ath5k_eeprom_detach(struct ath5k_hw *ah) 1584 { 1585 u8 mode; 1586 1587 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) 1588 ath5k_eeprom_free_pcal_info(ah, mode); 1589 } 1590 1591 /* Read conformance test limits used for regulatory control */ 1592 static int 1593 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah) 1594 { 1595 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1596 struct ath5k_edge_power *rep; 1597 unsigned int fmask, pmask; 1598 unsigned int ctl_mode; 1599 int ret, i, j; 1600 u32 offset; 1601 u16 val; 1602 1603 pmask = AR5K_EEPROM_POWER_M; 1604 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version); 1605 offset = AR5K_EEPROM_CTL(ee->ee_version); 1606 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version); 1607 for (i = 0; i < ee->ee_ctls; i += 2) { 1608 AR5K_EEPROM_READ(offset++, val); 1609 ee->ee_ctl[i] = (val >> 8) & 0xff; 1610 ee->ee_ctl[i + 1] = val & 0xff; 1611 } 1612 1613 offset = AR5K_EEPROM_GROUP8_OFFSET; 1614 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0) 1615 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) - 1616 AR5K_EEPROM_GROUP5_OFFSET; 1617 else 1618 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version); 1619 1620 rep = ee->ee_ctl_pwr; 1621 for(i = 0; i < ee->ee_ctls; i++) { 1622 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) { 1623 case AR5K_CTL_11A: 1624 case AR5K_CTL_TURBO: 1625 ctl_mode = AR5K_EEPROM_MODE_11A; 1626 break; 1627 default: 1628 ctl_mode = AR5K_EEPROM_MODE_11G; 1629 break; 1630 } 1631 if (ee->ee_ctl[i] == 0) { 1632 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) 1633 offset += 8; 1634 else 1635 offset += 7; 1636 rep += AR5K_EEPROM_N_EDGES; 1637 continue; 1638 } 1639 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { 1640 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) { 1641 AR5K_EEPROM_READ(offset++, val); 1642 rep[j].freq = (val >> 8) & fmask; 1643 rep[j + 1].freq = val & fmask; 1644 } 1645 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) { 1646 AR5K_EEPROM_READ(offset++, val); 1647 rep[j].edge = (val >> 8) & pmask; 1648 rep[j].flag = (val >> 14) & 1; 1649 rep[j + 1].edge = val & pmask; 1650 rep[j + 1].flag = (val >> 6) & 1; 1651 } 1652 } else { 1653 AR5K_EEPROM_READ(offset++, val); 1654 rep[0].freq = (val >> 9) & fmask; 1655 rep[1].freq = (val >> 2) & fmask; 1656 rep[2].freq = (val << 5) & fmask; 1657 1658 AR5K_EEPROM_READ(offset++, val); 1659 rep[2].freq |= (val >> 11) & 0x1f; 1660 rep[3].freq = (val >> 4) & fmask; 1661 rep[4].freq = (val << 3) & fmask; 1662 1663 AR5K_EEPROM_READ(offset++, val); 1664 rep[4].freq |= (val >> 13) & 0x7; 1665 rep[5].freq = (val >> 6) & fmask; 1666 rep[6].freq = (val << 1) & fmask; 1667 1668 AR5K_EEPROM_READ(offset++, val); 1669 rep[6].freq |= (val >> 15) & 0x1; 1670 rep[7].freq = (val >> 8) & fmask; 1671 1672 rep[0].edge = (val >> 2) & pmask; 1673 rep[1].edge = (val << 4) & pmask; 1674 1675 AR5K_EEPROM_READ(offset++, val); 1676 rep[1].edge |= (val >> 12) & 0xf; 1677 rep[2].edge = (val >> 6) & pmask; 1678 rep[3].edge = val & pmask; 1679 1680 AR5K_EEPROM_READ(offset++, val); 1681 rep[4].edge = (val >> 10) & pmask; 1682 rep[5].edge = (val >> 4) & pmask; 1683 rep[6].edge = (val << 2) & pmask; 1684 1685 AR5K_EEPROM_READ(offset++, val); 1686 rep[6].edge |= (val >> 14) & 0x3; 1687 rep[7].edge = (val >> 8) & pmask; 1688 } 1689 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) { 1690 rep[j].freq = ath5k_eeprom_bin2freq(ee, 1691 rep[j].freq, ctl_mode); 1692 } 1693 rep += AR5K_EEPROM_N_EDGES; 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int 1700 ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah) 1701 { 1702 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1703 u32 offset; 1704 u16 val; 1705 int ret = 0, i; 1706 1707 offset = AR5K_EEPROM_CTL(ee->ee_version) + 1708 AR5K_EEPROM_N_CTLS(ee->ee_version); 1709 1710 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) { 1711 /* No spur info for 5GHz */ 1712 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR; 1713 /* 2 channels for 2GHz (2464/2420) */ 1714 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1; 1715 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2; 1716 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR; 1717 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) { 1718 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1719 AR5K_EEPROM_READ(offset, val); 1720 ee->ee_spur_chans[i][0] = val; 1721 AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS, 1722 val); 1723 ee->ee_spur_chans[i][1] = val; 1724 offset++; 1725 } 1726 } 1727 1728 return ret; 1729 } 1730 1731 /* 1732 * Initialize eeprom data structure 1733 */ 1734 int 1735 ath5k_eeprom_init(struct ath5k_hw *ah) 1736 { 1737 int err; 1738 1739 err = ath5k_eeprom_init_header(ah); 1740 if (err < 0) 1741 return err; 1742 1743 err = ath5k_eeprom_init_modes(ah); 1744 if (err < 0) 1745 return err; 1746 1747 err = ath5k_eeprom_read_pcal_info(ah); 1748 if (err < 0) 1749 return err; 1750 1751 err = ath5k_eeprom_read_ctl_info(ah); 1752 if (err < 0) 1753 return err; 1754 1755 err = ath5k_eeprom_read_spur_chans(ah); 1756 if (err < 0) 1757 return err; 1758 1759 return 0; 1760 } 1761 1762 /* 1763 * Read the MAC address from eeprom 1764 */ 1765 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) 1766 { 1767 u8 mac_d[ETH_ALEN] = {}; 1768 u32 total, offset; 1769 u16 data; 1770 int octet, ret; 1771 1772 ret = ath5k_hw_eeprom_read(ah, 0x20, &data); 1773 if (ret) 1774 return ret; 1775 1776 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { 1777 ret = ath5k_hw_eeprom_read(ah, offset, &data); 1778 if (ret) 1779 return ret; 1780 1781 total += data; 1782 mac_d[octet + 1] = data & 0xff; 1783 mac_d[octet] = data >> 8; 1784 octet += 2; 1785 } 1786 1787 if (!total || total == 3 * 0xffff) 1788 return -EINVAL; 1789 1790 memcpy(mac, mac_d, ETH_ALEN); 1791 1792 return 0; 1793 } 1794