1 /*- 2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 */ 37 38 /* 39 * Definitions for the Atheros Wireless LAN controller driver. 40 */ 41 #ifndef _DEV_ATH_ATHVAR_H 42 #define _DEV_ATH_ATHVAR_H 43 44 #include <linux/interrupt.h> 45 #include <linux/list.h> 46 #include <linux/wireless.h> 47 #include <linux/if_ether.h> 48 #include <linux/leds.h> 49 #include <linux/rfkill.h> 50 #include <linux/workqueue.h> 51 52 #include "ath5k.h" 53 #include "debug.h" 54 #include "ani.h" 55 56 #include "../regd.h" 57 #include "../ath.h" 58 59 #define ATH_RXBUF 40 /* number of RX buffers */ 60 #define ATH_TXBUF 200 /* number of TX buffers */ 61 #define ATH_BCBUF 1 /* number of beacon buffers */ 62 63 struct ath5k_buf { 64 struct list_head list; 65 struct ath5k_desc *desc; /* virtual addr of desc */ 66 dma_addr_t daddr; /* physical addr of desc */ 67 struct sk_buff *skb; /* skbuff for buf */ 68 dma_addr_t skbaddr;/* physical addr of skb data */ 69 }; 70 71 /* 72 * Data transmit queue state. One of these exists for each 73 * hardware transmit queue. Packets sent to us from above 74 * are assigned to queues based on their priority. Not all 75 * devices support a complete set of hardware transmit queues. 76 * For those devices the array sc_ac2q will map multiple 77 * priorities to fewer hardware queues (typically all to one 78 * hardware queue). 79 */ 80 struct ath5k_txq { 81 unsigned int qnum; /* hardware q number */ 82 u32 *link; /* link ptr in last TX desc */ 83 struct list_head q; /* transmit queue */ 84 spinlock_t lock; /* lock on q and link */ 85 bool setup; 86 }; 87 88 #define ATH5K_LED_MAX_NAME_LEN 31 89 90 /* 91 * State for LED triggers 92 */ 93 struct ath5k_led 94 { 95 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */ 96 struct ath5k_softc *sc; /* driver state */ 97 struct led_classdev led_dev; /* led classdev */ 98 }; 99 100 /* Rfkill */ 101 struct ath5k_rfkill { 102 /* GPIO PIN for rfkill */ 103 u16 gpio; 104 /* polarity of rfkill GPIO PIN */ 105 bool polarity; 106 /* RFKILL toggle tasklet */ 107 struct tasklet_struct toggleq; 108 }; 109 110 /* statistics */ 111 struct ath5k_statistics { 112 /* antenna use */ 113 unsigned int antenna_rx[5]; /* frames count per antenna RX */ 114 unsigned int antenna_tx[5]; /* frames count per antenna TX */ 115 116 /* frame errors */ 117 unsigned int rx_all_count; /* all RX frames, including errors */ 118 unsigned int tx_all_count; /* all TX frames, including errors */ 119 unsigned int rxerr_crc; 120 unsigned int rxerr_phy; 121 unsigned int rxerr_phy_code[32]; 122 unsigned int rxerr_fifo; 123 unsigned int rxerr_decrypt; 124 unsigned int rxerr_mic; 125 unsigned int rxerr_proc; 126 unsigned int rxerr_jumbo; 127 unsigned int txerr_retry; 128 unsigned int txerr_fifo; 129 unsigned int txerr_filt; 130 131 /* MIB counters */ 132 unsigned int ack_fail; 133 unsigned int rts_fail; 134 unsigned int rts_ok; 135 unsigned int fcs_error; 136 unsigned int beacons; 137 138 unsigned int mib_intr; 139 unsigned int rxorn_intr; 140 unsigned int rxeol_intr; 141 }; 142 143 #if CHAN_DEBUG 144 #define ATH_CHAN_MAX (26+26+26+200+200) 145 #else 146 #define ATH_CHAN_MAX (14+14+14+252+20) 147 #endif 148 149 /* Software Carrier, keeps track of the driver state 150 * associated with an instance of a device */ 151 struct ath5k_softc { 152 struct pci_dev *pdev; /* for dma mapping */ 153 void __iomem *iobase; /* address of the device */ 154 struct mutex lock; /* dev-level lock */ 155 struct ieee80211_hw *hw; /* IEEE 802.11 common */ 156 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 157 struct ieee80211_channel channels[ATH_CHAN_MAX]; 158 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES]; 159 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES]; 160 enum nl80211_iftype opmode; 161 struct ath5k_hw *ah; /* Atheros HW */ 162 163 struct ieee80211_supported_band *curband; 164 165 #ifdef CONFIG_ATH5K_DEBUG 166 struct ath5k_dbg_info debug; /* debug info */ 167 #endif /* CONFIG_ATH5K_DEBUG */ 168 169 struct ath5k_buf *bufptr; /* allocated buffer ptr */ 170 struct ath5k_desc *desc; /* TX/RX descriptors */ 171 dma_addr_t desc_daddr; /* DMA (physical) address */ 172 size_t desc_len; /* size of TX/RX descriptors */ 173 174 DECLARE_BITMAP(status, 5); 175 #define ATH_STAT_INVALID 0 /* disable hardware accesses */ 176 #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */ 177 #define ATH_STAT_PROMISC 2 178 #define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */ 179 #define ATH_STAT_STARTED 4 /* opened & irqs enabled */ 180 181 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */ 182 unsigned int curmode; /* current phy mode */ 183 struct ieee80211_channel *curchan; /* current h/w channel */ 184 185 struct ieee80211_vif *vif; 186 187 enum ath5k_int imask; /* interrupt mask copy */ 188 189 u8 bssidmask[ETH_ALEN]; 190 191 unsigned int led_pin, /* GPIO pin for driving LED */ 192 led_on; /* pin setting for LED on */ 193 194 struct work_struct reset_work; /* deferred chip reset */ 195 196 unsigned int rxbufsize; /* rx size based on mtu */ 197 struct list_head rxbuf; /* receive buffer */ 198 spinlock_t rxbuflock; 199 u32 *rxlink; /* link ptr in last RX desc */ 200 struct tasklet_struct rxtq; /* rx intr tasklet */ 201 struct ath5k_led rx_led; /* rx led */ 202 203 struct list_head txbuf; /* transmit buffer */ 204 spinlock_t txbuflock; 205 unsigned int txbuf_len; /* buf count in txbuf list */ 206 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */ 207 struct ath5k_txq *txq; /* main tx queue */ 208 struct tasklet_struct txtq; /* tx intr tasklet */ 209 struct ath5k_led tx_led; /* tx led */ 210 211 struct ath5k_rfkill rf_kill; 212 213 struct tasklet_struct calib; /* calibration tasklet */ 214 215 spinlock_t block; /* protects beacon */ 216 struct tasklet_struct beacontq; /* beacon intr tasklet */ 217 struct ath5k_buf *bbuf; /* beacon buffer */ 218 unsigned int bhalq, /* SW q for outgoing beacons */ 219 bmisscount, /* missed beacon transmits */ 220 bintval, /* beacon interval in TU */ 221 bsent; 222 unsigned int nexttbtt; /* next beacon time in TU */ 223 struct ath5k_txq *cabq; /* content after beacon */ 224 225 int power_level; /* Requested tx power in dbm */ 226 bool assoc; /* associate state */ 227 bool enable_beacon; /* true if beacons are on */ 228 229 struct ath5k_statistics stats; 230 231 struct ath5k_ani_state ani_state; 232 struct tasklet_struct ani_tasklet; /* ANI calibration */ 233 }; 234 235 #define ath5k_hw_hasbssidmask(_ah) \ 236 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) 237 #define ath5k_hw_hasveol(_ah) \ 238 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) 239 240 #endif 241