1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/hardirq.h> 46 #include <linux/if.h> 47 #include <linux/io.h> 48 #include <linux/netdevice.h> 49 #include <linux/cache.h> 50 #include <linux/ethtool.h> 51 #include <linux/uaccess.h> 52 #include <linux/slab.h> 53 #include <linux/etherdevice.h> 54 55 #include <net/ieee80211_radiotap.h> 56 57 #include <asm/unaligned.h> 58 59 #include "base.h" 60 #include "reg.h" 61 #include "debug.h" 62 #include "ani.h" 63 64 #define CREATE_TRACE_POINTS 65 #include "trace.h" 66 67 int ath5k_modparam_nohwcrypt; 68 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 69 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 70 71 static int modparam_all_channels; 72 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 73 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 74 75 static int modparam_fastchanswitch; 76 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); 77 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 78 79 80 /* Module info */ 81 MODULE_AUTHOR("Jiri Slaby"); 82 MODULE_AUTHOR("Nick Kossifidis"); 83 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 84 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 85 MODULE_LICENSE("Dual BSD/GPL"); 86 87 static int ath5k_init(struct ieee80211_hw *hw); 88 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 89 bool skip_pcu); 90 int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 91 void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 92 93 /* Known SREVs */ 94 static const struct ath5k_srev_name srev_names[] = { 95 #ifdef CONFIG_ATHEROS_AR231X 96 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 97 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 98 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 99 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 100 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 101 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 102 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 103 #else 104 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 105 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 106 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 107 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 108 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 109 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 110 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 111 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 112 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 113 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 114 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 115 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 116 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 117 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 118 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 119 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 120 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 121 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 122 #endif 123 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 124 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 125 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 126 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 127 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 128 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 129 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 130 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 131 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 132 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 133 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 134 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 135 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 136 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 138 #ifdef CONFIG_ATHEROS_AR231X 139 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 140 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 141 #endif 142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 143 }; 144 145 static const struct ieee80211_rate ath5k_rates[] = { 146 { .bitrate = 10, 147 .hw_value = ATH5K_RATE_CODE_1M, }, 148 { .bitrate = 20, 149 .hw_value = ATH5K_RATE_CODE_2M, 150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 151 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 152 { .bitrate = 55, 153 .hw_value = ATH5K_RATE_CODE_5_5M, 154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 155 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 156 { .bitrate = 110, 157 .hw_value = ATH5K_RATE_CODE_11M, 158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 159 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 160 { .bitrate = 60, 161 .hw_value = ATH5K_RATE_CODE_6M, 162 .flags = 0 }, 163 { .bitrate = 90, 164 .hw_value = ATH5K_RATE_CODE_9M, 165 .flags = 0 }, 166 { .bitrate = 120, 167 .hw_value = ATH5K_RATE_CODE_12M, 168 .flags = 0 }, 169 { .bitrate = 180, 170 .hw_value = ATH5K_RATE_CODE_18M, 171 .flags = 0 }, 172 { .bitrate = 240, 173 .hw_value = ATH5K_RATE_CODE_24M, 174 .flags = 0 }, 175 { .bitrate = 360, 176 .hw_value = ATH5K_RATE_CODE_36M, 177 .flags = 0 }, 178 { .bitrate = 480, 179 .hw_value = ATH5K_RATE_CODE_48M, 180 .flags = 0 }, 181 { .bitrate = 540, 182 .hw_value = ATH5K_RATE_CODE_54M, 183 .flags = 0 }, 184 /* XR missing */ 185 }; 186 187 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 188 { 189 u64 tsf = ath5k_hw_get_tsf64(ah); 190 191 if ((tsf & 0x7fff) < rstamp) 192 tsf -= 0x8000; 193 194 return (tsf & ~0x7fff) | rstamp; 195 } 196 197 const char * 198 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 199 { 200 const char *name = "xxxxx"; 201 unsigned int i; 202 203 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 204 if (srev_names[i].sr_type != type) 205 continue; 206 207 if ((val & 0xf0) == srev_names[i].sr_val) 208 name = srev_names[i].sr_name; 209 210 if ((val & 0xff) == srev_names[i].sr_val) { 211 name = srev_names[i].sr_name; 212 break; 213 } 214 } 215 216 return name; 217 } 218 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 219 { 220 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 221 return ath5k_hw_reg_read(ah, reg_offset); 222 } 223 224 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 225 { 226 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 227 ath5k_hw_reg_write(ah, val, reg_offset); 228 } 229 230 static const struct ath_ops ath5k_common_ops = { 231 .read = ath5k_ioread32, 232 .write = ath5k_iowrite32, 233 }; 234 235 /***********************\ 236 * Driver Initialization * 237 \***********************/ 238 239 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 240 { 241 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 242 struct ath5k_softc *sc = hw->priv; 243 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 244 245 return ath_reg_notifier_apply(wiphy, request, regulatory); 246 } 247 248 /********************\ 249 * Channel/mode setup * 250 \********************/ 251 252 /* 253 * Returns true for the channel numbers used without all_channels modparam. 254 */ 255 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 256 { 257 if (band == IEEE80211_BAND_2GHZ && chan <= 14) 258 return true; 259 260 return /* UNII 1,2 */ 261 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 262 /* midband */ 263 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 264 /* UNII-3 */ 265 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 266 /* 802.11j 5.030-5.080 GHz (20MHz) */ 267 (chan == 8 || chan == 12 || chan == 16) || 268 /* 802.11j 4.9GHz (20MHz) */ 269 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 270 } 271 272 static unsigned int 273 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 274 unsigned int mode, unsigned int max) 275 { 276 unsigned int count, size, chfreq, freq, ch; 277 enum ieee80211_band band; 278 279 switch (mode) { 280 case AR5K_MODE_11A: 281 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 282 size = 220; 283 chfreq = CHANNEL_5GHZ; 284 band = IEEE80211_BAND_5GHZ; 285 break; 286 case AR5K_MODE_11B: 287 case AR5K_MODE_11G: 288 size = 26; 289 chfreq = CHANNEL_2GHZ; 290 band = IEEE80211_BAND_2GHZ; 291 break; 292 default: 293 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 294 return 0; 295 } 296 297 count = 0; 298 for (ch = 1; ch <= size && count < max; ch++) { 299 freq = ieee80211_channel_to_frequency(ch, band); 300 301 if (freq == 0) /* mapping failed - not a standard channel */ 302 continue; 303 304 /* Check if channel is supported by the chipset */ 305 if (!ath5k_channel_ok(ah, freq, chfreq)) 306 continue; 307 308 if (!modparam_all_channels && 309 !ath5k_is_standard_channel(ch, band)) 310 continue; 311 312 /* Write channel info and increment counter */ 313 channels[count].center_freq = freq; 314 channels[count].band = band; 315 switch (mode) { 316 case AR5K_MODE_11A: 317 case AR5K_MODE_11G: 318 channels[count].hw_value = chfreq | CHANNEL_OFDM; 319 break; 320 case AR5K_MODE_11B: 321 channels[count].hw_value = CHANNEL_B; 322 } 323 324 count++; 325 } 326 327 return count; 328 } 329 330 static void 331 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 332 { 333 u8 i; 334 335 for (i = 0; i < AR5K_MAX_RATES; i++) 336 sc->rate_idx[b->band][i] = -1; 337 338 for (i = 0; i < b->n_bitrates; i++) { 339 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 340 if (b->bitrates[i].hw_value_short) 341 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 342 } 343 } 344 345 static int 346 ath5k_setup_bands(struct ieee80211_hw *hw) 347 { 348 struct ath5k_softc *sc = hw->priv; 349 struct ath5k_hw *ah = sc->ah; 350 struct ieee80211_supported_band *sband; 351 int max_c, count_c = 0; 352 int i; 353 354 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 355 max_c = ARRAY_SIZE(sc->channels); 356 357 /* 2GHz band */ 358 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 359 sband->band = IEEE80211_BAND_2GHZ; 360 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 361 362 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 363 /* G mode */ 364 memcpy(sband->bitrates, &ath5k_rates[0], 365 sizeof(struct ieee80211_rate) * 12); 366 sband->n_bitrates = 12; 367 368 sband->channels = sc->channels; 369 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 370 AR5K_MODE_11G, max_c); 371 372 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 373 count_c = sband->n_channels; 374 max_c -= count_c; 375 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 376 /* B mode */ 377 memcpy(sband->bitrates, &ath5k_rates[0], 378 sizeof(struct ieee80211_rate) * 4); 379 sband->n_bitrates = 4; 380 381 /* 5211 only supports B rates and uses 4bit rate codes 382 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 383 * fix them up here: 384 */ 385 if (ah->ah_version == AR5K_AR5211) { 386 for (i = 0; i < 4; i++) { 387 sband->bitrates[i].hw_value = 388 sband->bitrates[i].hw_value & 0xF; 389 sband->bitrates[i].hw_value_short = 390 sband->bitrates[i].hw_value_short & 0xF; 391 } 392 } 393 394 sband->channels = sc->channels; 395 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 396 AR5K_MODE_11B, max_c); 397 398 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 399 count_c = sband->n_channels; 400 max_c -= count_c; 401 } 402 ath5k_setup_rate_idx(sc, sband); 403 404 /* 5GHz band, A mode */ 405 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 406 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 407 sband->band = IEEE80211_BAND_5GHZ; 408 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 409 410 memcpy(sband->bitrates, &ath5k_rates[4], 411 sizeof(struct ieee80211_rate) * 8); 412 sband->n_bitrates = 8; 413 414 sband->channels = &sc->channels[count_c]; 415 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 416 AR5K_MODE_11A, max_c); 417 418 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 419 } 420 ath5k_setup_rate_idx(sc, sband); 421 422 ath5k_debug_dump_bands(sc); 423 424 return 0; 425 } 426 427 /* 428 * Set/change channels. We always reset the chip. 429 * To accomplish this we must first cleanup any pending DMA, 430 * then restart stuff after a la ath5k_init. 431 * 432 * Called with sc->lock. 433 */ 434 int 435 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 436 { 437 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 438 "channel set, resetting (%u -> %u MHz)\n", 439 sc->curchan->center_freq, chan->center_freq); 440 441 /* 442 * To switch channels clear any pending DMA operations; 443 * wait long enough for the RX fifo to drain, reset the 444 * hardware at the new frequency, and then re-enable 445 * the relevant bits of the h/w. 446 */ 447 return ath5k_reset(sc, chan, true); 448 } 449 450 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 451 { 452 struct ath5k_vif_iter_data *iter_data = data; 453 int i; 454 struct ath5k_vif *avf = (void *)vif->drv_priv; 455 456 if (iter_data->hw_macaddr) 457 for (i = 0; i < ETH_ALEN; i++) 458 iter_data->mask[i] &= 459 ~(iter_data->hw_macaddr[i] ^ mac[i]); 460 461 if (!iter_data->found_active) { 462 iter_data->found_active = true; 463 memcpy(iter_data->active_mac, mac, ETH_ALEN); 464 } 465 466 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 467 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0) 468 iter_data->need_set_hw_addr = false; 469 470 if (!iter_data->any_assoc) { 471 if (avf->assoc) 472 iter_data->any_assoc = true; 473 } 474 475 /* Calculate combined mode - when APs are active, operate in AP mode. 476 * Otherwise use the mode of the new interface. This can currently 477 * only deal with combinations of APs and STAs. Only one ad-hoc 478 * interfaces is allowed. 479 */ 480 if (avf->opmode == NL80211_IFTYPE_AP) 481 iter_data->opmode = NL80211_IFTYPE_AP; 482 else { 483 if (avf->opmode == NL80211_IFTYPE_STATION) 484 iter_data->n_stas++; 485 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 486 iter_data->opmode = avf->opmode; 487 } 488 } 489 490 void 491 ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 492 struct ieee80211_vif *vif) 493 { 494 struct ath_common *common = ath5k_hw_common(sc->ah); 495 struct ath5k_vif_iter_data iter_data; 496 u32 rfilt; 497 498 /* 499 * Use the hardware MAC address as reference, the hardware uses it 500 * together with the BSSID mask when matching addresses. 501 */ 502 iter_data.hw_macaddr = common->macaddr; 503 memset(&iter_data.mask, 0xff, ETH_ALEN); 504 iter_data.found_active = false; 505 iter_data.need_set_hw_addr = true; 506 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 507 iter_data.n_stas = 0; 508 509 if (vif) 510 ath5k_vif_iter(&iter_data, vif->addr, vif); 511 512 /* Get list of all active MAC addresses */ 513 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 514 &iter_data); 515 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN); 516 517 sc->opmode = iter_data.opmode; 518 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED) 519 /* Nothing active, default to station mode */ 520 sc->opmode = NL80211_IFTYPE_STATION; 521 522 ath5k_hw_set_opmode(sc->ah, sc->opmode); 523 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 524 sc->opmode, ath_opmode_to_string(sc->opmode)); 525 526 if (iter_data.need_set_hw_addr && iter_data.found_active) 527 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac); 528 529 if (ath5k_hw_hasbssidmask(sc->ah)) 530 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 531 532 /* Set up RX Filter */ 533 if (iter_data.n_stas > 1) { 534 /* If you have multiple STA interfaces connected to 535 * different APs, ARPs are not received (most of the time?) 536 * Enabling PROMISC appears to fix that probem. 537 */ 538 sc->filter_flags |= AR5K_RX_FILTER_PROM; 539 } 540 541 rfilt = sc->filter_flags; 542 ath5k_hw_set_rx_filter(sc->ah, rfilt); 543 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 544 } 545 546 static inline int 547 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 548 { 549 int rix; 550 551 /* return base rate on errors */ 552 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 553 "hw_rix out of bounds: %x\n", hw_rix)) 554 return 0; 555 556 rix = sc->rate_idx[sc->curchan->band][hw_rix]; 557 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 558 rix = 0; 559 560 return rix; 561 } 562 563 /***************\ 564 * Buffers setup * 565 \***************/ 566 567 static 568 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 569 { 570 struct ath_common *common = ath5k_hw_common(sc->ah); 571 struct sk_buff *skb; 572 573 /* 574 * Allocate buffer with headroom_needed space for the 575 * fake physical layer header at the start. 576 */ 577 skb = ath_rxbuf_alloc(common, 578 common->rx_bufsize, 579 GFP_ATOMIC); 580 581 if (!skb) { 582 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 583 common->rx_bufsize); 584 return NULL; 585 } 586 587 *skb_addr = dma_map_single(sc->dev, 588 skb->data, common->rx_bufsize, 589 DMA_FROM_DEVICE); 590 591 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) { 592 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 593 dev_kfree_skb(skb); 594 return NULL; 595 } 596 return skb; 597 } 598 599 static int 600 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 601 { 602 struct ath5k_hw *ah = sc->ah; 603 struct sk_buff *skb = bf->skb; 604 struct ath5k_desc *ds; 605 int ret; 606 607 if (!skb) { 608 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 609 if (!skb) 610 return -ENOMEM; 611 bf->skb = skb; 612 } 613 614 /* 615 * Setup descriptors. For receive we always terminate 616 * the descriptor list with a self-linked entry so we'll 617 * not get overrun under high load (as can happen with a 618 * 5212 when ANI processing enables PHY error frames). 619 * 620 * To ensure the last descriptor is self-linked we create 621 * each descriptor as self-linked and add it to the end. As 622 * each additional descriptor is added the previous self-linked 623 * entry is "fixed" naturally. This should be safe even 624 * if DMA is happening. When processing RX interrupts we 625 * never remove/process the last, self-linked, entry on the 626 * descriptor list. This ensures the hardware always has 627 * someplace to write a new frame. 628 */ 629 ds = bf->desc; 630 ds->ds_link = bf->daddr; /* link to self */ 631 ds->ds_data = bf->skbaddr; 632 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 633 if (ret) { 634 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__); 635 return ret; 636 } 637 638 if (sc->rxlink != NULL) 639 *sc->rxlink = bf->daddr; 640 sc->rxlink = &ds->ds_link; 641 return 0; 642 } 643 644 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 645 { 646 struct ieee80211_hdr *hdr; 647 enum ath5k_pkt_type htype; 648 __le16 fc; 649 650 hdr = (struct ieee80211_hdr *)skb->data; 651 fc = hdr->frame_control; 652 653 if (ieee80211_is_beacon(fc)) 654 htype = AR5K_PKT_TYPE_BEACON; 655 else if (ieee80211_is_probe_resp(fc)) 656 htype = AR5K_PKT_TYPE_PROBE_RESP; 657 else if (ieee80211_is_atim(fc)) 658 htype = AR5K_PKT_TYPE_ATIM; 659 else if (ieee80211_is_pspoll(fc)) 660 htype = AR5K_PKT_TYPE_PSPOLL; 661 else 662 htype = AR5K_PKT_TYPE_NORMAL; 663 664 return htype; 665 } 666 667 static int 668 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 669 struct ath5k_txq *txq, int padsize) 670 { 671 struct ath5k_hw *ah = sc->ah; 672 struct ath5k_desc *ds = bf->desc; 673 struct sk_buff *skb = bf->skb; 674 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 675 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 676 struct ieee80211_rate *rate; 677 unsigned int mrr_rate[3], mrr_tries[3]; 678 int i, ret; 679 u16 hw_rate; 680 u16 cts_rate = 0; 681 u16 duration = 0; 682 u8 rc_flags; 683 684 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 685 686 /* XXX endianness */ 687 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 688 DMA_TO_DEVICE); 689 690 rate = ieee80211_get_tx_rate(sc->hw, info); 691 if (!rate) { 692 ret = -EINVAL; 693 goto err_unmap; 694 } 695 696 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 697 flags |= AR5K_TXDESC_NOACK; 698 699 rc_flags = info->control.rates[0].flags; 700 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 701 rate->hw_value_short : rate->hw_value; 702 703 pktlen = skb->len; 704 705 /* FIXME: If we are in g mode and rate is a CCK rate 706 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 707 * from tx power (value is in dB units already) */ 708 if (info->control.hw_key) { 709 keyidx = info->control.hw_key->hw_key_idx; 710 pktlen += info->control.hw_key->icv_len; 711 } 712 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 713 flags |= AR5K_TXDESC_RTSENA; 714 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 715 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 716 info->control.vif, pktlen, info)); 717 } 718 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 719 flags |= AR5K_TXDESC_CTSENA; 720 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 721 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 722 info->control.vif, pktlen, info)); 723 } 724 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 725 ieee80211_get_hdrlen_from_skb(skb), padsize, 726 get_hw_packet_type(skb), 727 (sc->power_level * 2), 728 hw_rate, 729 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 730 cts_rate, duration); 731 if (ret) 732 goto err_unmap; 733 734 memset(mrr_rate, 0, sizeof(mrr_rate)); 735 memset(mrr_tries, 0, sizeof(mrr_tries)); 736 for (i = 0; i < 3; i++) { 737 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 738 if (!rate) 739 break; 740 741 mrr_rate[i] = rate->hw_value; 742 mrr_tries[i] = info->control.rates[i + 1].count; 743 } 744 745 ath5k_hw_setup_mrr_tx_desc(ah, ds, 746 mrr_rate[0], mrr_tries[0], 747 mrr_rate[1], mrr_tries[1], 748 mrr_rate[2], mrr_tries[2]); 749 750 ds->ds_link = 0; 751 ds->ds_data = bf->skbaddr; 752 753 spin_lock_bh(&txq->lock); 754 list_add_tail(&bf->list, &txq->q); 755 txq->txq_len++; 756 if (txq->link == NULL) /* is this first packet? */ 757 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 758 else /* no, so only link it */ 759 *txq->link = bf->daddr; 760 761 txq->link = &ds->ds_link; 762 ath5k_hw_start_tx_dma(ah, txq->qnum); 763 mmiowb(); 764 spin_unlock_bh(&txq->lock); 765 766 return 0; 767 err_unmap: 768 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 769 return ret; 770 } 771 772 /*******************\ 773 * Descriptors setup * 774 \*******************/ 775 776 static int 777 ath5k_desc_alloc(struct ath5k_softc *sc) 778 { 779 struct ath5k_desc *ds; 780 struct ath5k_buf *bf; 781 dma_addr_t da; 782 unsigned int i; 783 int ret; 784 785 /* allocate descriptors */ 786 sc->desc_len = sizeof(struct ath5k_desc) * 787 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 788 789 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len, 790 &sc->desc_daddr, GFP_KERNEL); 791 if (sc->desc == NULL) { 792 ATH5K_ERR(sc, "can't allocate descriptors\n"); 793 ret = -ENOMEM; 794 goto err; 795 } 796 ds = sc->desc; 797 da = sc->desc_daddr; 798 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 799 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 800 801 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 802 sizeof(struct ath5k_buf), GFP_KERNEL); 803 if (bf == NULL) { 804 ATH5K_ERR(sc, "can't allocate bufptr\n"); 805 ret = -ENOMEM; 806 goto err_free; 807 } 808 sc->bufptr = bf; 809 810 INIT_LIST_HEAD(&sc->rxbuf); 811 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 812 bf->desc = ds; 813 bf->daddr = da; 814 list_add_tail(&bf->list, &sc->rxbuf); 815 } 816 817 INIT_LIST_HEAD(&sc->txbuf); 818 sc->txbuf_len = ATH_TXBUF; 819 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 820 da += sizeof(*ds)) { 821 bf->desc = ds; 822 bf->daddr = da; 823 list_add_tail(&bf->list, &sc->txbuf); 824 } 825 826 /* beacon buffers */ 827 INIT_LIST_HEAD(&sc->bcbuf); 828 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 829 bf->desc = ds; 830 bf->daddr = da; 831 list_add_tail(&bf->list, &sc->bcbuf); 832 } 833 834 return 0; 835 err_free: 836 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 837 err: 838 sc->desc = NULL; 839 return ret; 840 } 841 842 void 843 ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 844 { 845 BUG_ON(!bf); 846 if (!bf->skb) 847 return; 848 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len, 849 DMA_TO_DEVICE); 850 dev_kfree_skb_any(bf->skb); 851 bf->skb = NULL; 852 bf->skbaddr = 0; 853 bf->desc->ds_data = 0; 854 } 855 856 void 857 ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 858 { 859 struct ath5k_hw *ah = sc->ah; 860 struct ath_common *common = ath5k_hw_common(ah); 861 862 BUG_ON(!bf); 863 if (!bf->skb) 864 return; 865 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize, 866 DMA_FROM_DEVICE); 867 dev_kfree_skb_any(bf->skb); 868 bf->skb = NULL; 869 bf->skbaddr = 0; 870 bf->desc->ds_data = 0; 871 } 872 873 static void 874 ath5k_desc_free(struct ath5k_softc *sc) 875 { 876 struct ath5k_buf *bf; 877 878 list_for_each_entry(bf, &sc->txbuf, list) 879 ath5k_txbuf_free_skb(sc, bf); 880 list_for_each_entry(bf, &sc->rxbuf, list) 881 ath5k_rxbuf_free_skb(sc, bf); 882 list_for_each_entry(bf, &sc->bcbuf, list) 883 ath5k_txbuf_free_skb(sc, bf); 884 885 /* Free memory associated with all descriptors */ 886 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 887 sc->desc = NULL; 888 sc->desc_daddr = 0; 889 890 kfree(sc->bufptr); 891 sc->bufptr = NULL; 892 } 893 894 895 /**************\ 896 * Queues setup * 897 \**************/ 898 899 static struct ath5k_txq * 900 ath5k_txq_setup(struct ath5k_softc *sc, 901 int qtype, int subtype) 902 { 903 struct ath5k_hw *ah = sc->ah; 904 struct ath5k_txq *txq; 905 struct ath5k_txq_info qi = { 906 .tqi_subtype = subtype, 907 /* XXX: default values not correct for B and XR channels, 908 * but who cares? */ 909 .tqi_aifs = AR5K_TUNE_AIFS, 910 .tqi_cw_min = AR5K_TUNE_CWMIN, 911 .tqi_cw_max = AR5K_TUNE_CWMAX 912 }; 913 int qnum; 914 915 /* 916 * Enable interrupts only for EOL and DESC conditions. 917 * We mark tx descriptors to receive a DESC interrupt 918 * when a tx queue gets deep; otherwise we wait for the 919 * EOL to reap descriptors. Note that this is done to 920 * reduce interrupt load and this only defers reaping 921 * descriptors, never transmitting frames. Aside from 922 * reducing interrupts this also permits more concurrency. 923 * The only potential downside is if the tx queue backs 924 * up in which case the top half of the kernel may backup 925 * due to a lack of tx descriptors. 926 */ 927 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 928 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 929 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 930 if (qnum < 0) { 931 /* 932 * NB: don't print a message, this happens 933 * normally on parts with too few tx queues 934 */ 935 return ERR_PTR(qnum); 936 } 937 if (qnum >= ARRAY_SIZE(sc->txqs)) { 938 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 939 qnum, ARRAY_SIZE(sc->txqs)); 940 ath5k_hw_release_tx_queue(ah, qnum); 941 return ERR_PTR(-EINVAL); 942 } 943 txq = &sc->txqs[qnum]; 944 if (!txq->setup) { 945 txq->qnum = qnum; 946 txq->link = NULL; 947 INIT_LIST_HEAD(&txq->q); 948 spin_lock_init(&txq->lock); 949 txq->setup = true; 950 txq->txq_len = 0; 951 txq->txq_max = ATH5K_TXQ_LEN_MAX; 952 txq->txq_poll_mark = false; 953 txq->txq_stuck = 0; 954 } 955 return &sc->txqs[qnum]; 956 } 957 958 static int 959 ath5k_beaconq_setup(struct ath5k_hw *ah) 960 { 961 struct ath5k_txq_info qi = { 962 /* XXX: default values not correct for B and XR channels, 963 * but who cares? */ 964 .tqi_aifs = AR5K_TUNE_AIFS, 965 .tqi_cw_min = AR5K_TUNE_CWMIN, 966 .tqi_cw_max = AR5K_TUNE_CWMAX, 967 /* NB: for dynamic turbo, don't enable any other interrupts */ 968 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 969 }; 970 971 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 972 } 973 974 static int 975 ath5k_beaconq_config(struct ath5k_softc *sc) 976 { 977 struct ath5k_hw *ah = sc->ah; 978 struct ath5k_txq_info qi; 979 int ret; 980 981 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 982 if (ret) 983 goto err; 984 985 if (sc->opmode == NL80211_IFTYPE_AP || 986 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 987 /* 988 * Always burst out beacon and CAB traffic 989 * (aifs = cwmin = cwmax = 0) 990 */ 991 qi.tqi_aifs = 0; 992 qi.tqi_cw_min = 0; 993 qi.tqi_cw_max = 0; 994 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 995 /* 996 * Adhoc mode; backoff between 0 and (2 * cw_min). 997 */ 998 qi.tqi_aifs = 0; 999 qi.tqi_cw_min = 0; 1000 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 1001 } 1002 1003 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1004 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1005 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1006 1007 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1008 if (ret) { 1009 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1010 "hardware queue!\n", __func__); 1011 goto err; 1012 } 1013 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ 1014 if (ret) 1015 goto err; 1016 1017 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1018 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1019 if (ret) 1020 goto err; 1021 1022 qi.tqi_ready_time = (sc->bintval * 80) / 100; 1023 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1024 if (ret) 1025 goto err; 1026 1027 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1028 err: 1029 return ret; 1030 } 1031 1032 /** 1033 * ath5k_drain_tx_buffs - Empty tx buffers 1034 * 1035 * @sc The &struct ath5k_softc 1036 * 1037 * Empty tx buffers from all queues in preparation 1038 * of a reset or during shutdown. 1039 * 1040 * NB: this assumes output has been stopped and 1041 * we do not need to block ath5k_tx_tasklet 1042 */ 1043 static void 1044 ath5k_drain_tx_buffs(struct ath5k_softc *sc) 1045 { 1046 struct ath5k_txq *txq; 1047 struct ath5k_buf *bf, *bf0; 1048 int i; 1049 1050 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 1051 if (sc->txqs[i].setup) { 1052 txq = &sc->txqs[i]; 1053 spin_lock_bh(&txq->lock); 1054 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1055 ath5k_debug_printtxbuf(sc, bf); 1056 1057 ath5k_txbuf_free_skb(sc, bf); 1058 1059 spin_lock_bh(&sc->txbuflock); 1060 list_move_tail(&bf->list, &sc->txbuf); 1061 sc->txbuf_len++; 1062 txq->txq_len--; 1063 spin_unlock_bh(&sc->txbuflock); 1064 } 1065 txq->link = NULL; 1066 txq->txq_poll_mark = false; 1067 spin_unlock_bh(&txq->lock); 1068 } 1069 } 1070 } 1071 1072 static void 1073 ath5k_txq_release(struct ath5k_softc *sc) 1074 { 1075 struct ath5k_txq *txq = sc->txqs; 1076 unsigned int i; 1077 1078 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1079 if (txq->setup) { 1080 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1081 txq->setup = false; 1082 } 1083 } 1084 1085 1086 /*************\ 1087 * RX Handling * 1088 \*************/ 1089 1090 /* 1091 * Enable the receive h/w following a reset. 1092 */ 1093 static int 1094 ath5k_rx_start(struct ath5k_softc *sc) 1095 { 1096 struct ath5k_hw *ah = sc->ah; 1097 struct ath_common *common = ath5k_hw_common(ah); 1098 struct ath5k_buf *bf; 1099 int ret; 1100 1101 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1102 1103 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1104 common->cachelsz, common->rx_bufsize); 1105 1106 spin_lock_bh(&sc->rxbuflock); 1107 sc->rxlink = NULL; 1108 list_for_each_entry(bf, &sc->rxbuf, list) { 1109 ret = ath5k_rxbuf_setup(sc, bf); 1110 if (ret != 0) { 1111 spin_unlock_bh(&sc->rxbuflock); 1112 goto err; 1113 } 1114 } 1115 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1116 ath5k_hw_set_rxdp(ah, bf->daddr); 1117 spin_unlock_bh(&sc->rxbuflock); 1118 1119 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1120 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */ 1121 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1122 1123 return 0; 1124 err: 1125 return ret; 1126 } 1127 1128 /* 1129 * Disable the receive logic on PCU (DRU) 1130 * In preparation for a shutdown. 1131 * 1132 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1133 * does. 1134 */ 1135 static void 1136 ath5k_rx_stop(struct ath5k_softc *sc) 1137 { 1138 struct ath5k_hw *ah = sc->ah; 1139 1140 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1141 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1142 1143 ath5k_debug_printrxbuffs(sc, ah); 1144 } 1145 1146 static unsigned int 1147 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb, 1148 struct ath5k_rx_status *rs) 1149 { 1150 struct ath5k_hw *ah = sc->ah; 1151 struct ath_common *common = ath5k_hw_common(ah); 1152 struct ieee80211_hdr *hdr = (void *)skb->data; 1153 unsigned int keyix, hlen; 1154 1155 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1156 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1157 return RX_FLAG_DECRYPTED; 1158 1159 /* Apparently when a default key is used to decrypt the packet 1160 the hw does not set the index used to decrypt. In such cases 1161 get the index from the packet. */ 1162 hlen = ieee80211_hdrlen(hdr->frame_control); 1163 if (ieee80211_has_protected(hdr->frame_control) && 1164 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1165 skb->len >= hlen + 4) { 1166 keyix = skb->data[hlen + 3] >> 6; 1167 1168 if (test_bit(keyix, common->keymap)) 1169 return RX_FLAG_DECRYPTED; 1170 } 1171 1172 return 0; 1173 } 1174 1175 1176 static void 1177 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1178 struct ieee80211_rx_status *rxs) 1179 { 1180 struct ath_common *common = ath5k_hw_common(sc->ah); 1181 u64 tsf, bc_tstamp; 1182 u32 hw_tu; 1183 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1184 1185 if (ieee80211_is_beacon(mgmt->frame_control) && 1186 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1187 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1188 /* 1189 * Received an IBSS beacon with the same BSSID. Hardware *must* 1190 * have updated the local TSF. We have to work around various 1191 * hardware bugs, though... 1192 */ 1193 tsf = ath5k_hw_get_tsf64(sc->ah); 1194 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1195 hw_tu = TSF_TO_TU(tsf); 1196 1197 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1198 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1199 (unsigned long long)bc_tstamp, 1200 (unsigned long long)rxs->mactime, 1201 (unsigned long long)(rxs->mactime - bc_tstamp), 1202 (unsigned long long)tsf); 1203 1204 /* 1205 * Sometimes the HW will give us a wrong tstamp in the rx 1206 * status, causing the timestamp extension to go wrong. 1207 * (This seems to happen especially with beacon frames bigger 1208 * than 78 byte (incl. FCS)) 1209 * But we know that the receive timestamp must be later than the 1210 * timestamp of the beacon since HW must have synced to that. 1211 * 1212 * NOTE: here we assume mactime to be after the frame was 1213 * received, not like mac80211 which defines it at the start. 1214 */ 1215 if (bc_tstamp > rxs->mactime) { 1216 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1217 "fixing mactime from %llx to %llx\n", 1218 (unsigned long long)rxs->mactime, 1219 (unsigned long long)tsf); 1220 rxs->mactime = tsf; 1221 } 1222 1223 /* 1224 * Local TSF might have moved higher than our beacon timers, 1225 * in that case we have to update them to continue sending 1226 * beacons. This also takes care of synchronizing beacon sending 1227 * times with other stations. 1228 */ 1229 if (hw_tu >= sc->nexttbtt) 1230 ath5k_beacon_update_timers(sc, bc_tstamp); 1231 1232 /* Check if the beacon timers are still correct, because a TSF 1233 * update might have created a window between them - for a 1234 * longer description see the comment of this function: */ 1235 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) { 1236 ath5k_beacon_update_timers(sc, bc_tstamp); 1237 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1238 "fixed beacon timers after beacon receive\n"); 1239 } 1240 } 1241 } 1242 1243 static void 1244 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) 1245 { 1246 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1247 struct ath5k_hw *ah = sc->ah; 1248 struct ath_common *common = ath5k_hw_common(ah); 1249 1250 /* only beacons from our BSSID */ 1251 if (!ieee80211_is_beacon(mgmt->frame_control) || 1252 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) 1253 return; 1254 1255 ewma_add(&ah->ah_beacon_rssi_avg, rssi); 1256 1257 /* in IBSS mode we should keep RSSI statistics per neighbour */ 1258 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ 1259 } 1260 1261 /* 1262 * Compute padding position. skb must contain an IEEE 802.11 frame 1263 */ 1264 static int ath5k_common_padpos(struct sk_buff *skb) 1265 { 1266 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 1267 __le16 frame_control = hdr->frame_control; 1268 int padpos = 24; 1269 1270 if (ieee80211_has_a4(frame_control)) { 1271 padpos += ETH_ALEN; 1272 } 1273 if (ieee80211_is_data_qos(frame_control)) { 1274 padpos += IEEE80211_QOS_CTL_LEN; 1275 } 1276 1277 return padpos; 1278 } 1279 1280 /* 1281 * This function expects an 802.11 frame and returns the number of 1282 * bytes added, or -1 if we don't have enough header room. 1283 */ 1284 static int ath5k_add_padding(struct sk_buff *skb) 1285 { 1286 int padpos = ath5k_common_padpos(skb); 1287 int padsize = padpos & 3; 1288 1289 if (padsize && skb->len>padpos) { 1290 1291 if (skb_headroom(skb) < padsize) 1292 return -1; 1293 1294 skb_push(skb, padsize); 1295 memmove(skb->data, skb->data+padsize, padpos); 1296 return padsize; 1297 } 1298 1299 return 0; 1300 } 1301 1302 /* 1303 * The MAC header is padded to have 32-bit boundary if the 1304 * packet payload is non-zero. The general calculation for 1305 * padsize would take into account odd header lengths: 1306 * padsize = 4 - (hdrlen & 3); however, since only 1307 * even-length headers are used, padding can only be 0 or 2 1308 * bytes and we can optimize this a bit. We must not try to 1309 * remove padding from short control frames that do not have a 1310 * payload. 1311 * 1312 * This function expects an 802.11 frame and returns the number of 1313 * bytes removed. 1314 */ 1315 static int ath5k_remove_padding(struct sk_buff *skb) 1316 { 1317 int padpos = ath5k_common_padpos(skb); 1318 int padsize = padpos & 3; 1319 1320 if (padsize && skb->len>=padpos+padsize) { 1321 memmove(skb->data + padsize, skb->data, padpos); 1322 skb_pull(skb, padsize); 1323 return padsize; 1324 } 1325 1326 return 0; 1327 } 1328 1329 static void 1330 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb, 1331 struct ath5k_rx_status *rs) 1332 { 1333 struct ieee80211_rx_status *rxs; 1334 1335 ath5k_remove_padding(skb); 1336 1337 rxs = IEEE80211_SKB_RXCB(skb); 1338 1339 rxs->flag = 0; 1340 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1341 rxs->flag |= RX_FLAG_MMIC_ERROR; 1342 1343 /* 1344 * always extend the mac timestamp, since this information is 1345 * also needed for proper IBSS merging. 1346 * 1347 * XXX: it might be too late to do it here, since rs_tstamp is 1348 * 15bit only. that means TSF extension has to be done within 1349 * 32768usec (about 32ms). it might be necessary to move this to 1350 * the interrupt handler, like it is done in madwifi. 1351 * 1352 * Unfortunately we don't know when the hardware takes the rx 1353 * timestamp (beginning of phy frame, data frame, end of rx?). 1354 * The only thing we know is that it is hardware specific... 1355 * On AR5213 it seems the rx timestamp is at the end of the 1356 * frame, but i'm not sure. 1357 * 1358 * NOTE: mac80211 defines mactime at the beginning of the first 1359 * data symbol. Since we don't have any time references it's 1360 * impossible to comply to that. This affects IBSS merge only 1361 * right now, so it's not too bad... 1362 */ 1363 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp); 1364 rxs->flag |= RX_FLAG_MACTIME_MPDU; 1365 1366 rxs->freq = sc->curchan->center_freq; 1367 rxs->band = sc->curchan->band; 1368 1369 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi; 1370 1371 rxs->antenna = rs->rs_antenna; 1372 1373 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1374 sc->stats.antenna_rx[rs->rs_antenna]++; 1375 else 1376 sc->stats.antenna_rx[0]++; /* invalid */ 1377 1378 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate); 1379 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs); 1380 1381 if (rxs->rate_idx >= 0 && rs->rs_rate == 1382 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1383 rxs->flag |= RX_FLAG_SHORTPRE; 1384 1385 trace_ath5k_rx(sc, skb); 1386 1387 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi); 1388 1389 /* check beacons in IBSS mode */ 1390 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1391 ath5k_check_ibss_tsf(sc, skb, rxs); 1392 1393 ieee80211_rx(sc->hw, skb); 1394 } 1395 1396 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1397 * 1398 * Check if we want to further process this frame or not. Also update 1399 * statistics. Return true if we want this frame, false if not. 1400 */ 1401 static bool 1402 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) 1403 { 1404 sc->stats.rx_all_count++; 1405 sc->stats.rx_bytes_count += rs->rs_datalen; 1406 1407 if (unlikely(rs->rs_status)) { 1408 if (rs->rs_status & AR5K_RXERR_CRC) 1409 sc->stats.rxerr_crc++; 1410 if (rs->rs_status & AR5K_RXERR_FIFO) 1411 sc->stats.rxerr_fifo++; 1412 if (rs->rs_status & AR5K_RXERR_PHY) { 1413 sc->stats.rxerr_phy++; 1414 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1415 sc->stats.rxerr_phy_code[rs->rs_phyerr]++; 1416 return false; 1417 } 1418 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1419 /* 1420 * Decrypt error. If the error occurred 1421 * because there was no hardware key, then 1422 * let the frame through so the upper layers 1423 * can process it. This is necessary for 5210 1424 * parts which have no way to setup a ``clear'' 1425 * key cache entry. 1426 * 1427 * XXX do key cache faulting 1428 */ 1429 sc->stats.rxerr_decrypt++; 1430 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1431 !(rs->rs_status & AR5K_RXERR_CRC)) 1432 return true; 1433 } 1434 if (rs->rs_status & AR5K_RXERR_MIC) { 1435 sc->stats.rxerr_mic++; 1436 return true; 1437 } 1438 1439 /* reject any frames with non-crypto errors */ 1440 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) 1441 return false; 1442 } 1443 1444 if (unlikely(rs->rs_more)) { 1445 sc->stats.rxerr_jumbo++; 1446 return false; 1447 } 1448 return true; 1449 } 1450 1451 static void 1452 ath5k_set_current_imask(struct ath5k_softc *sc) 1453 { 1454 enum ath5k_int imask = sc->imask; 1455 unsigned long flags; 1456 1457 spin_lock_irqsave(&sc->irqlock, flags); 1458 if (sc->rx_pending) 1459 imask &= ~AR5K_INT_RX_ALL; 1460 if (sc->tx_pending) 1461 imask &= ~AR5K_INT_TX_ALL; 1462 ath5k_hw_set_imr(sc->ah, imask); 1463 spin_unlock_irqrestore(&sc->irqlock, flags); 1464 } 1465 1466 static void 1467 ath5k_tasklet_rx(unsigned long data) 1468 { 1469 struct ath5k_rx_status rs = {}; 1470 struct sk_buff *skb, *next_skb; 1471 dma_addr_t next_skb_addr; 1472 struct ath5k_softc *sc = (void *)data; 1473 struct ath5k_hw *ah = sc->ah; 1474 struct ath_common *common = ath5k_hw_common(ah); 1475 struct ath5k_buf *bf; 1476 struct ath5k_desc *ds; 1477 int ret; 1478 1479 spin_lock(&sc->rxbuflock); 1480 if (list_empty(&sc->rxbuf)) { 1481 ATH5K_WARN(sc, "empty rx buf pool\n"); 1482 goto unlock; 1483 } 1484 do { 1485 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1486 BUG_ON(bf->skb == NULL); 1487 skb = bf->skb; 1488 ds = bf->desc; 1489 1490 /* bail if HW is still using self-linked descriptor */ 1491 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1492 break; 1493 1494 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1495 if (unlikely(ret == -EINPROGRESS)) 1496 break; 1497 else if (unlikely(ret)) { 1498 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1499 sc->stats.rxerr_proc++; 1500 break; 1501 } 1502 1503 if (ath5k_receive_frame_ok(sc, &rs)) { 1504 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1505 1506 /* 1507 * If we can't replace bf->skb with a new skb under 1508 * memory pressure, just skip this packet 1509 */ 1510 if (!next_skb) 1511 goto next; 1512 1513 dma_unmap_single(sc->dev, bf->skbaddr, 1514 common->rx_bufsize, 1515 DMA_FROM_DEVICE); 1516 1517 skb_put(skb, rs.rs_datalen); 1518 1519 ath5k_receive_frame(sc, skb, &rs); 1520 1521 bf->skb = next_skb; 1522 bf->skbaddr = next_skb_addr; 1523 } 1524 next: 1525 list_move_tail(&bf->list, &sc->rxbuf); 1526 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1527 unlock: 1528 spin_unlock(&sc->rxbuflock); 1529 sc->rx_pending = false; 1530 ath5k_set_current_imask(sc); 1531 } 1532 1533 1534 /*************\ 1535 * TX Handling * 1536 \*************/ 1537 1538 void 1539 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1540 struct ath5k_txq *txq) 1541 { 1542 struct ath5k_softc *sc = hw->priv; 1543 struct ath5k_buf *bf; 1544 unsigned long flags; 1545 int padsize; 1546 1547 trace_ath5k_tx(sc, skb, txq); 1548 1549 /* 1550 * The hardware expects the header padded to 4 byte boundaries. 1551 * If this is not the case, we add the padding after the header. 1552 */ 1553 padsize = ath5k_add_padding(skb); 1554 if (padsize < 0) { 1555 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" 1556 " headroom to pad"); 1557 goto drop_packet; 1558 } 1559 1560 if (txq->txq_len >= txq->txq_max) 1561 ieee80211_stop_queue(hw, txq->qnum); 1562 1563 spin_lock_irqsave(&sc->txbuflock, flags); 1564 if (list_empty(&sc->txbuf)) { 1565 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 1566 spin_unlock_irqrestore(&sc->txbuflock, flags); 1567 ieee80211_stop_queues(hw); 1568 goto drop_packet; 1569 } 1570 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 1571 list_del(&bf->list); 1572 sc->txbuf_len--; 1573 if (list_empty(&sc->txbuf)) 1574 ieee80211_stop_queues(hw); 1575 spin_unlock_irqrestore(&sc->txbuflock, flags); 1576 1577 bf->skb = skb; 1578 1579 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { 1580 bf->skb = NULL; 1581 spin_lock_irqsave(&sc->txbuflock, flags); 1582 list_add_tail(&bf->list, &sc->txbuf); 1583 sc->txbuf_len++; 1584 spin_unlock_irqrestore(&sc->txbuflock, flags); 1585 goto drop_packet; 1586 } 1587 return; 1588 1589 drop_packet: 1590 dev_kfree_skb_any(skb); 1591 } 1592 1593 static void 1594 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, 1595 struct ath5k_txq *txq, struct ath5k_tx_status *ts) 1596 { 1597 struct ieee80211_tx_info *info; 1598 u8 tries[3]; 1599 int i; 1600 1601 sc->stats.tx_all_count++; 1602 sc->stats.tx_bytes_count += skb->len; 1603 info = IEEE80211_SKB_CB(skb); 1604 1605 tries[0] = info->status.rates[0].count; 1606 tries[1] = info->status.rates[1].count; 1607 tries[2] = info->status.rates[2].count; 1608 1609 ieee80211_tx_info_clear_status(info); 1610 1611 for (i = 0; i < ts->ts_final_idx; i++) { 1612 struct ieee80211_tx_rate *r = 1613 &info->status.rates[i]; 1614 1615 r->count = tries[i]; 1616 } 1617 1618 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1619 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1620 1621 if (unlikely(ts->ts_status)) { 1622 sc->stats.ack_fail++; 1623 if (ts->ts_status & AR5K_TXERR_FILT) { 1624 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1625 sc->stats.txerr_filt++; 1626 } 1627 if (ts->ts_status & AR5K_TXERR_XRETRY) 1628 sc->stats.txerr_retry++; 1629 if (ts->ts_status & AR5K_TXERR_FIFO) 1630 sc->stats.txerr_fifo++; 1631 } else { 1632 info->flags |= IEEE80211_TX_STAT_ACK; 1633 info->status.ack_signal = ts->ts_rssi; 1634 1635 /* count the successful attempt as well */ 1636 info->status.rates[ts->ts_final_idx].count++; 1637 } 1638 1639 /* 1640 * Remove MAC header padding before giving the frame 1641 * back to mac80211. 1642 */ 1643 ath5k_remove_padding(skb); 1644 1645 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1646 sc->stats.antenna_tx[ts->ts_antenna]++; 1647 else 1648 sc->stats.antenna_tx[0]++; /* invalid */ 1649 1650 trace_ath5k_tx_complete(sc, skb, txq, ts); 1651 ieee80211_tx_status(sc->hw, skb); 1652 } 1653 1654 static void 1655 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1656 { 1657 struct ath5k_tx_status ts = {}; 1658 struct ath5k_buf *bf, *bf0; 1659 struct ath5k_desc *ds; 1660 struct sk_buff *skb; 1661 int ret; 1662 1663 spin_lock(&txq->lock); 1664 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1665 1666 txq->txq_poll_mark = false; 1667 1668 /* skb might already have been processed last time. */ 1669 if (bf->skb != NULL) { 1670 ds = bf->desc; 1671 1672 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1673 if (unlikely(ret == -EINPROGRESS)) 1674 break; 1675 else if (unlikely(ret)) { 1676 ATH5K_ERR(sc, 1677 "error %d while processing " 1678 "queue %u\n", ret, txq->qnum); 1679 break; 1680 } 1681 1682 skb = bf->skb; 1683 bf->skb = NULL; 1684 1685 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, 1686 DMA_TO_DEVICE); 1687 ath5k_tx_frame_completed(sc, skb, txq, &ts); 1688 } 1689 1690 /* 1691 * It's possible that the hardware can say the buffer is 1692 * completed when it hasn't yet loaded the ds_link from 1693 * host memory and moved on. 1694 * Always keep the last descriptor to avoid HW races... 1695 */ 1696 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) { 1697 spin_lock(&sc->txbuflock); 1698 list_move_tail(&bf->list, &sc->txbuf); 1699 sc->txbuf_len++; 1700 txq->txq_len--; 1701 spin_unlock(&sc->txbuflock); 1702 } 1703 } 1704 spin_unlock(&txq->lock); 1705 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1706 ieee80211_wake_queue(sc->hw, txq->qnum); 1707 } 1708 1709 static void 1710 ath5k_tasklet_tx(unsigned long data) 1711 { 1712 int i; 1713 struct ath5k_softc *sc = (void *)data; 1714 1715 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 1716 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 1717 ath5k_tx_processq(sc, &sc->txqs[i]); 1718 1719 sc->tx_pending = false; 1720 ath5k_set_current_imask(sc); 1721 } 1722 1723 1724 /*****************\ 1725 * Beacon handling * 1726 \*****************/ 1727 1728 /* 1729 * Setup the beacon frame for transmit. 1730 */ 1731 static int 1732 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1733 { 1734 struct sk_buff *skb = bf->skb; 1735 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1736 struct ath5k_hw *ah = sc->ah; 1737 struct ath5k_desc *ds; 1738 int ret = 0; 1739 u8 antenna; 1740 u32 flags; 1741 const int padsize = 0; 1742 1743 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 1744 DMA_TO_DEVICE); 1745 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1746 "skbaddr %llx\n", skb, skb->data, skb->len, 1747 (unsigned long long)bf->skbaddr); 1748 1749 if (dma_mapping_error(sc->dev, bf->skbaddr)) { 1750 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 1751 return -EIO; 1752 } 1753 1754 ds = bf->desc; 1755 antenna = ah->ah_tx_ant; 1756 1757 flags = AR5K_TXDESC_NOACK; 1758 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1759 ds->ds_link = bf->daddr; /* self-linked */ 1760 flags |= AR5K_TXDESC_VEOL; 1761 } else 1762 ds->ds_link = 0; 1763 1764 /* 1765 * If we use multiple antennas on AP and use 1766 * the Sectored AP scenario, switch antenna every 1767 * 4 beacons to make sure everybody hears our AP. 1768 * When a client tries to associate, hw will keep 1769 * track of the tx antenna to be used for this client 1770 * automaticaly, based on ACKed packets. 1771 * 1772 * Note: AP still listens and transmits RTS on the 1773 * default antenna which is supposed to be an omni. 1774 * 1775 * Note2: On sectored scenarios it's possible to have 1776 * multiple antennas (1 omni -- the default -- and 14 1777 * sectors), so if we choose to actually support this 1778 * mode, we need to allow the user to set how many antennas 1779 * we have and tweak the code below to send beacons 1780 * on all of them. 1781 */ 1782 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1783 antenna = sc->bsent & 4 ? 2 : 1; 1784 1785 1786 /* FIXME: If we are in g mode and rate is a CCK rate 1787 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1788 * from tx power (value is in dB units already) */ 1789 ds->ds_data = bf->skbaddr; 1790 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1791 ieee80211_get_hdrlen_from_skb(skb), padsize, 1792 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 1793 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 1794 1, AR5K_TXKEYIX_INVALID, 1795 antenna, flags, 0, 0); 1796 if (ret) 1797 goto err_unmap; 1798 1799 return 0; 1800 err_unmap: 1801 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1802 return ret; 1803 } 1804 1805 /* 1806 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1807 * this is called only once at config_bss time, for AP we do it every 1808 * SWBA interrupt so that the TIM will reflect buffered frames. 1809 * 1810 * Called with the beacon lock. 1811 */ 1812 int 1813 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1814 { 1815 int ret; 1816 struct ath5k_softc *sc = hw->priv; 1817 struct ath5k_vif *avf = (void *)vif->drv_priv; 1818 struct sk_buff *skb; 1819 1820 if (WARN_ON(!vif)) { 1821 ret = -EINVAL; 1822 goto out; 1823 } 1824 1825 skb = ieee80211_beacon_get(hw, vif); 1826 1827 if (!skb) { 1828 ret = -ENOMEM; 1829 goto out; 1830 } 1831 1832 ath5k_txbuf_free_skb(sc, avf->bbuf); 1833 avf->bbuf->skb = skb; 1834 ret = ath5k_beacon_setup(sc, avf->bbuf); 1835 if (ret) 1836 avf->bbuf->skb = NULL; 1837 out: 1838 return ret; 1839 } 1840 1841 /* 1842 * Transmit a beacon frame at SWBA. Dynamic updates to the 1843 * frame contents are done as needed and the slot time is 1844 * also adjusted based on current state. 1845 * 1846 * This is called from software irq context (beacontq tasklets) 1847 * or user context from ath5k_beacon_config. 1848 */ 1849 static void 1850 ath5k_beacon_send(struct ath5k_softc *sc) 1851 { 1852 struct ath5k_hw *ah = sc->ah; 1853 struct ieee80211_vif *vif; 1854 struct ath5k_vif *avf; 1855 struct ath5k_buf *bf; 1856 struct sk_buff *skb; 1857 1858 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1859 1860 /* 1861 * Check if the previous beacon has gone out. If 1862 * not, don't don't try to post another: skip this 1863 * period and wait for the next. Missed beacons 1864 * indicate a problem and should not occur. If we 1865 * miss too many consecutive beacons reset the device. 1866 */ 1867 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 1868 sc->bmisscount++; 1869 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1870 "missed %u consecutive beacons\n", sc->bmisscount); 1871 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 1872 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1873 "stuck beacon time (%u missed)\n", 1874 sc->bmisscount); 1875 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 1876 "stuck beacon, resetting\n"); 1877 ieee80211_queue_work(sc->hw, &sc->reset_work); 1878 } 1879 return; 1880 } 1881 if (unlikely(sc->bmisscount != 0)) { 1882 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1883 "resume beacon xmit after %u misses\n", 1884 sc->bmisscount); 1885 sc->bmisscount = 0; 1886 } 1887 1888 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) || 1889 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1890 u64 tsf = ath5k_hw_get_tsf64(ah); 1891 u32 tsftu = TSF_TO_TU(tsf); 1892 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; 1893 vif = sc->bslot[(slot + 1) % ATH_BCBUF]; 1894 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1895 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1896 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif); 1897 } else /* only one interface */ 1898 vif = sc->bslot[0]; 1899 1900 if (!vif) 1901 return; 1902 1903 avf = (void *)vif->drv_priv; 1904 bf = avf->bbuf; 1905 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 1906 sc->opmode == NL80211_IFTYPE_MONITOR)) { 1907 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 1908 return; 1909 } 1910 1911 /* 1912 * Stop any current dma and put the new frame on the queue. 1913 * This should never fail since we check above that no frames 1914 * are still pending on the queue. 1915 */ 1916 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) { 1917 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 1918 /* NB: hw still stops DMA, so proceed */ 1919 } 1920 1921 /* refresh the beacon for AP or MESH mode */ 1922 if (sc->opmode == NL80211_IFTYPE_AP || 1923 sc->opmode == NL80211_IFTYPE_MESH_POINT) 1924 ath5k_beacon_update(sc->hw, vif); 1925 1926 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]); 1927 1928 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 1929 ath5k_hw_start_tx_dma(ah, sc->bhalq); 1930 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1931 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 1932 1933 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1934 while (skb) { 1935 ath5k_tx_queue(sc->hw, skb, sc->cabq); 1936 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1937 } 1938 1939 sc->bsent++; 1940 } 1941 1942 /** 1943 * ath5k_beacon_update_timers - update beacon timers 1944 * 1945 * @sc: struct ath5k_softc pointer we are operating on 1946 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1947 * beacon timer update based on the current HW TSF. 1948 * 1949 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 1950 * of a received beacon or the current local hardware TSF and write it to the 1951 * beacon timer registers. 1952 * 1953 * This is called in a variety of situations, e.g. when a beacon is received, 1954 * when a TSF update has been detected, but also when an new IBSS is created or 1955 * when we otherwise know we have to update the timers, but we keep it in this 1956 * function to have it all together in one place. 1957 */ 1958 void 1959 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 1960 { 1961 struct ath5k_hw *ah = sc->ah; 1962 u32 nexttbtt, intval, hw_tu, bc_tu; 1963 u64 hw_tsf; 1964 1965 intval = sc->bintval & AR5K_BEACON_PERIOD; 1966 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { 1967 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 1968 if (intval < 15) 1969 ATH5K_WARN(sc, "intval %u is too low, min 15\n", 1970 intval); 1971 } 1972 if (WARN_ON(!intval)) 1973 return; 1974 1975 /* beacon TSF converted to TU */ 1976 bc_tu = TSF_TO_TU(bc_tsf); 1977 1978 /* current TSF converted to TU */ 1979 hw_tsf = ath5k_hw_get_tsf64(ah); 1980 hw_tu = TSF_TO_TU(hw_tsf); 1981 1982 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3 1983 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 1984 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 1985 * configuration we need to make sure it is bigger than that. */ 1986 1987 if (bc_tsf == -1) { 1988 /* 1989 * no beacons received, called internally. 1990 * just need to refresh timers based on HW TSF. 1991 */ 1992 nexttbtt = roundup(hw_tu + FUDGE, intval); 1993 } else if (bc_tsf == 0) { 1994 /* 1995 * no beacon received, probably called by ath5k_reset_tsf(). 1996 * reset TSF to start with 0. 1997 */ 1998 nexttbtt = intval; 1999 intval |= AR5K_BEACON_RESET_TSF; 2000 } else if (bc_tsf > hw_tsf) { 2001 /* 2002 * beacon received, SW merge happened but HW TSF not yet updated. 2003 * not possible to reconfigure timers yet, but next time we 2004 * receive a beacon with the same BSSID, the hardware will 2005 * automatically update the TSF and then we need to reconfigure 2006 * the timers. 2007 */ 2008 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2009 "need to wait for HW TSF sync\n"); 2010 return; 2011 } else { 2012 /* 2013 * most important case for beacon synchronization between STA. 2014 * 2015 * beacon received and HW TSF has been already updated by HW. 2016 * update next TBTT based on the TSF of the beacon, but make 2017 * sure it is ahead of our local TSF timer. 2018 */ 2019 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2020 } 2021 #undef FUDGE 2022 2023 sc->nexttbtt = nexttbtt; 2024 2025 intval |= AR5K_BEACON_ENA; 2026 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2027 2028 /* 2029 * debugging output last in order to preserve the time critical aspect 2030 * of this function 2031 */ 2032 if (bc_tsf == -1) 2033 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2034 "reconfigured timers based on HW TSF\n"); 2035 else if (bc_tsf == 0) 2036 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2037 "reset HW TSF and timers\n"); 2038 else 2039 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2040 "updated timers based on beacon TSF\n"); 2041 2042 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2043 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2044 (unsigned long long) bc_tsf, 2045 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2046 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2047 intval & AR5K_BEACON_PERIOD, 2048 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2049 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2050 } 2051 2052 /** 2053 * ath5k_beacon_config - Configure the beacon queues and interrupts 2054 * 2055 * @sc: struct ath5k_softc pointer we are operating on 2056 * 2057 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2058 * interrupts to detect TSF updates only. 2059 */ 2060 void 2061 ath5k_beacon_config(struct ath5k_softc *sc) 2062 { 2063 struct ath5k_hw *ah = sc->ah; 2064 unsigned long flags; 2065 2066 spin_lock_irqsave(&sc->block, flags); 2067 sc->bmisscount = 0; 2068 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2069 2070 if (sc->enable_beacon) { 2071 /* 2072 * In IBSS mode we use a self-linked tx descriptor and let the 2073 * hardware send the beacons automatically. We have to load it 2074 * only once here. 2075 * We use the SWBA interrupt only to keep track of the beacon 2076 * timers in order to detect automatic TSF updates. 2077 */ 2078 ath5k_beaconq_config(sc); 2079 2080 sc->imask |= AR5K_INT_SWBA; 2081 2082 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2083 if (ath5k_hw_hasveol(ah)) 2084 ath5k_beacon_send(sc); 2085 } else 2086 ath5k_beacon_update_timers(sc, -1); 2087 } else { 2088 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq); 2089 } 2090 2091 ath5k_hw_set_imr(ah, sc->imask); 2092 mmiowb(); 2093 spin_unlock_irqrestore(&sc->block, flags); 2094 } 2095 2096 static void ath5k_tasklet_beacon(unsigned long data) 2097 { 2098 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2099 2100 /* 2101 * Software beacon alert--time to send a beacon. 2102 * 2103 * In IBSS mode we use this interrupt just to 2104 * keep track of the next TBTT (target beacon 2105 * transmission time) in order to detect wether 2106 * automatic TSF updates happened. 2107 */ 2108 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2109 /* XXX: only if VEOL suppported */ 2110 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2111 sc->nexttbtt += sc->bintval; 2112 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2113 "SWBA nexttbtt: %x hw_tu: %x " 2114 "TSF: %llx\n", 2115 sc->nexttbtt, 2116 TSF_TO_TU(tsf), 2117 (unsigned long long) tsf); 2118 } else { 2119 spin_lock(&sc->block); 2120 ath5k_beacon_send(sc); 2121 spin_unlock(&sc->block); 2122 } 2123 } 2124 2125 2126 /********************\ 2127 * Interrupt handling * 2128 \********************/ 2129 2130 static void 2131 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2132 { 2133 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2134 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) { 2135 /* run ANI only when full calibration is not active */ 2136 ah->ah_cal_next_ani = jiffies + 2137 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2138 tasklet_schedule(&ah->ah_sc->ani_tasklet); 2139 2140 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2141 ah->ah_cal_next_full = jiffies + 2142 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2143 tasklet_schedule(&ah->ah_sc->calib); 2144 } 2145 /* we could use SWI to generate enough interrupts to meet our 2146 * calibration interval requirements, if necessary: 2147 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2148 } 2149 2150 static void 2151 ath5k_schedule_rx(struct ath5k_softc *sc) 2152 { 2153 sc->rx_pending = true; 2154 tasklet_schedule(&sc->rxtq); 2155 } 2156 2157 static void 2158 ath5k_schedule_tx(struct ath5k_softc *sc) 2159 { 2160 sc->tx_pending = true; 2161 tasklet_schedule(&sc->txtq); 2162 } 2163 2164 irqreturn_t 2165 ath5k_intr(int irq, void *dev_id) 2166 { 2167 struct ath5k_softc *sc = dev_id; 2168 struct ath5k_hw *ah = sc->ah; 2169 enum ath5k_int status; 2170 unsigned int counter = 1000; 2171 2172 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2173 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2174 !ath5k_hw_is_intr_pending(ah)))) 2175 return IRQ_NONE; 2176 2177 do { 2178 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2179 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2180 status, sc->imask); 2181 if (unlikely(status & AR5K_INT_FATAL)) { 2182 /* 2183 * Fatal errors are unrecoverable. 2184 * Typically these are caused by DMA errors. 2185 */ 2186 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2187 "fatal int, resetting\n"); 2188 ieee80211_queue_work(sc->hw, &sc->reset_work); 2189 } else if (unlikely(status & AR5K_INT_RXORN)) { 2190 /* 2191 * Receive buffers are full. Either the bus is busy or 2192 * the CPU is not fast enough to process all received 2193 * frames. 2194 * Older chipsets need a reset to come out of this 2195 * condition, but we treat it as RX for newer chips. 2196 * We don't know exactly which versions need a reset - 2197 * this guess is copied from the HAL. 2198 */ 2199 sc->stats.rxorn_intr++; 2200 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2201 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2202 "rx overrun, resetting\n"); 2203 ieee80211_queue_work(sc->hw, &sc->reset_work); 2204 } 2205 else 2206 ath5k_schedule_rx(sc); 2207 } else { 2208 if (status & AR5K_INT_SWBA) { 2209 tasklet_hi_schedule(&sc->beacontq); 2210 } 2211 if (status & AR5K_INT_RXEOL) { 2212 /* 2213 * NB: the hardware should re-read the link when 2214 * RXE bit is written, but it doesn't work at 2215 * least on older hardware revs. 2216 */ 2217 sc->stats.rxeol_intr++; 2218 } 2219 if (status & AR5K_INT_TXURN) { 2220 /* bump tx trigger level */ 2221 ath5k_hw_update_tx_triglevel(ah, true); 2222 } 2223 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2224 ath5k_schedule_rx(sc); 2225 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2226 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2227 ath5k_schedule_tx(sc); 2228 if (status & AR5K_INT_BMISS) { 2229 /* TODO */ 2230 } 2231 if (status & AR5K_INT_MIB) { 2232 sc->stats.mib_intr++; 2233 ath5k_hw_update_mib_counters(ah); 2234 ath5k_ani_mib_intr(ah); 2235 } 2236 if (status & AR5K_INT_GPIO) 2237 tasklet_schedule(&sc->rf_kill.toggleq); 2238 2239 } 2240 2241 if (ath5k_get_bus_type(ah) == ATH_AHB) 2242 break; 2243 2244 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2245 2246 if (sc->rx_pending || sc->tx_pending) 2247 ath5k_set_current_imask(sc); 2248 2249 if (unlikely(!counter)) 2250 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2251 2252 ath5k_intr_calibration_poll(ah); 2253 2254 return IRQ_HANDLED; 2255 } 2256 2257 /* 2258 * Periodically recalibrate the PHY to account 2259 * for temperature/environment changes. 2260 */ 2261 static void 2262 ath5k_tasklet_calibrate(unsigned long data) 2263 { 2264 struct ath5k_softc *sc = (void *)data; 2265 struct ath5k_hw *ah = sc->ah; 2266 2267 /* Only full calibration for now */ 2268 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2269 2270 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2271 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2272 sc->curchan->hw_value); 2273 2274 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2275 /* 2276 * Rfgain is out of bounds, reset the chip 2277 * to load new gain values. 2278 */ 2279 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2280 ieee80211_queue_work(sc->hw, &sc->reset_work); 2281 } 2282 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2283 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2284 ieee80211_frequency_to_channel( 2285 sc->curchan->center_freq)); 2286 2287 /* Noise floor calibration interrupts rx/tx path while I/Q calibration 2288 * doesn't. 2289 * TODO: We should stop TX here, so that it doesn't interfere. 2290 * Note that stopping the queues is not enough to stop TX! */ 2291 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) { 2292 ah->ah_cal_next_nf = jiffies + 2293 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF); 2294 ath5k_hw_update_noise_floor(ah); 2295 } 2296 2297 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2298 } 2299 2300 2301 static void 2302 ath5k_tasklet_ani(unsigned long data) 2303 { 2304 struct ath5k_softc *sc = (void *)data; 2305 struct ath5k_hw *ah = sc->ah; 2306 2307 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2308 ath5k_ani_calibration(ah); 2309 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2310 } 2311 2312 2313 static void 2314 ath5k_tx_complete_poll_work(struct work_struct *work) 2315 { 2316 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2317 tx_complete_work.work); 2318 struct ath5k_txq *txq; 2319 int i; 2320 bool needreset = false; 2321 2322 mutex_lock(&sc->lock); 2323 2324 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 2325 if (sc->txqs[i].setup) { 2326 txq = &sc->txqs[i]; 2327 spin_lock_bh(&txq->lock); 2328 if (txq->txq_len > 1) { 2329 if (txq->txq_poll_mark) { 2330 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, 2331 "TX queue stuck %d\n", 2332 txq->qnum); 2333 needreset = true; 2334 txq->txq_stuck++; 2335 spin_unlock_bh(&txq->lock); 2336 break; 2337 } else { 2338 txq->txq_poll_mark = true; 2339 } 2340 } 2341 spin_unlock_bh(&txq->lock); 2342 } 2343 } 2344 2345 if (needreset) { 2346 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2347 "TX queues stuck, resetting\n"); 2348 ath5k_reset(sc, NULL, true); 2349 } 2350 2351 mutex_unlock(&sc->lock); 2352 2353 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2354 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2355 } 2356 2357 2358 /*************************\ 2359 * Initialization routines * 2360 \*************************/ 2361 2362 int 2363 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) 2364 { 2365 struct ieee80211_hw *hw = sc->hw; 2366 struct ath_common *common; 2367 int ret; 2368 int csz; 2369 2370 /* Initialize driver private data */ 2371 SET_IEEE80211_DEV(hw, sc->dev); 2372 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2373 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2374 IEEE80211_HW_SIGNAL_DBM | 2375 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 2376 2377 hw->wiphy->interface_modes = 2378 BIT(NL80211_IFTYPE_AP) | 2379 BIT(NL80211_IFTYPE_STATION) | 2380 BIT(NL80211_IFTYPE_ADHOC) | 2381 BIT(NL80211_IFTYPE_MESH_POINT); 2382 2383 /* both antennas can be configured as RX or TX */ 2384 hw->wiphy->available_antennas_tx = 0x3; 2385 hw->wiphy->available_antennas_rx = 0x3; 2386 2387 hw->extra_tx_headroom = 2; 2388 hw->channel_change_time = 5000; 2389 2390 /* 2391 * Mark the device as detached to avoid processing 2392 * interrupts until setup is complete. 2393 */ 2394 __set_bit(ATH_STAT_INVALID, sc->status); 2395 2396 sc->opmode = NL80211_IFTYPE_STATION; 2397 sc->bintval = 1000; 2398 mutex_init(&sc->lock); 2399 spin_lock_init(&sc->rxbuflock); 2400 spin_lock_init(&sc->txbuflock); 2401 spin_lock_init(&sc->block); 2402 spin_lock_init(&sc->irqlock); 2403 2404 /* Setup interrupt handler */ 2405 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 2406 if (ret) { 2407 ATH5K_ERR(sc, "request_irq failed\n"); 2408 goto err; 2409 } 2410 2411 /* If we passed the test, malloc an ath5k_hw struct */ 2412 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); 2413 if (!sc->ah) { 2414 ret = -ENOMEM; 2415 ATH5K_ERR(sc, "out of memory\n"); 2416 goto err_irq; 2417 } 2418 2419 sc->ah->ah_sc = sc; 2420 sc->ah->ah_iobase = sc->iobase; 2421 common = ath5k_hw_common(sc->ah); 2422 common->ops = &ath5k_common_ops; 2423 common->bus_ops = bus_ops; 2424 common->ah = sc->ah; 2425 common->hw = hw; 2426 common->priv = sc; 2427 2428 /* 2429 * Cache line size is used to size and align various 2430 * structures used to communicate with the hardware. 2431 */ 2432 ath5k_read_cachesize(common, &csz); 2433 common->cachelsz = csz << 2; /* convert to bytes */ 2434 2435 spin_lock_init(&common->cc_lock); 2436 2437 /* Initialize device */ 2438 ret = ath5k_hw_init(sc); 2439 if (ret) 2440 goto err_free_ah; 2441 2442 /* set up multi-rate retry capabilities */ 2443 if (sc->ah->ah_version == AR5K_AR5212) { 2444 hw->max_rates = 4; 2445 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2446 AR5K_INIT_RETRY_LONG); 2447 } 2448 2449 hw->vif_data_size = sizeof(struct ath5k_vif); 2450 2451 /* Finish private driver data initialization */ 2452 ret = ath5k_init(hw); 2453 if (ret) 2454 goto err_ah; 2455 2456 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2457 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 2458 sc->ah->ah_mac_srev, 2459 sc->ah->ah_phy_revision); 2460 2461 if (!sc->ah->ah_single_chip) { 2462 /* Single chip radio (!RF5111) */ 2463 if (sc->ah->ah_radio_5ghz_revision && 2464 !sc->ah->ah_radio_2ghz_revision) { 2465 /* No 5GHz support -> report 2GHz radio */ 2466 if (!test_bit(AR5K_MODE_11A, 2467 sc->ah->ah_capabilities.cap_mode)) { 2468 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2469 ath5k_chip_name(AR5K_VERSION_RAD, 2470 sc->ah->ah_radio_5ghz_revision), 2471 sc->ah->ah_radio_5ghz_revision); 2472 /* No 2GHz support (5110 and some 2473 * 5Ghz only cards) -> report 5Ghz radio */ 2474 } else if (!test_bit(AR5K_MODE_11B, 2475 sc->ah->ah_capabilities.cap_mode)) { 2476 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2477 ath5k_chip_name(AR5K_VERSION_RAD, 2478 sc->ah->ah_radio_5ghz_revision), 2479 sc->ah->ah_radio_5ghz_revision); 2480 /* Multiband radio */ 2481 } else { 2482 ATH5K_INFO(sc, "RF%s multiband radio found" 2483 " (0x%x)\n", 2484 ath5k_chip_name(AR5K_VERSION_RAD, 2485 sc->ah->ah_radio_5ghz_revision), 2486 sc->ah->ah_radio_5ghz_revision); 2487 } 2488 } 2489 /* Multi chip radio (RF5111 - RF2111) -> 2490 * report both 2GHz/5GHz radios */ 2491 else if (sc->ah->ah_radio_5ghz_revision && 2492 sc->ah->ah_radio_2ghz_revision){ 2493 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2494 ath5k_chip_name(AR5K_VERSION_RAD, 2495 sc->ah->ah_radio_5ghz_revision), 2496 sc->ah->ah_radio_5ghz_revision); 2497 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2498 ath5k_chip_name(AR5K_VERSION_RAD, 2499 sc->ah->ah_radio_2ghz_revision), 2500 sc->ah->ah_radio_2ghz_revision); 2501 } 2502 } 2503 2504 ath5k_debug_init_device(sc); 2505 2506 /* ready to process interrupts */ 2507 __clear_bit(ATH_STAT_INVALID, sc->status); 2508 2509 return 0; 2510 err_ah: 2511 ath5k_hw_deinit(sc->ah); 2512 err_free_ah: 2513 kfree(sc->ah); 2514 err_irq: 2515 free_irq(sc->irq, sc); 2516 err: 2517 return ret; 2518 } 2519 2520 static int 2521 ath5k_stop_locked(struct ath5k_softc *sc) 2522 { 2523 struct ath5k_hw *ah = sc->ah; 2524 2525 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2526 test_bit(ATH_STAT_INVALID, sc->status)); 2527 2528 /* 2529 * Shutdown the hardware and driver: 2530 * stop output from above 2531 * disable interrupts 2532 * turn off timers 2533 * turn off the radio 2534 * clear transmit machinery 2535 * clear receive machinery 2536 * drain and release tx queues 2537 * reclaim beacon resources 2538 * power down hardware 2539 * 2540 * Note that some of this work is not possible if the 2541 * hardware is gone (invalid). 2542 */ 2543 ieee80211_stop_queues(sc->hw); 2544 2545 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2546 ath5k_led_off(sc); 2547 ath5k_hw_set_imr(ah, 0); 2548 synchronize_irq(sc->irq); 2549 ath5k_rx_stop(sc); 2550 ath5k_hw_dma_stop(ah); 2551 ath5k_drain_tx_buffs(sc); 2552 ath5k_hw_phy_disable(ah); 2553 } 2554 2555 return 0; 2556 } 2557 2558 int 2559 ath5k_init_hw(struct ath5k_softc *sc) 2560 { 2561 struct ath5k_hw *ah = sc->ah; 2562 struct ath_common *common = ath5k_hw_common(ah); 2563 int ret, i; 2564 2565 mutex_lock(&sc->lock); 2566 2567 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2568 2569 /* 2570 * Stop anything previously setup. This is safe 2571 * no matter this is the first time through or not. 2572 */ 2573 ath5k_stop_locked(sc); 2574 2575 /* 2576 * The basic interface to setting the hardware in a good 2577 * state is ``reset''. On return the hardware is known to 2578 * be powered up and with interrupts disabled. This must 2579 * be followed by initialization of the appropriate bits 2580 * and then setup of the interrupt mask. 2581 */ 2582 sc->curchan = sc->hw->conf.channel; 2583 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2584 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2585 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; 2586 2587 ret = ath5k_reset(sc, NULL, false); 2588 if (ret) 2589 goto done; 2590 2591 ath5k_rfkill_hw_start(ah); 2592 2593 /* 2594 * Reset the key cache since some parts do not reset the 2595 * contents on initial power up or resume from suspend. 2596 */ 2597 for (i = 0; i < common->keymax; i++) 2598 ath_hw_keyreset(common, (u16) i); 2599 2600 /* Use higher rates for acks instead of base 2601 * rate */ 2602 ah->ah_ack_bitrate_high = true; 2603 2604 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++) 2605 sc->bslot[i] = NULL; 2606 2607 ret = 0; 2608 done: 2609 mmiowb(); 2610 mutex_unlock(&sc->lock); 2611 2612 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2613 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2614 2615 return ret; 2616 } 2617 2618 static void stop_tasklets(struct ath5k_softc *sc) 2619 { 2620 sc->rx_pending = false; 2621 sc->tx_pending = false; 2622 tasklet_kill(&sc->rxtq); 2623 tasklet_kill(&sc->txtq); 2624 tasklet_kill(&sc->calib); 2625 tasklet_kill(&sc->beacontq); 2626 tasklet_kill(&sc->ani_tasklet); 2627 } 2628 2629 /* 2630 * Stop the device, grabbing the top-level lock to protect 2631 * against concurrent entry through ath5k_init (which can happen 2632 * if another thread does a system call and the thread doing the 2633 * stop is preempted). 2634 */ 2635 int 2636 ath5k_stop_hw(struct ath5k_softc *sc) 2637 { 2638 int ret; 2639 2640 mutex_lock(&sc->lock); 2641 ret = ath5k_stop_locked(sc); 2642 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2643 /* 2644 * Don't set the card in full sleep mode! 2645 * 2646 * a) When the device is in this state it must be carefully 2647 * woken up or references to registers in the PCI clock 2648 * domain may freeze the bus (and system). This varies 2649 * by chip and is mostly an issue with newer parts 2650 * (madwifi sources mentioned srev >= 0x78) that go to 2651 * sleep more quickly. 2652 * 2653 * b) On older chips full sleep results a weird behaviour 2654 * during wakeup. I tested various cards with srev < 0x78 2655 * and they don't wake up after module reload, a second 2656 * module reload is needed to bring the card up again. 2657 * 2658 * Until we figure out what's going on don't enable 2659 * full chip reset on any chip (this is what Legacy HAL 2660 * and Sam's HAL do anyway). Instead Perform a full reset 2661 * on the device (same as initial state after attach) and 2662 * leave it idle (keep MAC/BB on warm reset) */ 2663 ret = ath5k_hw_on_hold(sc->ah); 2664 2665 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2666 "putting device to sleep\n"); 2667 } 2668 2669 mmiowb(); 2670 mutex_unlock(&sc->lock); 2671 2672 stop_tasklets(sc); 2673 2674 cancel_delayed_work_sync(&sc->tx_complete_work); 2675 2676 ath5k_rfkill_hw_stop(sc->ah); 2677 2678 return ret; 2679 } 2680 2681 /* 2682 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2683 * and change to the given channel. 2684 * 2685 * This should be called with sc->lock. 2686 */ 2687 static int 2688 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 2689 bool skip_pcu) 2690 { 2691 struct ath5k_hw *ah = sc->ah; 2692 struct ath_common *common = ath5k_hw_common(ah); 2693 int ret, ani_mode; 2694 bool fast; 2695 2696 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2697 2698 ath5k_hw_set_imr(ah, 0); 2699 synchronize_irq(sc->irq); 2700 stop_tasklets(sc); 2701 2702 /* Save ani mode and disable ANI during 2703 * reset. If we don't we might get false 2704 * PHY error interrupts. */ 2705 ani_mode = ah->ah_sc->ani_state.ani_mode; 2706 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2707 2708 /* We are going to empty hw queues 2709 * so we should also free any remaining 2710 * tx buffers */ 2711 ath5k_drain_tx_buffs(sc); 2712 if (chan) 2713 sc->curchan = chan; 2714 2715 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2716 2717 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, 2718 skip_pcu); 2719 if (ret) { 2720 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2721 goto err; 2722 } 2723 2724 ret = ath5k_rx_start(sc); 2725 if (ret) { 2726 ATH5K_ERR(sc, "can't start recv logic\n"); 2727 goto err; 2728 } 2729 2730 ath5k_ani_init(ah, ani_mode); 2731 2732 ah->ah_cal_next_full = jiffies; 2733 ah->ah_cal_next_ani = jiffies; 2734 ah->ah_cal_next_nf = jiffies; 2735 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2736 2737 /* clear survey data and cycle counters */ 2738 memset(&sc->survey, 0, sizeof(sc->survey)); 2739 spin_lock_bh(&common->cc_lock); 2740 ath_hw_cycle_counters_update(common); 2741 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2742 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2743 spin_unlock_bh(&common->cc_lock); 2744 2745 /* 2746 * Change channels and update the h/w rate map if we're switching; 2747 * e.g. 11a to 11b/g. 2748 * 2749 * We may be doing a reset in response to an ioctl that changes the 2750 * channel so update any state that might change as a result. 2751 * 2752 * XXX needed? 2753 */ 2754 /* ath5k_chan_change(sc, c); */ 2755 2756 ath5k_beacon_config(sc); 2757 /* intrs are enabled by ath5k_beacon_config */ 2758 2759 ieee80211_wake_queues(sc->hw); 2760 2761 return 0; 2762 err: 2763 return ret; 2764 } 2765 2766 static void ath5k_reset_work(struct work_struct *work) 2767 { 2768 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2769 reset_work); 2770 2771 mutex_lock(&sc->lock); 2772 ath5k_reset(sc, NULL, true); 2773 mutex_unlock(&sc->lock); 2774 } 2775 2776 static int 2777 ath5k_init(struct ieee80211_hw *hw) 2778 { 2779 2780 struct ath5k_softc *sc = hw->priv; 2781 struct ath5k_hw *ah = sc->ah; 2782 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2783 struct ath5k_txq *txq; 2784 u8 mac[ETH_ALEN] = {}; 2785 int ret; 2786 2787 2788 /* 2789 * Check if the MAC has multi-rate retry support. 2790 * We do this by trying to setup a fake extended 2791 * descriptor. MACs that don't have support will 2792 * return false w/o doing anything. MACs that do 2793 * support it will return true w/o doing anything. 2794 */ 2795 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 2796 2797 if (ret < 0) 2798 goto err; 2799 if (ret > 0) 2800 __set_bit(ATH_STAT_MRRETRY, sc->status); 2801 2802 /* 2803 * Collect the channel list. The 802.11 layer 2804 * is resposible for filtering this list based 2805 * on settings like the phy mode and regulatory 2806 * domain restrictions. 2807 */ 2808 ret = ath5k_setup_bands(hw); 2809 if (ret) { 2810 ATH5K_ERR(sc, "can't get channels\n"); 2811 goto err; 2812 } 2813 2814 /* 2815 * Allocate tx+rx descriptors and populate the lists. 2816 */ 2817 ret = ath5k_desc_alloc(sc); 2818 if (ret) { 2819 ATH5K_ERR(sc, "can't allocate descriptors\n"); 2820 goto err; 2821 } 2822 2823 /* 2824 * Allocate hardware transmit queues: one queue for 2825 * beacon frames and one data queue for each QoS 2826 * priority. Note that hw functions handle resetting 2827 * these queues at the needed time. 2828 */ 2829 ret = ath5k_beaconq_setup(ah); 2830 if (ret < 0) { 2831 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 2832 goto err_desc; 2833 } 2834 sc->bhalq = ret; 2835 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 2836 if (IS_ERR(sc->cabq)) { 2837 ATH5K_ERR(sc, "can't setup cab queue\n"); 2838 ret = PTR_ERR(sc->cabq); 2839 goto err_bhal; 2840 } 2841 2842 /* 5211 and 5212 usually support 10 queues but we better rely on the 2843 * capability information */ 2844 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2845 /* This order matches mac80211's queue priority, so we can 2846 * directly use the mac80211 queue number without any mapping */ 2847 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2848 if (IS_ERR(txq)) { 2849 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2850 ret = PTR_ERR(txq); 2851 goto err_queues; 2852 } 2853 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2854 if (IS_ERR(txq)) { 2855 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2856 ret = PTR_ERR(txq); 2857 goto err_queues; 2858 } 2859 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2860 if (IS_ERR(txq)) { 2861 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2862 ret = PTR_ERR(txq); 2863 goto err_queues; 2864 } 2865 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2866 if (IS_ERR(txq)) { 2867 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2868 ret = PTR_ERR(txq); 2869 goto err_queues; 2870 } 2871 hw->queues = 4; 2872 } else { 2873 /* older hardware (5210) can only support one data queue */ 2874 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2875 if (IS_ERR(txq)) { 2876 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2877 ret = PTR_ERR(txq); 2878 goto err_queues; 2879 } 2880 hw->queues = 1; 2881 } 2882 2883 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 2884 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 2885 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 2886 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 2887 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); 2888 2889 INIT_WORK(&sc->reset_work, ath5k_reset_work); 2890 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work); 2891 2892 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 2893 if (ret) { 2894 ATH5K_ERR(sc, "unable to read address from EEPROM\n"); 2895 goto err_queues; 2896 } 2897 2898 SET_IEEE80211_PERM_ADDR(hw, mac); 2899 memcpy(&sc->lladdr, mac, ETH_ALEN); 2900 /* All MAC address bits matter for ACKs */ 2901 ath5k_update_bssid_mask_and_opmode(sc, NULL); 2902 2903 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 2904 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 2905 if (ret) { 2906 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 2907 goto err_queues; 2908 } 2909 2910 ret = ieee80211_register_hw(hw); 2911 if (ret) { 2912 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 2913 goto err_queues; 2914 } 2915 2916 if (!ath_is_world_regd(regulatory)) 2917 regulatory_hint(hw->wiphy, regulatory->alpha2); 2918 2919 ath5k_init_leds(sc); 2920 2921 ath5k_sysfs_register(sc); 2922 2923 return 0; 2924 err_queues: 2925 ath5k_txq_release(sc); 2926 err_bhal: 2927 ath5k_hw_release_tx_queue(ah, sc->bhalq); 2928 err_desc: 2929 ath5k_desc_free(sc); 2930 err: 2931 return ret; 2932 } 2933 2934 void 2935 ath5k_deinit_softc(struct ath5k_softc *sc) 2936 { 2937 struct ieee80211_hw *hw = sc->hw; 2938 2939 /* 2940 * NB: the order of these is important: 2941 * o call the 802.11 layer before detaching ath5k_hw to 2942 * ensure callbacks into the driver to delete global 2943 * key cache entries can be handled 2944 * o reclaim the tx queue data structures after calling 2945 * the 802.11 layer as we'll get called back to reclaim 2946 * node state and potentially want to use them 2947 * o to cleanup the tx queues the hal is called, so detach 2948 * it last 2949 * XXX: ??? detach ath5k_hw ??? 2950 * Other than that, it's straightforward... 2951 */ 2952 ieee80211_unregister_hw(hw); 2953 ath5k_desc_free(sc); 2954 ath5k_txq_release(sc); 2955 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 2956 ath5k_unregister_leds(sc); 2957 2958 ath5k_sysfs_unregister(sc); 2959 /* 2960 * NB: can't reclaim these until after ieee80211_ifdetach 2961 * returns because we'll get called back to reclaim node 2962 * state and potentially want to use them. 2963 */ 2964 ath5k_hw_deinit(sc->ah); 2965 free_irq(sc->irq, sc); 2966 } 2967 2968 bool 2969 ath_any_vif_assoc(struct ath5k_softc *sc) 2970 { 2971 struct ath5k_vif_iter_data iter_data; 2972 iter_data.hw_macaddr = NULL; 2973 iter_data.any_assoc = false; 2974 iter_data.need_set_hw_addr = false; 2975 iter_data.found_active = true; 2976 2977 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 2978 &iter_data); 2979 return iter_data.any_assoc; 2980 } 2981 2982 void 2983 set_beacon_filter(struct ieee80211_hw *hw, bool enable) 2984 { 2985 struct ath5k_softc *sc = hw->priv; 2986 struct ath5k_hw *ah = sc->ah; 2987 u32 rfilt; 2988 rfilt = ath5k_hw_get_rx_filter(ah); 2989 if (enable) 2990 rfilt |= AR5K_RX_FILTER_BEACON; 2991 else 2992 rfilt &= ~AR5K_RX_FILTER_BEACON; 2993 ath5k_hw_set_rx_filter(ah, rfilt); 2994 sc->filter_flags = rfilt; 2995 } 2996