1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/hardirq.h> 46 #include <linux/if.h> 47 #include <linux/io.h> 48 #include <linux/netdevice.h> 49 #include <linux/cache.h> 50 #include <linux/pci.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 54 #include <net/ieee80211_radiotap.h> 55 56 #include <asm/unaligned.h> 57 58 #include "base.h" 59 #include "reg.h" 60 #include "debug.h" 61 62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */ 63 static int modparam_nohwcrypt; 64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 66 67 static int modparam_all_channels; 68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 70 71 72 /******************\ 73 * Internal defines * 74 \******************/ 75 76 /* Module info */ 77 MODULE_AUTHOR("Jiri Slaby"); 78 MODULE_AUTHOR("Nick Kossifidis"); 79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 81 MODULE_LICENSE("Dual BSD/GPL"); 82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)"); 83 84 85 /* Known PCI ids */ 86 static const struct pci_device_id ath5k_pci_id_table[] = { 87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ 96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ 97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ 98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ 99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ 100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ 101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 105 { 0 } 106 }; 107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 108 109 /* Known SREVs */ 110 static const struct ath5k_srev_name srev_names[] = { 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 147 }; 148 149 static const struct ieee80211_rate ath5k_rates[] = { 150 { .bitrate = 10, 151 .hw_value = ATH5K_RATE_CODE_1M, }, 152 { .bitrate = 20, 153 .hw_value = ATH5K_RATE_CODE_2M, 154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 155 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 156 { .bitrate = 55, 157 .hw_value = ATH5K_RATE_CODE_5_5M, 158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 159 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 160 { .bitrate = 110, 161 .hw_value = ATH5K_RATE_CODE_11M, 162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 163 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 164 { .bitrate = 60, 165 .hw_value = ATH5K_RATE_CODE_6M, 166 .flags = 0 }, 167 { .bitrate = 90, 168 .hw_value = ATH5K_RATE_CODE_9M, 169 .flags = 0 }, 170 { .bitrate = 120, 171 .hw_value = ATH5K_RATE_CODE_12M, 172 .flags = 0 }, 173 { .bitrate = 180, 174 .hw_value = ATH5K_RATE_CODE_18M, 175 .flags = 0 }, 176 { .bitrate = 240, 177 .hw_value = ATH5K_RATE_CODE_24M, 178 .flags = 0 }, 179 { .bitrate = 360, 180 .hw_value = ATH5K_RATE_CODE_36M, 181 .flags = 0 }, 182 { .bitrate = 480, 183 .hw_value = ATH5K_RATE_CODE_48M, 184 .flags = 0 }, 185 { .bitrate = 540, 186 .hw_value = ATH5K_RATE_CODE_54M, 187 .flags = 0 }, 188 /* XR missing */ 189 }; 190 191 /* 192 * Prototypes - PCI stack related functions 193 */ 194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev, 195 const struct pci_device_id *id); 196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev); 197 #ifdef CONFIG_PM 198 static int ath5k_pci_suspend(struct pci_dev *pdev, 199 pm_message_t state); 200 static int ath5k_pci_resume(struct pci_dev *pdev); 201 #else 202 #define ath5k_pci_suspend NULL 203 #define ath5k_pci_resume NULL 204 #endif /* CONFIG_PM */ 205 206 static struct pci_driver ath5k_pci_driver = { 207 .name = KBUILD_MODNAME, 208 .id_table = ath5k_pci_id_table, 209 .probe = ath5k_pci_probe, 210 .remove = __devexit_p(ath5k_pci_remove), 211 .suspend = ath5k_pci_suspend, 212 .resume = ath5k_pci_resume, 213 }; 214 215 216 217 /* 218 * Prototypes - MAC 802.11 stack related functions 219 */ 220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb); 221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 222 struct ath5k_txq *txq); 223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan); 224 static int ath5k_reset_wake(struct ath5k_softc *sc); 225 static int ath5k_start(struct ieee80211_hw *hw); 226 static void ath5k_stop(struct ieee80211_hw *hw); 227 static int ath5k_add_interface(struct ieee80211_hw *hw, 228 struct ieee80211_if_init_conf *conf); 229 static void ath5k_remove_interface(struct ieee80211_hw *hw, 230 struct ieee80211_if_init_conf *conf); 231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed); 232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 233 int mc_count, struct dev_addr_list *mc_list); 234 static void ath5k_configure_filter(struct ieee80211_hw *hw, 235 unsigned int changed_flags, 236 unsigned int *new_flags, 237 u64 multicast); 238 static int ath5k_set_key(struct ieee80211_hw *hw, 239 enum set_key_cmd cmd, 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 241 struct ieee80211_key_conf *key); 242 static int ath5k_get_stats(struct ieee80211_hw *hw, 243 struct ieee80211_low_level_stats *stats); 244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw, 245 struct ieee80211_tx_queue_stats *stats); 246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw); 247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf); 248 static void ath5k_reset_tsf(struct ieee80211_hw *hw); 249 static int ath5k_beacon_update(struct ieee80211_hw *hw, 250 struct ieee80211_vif *vif); 251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 252 struct ieee80211_vif *vif, 253 struct ieee80211_bss_conf *bss_conf, 254 u32 changes); 255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw); 256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw); 257 258 static const struct ieee80211_ops ath5k_hw_ops = { 259 .tx = ath5k_tx, 260 .start = ath5k_start, 261 .stop = ath5k_stop, 262 .add_interface = ath5k_add_interface, 263 .remove_interface = ath5k_remove_interface, 264 .config = ath5k_config, 265 .prepare_multicast = ath5k_prepare_multicast, 266 .configure_filter = ath5k_configure_filter, 267 .set_key = ath5k_set_key, 268 .get_stats = ath5k_get_stats, 269 .conf_tx = NULL, 270 .get_tx_stats = ath5k_get_tx_stats, 271 .get_tsf = ath5k_get_tsf, 272 .set_tsf = ath5k_set_tsf, 273 .reset_tsf = ath5k_reset_tsf, 274 .bss_info_changed = ath5k_bss_info_changed, 275 .sw_scan_start = ath5k_sw_scan_start, 276 .sw_scan_complete = ath5k_sw_scan_complete, 277 }; 278 279 /* 280 * Prototypes - Internal functions 281 */ 282 /* Attach detach */ 283 static int ath5k_attach(struct pci_dev *pdev, 284 struct ieee80211_hw *hw); 285 static void ath5k_detach(struct pci_dev *pdev, 286 struct ieee80211_hw *hw); 287 /* Channel/mode setup */ 288 static inline short ath5k_ieee2mhz(short chan); 289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, 290 struct ieee80211_channel *channels, 291 unsigned int mode, 292 unsigned int max); 293 static int ath5k_setup_bands(struct ieee80211_hw *hw); 294 static int ath5k_chan_set(struct ath5k_softc *sc, 295 struct ieee80211_channel *chan); 296 static void ath5k_setcurmode(struct ath5k_softc *sc, 297 unsigned int mode); 298 static void ath5k_mode_setup(struct ath5k_softc *sc); 299 300 /* Descriptor setup */ 301 static int ath5k_desc_alloc(struct ath5k_softc *sc, 302 struct pci_dev *pdev); 303 static void ath5k_desc_free(struct ath5k_softc *sc, 304 struct pci_dev *pdev); 305 /* Buffers setup */ 306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc, 307 struct ath5k_buf *bf); 308 static int ath5k_txbuf_setup(struct ath5k_softc *sc, 309 struct ath5k_buf *bf, 310 struct ath5k_txq *txq); 311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc, 312 struct ath5k_buf *bf) 313 { 314 BUG_ON(!bf); 315 if (!bf->skb) 316 return; 317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, 318 PCI_DMA_TODEVICE); 319 dev_kfree_skb_any(bf->skb); 320 bf->skb = NULL; 321 } 322 323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc, 324 struct ath5k_buf *bf) 325 { 326 BUG_ON(!bf); 327 if (!bf->skb) 328 return; 329 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, 330 PCI_DMA_FROMDEVICE); 331 dev_kfree_skb_any(bf->skb); 332 bf->skb = NULL; 333 } 334 335 336 /* Queues setup */ 337 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc, 338 int qtype, int subtype); 339 static int ath5k_beaconq_setup(struct ath5k_hw *ah); 340 static int ath5k_beaconq_config(struct ath5k_softc *sc); 341 static void ath5k_txq_drainq(struct ath5k_softc *sc, 342 struct ath5k_txq *txq); 343 static void ath5k_txq_cleanup(struct ath5k_softc *sc); 344 static void ath5k_txq_release(struct ath5k_softc *sc); 345 /* Rx handling */ 346 static int ath5k_rx_start(struct ath5k_softc *sc); 347 static void ath5k_rx_stop(struct ath5k_softc *sc); 348 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, 349 struct ath5k_desc *ds, 350 struct sk_buff *skb, 351 struct ath5k_rx_status *rs); 352 static void ath5k_tasklet_rx(unsigned long data); 353 /* Tx handling */ 354 static void ath5k_tx_processq(struct ath5k_softc *sc, 355 struct ath5k_txq *txq); 356 static void ath5k_tasklet_tx(unsigned long data); 357 /* Beacon handling */ 358 static int ath5k_beacon_setup(struct ath5k_softc *sc, 359 struct ath5k_buf *bf); 360 static void ath5k_beacon_send(struct ath5k_softc *sc); 361 static void ath5k_beacon_config(struct ath5k_softc *sc); 362 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 363 static void ath5k_tasklet_beacon(unsigned long data); 364 365 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 366 { 367 u64 tsf = ath5k_hw_get_tsf64(ah); 368 369 if ((tsf & 0x7fff) < rstamp) 370 tsf -= 0x8000; 371 372 return (tsf & ~0x7fff) | rstamp; 373 } 374 375 /* Interrupt handling */ 376 static int ath5k_init(struct ath5k_softc *sc); 377 static int ath5k_stop_locked(struct ath5k_softc *sc); 378 static int ath5k_stop_hw(struct ath5k_softc *sc); 379 static irqreturn_t ath5k_intr(int irq, void *dev_id); 380 static void ath5k_tasklet_reset(unsigned long data); 381 382 static void ath5k_tasklet_calibrate(unsigned long data); 383 384 /* 385 * Module init/exit functions 386 */ 387 static int __init 388 init_ath5k_pci(void) 389 { 390 int ret; 391 392 ath5k_debug_init(); 393 394 ret = pci_register_driver(&ath5k_pci_driver); 395 if (ret) { 396 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 397 return ret; 398 } 399 400 return 0; 401 } 402 403 static void __exit 404 exit_ath5k_pci(void) 405 { 406 pci_unregister_driver(&ath5k_pci_driver); 407 408 ath5k_debug_finish(); 409 } 410 411 module_init(init_ath5k_pci); 412 module_exit(exit_ath5k_pci); 413 414 415 /********************\ 416 * PCI Initialization * 417 \********************/ 418 419 static const char * 420 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 421 { 422 const char *name = "xxxxx"; 423 unsigned int i; 424 425 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 426 if (srev_names[i].sr_type != type) 427 continue; 428 429 if ((val & 0xf0) == srev_names[i].sr_val) 430 name = srev_names[i].sr_name; 431 432 if ((val & 0xff) == srev_names[i].sr_val) { 433 name = srev_names[i].sr_name; 434 break; 435 } 436 } 437 438 return name; 439 } 440 441 static int __devinit 442 ath5k_pci_probe(struct pci_dev *pdev, 443 const struct pci_device_id *id) 444 { 445 void __iomem *mem; 446 struct ath5k_softc *sc; 447 struct ieee80211_hw *hw; 448 int ret; 449 u8 csz; 450 451 ret = pci_enable_device(pdev); 452 if (ret) { 453 dev_err(&pdev->dev, "can't enable device\n"); 454 goto err; 455 } 456 457 /* XXX 32-bit addressing only */ 458 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 459 if (ret) { 460 dev_err(&pdev->dev, "32-bit DMA not available\n"); 461 goto err_dis; 462 } 463 464 /* 465 * Cache line size is used to size and align various 466 * structures used to communicate with the hardware. 467 */ 468 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 469 if (csz == 0) { 470 /* 471 * Linux 2.4.18 (at least) writes the cache line size 472 * register as a 16-bit wide register which is wrong. 473 * We must have this setup properly for rx buffer 474 * DMA to work so force a reasonable value here if it 475 * comes up zero. 476 */ 477 csz = L1_CACHE_BYTES >> 2; 478 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 479 } 480 /* 481 * The default setting of latency timer yields poor results, 482 * set it to the value used by other systems. It may be worth 483 * tweaking this setting more. 484 */ 485 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 486 487 /* Enable bus mastering */ 488 pci_set_master(pdev); 489 490 /* 491 * Disable the RETRY_TIMEOUT register (0x41) to keep 492 * PCI Tx retries from interfering with C3 CPU state. 493 */ 494 pci_write_config_byte(pdev, 0x41, 0); 495 496 ret = pci_request_region(pdev, 0, "ath5k"); 497 if (ret) { 498 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 499 goto err_dis; 500 } 501 502 mem = pci_iomap(pdev, 0, 0); 503 if (!mem) { 504 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; 505 ret = -EIO; 506 goto err_reg; 507 } 508 509 /* 510 * Allocate hw (mac80211 main struct) 511 * and hw->priv (driver private data) 512 */ 513 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); 514 if (hw == NULL) { 515 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 516 ret = -ENOMEM; 517 goto err_map; 518 } 519 520 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 521 522 /* Initialize driver private data */ 523 SET_IEEE80211_DEV(hw, &pdev->dev); 524 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 525 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 526 IEEE80211_HW_SIGNAL_DBM | 527 IEEE80211_HW_NOISE_DBM; 528 529 hw->wiphy->interface_modes = 530 BIT(NL80211_IFTYPE_AP) | 531 BIT(NL80211_IFTYPE_STATION) | 532 BIT(NL80211_IFTYPE_ADHOC) | 533 BIT(NL80211_IFTYPE_MESH_POINT); 534 535 hw->extra_tx_headroom = 2; 536 hw->channel_change_time = 5000; 537 sc = hw->priv; 538 sc->hw = hw; 539 sc->pdev = pdev; 540 541 ath5k_debug_init_device(sc); 542 543 /* 544 * Mark the device as detached to avoid processing 545 * interrupts until setup is complete. 546 */ 547 __set_bit(ATH_STAT_INVALID, sc->status); 548 549 sc->iobase = mem; /* So we can unmap it on detach */ 550 sc->common.cachelsz = csz << 2; /* convert to bytes */ 551 sc->opmode = NL80211_IFTYPE_STATION; 552 sc->bintval = 1000; 553 mutex_init(&sc->lock); 554 spin_lock_init(&sc->rxbuflock); 555 spin_lock_init(&sc->txbuflock); 556 spin_lock_init(&sc->block); 557 558 /* Set private data */ 559 pci_set_drvdata(pdev, hw); 560 561 /* Setup interrupt handler */ 562 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 563 if (ret) { 564 ATH5K_ERR(sc, "request_irq failed\n"); 565 goto err_free; 566 } 567 568 /* Initialize device */ 569 sc->ah = ath5k_hw_attach(sc); 570 if (IS_ERR(sc->ah)) { 571 ret = PTR_ERR(sc->ah); 572 goto err_irq; 573 } 574 575 /* set up multi-rate retry capabilities */ 576 if (sc->ah->ah_version == AR5K_AR5212) { 577 hw->max_rates = 4; 578 hw->max_rate_tries = 11; 579 } 580 581 /* Finish private driver data initialization */ 582 ret = ath5k_attach(pdev, hw); 583 if (ret) 584 goto err_ah; 585 586 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 587 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 588 sc->ah->ah_mac_srev, 589 sc->ah->ah_phy_revision); 590 591 if (!sc->ah->ah_single_chip) { 592 /* Single chip radio (!RF5111) */ 593 if (sc->ah->ah_radio_5ghz_revision && 594 !sc->ah->ah_radio_2ghz_revision) { 595 /* No 5GHz support -> report 2GHz radio */ 596 if (!test_bit(AR5K_MODE_11A, 597 sc->ah->ah_capabilities.cap_mode)) { 598 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 599 ath5k_chip_name(AR5K_VERSION_RAD, 600 sc->ah->ah_radio_5ghz_revision), 601 sc->ah->ah_radio_5ghz_revision); 602 /* No 2GHz support (5110 and some 603 * 5Ghz only cards) -> report 5Ghz radio */ 604 } else if (!test_bit(AR5K_MODE_11B, 605 sc->ah->ah_capabilities.cap_mode)) { 606 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 607 ath5k_chip_name(AR5K_VERSION_RAD, 608 sc->ah->ah_radio_5ghz_revision), 609 sc->ah->ah_radio_5ghz_revision); 610 /* Multiband radio */ 611 } else { 612 ATH5K_INFO(sc, "RF%s multiband radio found" 613 " (0x%x)\n", 614 ath5k_chip_name(AR5K_VERSION_RAD, 615 sc->ah->ah_radio_5ghz_revision), 616 sc->ah->ah_radio_5ghz_revision); 617 } 618 } 619 /* Multi chip radio (RF5111 - RF2111) -> 620 * report both 2GHz/5GHz radios */ 621 else if (sc->ah->ah_radio_5ghz_revision && 622 sc->ah->ah_radio_2ghz_revision){ 623 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 624 ath5k_chip_name(AR5K_VERSION_RAD, 625 sc->ah->ah_radio_5ghz_revision), 626 sc->ah->ah_radio_5ghz_revision); 627 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 628 ath5k_chip_name(AR5K_VERSION_RAD, 629 sc->ah->ah_radio_2ghz_revision), 630 sc->ah->ah_radio_2ghz_revision); 631 } 632 } 633 634 635 /* ready to process interrupts */ 636 __clear_bit(ATH_STAT_INVALID, sc->status); 637 638 return 0; 639 err_ah: 640 ath5k_hw_detach(sc->ah); 641 err_irq: 642 free_irq(pdev->irq, sc); 643 err_free: 644 ieee80211_free_hw(hw); 645 err_map: 646 pci_iounmap(pdev, mem); 647 err_reg: 648 pci_release_region(pdev, 0); 649 err_dis: 650 pci_disable_device(pdev); 651 err: 652 return ret; 653 } 654 655 static void __devexit 656 ath5k_pci_remove(struct pci_dev *pdev) 657 { 658 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 659 struct ath5k_softc *sc = hw->priv; 660 661 ath5k_debug_finish_device(sc); 662 ath5k_detach(pdev, hw); 663 ath5k_hw_detach(sc->ah); 664 free_irq(pdev->irq, sc); 665 pci_iounmap(pdev, sc->iobase); 666 pci_release_region(pdev, 0); 667 pci_disable_device(pdev); 668 ieee80211_free_hw(hw); 669 } 670 671 #ifdef CONFIG_PM 672 static int 673 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state) 674 { 675 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 676 struct ath5k_softc *sc = hw->priv; 677 678 ath5k_led_off(sc); 679 680 pci_save_state(pdev); 681 pci_disable_device(pdev); 682 pci_set_power_state(pdev, PCI_D3hot); 683 684 return 0; 685 } 686 687 static int 688 ath5k_pci_resume(struct pci_dev *pdev) 689 { 690 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 691 struct ath5k_softc *sc = hw->priv; 692 int err; 693 694 pci_restore_state(pdev); 695 696 err = pci_enable_device(pdev); 697 if (err) 698 return err; 699 700 /* 701 * Suspend/Resume resets the PCI configuration space, so we have to 702 * re-disable the RETRY_TIMEOUT register (0x41) to keep 703 * PCI Tx retries from interfering with C3 CPU state 704 */ 705 pci_write_config_byte(pdev, 0x41, 0); 706 707 ath5k_led_enable(sc); 708 return 0; 709 } 710 #endif /* CONFIG_PM */ 711 712 713 /***********************\ 714 * Driver Initialization * 715 \***********************/ 716 717 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 718 { 719 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 720 struct ath5k_softc *sc = hw->priv; 721 struct ath_regulatory *regulatory = &sc->common.regulatory; 722 723 return ath_reg_notifier_apply(wiphy, request, regulatory); 724 } 725 726 static int 727 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) 728 { 729 struct ath5k_softc *sc = hw->priv; 730 struct ath5k_hw *ah = sc->ah; 731 struct ath_regulatory *regulatory = &sc->common.regulatory; 732 u8 mac[ETH_ALEN] = {}; 733 int ret; 734 735 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device); 736 737 /* 738 * Check if the MAC has multi-rate retry support. 739 * We do this by trying to setup a fake extended 740 * descriptor. MAC's that don't have support will 741 * return false w/o doing anything. MAC's that do 742 * support it will return true w/o doing anything. 743 */ 744 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 745 if (ret < 0) 746 goto err; 747 if (ret > 0) 748 __set_bit(ATH_STAT_MRRETRY, sc->status); 749 750 /* 751 * Collect the channel list. The 802.11 layer 752 * is resposible for filtering this list based 753 * on settings like the phy mode and regulatory 754 * domain restrictions. 755 */ 756 ret = ath5k_setup_bands(hw); 757 if (ret) { 758 ATH5K_ERR(sc, "can't get channels\n"); 759 goto err; 760 } 761 762 /* NB: setup here so ath5k_rate_update is happy */ 763 if (test_bit(AR5K_MODE_11A, ah->ah_modes)) 764 ath5k_setcurmode(sc, AR5K_MODE_11A); 765 else 766 ath5k_setcurmode(sc, AR5K_MODE_11B); 767 768 /* 769 * Allocate tx+rx descriptors and populate the lists. 770 */ 771 ret = ath5k_desc_alloc(sc, pdev); 772 if (ret) { 773 ATH5K_ERR(sc, "can't allocate descriptors\n"); 774 goto err; 775 } 776 777 /* 778 * Allocate hardware transmit queues: one queue for 779 * beacon frames and one data queue for each QoS 780 * priority. Note that hw functions handle reseting 781 * these queues at the needed time. 782 */ 783 ret = ath5k_beaconq_setup(ah); 784 if (ret < 0) { 785 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 786 goto err_desc; 787 } 788 sc->bhalq = ret; 789 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 790 if (IS_ERR(sc->cabq)) { 791 ATH5K_ERR(sc, "can't setup cab queue\n"); 792 ret = PTR_ERR(sc->cabq); 793 goto err_bhal; 794 } 795 796 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 797 if (IS_ERR(sc->txq)) { 798 ATH5K_ERR(sc, "can't setup xmit queue\n"); 799 ret = PTR_ERR(sc->txq); 800 goto err_queues; 801 } 802 803 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 804 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 805 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc); 806 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 807 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 808 809 ret = ath5k_eeprom_read_mac(ah, mac); 810 if (ret) { 811 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n", 812 sc->pdev->device); 813 goto err_queues; 814 } 815 816 SET_IEEE80211_PERM_ADDR(hw, mac); 817 /* All MAC address bits matter for ACKs */ 818 memset(sc->bssidmask, 0xff, ETH_ALEN); 819 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 820 821 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 822 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 823 if (ret) { 824 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 825 goto err_queues; 826 } 827 828 ret = ieee80211_register_hw(hw); 829 if (ret) { 830 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 831 goto err_queues; 832 } 833 834 if (!ath_is_world_regd(regulatory)) 835 regulatory_hint(hw->wiphy, regulatory->alpha2); 836 837 ath5k_init_leds(sc); 838 839 return 0; 840 err_queues: 841 ath5k_txq_release(sc); 842 err_bhal: 843 ath5k_hw_release_tx_queue(ah, sc->bhalq); 844 err_desc: 845 ath5k_desc_free(sc, pdev); 846 err: 847 return ret; 848 } 849 850 static void 851 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) 852 { 853 struct ath5k_softc *sc = hw->priv; 854 855 /* 856 * NB: the order of these is important: 857 * o call the 802.11 layer before detaching ath5k_hw to 858 * insure callbacks into the driver to delete global 859 * key cache entries can be handled 860 * o reclaim the tx queue data structures after calling 861 * the 802.11 layer as we'll get called back to reclaim 862 * node state and potentially want to use them 863 * o to cleanup the tx queues the hal is called, so detach 864 * it last 865 * XXX: ??? detach ath5k_hw ??? 866 * Other than that, it's straightforward... 867 */ 868 ieee80211_unregister_hw(hw); 869 ath5k_desc_free(sc, pdev); 870 ath5k_txq_release(sc); 871 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 872 ath5k_unregister_leds(sc); 873 874 /* 875 * NB: can't reclaim these until after ieee80211_ifdetach 876 * returns because we'll get called back to reclaim node 877 * state and potentially want to use them. 878 */ 879 } 880 881 882 883 884 /********************\ 885 * Channel/mode setup * 886 \********************/ 887 888 /* 889 * Convert IEEE channel number to MHz frequency. 890 */ 891 static inline short 892 ath5k_ieee2mhz(short chan) 893 { 894 if (chan <= 14 || chan >= 27) 895 return ieee80211chan2mhz(chan); 896 else 897 return 2212 + chan * 20; 898 } 899 900 /* 901 * Returns true for the channel numbers used without all_channels modparam. 902 */ 903 static bool ath5k_is_standard_channel(short chan) 904 { 905 return ((chan <= 14) || 906 /* UNII 1,2 */ 907 ((chan & 3) == 0 && chan >= 36 && chan <= 64) || 908 /* midband */ 909 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 910 /* UNII-3 */ 911 ((chan & 3) == 1 && chan >= 149 && chan <= 165)); 912 } 913 914 static unsigned int 915 ath5k_copy_channels(struct ath5k_hw *ah, 916 struct ieee80211_channel *channels, 917 unsigned int mode, 918 unsigned int max) 919 { 920 unsigned int i, count, size, chfreq, freq, ch; 921 922 if (!test_bit(mode, ah->ah_modes)) 923 return 0; 924 925 switch (mode) { 926 case AR5K_MODE_11A: 927 case AR5K_MODE_11A_TURBO: 928 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 929 size = 220 ; 930 chfreq = CHANNEL_5GHZ; 931 break; 932 case AR5K_MODE_11B: 933 case AR5K_MODE_11G: 934 case AR5K_MODE_11G_TURBO: 935 size = 26; 936 chfreq = CHANNEL_2GHZ; 937 break; 938 default: 939 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 940 return 0; 941 } 942 943 for (i = 0, count = 0; i < size && max > 0; i++) { 944 ch = i + 1 ; 945 freq = ath5k_ieee2mhz(ch); 946 947 /* Check if channel is supported by the chipset */ 948 if (!ath5k_channel_ok(ah, freq, chfreq)) 949 continue; 950 951 if (!modparam_all_channels && !ath5k_is_standard_channel(ch)) 952 continue; 953 954 /* Write channel info and increment counter */ 955 channels[count].center_freq = freq; 956 channels[count].band = (chfreq == CHANNEL_2GHZ) ? 957 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; 958 switch (mode) { 959 case AR5K_MODE_11A: 960 case AR5K_MODE_11G: 961 channels[count].hw_value = chfreq | CHANNEL_OFDM; 962 break; 963 case AR5K_MODE_11A_TURBO: 964 case AR5K_MODE_11G_TURBO: 965 channels[count].hw_value = chfreq | 966 CHANNEL_OFDM | CHANNEL_TURBO; 967 break; 968 case AR5K_MODE_11B: 969 channels[count].hw_value = CHANNEL_B; 970 } 971 972 count++; 973 max--; 974 } 975 976 return count; 977 } 978 979 static void 980 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 981 { 982 u8 i; 983 984 for (i = 0; i < AR5K_MAX_RATES; i++) 985 sc->rate_idx[b->band][i] = -1; 986 987 for (i = 0; i < b->n_bitrates; i++) { 988 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 989 if (b->bitrates[i].hw_value_short) 990 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 991 } 992 } 993 994 static int 995 ath5k_setup_bands(struct ieee80211_hw *hw) 996 { 997 struct ath5k_softc *sc = hw->priv; 998 struct ath5k_hw *ah = sc->ah; 999 struct ieee80211_supported_band *sband; 1000 int max_c, count_c = 0; 1001 int i; 1002 1003 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 1004 max_c = ARRAY_SIZE(sc->channels); 1005 1006 /* 2GHz band */ 1007 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1008 sband->band = IEEE80211_BAND_2GHZ; 1009 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 1010 1011 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 1012 /* G mode */ 1013 memcpy(sband->bitrates, &ath5k_rates[0], 1014 sizeof(struct ieee80211_rate) * 12); 1015 sband->n_bitrates = 12; 1016 1017 sband->channels = sc->channels; 1018 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1019 AR5K_MODE_11G, max_c); 1020 1021 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1022 count_c = sband->n_channels; 1023 max_c -= count_c; 1024 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 1025 /* B mode */ 1026 memcpy(sband->bitrates, &ath5k_rates[0], 1027 sizeof(struct ieee80211_rate) * 4); 1028 sband->n_bitrates = 4; 1029 1030 /* 5211 only supports B rates and uses 4bit rate codes 1031 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 1032 * fix them up here: 1033 */ 1034 if (ah->ah_version == AR5K_AR5211) { 1035 for (i = 0; i < 4; i++) { 1036 sband->bitrates[i].hw_value = 1037 sband->bitrates[i].hw_value & 0xF; 1038 sband->bitrates[i].hw_value_short = 1039 sband->bitrates[i].hw_value_short & 0xF; 1040 } 1041 } 1042 1043 sband->channels = sc->channels; 1044 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1045 AR5K_MODE_11B, max_c); 1046 1047 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1048 count_c = sband->n_channels; 1049 max_c -= count_c; 1050 } 1051 ath5k_setup_rate_idx(sc, sband); 1052 1053 /* 5GHz band, A mode */ 1054 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 1055 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1056 sband->band = IEEE80211_BAND_5GHZ; 1057 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 1058 1059 memcpy(sband->bitrates, &ath5k_rates[4], 1060 sizeof(struct ieee80211_rate) * 8); 1061 sband->n_bitrates = 8; 1062 1063 sband->channels = &sc->channels[count_c]; 1064 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1065 AR5K_MODE_11A, max_c); 1066 1067 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 1068 } 1069 ath5k_setup_rate_idx(sc, sband); 1070 1071 ath5k_debug_dump_bands(sc); 1072 1073 return 0; 1074 } 1075 1076 /* 1077 * Set/change channels. We always reset the chip. 1078 * To accomplish this we must first cleanup any pending DMA, 1079 * then restart stuff after a la ath5k_init. 1080 * 1081 * Called with sc->lock. 1082 */ 1083 static int 1084 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 1085 { 1086 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", 1087 sc->curchan->center_freq, chan->center_freq); 1088 1089 /* 1090 * To switch channels clear any pending DMA operations; 1091 * wait long enough for the RX fifo to drain, reset the 1092 * hardware at the new frequency, and then re-enable 1093 * the relevant bits of the h/w. 1094 */ 1095 return ath5k_reset(sc, chan); 1096 } 1097 1098 static void 1099 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) 1100 { 1101 sc->curmode = mode; 1102 1103 if (mode == AR5K_MODE_11A) { 1104 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1105 } else { 1106 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1107 } 1108 } 1109 1110 static void 1111 ath5k_mode_setup(struct ath5k_softc *sc) 1112 { 1113 struct ath5k_hw *ah = sc->ah; 1114 u32 rfilt; 1115 1116 ah->ah_op_mode = sc->opmode; 1117 1118 /* configure rx filter */ 1119 rfilt = sc->filter_flags; 1120 ath5k_hw_set_rx_filter(ah, rfilt); 1121 1122 if (ath5k_hw_hasbssidmask(ah)) 1123 ath5k_hw_set_bssid_mask(ah, sc->bssidmask); 1124 1125 /* configure operational mode */ 1126 ath5k_hw_set_opmode(ah); 1127 1128 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 1129 } 1130 1131 static inline int 1132 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 1133 { 1134 int rix; 1135 1136 /* return base rate on errors */ 1137 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 1138 "hw_rix out of bounds: %x\n", hw_rix)) 1139 return 0; 1140 1141 rix = sc->rate_idx[sc->curband->band][hw_rix]; 1142 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 1143 rix = 0; 1144 1145 return rix; 1146 } 1147 1148 /***************\ 1149 * Buffers setup * 1150 \***************/ 1151 1152 static 1153 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 1154 { 1155 struct sk_buff *skb; 1156 1157 /* 1158 * Allocate buffer with headroom_needed space for the 1159 * fake physical layer header at the start. 1160 */ 1161 skb = ath_rxbuf_alloc(&sc->common, 1162 sc->rxbufsize + sc->common.cachelsz - 1, 1163 GFP_ATOMIC); 1164 1165 if (!skb) { 1166 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 1167 sc->rxbufsize + sc->common.cachelsz - 1); 1168 return NULL; 1169 } 1170 1171 *skb_addr = pci_map_single(sc->pdev, 1172 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE); 1173 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) { 1174 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 1175 dev_kfree_skb(skb); 1176 return NULL; 1177 } 1178 return skb; 1179 } 1180 1181 static int 1182 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1183 { 1184 struct ath5k_hw *ah = sc->ah; 1185 struct sk_buff *skb = bf->skb; 1186 struct ath5k_desc *ds; 1187 1188 if (!skb) { 1189 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 1190 if (!skb) 1191 return -ENOMEM; 1192 bf->skb = skb; 1193 } 1194 1195 /* 1196 * Setup descriptors. For receive we always terminate 1197 * the descriptor list with a self-linked entry so we'll 1198 * not get overrun under high load (as can happen with a 1199 * 5212 when ANI processing enables PHY error frames). 1200 * 1201 * To insure the last descriptor is self-linked we create 1202 * each descriptor as self-linked and add it to the end. As 1203 * each additional descriptor is added the previous self-linked 1204 * entry is ``fixed'' naturally. This should be safe even 1205 * if DMA is happening. When processing RX interrupts we 1206 * never remove/process the last, self-linked, entry on the 1207 * descriptor list. This insures the hardware always has 1208 * someplace to write a new frame. 1209 */ 1210 ds = bf->desc; 1211 ds->ds_link = bf->daddr; /* link to self */ 1212 ds->ds_data = bf->skbaddr; 1213 ah->ah_setup_rx_desc(ah, ds, 1214 skb_tailroom(skb), /* buffer size */ 1215 0); 1216 1217 if (sc->rxlink != NULL) 1218 *sc->rxlink = bf->daddr; 1219 sc->rxlink = &ds->ds_link; 1220 return 0; 1221 } 1222 1223 static int 1224 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1225 struct ath5k_txq *txq) 1226 { 1227 struct ath5k_hw *ah = sc->ah; 1228 struct ath5k_desc *ds = bf->desc; 1229 struct sk_buff *skb = bf->skb; 1230 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1231 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 1232 struct ieee80211_rate *rate; 1233 unsigned int mrr_rate[3], mrr_tries[3]; 1234 int i, ret; 1235 u16 hw_rate; 1236 u16 cts_rate = 0; 1237 u16 duration = 0; 1238 u8 rc_flags; 1239 1240 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 1241 1242 /* XXX endianness */ 1243 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 1244 PCI_DMA_TODEVICE); 1245 1246 rate = ieee80211_get_tx_rate(sc->hw, info); 1247 1248 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1249 flags |= AR5K_TXDESC_NOACK; 1250 1251 rc_flags = info->control.rates[0].flags; 1252 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 1253 rate->hw_value_short : rate->hw_value; 1254 1255 pktlen = skb->len; 1256 1257 /* FIXME: If we are in g mode and rate is a CCK rate 1258 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1259 * from tx power (value is in dB units already) */ 1260 if (info->control.hw_key) { 1261 keyidx = info->control.hw_key->hw_key_idx; 1262 pktlen += info->control.hw_key->icv_len; 1263 } 1264 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1265 flags |= AR5K_TXDESC_RTSENA; 1266 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1267 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 1268 sc->vif, pktlen, info)); 1269 } 1270 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1271 flags |= AR5K_TXDESC_CTSENA; 1272 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1273 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 1274 sc->vif, pktlen, info)); 1275 } 1276 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 1277 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, 1278 (sc->power_level * 2), 1279 hw_rate, 1280 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 1281 cts_rate, duration); 1282 if (ret) 1283 goto err_unmap; 1284 1285 memset(mrr_rate, 0, sizeof(mrr_rate)); 1286 memset(mrr_tries, 0, sizeof(mrr_tries)); 1287 for (i = 0; i < 3; i++) { 1288 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 1289 if (!rate) 1290 break; 1291 1292 mrr_rate[i] = rate->hw_value; 1293 mrr_tries[i] = info->control.rates[i + 1].count; 1294 } 1295 1296 ah->ah_setup_mrr_tx_desc(ah, ds, 1297 mrr_rate[0], mrr_tries[0], 1298 mrr_rate[1], mrr_tries[1], 1299 mrr_rate[2], mrr_tries[2]); 1300 1301 ds->ds_link = 0; 1302 ds->ds_data = bf->skbaddr; 1303 1304 spin_lock_bh(&txq->lock); 1305 list_add_tail(&bf->list, &txq->q); 1306 sc->tx_stats[txq->qnum].len++; 1307 if (txq->link == NULL) /* is this first packet? */ 1308 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 1309 else /* no, so only link it */ 1310 *txq->link = bf->daddr; 1311 1312 txq->link = &ds->ds_link; 1313 ath5k_hw_start_tx_dma(ah, txq->qnum); 1314 mmiowb(); 1315 spin_unlock_bh(&txq->lock); 1316 1317 return 0; 1318 err_unmap: 1319 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 1320 return ret; 1321 } 1322 1323 /*******************\ 1324 * Descriptors setup * 1325 \*******************/ 1326 1327 static int 1328 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev) 1329 { 1330 struct ath5k_desc *ds; 1331 struct ath5k_buf *bf; 1332 dma_addr_t da; 1333 unsigned int i; 1334 int ret; 1335 1336 /* allocate descriptors */ 1337 sc->desc_len = sizeof(struct ath5k_desc) * 1338 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 1339 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); 1340 if (sc->desc == NULL) { 1341 ATH5K_ERR(sc, "can't allocate descriptors\n"); 1342 ret = -ENOMEM; 1343 goto err; 1344 } 1345 ds = sc->desc; 1346 da = sc->desc_daddr; 1347 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 1348 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 1349 1350 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 1351 sizeof(struct ath5k_buf), GFP_KERNEL); 1352 if (bf == NULL) { 1353 ATH5K_ERR(sc, "can't allocate bufptr\n"); 1354 ret = -ENOMEM; 1355 goto err_free; 1356 } 1357 sc->bufptr = bf; 1358 1359 INIT_LIST_HEAD(&sc->rxbuf); 1360 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 1361 bf->desc = ds; 1362 bf->daddr = da; 1363 list_add_tail(&bf->list, &sc->rxbuf); 1364 } 1365 1366 INIT_LIST_HEAD(&sc->txbuf); 1367 sc->txbuf_len = ATH_TXBUF; 1368 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 1369 da += sizeof(*ds)) { 1370 bf->desc = ds; 1371 bf->daddr = da; 1372 list_add_tail(&bf->list, &sc->txbuf); 1373 } 1374 1375 /* beacon buffer */ 1376 bf->desc = ds; 1377 bf->daddr = da; 1378 sc->bbuf = bf; 1379 1380 return 0; 1381 err_free: 1382 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1383 err: 1384 sc->desc = NULL; 1385 return ret; 1386 } 1387 1388 static void 1389 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) 1390 { 1391 struct ath5k_buf *bf; 1392 1393 ath5k_txbuf_free(sc, sc->bbuf); 1394 list_for_each_entry(bf, &sc->txbuf, list) 1395 ath5k_txbuf_free(sc, bf); 1396 list_for_each_entry(bf, &sc->rxbuf, list) 1397 ath5k_rxbuf_free(sc, bf); 1398 1399 /* Free memory associated with all descriptors */ 1400 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1401 1402 kfree(sc->bufptr); 1403 sc->bufptr = NULL; 1404 } 1405 1406 1407 1408 1409 1410 /**************\ 1411 * Queues setup * 1412 \**************/ 1413 1414 static struct ath5k_txq * 1415 ath5k_txq_setup(struct ath5k_softc *sc, 1416 int qtype, int subtype) 1417 { 1418 struct ath5k_hw *ah = sc->ah; 1419 struct ath5k_txq *txq; 1420 struct ath5k_txq_info qi = { 1421 .tqi_subtype = subtype, 1422 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1423 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1424 .tqi_cw_max = AR5K_TXQ_USEDEFAULT 1425 }; 1426 int qnum; 1427 1428 /* 1429 * Enable interrupts only for EOL and DESC conditions. 1430 * We mark tx descriptors to receive a DESC interrupt 1431 * when a tx queue gets deep; otherwise waiting for the 1432 * EOL to reap descriptors. Note that this is done to 1433 * reduce interrupt load and this only defers reaping 1434 * descriptors, never transmitting frames. Aside from 1435 * reducing interrupts this also permits more concurrency. 1436 * The only potential downside is if the tx queue backs 1437 * up in which case the top half of the kernel may backup 1438 * due to a lack of tx descriptors. 1439 */ 1440 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 1441 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1442 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1443 if (qnum < 0) { 1444 /* 1445 * NB: don't print a message, this happens 1446 * normally on parts with too few tx queues 1447 */ 1448 return ERR_PTR(qnum); 1449 } 1450 if (qnum >= ARRAY_SIZE(sc->txqs)) { 1451 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 1452 qnum, ARRAY_SIZE(sc->txqs)); 1453 ath5k_hw_release_tx_queue(ah, qnum); 1454 return ERR_PTR(-EINVAL); 1455 } 1456 txq = &sc->txqs[qnum]; 1457 if (!txq->setup) { 1458 txq->qnum = qnum; 1459 txq->link = NULL; 1460 INIT_LIST_HEAD(&txq->q); 1461 spin_lock_init(&txq->lock); 1462 txq->setup = true; 1463 } 1464 return &sc->txqs[qnum]; 1465 } 1466 1467 static int 1468 ath5k_beaconq_setup(struct ath5k_hw *ah) 1469 { 1470 struct ath5k_txq_info qi = { 1471 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1472 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1473 .tqi_cw_max = AR5K_TXQ_USEDEFAULT, 1474 /* NB: for dynamic turbo, don't enable any other interrupts */ 1475 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1476 }; 1477 1478 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1479 } 1480 1481 static int 1482 ath5k_beaconq_config(struct ath5k_softc *sc) 1483 { 1484 struct ath5k_hw *ah = sc->ah; 1485 struct ath5k_txq_info qi; 1486 int ret; 1487 1488 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 1489 if (ret) 1490 return ret; 1491 if (sc->opmode == NL80211_IFTYPE_AP || 1492 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1493 /* 1494 * Always burst out beacon and CAB traffic 1495 * (aifs = cwmin = cwmax = 0) 1496 */ 1497 qi.tqi_aifs = 0; 1498 qi.tqi_cw_min = 0; 1499 qi.tqi_cw_max = 0; 1500 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 1501 /* 1502 * Adhoc mode; backoff between 0 and (2 * cw_min). 1503 */ 1504 qi.tqi_aifs = 0; 1505 qi.tqi_cw_min = 0; 1506 qi.tqi_cw_max = 2 * ah->ah_cw_min; 1507 } 1508 1509 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1510 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1511 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1512 1513 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1514 if (ret) { 1515 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1516 "hardware queue!\n", __func__); 1517 return ret; 1518 } 1519 1520 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; 1521 } 1522 1523 static void 1524 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1525 { 1526 struct ath5k_buf *bf, *bf0; 1527 1528 /* 1529 * NB: this assumes output has been stopped and 1530 * we do not need to block ath5k_tx_tasklet 1531 */ 1532 spin_lock_bh(&txq->lock); 1533 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1534 ath5k_debug_printtxbuf(sc, bf); 1535 1536 ath5k_txbuf_free(sc, bf); 1537 1538 spin_lock_bh(&sc->txbuflock); 1539 sc->tx_stats[txq->qnum].len--; 1540 list_move_tail(&bf->list, &sc->txbuf); 1541 sc->txbuf_len++; 1542 spin_unlock_bh(&sc->txbuflock); 1543 } 1544 txq->link = NULL; 1545 spin_unlock_bh(&txq->lock); 1546 } 1547 1548 /* 1549 * Drain the transmit queues and reclaim resources. 1550 */ 1551 static void 1552 ath5k_txq_cleanup(struct ath5k_softc *sc) 1553 { 1554 struct ath5k_hw *ah = sc->ah; 1555 unsigned int i; 1556 1557 /* XXX return value */ 1558 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) { 1559 /* don't touch the hardware if marked invalid */ 1560 ath5k_hw_stop_tx_dma(ah, sc->bhalq); 1561 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", 1562 ath5k_hw_get_txdp(ah, sc->bhalq)); 1563 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1564 if (sc->txqs[i].setup) { 1565 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); 1566 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " 1567 "link %p\n", 1568 sc->txqs[i].qnum, 1569 ath5k_hw_get_txdp(ah, 1570 sc->txqs[i].qnum), 1571 sc->txqs[i].link); 1572 } 1573 } 1574 ieee80211_wake_queues(sc->hw); /* XXX move to callers */ 1575 1576 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1577 if (sc->txqs[i].setup) 1578 ath5k_txq_drainq(sc, &sc->txqs[i]); 1579 } 1580 1581 static void 1582 ath5k_txq_release(struct ath5k_softc *sc) 1583 { 1584 struct ath5k_txq *txq = sc->txqs; 1585 unsigned int i; 1586 1587 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1588 if (txq->setup) { 1589 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1590 txq->setup = false; 1591 } 1592 } 1593 1594 1595 1596 1597 /*************\ 1598 * RX Handling * 1599 \*************/ 1600 1601 /* 1602 * Enable the receive h/w following a reset. 1603 */ 1604 static int 1605 ath5k_rx_start(struct ath5k_softc *sc) 1606 { 1607 struct ath5k_hw *ah = sc->ah; 1608 struct ath5k_buf *bf; 1609 int ret; 1610 1611 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->common.cachelsz); 1612 1613 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n", 1614 sc->common.cachelsz, sc->rxbufsize); 1615 1616 spin_lock_bh(&sc->rxbuflock); 1617 sc->rxlink = NULL; 1618 list_for_each_entry(bf, &sc->rxbuf, list) { 1619 ret = ath5k_rxbuf_setup(sc, bf); 1620 if (ret != 0) { 1621 spin_unlock_bh(&sc->rxbuflock); 1622 goto err; 1623 } 1624 } 1625 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1626 ath5k_hw_set_rxdp(ah, bf->daddr); 1627 spin_unlock_bh(&sc->rxbuflock); 1628 1629 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1630 ath5k_mode_setup(sc); /* set filters, etc. */ 1631 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1632 1633 return 0; 1634 err: 1635 return ret; 1636 } 1637 1638 /* 1639 * Disable the receive h/w in preparation for a reset. 1640 */ 1641 static void 1642 ath5k_rx_stop(struct ath5k_softc *sc) 1643 { 1644 struct ath5k_hw *ah = sc->ah; 1645 1646 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1647 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1648 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ 1649 1650 ath5k_debug_printrxbuffs(sc, ah); 1651 1652 sc->rxlink = NULL; /* just in case */ 1653 } 1654 1655 static unsigned int 1656 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, 1657 struct sk_buff *skb, struct ath5k_rx_status *rs) 1658 { 1659 struct ieee80211_hdr *hdr = (void *)skb->data; 1660 unsigned int keyix, hlen; 1661 1662 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1663 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1664 return RX_FLAG_DECRYPTED; 1665 1666 /* Apparently when a default key is used to decrypt the packet 1667 the hw does not set the index used to decrypt. In such cases 1668 get the index from the packet. */ 1669 hlen = ieee80211_hdrlen(hdr->frame_control); 1670 if (ieee80211_has_protected(hdr->frame_control) && 1671 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1672 skb->len >= hlen + 4) { 1673 keyix = skb->data[hlen + 3] >> 6; 1674 1675 if (test_bit(keyix, sc->keymap)) 1676 return RX_FLAG_DECRYPTED; 1677 } 1678 1679 return 0; 1680 } 1681 1682 1683 static void 1684 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1685 struct ieee80211_rx_status *rxs) 1686 { 1687 u64 tsf, bc_tstamp; 1688 u32 hw_tu; 1689 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1690 1691 if (ieee80211_is_beacon(mgmt->frame_control) && 1692 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1693 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) { 1694 /* 1695 * Received an IBSS beacon with the same BSSID. Hardware *must* 1696 * have updated the local TSF. We have to work around various 1697 * hardware bugs, though... 1698 */ 1699 tsf = ath5k_hw_get_tsf64(sc->ah); 1700 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1701 hw_tu = TSF_TO_TU(tsf); 1702 1703 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1704 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1705 (unsigned long long)bc_tstamp, 1706 (unsigned long long)rxs->mactime, 1707 (unsigned long long)(rxs->mactime - bc_tstamp), 1708 (unsigned long long)tsf); 1709 1710 /* 1711 * Sometimes the HW will give us a wrong tstamp in the rx 1712 * status, causing the timestamp extension to go wrong. 1713 * (This seems to happen especially with beacon frames bigger 1714 * than 78 byte (incl. FCS)) 1715 * But we know that the receive timestamp must be later than the 1716 * timestamp of the beacon since HW must have synced to that. 1717 * 1718 * NOTE: here we assume mactime to be after the frame was 1719 * received, not like mac80211 which defines it at the start. 1720 */ 1721 if (bc_tstamp > rxs->mactime) { 1722 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1723 "fixing mactime from %llx to %llx\n", 1724 (unsigned long long)rxs->mactime, 1725 (unsigned long long)tsf); 1726 rxs->mactime = tsf; 1727 } 1728 1729 /* 1730 * Local TSF might have moved higher than our beacon timers, 1731 * in that case we have to update them to continue sending 1732 * beacons. This also takes care of synchronizing beacon sending 1733 * times with other stations. 1734 */ 1735 if (hw_tu >= sc->nexttbtt) 1736 ath5k_beacon_update_timers(sc, bc_tstamp); 1737 } 1738 } 1739 1740 static void 1741 ath5k_tasklet_rx(unsigned long data) 1742 { 1743 struct ieee80211_rx_status *rxs; 1744 struct ath5k_rx_status rs = {}; 1745 struct sk_buff *skb, *next_skb; 1746 dma_addr_t next_skb_addr; 1747 struct ath5k_softc *sc = (void *)data; 1748 struct ath5k_buf *bf; 1749 struct ath5k_desc *ds; 1750 int ret; 1751 int hdrlen; 1752 int padsize; 1753 int rx_flag; 1754 1755 spin_lock(&sc->rxbuflock); 1756 if (list_empty(&sc->rxbuf)) { 1757 ATH5K_WARN(sc, "empty rx buf pool\n"); 1758 goto unlock; 1759 } 1760 do { 1761 rx_flag = 0; 1762 1763 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1764 BUG_ON(bf->skb == NULL); 1765 skb = bf->skb; 1766 ds = bf->desc; 1767 1768 /* bail if HW is still using self-linked descriptor */ 1769 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1770 break; 1771 1772 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1773 if (unlikely(ret == -EINPROGRESS)) 1774 break; 1775 else if (unlikely(ret)) { 1776 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1777 spin_unlock(&sc->rxbuflock); 1778 return; 1779 } 1780 1781 if (unlikely(rs.rs_more)) { 1782 ATH5K_WARN(sc, "unsupported jumbo\n"); 1783 goto next; 1784 } 1785 1786 if (unlikely(rs.rs_status)) { 1787 if (rs.rs_status & AR5K_RXERR_PHY) 1788 goto next; 1789 if (rs.rs_status & AR5K_RXERR_DECRYPT) { 1790 /* 1791 * Decrypt error. If the error occurred 1792 * because there was no hardware key, then 1793 * let the frame through so the upper layers 1794 * can process it. This is necessary for 5210 1795 * parts which have no way to setup a ``clear'' 1796 * key cache entry. 1797 * 1798 * XXX do key cache faulting 1799 */ 1800 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && 1801 !(rs.rs_status & AR5K_RXERR_CRC)) 1802 goto accept; 1803 } 1804 if (rs.rs_status & AR5K_RXERR_MIC) { 1805 rx_flag |= RX_FLAG_MMIC_ERROR; 1806 goto accept; 1807 } 1808 1809 /* let crypto-error packets fall through in MNTR */ 1810 if ((rs.rs_status & 1811 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || 1812 sc->opmode != NL80211_IFTYPE_MONITOR) 1813 goto next; 1814 } 1815 accept: 1816 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1817 1818 /* 1819 * If we can't replace bf->skb with a new skb under memory 1820 * pressure, just skip this packet 1821 */ 1822 if (!next_skb) 1823 goto next; 1824 1825 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize, 1826 PCI_DMA_FROMDEVICE); 1827 skb_put(skb, rs.rs_datalen); 1828 1829 /* The MAC header is padded to have 32-bit boundary if the 1830 * packet payload is non-zero. The general calculation for 1831 * padsize would take into account odd header lengths: 1832 * padsize = (4 - hdrlen % 4) % 4; However, since only 1833 * even-length headers are used, padding can only be 0 or 2 1834 * bytes and we can optimize this a bit. In addition, we must 1835 * not try to remove padding from short control frames that do 1836 * not have payload. */ 1837 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1838 padsize = ath5k_pad_size(hdrlen); 1839 if (padsize) { 1840 memmove(skb->data + padsize, skb->data, hdrlen); 1841 skb_pull(skb, padsize); 1842 } 1843 rxs = IEEE80211_SKB_RXCB(skb); 1844 1845 /* 1846 * always extend the mac timestamp, since this information is 1847 * also needed for proper IBSS merging. 1848 * 1849 * XXX: it might be too late to do it here, since rs_tstamp is 1850 * 15bit only. that means TSF extension has to be done within 1851 * 32768usec (about 32ms). it might be necessary to move this to 1852 * the interrupt handler, like it is done in madwifi. 1853 * 1854 * Unfortunately we don't know when the hardware takes the rx 1855 * timestamp (beginning of phy frame, data frame, end of rx?). 1856 * The only thing we know is that it is hardware specific... 1857 * On AR5213 it seems the rx timestamp is at the end of the 1858 * frame, but i'm not sure. 1859 * 1860 * NOTE: mac80211 defines mactime at the beginning of the first 1861 * data symbol. Since we don't have any time references it's 1862 * impossible to comply to that. This affects IBSS merge only 1863 * right now, so it's not too bad... 1864 */ 1865 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp); 1866 rxs->flag = rx_flag | RX_FLAG_TSFT; 1867 1868 rxs->freq = sc->curchan->center_freq; 1869 rxs->band = sc->curband->band; 1870 1871 rxs->noise = sc->ah->ah_noise_floor; 1872 rxs->signal = rxs->noise + rs.rs_rssi; 1873 1874 /* An rssi of 35 indicates you should be able use 1875 * 54 Mbps reliably. A more elaborate scheme can be used 1876 * here but it requires a map of SNR/throughput for each 1877 * possible mode used */ 1878 rxs->qual = rs.rs_rssi * 100 / 35; 1879 1880 /* rssi can be more than 35 though, anything above that 1881 * should be considered at 100% */ 1882 if (rxs->qual > 100) 1883 rxs->qual = 100; 1884 1885 rxs->antenna = rs.rs_antenna; 1886 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); 1887 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs); 1888 1889 if (rxs->rate_idx >= 0 && rs.rs_rate == 1890 sc->curband->bitrates[rxs->rate_idx].hw_value_short) 1891 rxs->flag |= RX_FLAG_SHORTPRE; 1892 1893 ath5k_debug_dump_skb(sc, skb, "RX ", 0); 1894 1895 /* check beacons in IBSS mode */ 1896 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1897 ath5k_check_ibss_tsf(sc, skb, rxs); 1898 1899 ieee80211_rx(sc->hw, skb); 1900 1901 bf->skb = next_skb; 1902 bf->skbaddr = next_skb_addr; 1903 next: 1904 list_move_tail(&bf->list, &sc->rxbuf); 1905 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1906 unlock: 1907 spin_unlock(&sc->rxbuflock); 1908 } 1909 1910 1911 1912 1913 /*************\ 1914 * TX Handling * 1915 \*************/ 1916 1917 static void 1918 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1919 { 1920 struct ath5k_tx_status ts = {}; 1921 struct ath5k_buf *bf, *bf0; 1922 struct ath5k_desc *ds; 1923 struct sk_buff *skb; 1924 struct ieee80211_tx_info *info; 1925 int i, ret; 1926 1927 spin_lock(&txq->lock); 1928 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1929 ds = bf->desc; 1930 1931 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1932 if (unlikely(ret == -EINPROGRESS)) 1933 break; 1934 else if (unlikely(ret)) { 1935 ATH5K_ERR(sc, "error %d while processing queue %u\n", 1936 ret, txq->qnum); 1937 break; 1938 } 1939 1940 skb = bf->skb; 1941 info = IEEE80211_SKB_CB(skb); 1942 bf->skb = NULL; 1943 1944 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, 1945 PCI_DMA_TODEVICE); 1946 1947 ieee80211_tx_info_clear_status(info); 1948 for (i = 0; i < 4; i++) { 1949 struct ieee80211_tx_rate *r = 1950 &info->status.rates[i]; 1951 1952 if (ts.ts_rate[i]) { 1953 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]); 1954 r->count = ts.ts_retry[i]; 1955 } else { 1956 r->idx = -1; 1957 r->count = 0; 1958 } 1959 } 1960 1961 /* count the successful attempt as well */ 1962 info->status.rates[ts.ts_final_idx].count++; 1963 1964 if (unlikely(ts.ts_status)) { 1965 sc->ll_stats.dot11ACKFailureCount++; 1966 if (ts.ts_status & AR5K_TXERR_FILT) 1967 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1968 } else { 1969 info->flags |= IEEE80211_TX_STAT_ACK; 1970 info->status.ack_signal = ts.ts_rssi; 1971 } 1972 1973 ieee80211_tx_status(sc->hw, skb); 1974 sc->tx_stats[txq->qnum].count++; 1975 1976 spin_lock(&sc->txbuflock); 1977 sc->tx_stats[txq->qnum].len--; 1978 list_move_tail(&bf->list, &sc->txbuf); 1979 sc->txbuf_len++; 1980 spin_unlock(&sc->txbuflock); 1981 } 1982 if (likely(list_empty(&txq->q))) 1983 txq->link = NULL; 1984 spin_unlock(&txq->lock); 1985 if (sc->txbuf_len > ATH_TXBUF / 5) 1986 ieee80211_wake_queues(sc->hw); 1987 } 1988 1989 static void 1990 ath5k_tasklet_tx(unsigned long data) 1991 { 1992 int i; 1993 struct ath5k_softc *sc = (void *)data; 1994 1995 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 1996 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 1997 ath5k_tx_processq(sc, &sc->txqs[i]); 1998 } 1999 2000 2001 /*****************\ 2002 * Beacon handling * 2003 \*****************/ 2004 2005 /* 2006 * Setup the beacon frame for transmit. 2007 */ 2008 static int 2009 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 2010 { 2011 struct sk_buff *skb = bf->skb; 2012 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2013 struct ath5k_hw *ah = sc->ah; 2014 struct ath5k_desc *ds; 2015 int ret = 0; 2016 u8 antenna; 2017 u32 flags; 2018 2019 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 2020 PCI_DMA_TODEVICE); 2021 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 2022 "skbaddr %llx\n", skb, skb->data, skb->len, 2023 (unsigned long long)bf->skbaddr); 2024 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) { 2025 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 2026 return -EIO; 2027 } 2028 2029 ds = bf->desc; 2030 antenna = ah->ah_tx_ant; 2031 2032 flags = AR5K_TXDESC_NOACK; 2033 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 2034 ds->ds_link = bf->daddr; /* self-linked */ 2035 flags |= AR5K_TXDESC_VEOL; 2036 } else 2037 ds->ds_link = 0; 2038 2039 /* 2040 * If we use multiple antennas on AP and use 2041 * the Sectored AP scenario, switch antenna every 2042 * 4 beacons to make sure everybody hears our AP. 2043 * When a client tries to associate, hw will keep 2044 * track of the tx antenna to be used for this client 2045 * automaticaly, based on ACKed packets. 2046 * 2047 * Note: AP still listens and transmits RTS on the 2048 * default antenna which is supposed to be an omni. 2049 * 2050 * Note2: On sectored scenarios it's possible to have 2051 * multiple antennas (1omni -the default- and 14 sectors) 2052 * so if we choose to actually support this mode we need 2053 * to allow user to set how many antennas we have and tweak 2054 * the code below to send beacons on all of them. 2055 */ 2056 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 2057 antenna = sc->bsent & 4 ? 2 : 1; 2058 2059 2060 /* FIXME: If we are in g mode and rate is a CCK rate 2061 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 2062 * from tx power (value is in dB units already) */ 2063 ds->ds_data = bf->skbaddr; 2064 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 2065 ieee80211_get_hdrlen_from_skb(skb), 2066 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 2067 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 2068 1, AR5K_TXKEYIX_INVALID, 2069 antenna, flags, 0, 0); 2070 if (ret) 2071 goto err_unmap; 2072 2073 return 0; 2074 err_unmap: 2075 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 2076 return ret; 2077 } 2078 2079 /* 2080 * Transmit a beacon frame at SWBA. Dynamic updates to the 2081 * frame contents are done as needed and the slot time is 2082 * also adjusted based on current state. 2083 * 2084 * This is called from software irq context (beacontq or restq 2085 * tasklets) or user context from ath5k_beacon_config. 2086 */ 2087 static void 2088 ath5k_beacon_send(struct ath5k_softc *sc) 2089 { 2090 struct ath5k_buf *bf = sc->bbuf; 2091 struct ath5k_hw *ah = sc->ah; 2092 struct sk_buff *skb; 2093 2094 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 2095 2096 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 2097 sc->opmode == NL80211_IFTYPE_MONITOR)) { 2098 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 2099 return; 2100 } 2101 /* 2102 * Check if the previous beacon has gone out. If 2103 * not don't don't try to post another, skip this 2104 * period and wait for the next. Missed beacons 2105 * indicate a problem and should not occur. If we 2106 * miss too many consecutive beacons reset the device. 2107 */ 2108 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 2109 sc->bmisscount++; 2110 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2111 "missed %u consecutive beacons\n", sc->bmisscount); 2112 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 2113 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2114 "stuck beacon time (%u missed)\n", 2115 sc->bmisscount); 2116 tasklet_schedule(&sc->restq); 2117 } 2118 return; 2119 } 2120 if (unlikely(sc->bmisscount != 0)) { 2121 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2122 "resume beacon xmit after %u misses\n", 2123 sc->bmisscount); 2124 sc->bmisscount = 0; 2125 } 2126 2127 /* 2128 * Stop any current dma and put the new frame on the queue. 2129 * This should never fail since we check above that no frames 2130 * are still pending on the queue. 2131 */ 2132 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { 2133 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 2134 /* NB: hw still stops DMA, so proceed */ 2135 } 2136 2137 /* refresh the beacon for AP mode */ 2138 if (sc->opmode == NL80211_IFTYPE_AP) 2139 ath5k_beacon_update(sc->hw, sc->vif); 2140 2141 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 2142 ath5k_hw_start_tx_dma(ah, sc->bhalq); 2143 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 2144 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 2145 2146 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2147 while (skb) { 2148 ath5k_tx_queue(sc->hw, skb, sc->cabq); 2149 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2150 } 2151 2152 sc->bsent++; 2153 } 2154 2155 2156 /** 2157 * ath5k_beacon_update_timers - update beacon timers 2158 * 2159 * @sc: struct ath5k_softc pointer we are operating on 2160 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2161 * beacon timer update based on the current HW TSF. 2162 * 2163 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2164 * of a received beacon or the current local hardware TSF and write it to the 2165 * beacon timer registers. 2166 * 2167 * This is called in a variety of situations, e.g. when a beacon is received, 2168 * when a TSF update has been detected, but also when an new IBSS is created or 2169 * when we otherwise know we have to update the timers, but we keep it in this 2170 * function to have it all together in one place. 2171 */ 2172 static void 2173 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 2174 { 2175 struct ath5k_hw *ah = sc->ah; 2176 u32 nexttbtt, intval, hw_tu, bc_tu; 2177 u64 hw_tsf; 2178 2179 intval = sc->bintval & AR5K_BEACON_PERIOD; 2180 if (WARN_ON(!intval)) 2181 return; 2182 2183 /* beacon TSF converted to TU */ 2184 bc_tu = TSF_TO_TU(bc_tsf); 2185 2186 /* current TSF converted to TU */ 2187 hw_tsf = ath5k_hw_get_tsf64(ah); 2188 hw_tu = TSF_TO_TU(hw_tsf); 2189 2190 #define FUDGE 3 2191 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */ 2192 if (bc_tsf == -1) { 2193 /* 2194 * no beacons received, called internally. 2195 * just need to refresh timers based on HW TSF. 2196 */ 2197 nexttbtt = roundup(hw_tu + FUDGE, intval); 2198 } else if (bc_tsf == 0) { 2199 /* 2200 * no beacon received, probably called by ath5k_reset_tsf(). 2201 * reset TSF to start with 0. 2202 */ 2203 nexttbtt = intval; 2204 intval |= AR5K_BEACON_RESET_TSF; 2205 } else if (bc_tsf > hw_tsf) { 2206 /* 2207 * beacon received, SW merge happend but HW TSF not yet updated. 2208 * not possible to reconfigure timers yet, but next time we 2209 * receive a beacon with the same BSSID, the hardware will 2210 * automatically update the TSF and then we need to reconfigure 2211 * the timers. 2212 */ 2213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2214 "need to wait for HW TSF sync\n"); 2215 return; 2216 } else { 2217 /* 2218 * most important case for beacon synchronization between STA. 2219 * 2220 * beacon received and HW TSF has been already updated by HW. 2221 * update next TBTT based on the TSF of the beacon, but make 2222 * sure it is ahead of our local TSF timer. 2223 */ 2224 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2225 } 2226 #undef FUDGE 2227 2228 sc->nexttbtt = nexttbtt; 2229 2230 intval |= AR5K_BEACON_ENA; 2231 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2232 2233 /* 2234 * debugging output last in order to preserve the time critical aspect 2235 * of this function 2236 */ 2237 if (bc_tsf == -1) 2238 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2239 "reconfigured timers based on HW TSF\n"); 2240 else if (bc_tsf == 0) 2241 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2242 "reset HW TSF and timers\n"); 2243 else 2244 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2245 "updated timers based on beacon TSF\n"); 2246 2247 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2248 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2249 (unsigned long long) bc_tsf, 2250 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2251 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2252 intval & AR5K_BEACON_PERIOD, 2253 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2254 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2255 } 2256 2257 2258 /** 2259 * ath5k_beacon_config - Configure the beacon queues and interrupts 2260 * 2261 * @sc: struct ath5k_softc pointer we are operating on 2262 * 2263 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2264 * interrupts to detect TSF updates only. 2265 */ 2266 static void 2267 ath5k_beacon_config(struct ath5k_softc *sc) 2268 { 2269 struct ath5k_hw *ah = sc->ah; 2270 unsigned long flags; 2271 2272 spin_lock_irqsave(&sc->block, flags); 2273 sc->bmisscount = 0; 2274 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2275 2276 if (sc->enable_beacon) { 2277 /* 2278 * In IBSS mode we use a self-linked tx descriptor and let the 2279 * hardware send the beacons automatically. We have to load it 2280 * only once here. 2281 * We use the SWBA interrupt only to keep track of the beacon 2282 * timers in order to detect automatic TSF updates. 2283 */ 2284 ath5k_beaconq_config(sc); 2285 2286 sc->imask |= AR5K_INT_SWBA; 2287 2288 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2289 if (ath5k_hw_hasveol(ah)) 2290 ath5k_beacon_send(sc); 2291 } else 2292 ath5k_beacon_update_timers(sc, -1); 2293 } else { 2294 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq); 2295 } 2296 2297 ath5k_hw_set_imr(ah, sc->imask); 2298 mmiowb(); 2299 spin_unlock_irqrestore(&sc->block, flags); 2300 } 2301 2302 static void ath5k_tasklet_beacon(unsigned long data) 2303 { 2304 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2305 2306 /* 2307 * Software beacon alert--time to send a beacon. 2308 * 2309 * In IBSS mode we use this interrupt just to 2310 * keep track of the next TBTT (target beacon 2311 * transmission time) in order to detect wether 2312 * automatic TSF updates happened. 2313 */ 2314 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2315 /* XXX: only if VEOL suppported */ 2316 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2317 sc->nexttbtt += sc->bintval; 2318 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2319 "SWBA nexttbtt: %x hw_tu: %x " 2320 "TSF: %llx\n", 2321 sc->nexttbtt, 2322 TSF_TO_TU(tsf), 2323 (unsigned long long) tsf); 2324 } else { 2325 spin_lock(&sc->block); 2326 ath5k_beacon_send(sc); 2327 spin_unlock(&sc->block); 2328 } 2329 } 2330 2331 2332 /********************\ 2333 * Interrupt handling * 2334 \********************/ 2335 2336 static int 2337 ath5k_init(struct ath5k_softc *sc) 2338 { 2339 struct ath5k_hw *ah = sc->ah; 2340 int ret, i; 2341 2342 mutex_lock(&sc->lock); 2343 2344 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2345 2346 /* 2347 * Stop anything previously setup. This is safe 2348 * no matter this is the first time through or not. 2349 */ 2350 ath5k_stop_locked(sc); 2351 2352 /* 2353 * The basic interface to setting the hardware in a good 2354 * state is ``reset''. On return the hardware is known to 2355 * be powered up and with interrupts disabled. This must 2356 * be followed by initialization of the appropriate bits 2357 * and then setup of the interrupt mask. 2358 */ 2359 sc->curchan = sc->hw->conf.channel; 2360 sc->curband = &sc->sbands[sc->curchan->band]; 2361 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2362 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2363 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI; 2364 ret = ath5k_reset(sc, NULL); 2365 if (ret) 2366 goto done; 2367 2368 ath5k_rfkill_hw_start(ah); 2369 2370 /* 2371 * Reset the key cache since some parts do not reset the 2372 * contents on initial power up or resume from suspend. 2373 */ 2374 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) 2375 ath5k_hw_reset_key(ah, i); 2376 2377 /* Set ack to be sent at low bit-rates */ 2378 ath5k_hw_set_ack_bitrate_high(ah, false); 2379 2380 /* Set PHY calibration inteval */ 2381 ah->ah_cal_intval = ath5k_calinterval; 2382 2383 ret = 0; 2384 done: 2385 mmiowb(); 2386 mutex_unlock(&sc->lock); 2387 return ret; 2388 } 2389 2390 static int 2391 ath5k_stop_locked(struct ath5k_softc *sc) 2392 { 2393 struct ath5k_hw *ah = sc->ah; 2394 2395 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2396 test_bit(ATH_STAT_INVALID, sc->status)); 2397 2398 /* 2399 * Shutdown the hardware and driver: 2400 * stop output from above 2401 * disable interrupts 2402 * turn off timers 2403 * turn off the radio 2404 * clear transmit machinery 2405 * clear receive machinery 2406 * drain and release tx queues 2407 * reclaim beacon resources 2408 * power down hardware 2409 * 2410 * Note that some of this work is not possible if the 2411 * hardware is gone (invalid). 2412 */ 2413 ieee80211_stop_queues(sc->hw); 2414 2415 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2416 ath5k_led_off(sc); 2417 ath5k_hw_set_imr(ah, 0); 2418 synchronize_irq(sc->pdev->irq); 2419 } 2420 ath5k_txq_cleanup(sc); 2421 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2422 ath5k_rx_stop(sc); 2423 ath5k_hw_phy_disable(ah); 2424 } else 2425 sc->rxlink = NULL; 2426 2427 return 0; 2428 } 2429 2430 /* 2431 * Stop the device, grabbing the top-level lock to protect 2432 * against concurrent entry through ath5k_init (which can happen 2433 * if another thread does a system call and the thread doing the 2434 * stop is preempted). 2435 */ 2436 static int 2437 ath5k_stop_hw(struct ath5k_softc *sc) 2438 { 2439 int ret; 2440 2441 mutex_lock(&sc->lock); 2442 ret = ath5k_stop_locked(sc); 2443 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2444 /* 2445 * Don't set the card in full sleep mode! 2446 * 2447 * a) When the device is in this state it must be carefully 2448 * woken up or references to registers in the PCI clock 2449 * domain may freeze the bus (and system). This varies 2450 * by chip and is mostly an issue with newer parts 2451 * (madwifi sources mentioned srev >= 0x78) that go to 2452 * sleep more quickly. 2453 * 2454 * b) On older chips full sleep results a weird behaviour 2455 * during wakeup. I tested various cards with srev < 0x78 2456 * and they don't wake up after module reload, a second 2457 * module reload is needed to bring the card up again. 2458 * 2459 * Until we figure out what's going on don't enable 2460 * full chip reset on any chip (this is what Legacy HAL 2461 * and Sam's HAL do anyway). Instead Perform a full reset 2462 * on the device (same as initial state after attach) and 2463 * leave it idle (keep MAC/BB on warm reset) */ 2464 ret = ath5k_hw_on_hold(sc->ah); 2465 2466 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2467 "putting device to sleep\n"); 2468 } 2469 ath5k_txbuf_free(sc, sc->bbuf); 2470 2471 mmiowb(); 2472 mutex_unlock(&sc->lock); 2473 2474 tasklet_kill(&sc->rxtq); 2475 tasklet_kill(&sc->txtq); 2476 tasklet_kill(&sc->restq); 2477 tasklet_kill(&sc->calib); 2478 tasklet_kill(&sc->beacontq); 2479 2480 ath5k_rfkill_hw_stop(sc->ah); 2481 2482 return ret; 2483 } 2484 2485 static irqreturn_t 2486 ath5k_intr(int irq, void *dev_id) 2487 { 2488 struct ath5k_softc *sc = dev_id; 2489 struct ath5k_hw *ah = sc->ah; 2490 enum ath5k_int status; 2491 unsigned int counter = 1000; 2492 2493 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2494 !ath5k_hw_is_intr_pending(ah))) 2495 return IRQ_NONE; 2496 2497 do { 2498 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2499 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2500 status, sc->imask); 2501 if (unlikely(status & AR5K_INT_FATAL)) { 2502 /* 2503 * Fatal errors are unrecoverable. 2504 * Typically these are caused by DMA errors. 2505 */ 2506 tasklet_schedule(&sc->restq); 2507 } else if (unlikely(status & AR5K_INT_RXORN)) { 2508 tasklet_schedule(&sc->restq); 2509 } else { 2510 if (status & AR5K_INT_SWBA) { 2511 tasklet_hi_schedule(&sc->beacontq); 2512 } 2513 if (status & AR5K_INT_RXEOL) { 2514 /* 2515 * NB: the hardware should re-read the link when 2516 * RXE bit is written, but it doesn't work at 2517 * least on older hardware revs. 2518 */ 2519 sc->rxlink = NULL; 2520 } 2521 if (status & AR5K_INT_TXURN) { 2522 /* bump tx trigger level */ 2523 ath5k_hw_update_tx_triglevel(ah, true); 2524 } 2525 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2526 tasklet_schedule(&sc->rxtq); 2527 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2528 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2529 tasklet_schedule(&sc->txtq); 2530 if (status & AR5K_INT_BMISS) { 2531 /* TODO */ 2532 } 2533 if (status & AR5K_INT_SWI) { 2534 tasklet_schedule(&sc->calib); 2535 } 2536 if (status & AR5K_INT_MIB) { 2537 /* 2538 * These stats are also used for ANI i think 2539 * so how about updating them more often ? 2540 */ 2541 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 2542 } 2543 if (status & AR5K_INT_GPIO) 2544 tasklet_schedule(&sc->rf_kill.toggleq); 2545 2546 } 2547 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2548 2549 if (unlikely(!counter)) 2550 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2551 2552 ath5k_hw_calibration_poll(ah); 2553 2554 return IRQ_HANDLED; 2555 } 2556 2557 static void 2558 ath5k_tasklet_reset(unsigned long data) 2559 { 2560 struct ath5k_softc *sc = (void *)data; 2561 2562 ath5k_reset_wake(sc); 2563 } 2564 2565 /* 2566 * Periodically recalibrate the PHY to account 2567 * for temperature/environment changes. 2568 */ 2569 static void 2570 ath5k_tasklet_calibrate(unsigned long data) 2571 { 2572 struct ath5k_softc *sc = (void *)data; 2573 struct ath5k_hw *ah = sc->ah; 2574 2575 /* Only full calibration for now */ 2576 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION) 2577 return; 2578 2579 /* Stop queues so that calibration 2580 * doesn't interfere with tx */ 2581 ieee80211_stop_queues(sc->hw); 2582 2583 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2584 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2585 sc->curchan->hw_value); 2586 2587 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2588 /* 2589 * Rfgain is out of bounds, reset the chip 2590 * to load new gain values. 2591 */ 2592 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2593 ath5k_reset_wake(sc); 2594 } 2595 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2596 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2597 ieee80211_frequency_to_channel( 2598 sc->curchan->center_freq)); 2599 2600 ah->ah_swi_mask = 0; 2601 2602 /* Wake queues */ 2603 ieee80211_wake_queues(sc->hw); 2604 2605 } 2606 2607 2608 /********************\ 2609 * Mac80211 functions * 2610 \********************/ 2611 2612 static int 2613 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2614 { 2615 struct ath5k_softc *sc = hw->priv; 2616 2617 return ath5k_tx_queue(hw, skb, sc->txq); 2618 } 2619 2620 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 2621 struct ath5k_txq *txq) 2622 { 2623 struct ath5k_softc *sc = hw->priv; 2624 struct ath5k_buf *bf; 2625 unsigned long flags; 2626 int hdrlen; 2627 int padsize; 2628 2629 ath5k_debug_dump_skb(sc, skb, "TX ", 1); 2630 2631 if (sc->opmode == NL80211_IFTYPE_MONITOR) 2632 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n"); 2633 2634 /* 2635 * the hardware expects the header padded to 4 byte boundaries 2636 * if this is not the case we add the padding after the header 2637 */ 2638 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 2639 padsize = ath5k_pad_size(hdrlen); 2640 if (padsize) { 2641 2642 if (skb_headroom(skb) < padsize) { 2643 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough" 2644 " headroom to pad %d\n", hdrlen, padsize); 2645 goto drop_packet; 2646 } 2647 skb_push(skb, padsize); 2648 memmove(skb->data, skb->data+padsize, hdrlen); 2649 } 2650 2651 spin_lock_irqsave(&sc->txbuflock, flags); 2652 if (list_empty(&sc->txbuf)) { 2653 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 2654 spin_unlock_irqrestore(&sc->txbuflock, flags); 2655 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 2656 goto drop_packet; 2657 } 2658 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 2659 list_del(&bf->list); 2660 sc->txbuf_len--; 2661 if (list_empty(&sc->txbuf)) 2662 ieee80211_stop_queues(hw); 2663 spin_unlock_irqrestore(&sc->txbuflock, flags); 2664 2665 bf->skb = skb; 2666 2667 if (ath5k_txbuf_setup(sc, bf, txq)) { 2668 bf->skb = NULL; 2669 spin_lock_irqsave(&sc->txbuflock, flags); 2670 list_add_tail(&bf->list, &sc->txbuf); 2671 sc->txbuf_len++; 2672 spin_unlock_irqrestore(&sc->txbuflock, flags); 2673 goto drop_packet; 2674 } 2675 return NETDEV_TX_OK; 2676 2677 drop_packet: 2678 dev_kfree_skb_any(skb); 2679 return NETDEV_TX_OK; 2680 } 2681 2682 /* 2683 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2684 * and change to the given channel. 2685 */ 2686 static int 2687 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan) 2688 { 2689 struct ath5k_hw *ah = sc->ah; 2690 int ret; 2691 2692 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2693 2694 if (chan) { 2695 ath5k_hw_set_imr(ah, 0); 2696 ath5k_txq_cleanup(sc); 2697 ath5k_rx_stop(sc); 2698 2699 sc->curchan = chan; 2700 sc->curband = &sc->sbands[chan->band]; 2701 } 2702 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL); 2703 if (ret) { 2704 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2705 goto err; 2706 } 2707 2708 ret = ath5k_rx_start(sc); 2709 if (ret) { 2710 ATH5K_ERR(sc, "can't start recv logic\n"); 2711 goto err; 2712 } 2713 2714 /* 2715 * Change channels and update the h/w rate map if we're switching; 2716 * e.g. 11a to 11b/g. 2717 * 2718 * We may be doing a reset in response to an ioctl that changes the 2719 * channel so update any state that might change as a result. 2720 * 2721 * XXX needed? 2722 */ 2723 /* ath5k_chan_change(sc, c); */ 2724 2725 ath5k_beacon_config(sc); 2726 /* intrs are enabled by ath5k_beacon_config */ 2727 2728 return 0; 2729 err: 2730 return ret; 2731 } 2732 2733 static int 2734 ath5k_reset_wake(struct ath5k_softc *sc) 2735 { 2736 int ret; 2737 2738 ret = ath5k_reset(sc, sc->curchan); 2739 if (!ret) 2740 ieee80211_wake_queues(sc->hw); 2741 2742 return ret; 2743 } 2744 2745 static int ath5k_start(struct ieee80211_hw *hw) 2746 { 2747 return ath5k_init(hw->priv); 2748 } 2749 2750 static void ath5k_stop(struct ieee80211_hw *hw) 2751 { 2752 ath5k_stop_hw(hw->priv); 2753 } 2754 2755 static int ath5k_add_interface(struct ieee80211_hw *hw, 2756 struct ieee80211_if_init_conf *conf) 2757 { 2758 struct ath5k_softc *sc = hw->priv; 2759 int ret; 2760 2761 mutex_lock(&sc->lock); 2762 if (sc->vif) { 2763 ret = 0; 2764 goto end; 2765 } 2766 2767 sc->vif = conf->vif; 2768 2769 switch (conf->type) { 2770 case NL80211_IFTYPE_AP: 2771 case NL80211_IFTYPE_STATION: 2772 case NL80211_IFTYPE_ADHOC: 2773 case NL80211_IFTYPE_MESH_POINT: 2774 case NL80211_IFTYPE_MONITOR: 2775 sc->opmode = conf->type; 2776 break; 2777 default: 2778 ret = -EOPNOTSUPP; 2779 goto end; 2780 } 2781 2782 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr); 2783 ath5k_mode_setup(sc); 2784 2785 ret = 0; 2786 end: 2787 mutex_unlock(&sc->lock); 2788 return ret; 2789 } 2790 2791 static void 2792 ath5k_remove_interface(struct ieee80211_hw *hw, 2793 struct ieee80211_if_init_conf *conf) 2794 { 2795 struct ath5k_softc *sc = hw->priv; 2796 u8 mac[ETH_ALEN] = {}; 2797 2798 mutex_lock(&sc->lock); 2799 if (sc->vif != conf->vif) 2800 goto end; 2801 2802 ath5k_hw_set_lladdr(sc->ah, mac); 2803 sc->vif = NULL; 2804 end: 2805 mutex_unlock(&sc->lock); 2806 } 2807 2808 /* 2809 * TODO: Phy disable/diversity etc 2810 */ 2811 static int 2812 ath5k_config(struct ieee80211_hw *hw, u32 changed) 2813 { 2814 struct ath5k_softc *sc = hw->priv; 2815 struct ath5k_hw *ah = sc->ah; 2816 struct ieee80211_conf *conf = &hw->conf; 2817 int ret = 0; 2818 2819 mutex_lock(&sc->lock); 2820 2821 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 2822 ret = ath5k_chan_set(sc, conf->channel); 2823 if (ret < 0) 2824 goto unlock; 2825 } 2826 2827 if ((changed & IEEE80211_CONF_CHANGE_POWER) && 2828 (sc->power_level != conf->power_level)) { 2829 sc->power_level = conf->power_level; 2830 2831 /* Half dB steps */ 2832 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2)); 2833 } 2834 2835 /* TODO: 2836 * 1) Move this on config_interface and handle each case 2837 * separately eg. when we have only one STA vif, use 2838 * AR5K_ANTMODE_SINGLE_AP 2839 * 2840 * 2) Allow the user to change antenna mode eg. when only 2841 * one antenna is present 2842 * 2843 * 3) Allow the user to set default/tx antenna when possible 2844 * 2845 * 4) Default mode should handle 90% of the cases, together 2846 * with fixed a/b and single AP modes we should be able to 2847 * handle 99%. Sectored modes are extreme cases and i still 2848 * haven't found a usage for them. If we decide to support them, 2849 * then we must allow the user to set how many tx antennas we 2850 * have available 2851 */ 2852 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT); 2853 2854 unlock: 2855 mutex_unlock(&sc->lock); 2856 return ret; 2857 } 2858 2859 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 2860 int mc_count, struct dev_addr_list *mclist) 2861 { 2862 u32 mfilt[2], val; 2863 int i; 2864 u8 pos; 2865 2866 mfilt[0] = 0; 2867 mfilt[1] = 1; 2868 2869 for (i = 0; i < mc_count; i++) { 2870 if (!mclist) 2871 break; 2872 /* calculate XOR of eight 6-bit values */ 2873 val = get_unaligned_le32(mclist->dmi_addr + 0); 2874 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2875 val = get_unaligned_le32(mclist->dmi_addr + 3); 2876 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2877 pos &= 0x3f; 2878 mfilt[pos / 32] |= (1 << (pos % 32)); 2879 /* XXX: we might be able to just do this instead, 2880 * but not sure, needs testing, if we do use this we'd 2881 * neet to inform below to not reset the mcast */ 2882 /* ath5k_hw_set_mcast_filterindex(ah, 2883 * mclist->dmi_addr[5]); */ 2884 mclist = mclist->next; 2885 } 2886 2887 return ((u64)(mfilt[1]) << 32) | mfilt[0]; 2888 } 2889 2890 #define SUPPORTED_FIF_FLAGS \ 2891 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ 2892 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ 2893 FIF_BCN_PRBRESP_PROMISC 2894 /* 2895 * o always accept unicast, broadcast, and multicast traffic 2896 * o multicast traffic for all BSSIDs will be enabled if mac80211 2897 * says it should be 2898 * o maintain current state of phy ofdm or phy cck error reception. 2899 * If the hardware detects any of these type of errors then 2900 * ath5k_hw_get_rx_filter() will pass to us the respective 2901 * hardware filters to be able to receive these type of frames. 2902 * o probe request frames are accepted only when operating in 2903 * hostap, adhoc, or monitor modes 2904 * o enable promiscuous mode according to the interface state 2905 * o accept beacons: 2906 * - when operating in adhoc mode so the 802.11 layer creates 2907 * node table entries for peers, 2908 * - when operating in station mode for collecting rssi data when 2909 * the station is otherwise quiet, or 2910 * - when scanning 2911 */ 2912 static void ath5k_configure_filter(struct ieee80211_hw *hw, 2913 unsigned int changed_flags, 2914 unsigned int *new_flags, 2915 u64 multicast) 2916 { 2917 struct ath5k_softc *sc = hw->priv; 2918 struct ath5k_hw *ah = sc->ah; 2919 u32 mfilt[2], rfilt; 2920 2921 mutex_lock(&sc->lock); 2922 2923 mfilt[0] = multicast; 2924 mfilt[1] = multicast >> 32; 2925 2926 /* Only deal with supported flags */ 2927 changed_flags &= SUPPORTED_FIF_FLAGS; 2928 *new_flags &= SUPPORTED_FIF_FLAGS; 2929 2930 /* If HW detects any phy or radar errors, leave those filters on. 2931 * Also, always enable Unicast, Broadcasts and Multicast 2932 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */ 2933 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) | 2934 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | 2935 AR5K_RX_FILTER_MCAST); 2936 2937 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { 2938 if (*new_flags & FIF_PROMISC_IN_BSS) { 2939 rfilt |= AR5K_RX_FILTER_PROM; 2940 __set_bit(ATH_STAT_PROMISC, sc->status); 2941 } else { 2942 __clear_bit(ATH_STAT_PROMISC, sc->status); 2943 } 2944 } 2945 2946 /* Note, AR5K_RX_FILTER_MCAST is already enabled */ 2947 if (*new_flags & FIF_ALLMULTI) { 2948 mfilt[0] = ~0; 2949 mfilt[1] = ~0; 2950 } 2951 2952 /* This is the best we can do */ 2953 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)) 2954 rfilt |= AR5K_RX_FILTER_PHYERR; 2955 2956 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons 2957 * and probes for any BSSID, this needs testing */ 2958 if (*new_flags & FIF_BCN_PRBRESP_PROMISC) 2959 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ; 2960 2961 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not 2962 * set we should only pass on control frames for this 2963 * station. This needs testing. I believe right now this 2964 * enables *all* control frames, which is OK.. but 2965 * but we should see if we can improve on granularity */ 2966 if (*new_flags & FIF_CONTROL) 2967 rfilt |= AR5K_RX_FILTER_CONTROL; 2968 2969 /* Additional settings per mode -- this is per ath5k */ 2970 2971 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ 2972 2973 switch (sc->opmode) { 2974 case NL80211_IFTYPE_MESH_POINT: 2975 case NL80211_IFTYPE_MONITOR: 2976 rfilt |= AR5K_RX_FILTER_CONTROL | 2977 AR5K_RX_FILTER_BEACON | 2978 AR5K_RX_FILTER_PROBEREQ | 2979 AR5K_RX_FILTER_PROM; 2980 break; 2981 case NL80211_IFTYPE_AP: 2982 case NL80211_IFTYPE_ADHOC: 2983 rfilt |= AR5K_RX_FILTER_PROBEREQ | 2984 AR5K_RX_FILTER_BEACON; 2985 break; 2986 case NL80211_IFTYPE_STATION: 2987 if (sc->assoc) 2988 rfilt |= AR5K_RX_FILTER_BEACON; 2989 default: 2990 break; 2991 } 2992 2993 /* Set filters */ 2994 ath5k_hw_set_rx_filter(ah, rfilt); 2995 2996 /* Set multicast bits */ 2997 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); 2998 /* Set the cached hw filter flags, this will alter actually 2999 * be set in HW */ 3000 sc->filter_flags = rfilt; 3001 3002 mutex_unlock(&sc->lock); 3003 } 3004 3005 static int 3006 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3007 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3008 struct ieee80211_key_conf *key) 3009 { 3010 struct ath5k_softc *sc = hw->priv; 3011 int ret = 0; 3012 3013 if (modparam_nohwcrypt) 3014 return -EOPNOTSUPP; 3015 3016 if (sc->opmode == NL80211_IFTYPE_AP) 3017 return -EOPNOTSUPP; 3018 3019 switch (key->alg) { 3020 case ALG_WEP: 3021 case ALG_TKIP: 3022 break; 3023 case ALG_CCMP: 3024 if (sc->ah->ah_aes_support) 3025 break; 3026 3027 return -EOPNOTSUPP; 3028 default: 3029 WARN_ON(1); 3030 return -EINVAL; 3031 } 3032 3033 mutex_lock(&sc->lock); 3034 3035 switch (cmd) { 3036 case SET_KEY: 3037 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, 3038 sta ? sta->addr : NULL); 3039 if (ret) { 3040 ATH5K_ERR(sc, "can't set the key\n"); 3041 goto unlock; 3042 } 3043 __set_bit(key->keyidx, sc->keymap); 3044 key->hw_key_idx = key->keyidx; 3045 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV | 3046 IEEE80211_KEY_FLAG_GENERATE_MMIC); 3047 break; 3048 case DISABLE_KEY: 3049 ath5k_hw_reset_key(sc->ah, key->keyidx); 3050 __clear_bit(key->keyidx, sc->keymap); 3051 break; 3052 default: 3053 ret = -EINVAL; 3054 goto unlock; 3055 } 3056 3057 unlock: 3058 mmiowb(); 3059 mutex_unlock(&sc->lock); 3060 return ret; 3061 } 3062 3063 static int 3064 ath5k_get_stats(struct ieee80211_hw *hw, 3065 struct ieee80211_low_level_stats *stats) 3066 { 3067 struct ath5k_softc *sc = hw->priv; 3068 struct ath5k_hw *ah = sc->ah; 3069 3070 /* Force update */ 3071 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 3072 3073 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); 3074 3075 return 0; 3076 } 3077 3078 static int 3079 ath5k_get_tx_stats(struct ieee80211_hw *hw, 3080 struct ieee80211_tx_queue_stats *stats) 3081 { 3082 struct ath5k_softc *sc = hw->priv; 3083 3084 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); 3085 3086 return 0; 3087 } 3088 3089 static u64 3090 ath5k_get_tsf(struct ieee80211_hw *hw) 3091 { 3092 struct ath5k_softc *sc = hw->priv; 3093 3094 return ath5k_hw_get_tsf64(sc->ah); 3095 } 3096 3097 static void 3098 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3099 { 3100 struct ath5k_softc *sc = hw->priv; 3101 3102 ath5k_hw_set_tsf64(sc->ah, tsf); 3103 } 3104 3105 static void 3106 ath5k_reset_tsf(struct ieee80211_hw *hw) 3107 { 3108 struct ath5k_softc *sc = hw->priv; 3109 3110 /* 3111 * in IBSS mode we need to update the beacon timers too. 3112 * this will also reset the TSF if we call it with 0 3113 */ 3114 if (sc->opmode == NL80211_IFTYPE_ADHOC) 3115 ath5k_beacon_update_timers(sc, 0); 3116 else 3117 ath5k_hw_reset_tsf(sc->ah); 3118 } 3119 3120 /* 3121 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 3122 * this is called only once at config_bss time, for AP we do it every 3123 * SWBA interrupt so that the TIM will reflect buffered frames. 3124 * 3125 * Called with the beacon lock. 3126 */ 3127 static int 3128 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 3129 { 3130 int ret; 3131 struct ath5k_softc *sc = hw->priv; 3132 struct sk_buff *skb; 3133 3134 if (WARN_ON(!vif)) { 3135 ret = -EINVAL; 3136 goto out; 3137 } 3138 3139 skb = ieee80211_beacon_get(hw, vif); 3140 3141 if (!skb) { 3142 ret = -ENOMEM; 3143 goto out; 3144 } 3145 3146 ath5k_debug_dump_skb(sc, skb, "BC ", 1); 3147 3148 ath5k_txbuf_free(sc, sc->bbuf); 3149 sc->bbuf->skb = skb; 3150 ret = ath5k_beacon_setup(sc, sc->bbuf); 3151 if (ret) 3152 sc->bbuf->skb = NULL; 3153 out: 3154 return ret; 3155 } 3156 3157 static void 3158 set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3159 { 3160 struct ath5k_softc *sc = hw->priv; 3161 struct ath5k_hw *ah = sc->ah; 3162 u32 rfilt; 3163 rfilt = ath5k_hw_get_rx_filter(ah); 3164 if (enable) 3165 rfilt |= AR5K_RX_FILTER_BEACON; 3166 else 3167 rfilt &= ~AR5K_RX_FILTER_BEACON; 3168 ath5k_hw_set_rx_filter(ah, rfilt); 3169 sc->filter_flags = rfilt; 3170 } 3171 3172 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 3173 struct ieee80211_vif *vif, 3174 struct ieee80211_bss_conf *bss_conf, 3175 u32 changes) 3176 { 3177 struct ath5k_softc *sc = hw->priv; 3178 struct ath5k_hw *ah = sc->ah; 3179 unsigned long flags; 3180 3181 mutex_lock(&sc->lock); 3182 if (WARN_ON(sc->vif != vif)) 3183 goto unlock; 3184 3185 if (changes & BSS_CHANGED_BSSID) { 3186 /* Cache for later use during resets */ 3187 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN); 3188 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have 3189 * a clean way of letting us retrieve this yet. */ 3190 ath5k_hw_set_associd(ah, ah->ah_bssid, 0); 3191 mmiowb(); 3192 } 3193 3194 if (changes & BSS_CHANGED_BEACON_INT) 3195 sc->bintval = bss_conf->beacon_int; 3196 3197 if (changes & BSS_CHANGED_ASSOC) { 3198 sc->assoc = bss_conf->assoc; 3199 if (sc->opmode == NL80211_IFTYPE_STATION) 3200 set_beacon_filter(hw, sc->assoc); 3201 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3202 AR5K_LED_ASSOC : AR5K_LED_INIT); 3203 } 3204 3205 if (changes & BSS_CHANGED_BEACON) { 3206 spin_lock_irqsave(&sc->block, flags); 3207 ath5k_beacon_update(hw, vif); 3208 spin_unlock_irqrestore(&sc->block, flags); 3209 } 3210 3211 if (changes & BSS_CHANGED_BEACON_ENABLED) 3212 sc->enable_beacon = bss_conf->enable_beacon; 3213 3214 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | 3215 BSS_CHANGED_BEACON_INT)) 3216 ath5k_beacon_config(sc); 3217 3218 unlock: 3219 mutex_unlock(&sc->lock); 3220 } 3221 3222 static void ath5k_sw_scan_start(struct ieee80211_hw *hw) 3223 { 3224 struct ath5k_softc *sc = hw->priv; 3225 if (!sc->assoc) 3226 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN); 3227 } 3228 3229 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw) 3230 { 3231 struct ath5k_softc *sc = hw->priv; 3232 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3233 AR5K_LED_ASSOC : AR5K_LED_INIT); 3234 } 3235