1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/hardirq.h> 47 #include <linux/if.h> 48 #include <linux/io.h> 49 #include <linux/netdevice.h> 50 #include <linux/cache.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 #include <linux/slab.h> 54 #include <linux/etherdevice.h> 55 56 #include <net/ieee80211_radiotap.h> 57 58 #include <asm/unaligned.h> 59 60 #include "base.h" 61 #include "reg.h" 62 #include "debug.h" 63 #include "ani.h" 64 65 #define CREATE_TRACE_POINTS 66 #include "trace.h" 67 68 int ath5k_modparam_nohwcrypt; 69 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 70 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 71 72 static int modparam_all_channels; 73 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 74 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 75 76 static int modparam_fastchanswitch; 77 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); 78 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 79 80 81 /* Module info */ 82 MODULE_AUTHOR("Jiri Slaby"); 83 MODULE_AUTHOR("Nick Kossifidis"); 84 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 85 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 86 MODULE_LICENSE("Dual BSD/GPL"); 87 88 static int ath5k_init(struct ieee80211_hw *hw); 89 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 90 bool skip_pcu); 91 92 /* Known SREVs */ 93 static const struct ath5k_srev_name srev_names[] = { 94 #ifdef CONFIG_ATHEROS_AR231X 95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 96 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 97 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 99 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 101 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 102 #else 103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 121 #endif 122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 135 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 136 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 137 #ifdef CONFIG_ATHEROS_AR231X 138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 140 #endif 141 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 142 }; 143 144 static const struct ieee80211_rate ath5k_rates[] = { 145 { .bitrate = 10, 146 .hw_value = ATH5K_RATE_CODE_1M, }, 147 { .bitrate = 20, 148 .hw_value = ATH5K_RATE_CODE_2M, 149 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 150 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 151 { .bitrate = 55, 152 .hw_value = ATH5K_RATE_CODE_5_5M, 153 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 154 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 155 { .bitrate = 110, 156 .hw_value = ATH5K_RATE_CODE_11M, 157 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 158 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 159 { .bitrate = 60, 160 .hw_value = ATH5K_RATE_CODE_6M, 161 .flags = 0 }, 162 { .bitrate = 90, 163 .hw_value = ATH5K_RATE_CODE_9M, 164 .flags = 0 }, 165 { .bitrate = 120, 166 .hw_value = ATH5K_RATE_CODE_12M, 167 .flags = 0 }, 168 { .bitrate = 180, 169 .hw_value = ATH5K_RATE_CODE_18M, 170 .flags = 0 }, 171 { .bitrate = 240, 172 .hw_value = ATH5K_RATE_CODE_24M, 173 .flags = 0 }, 174 { .bitrate = 360, 175 .hw_value = ATH5K_RATE_CODE_36M, 176 .flags = 0 }, 177 { .bitrate = 480, 178 .hw_value = ATH5K_RATE_CODE_48M, 179 .flags = 0 }, 180 { .bitrate = 540, 181 .hw_value = ATH5K_RATE_CODE_54M, 182 .flags = 0 }, 183 /* XR missing */ 184 }; 185 186 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 187 { 188 u64 tsf = ath5k_hw_get_tsf64(ah); 189 190 if ((tsf & 0x7fff) < rstamp) 191 tsf -= 0x8000; 192 193 return (tsf & ~0x7fff) | rstamp; 194 } 195 196 const char * 197 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 198 { 199 const char *name = "xxxxx"; 200 unsigned int i; 201 202 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 203 if (srev_names[i].sr_type != type) 204 continue; 205 206 if ((val & 0xf0) == srev_names[i].sr_val) 207 name = srev_names[i].sr_name; 208 209 if ((val & 0xff) == srev_names[i].sr_val) { 210 name = srev_names[i].sr_name; 211 break; 212 } 213 } 214 215 return name; 216 } 217 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 218 { 219 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 220 return ath5k_hw_reg_read(ah, reg_offset); 221 } 222 223 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 224 { 225 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 226 ath5k_hw_reg_write(ah, val, reg_offset); 227 } 228 229 static const struct ath_ops ath5k_common_ops = { 230 .read = ath5k_ioread32, 231 .write = ath5k_iowrite32, 232 }; 233 234 /***********************\ 235 * Driver Initialization * 236 \***********************/ 237 238 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 239 { 240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 241 struct ath5k_hw *ah = hw->priv; 242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 243 244 return ath_reg_notifier_apply(wiphy, request, regulatory); 245 } 246 247 /********************\ 248 * Channel/mode setup * 249 \********************/ 250 251 /* 252 * Returns true for the channel numbers used without all_channels modparam. 253 */ 254 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 255 { 256 if (band == IEEE80211_BAND_2GHZ && chan <= 14) 257 return true; 258 259 return /* UNII 1,2 */ 260 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 261 /* midband */ 262 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 263 /* UNII-3 */ 264 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 265 /* 802.11j 5.030-5.080 GHz (20MHz) */ 266 (chan == 8 || chan == 12 || chan == 16) || 267 /* 802.11j 4.9GHz (20MHz) */ 268 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 269 } 270 271 static unsigned int 272 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 273 unsigned int mode, unsigned int max) 274 { 275 unsigned int count, size, chfreq, freq, ch; 276 enum ieee80211_band band; 277 278 switch (mode) { 279 case AR5K_MODE_11A: 280 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 281 size = 220; 282 chfreq = CHANNEL_5GHZ; 283 band = IEEE80211_BAND_5GHZ; 284 break; 285 case AR5K_MODE_11B: 286 case AR5K_MODE_11G: 287 size = 26; 288 chfreq = CHANNEL_2GHZ; 289 band = IEEE80211_BAND_2GHZ; 290 break; 291 default: 292 ATH5K_WARN(ah, "bad mode, not copying channels\n"); 293 return 0; 294 } 295 296 count = 0; 297 for (ch = 1; ch <= size && count < max; ch++) { 298 freq = ieee80211_channel_to_frequency(ch, band); 299 300 if (freq == 0) /* mapping failed - not a standard channel */ 301 continue; 302 303 /* Check if channel is supported by the chipset */ 304 if (!ath5k_channel_ok(ah, freq, chfreq)) 305 continue; 306 307 if (!modparam_all_channels && 308 !ath5k_is_standard_channel(ch, band)) 309 continue; 310 311 /* Write channel info and increment counter */ 312 channels[count].center_freq = freq; 313 channels[count].band = band; 314 switch (mode) { 315 case AR5K_MODE_11A: 316 case AR5K_MODE_11G: 317 channels[count].hw_value = chfreq | CHANNEL_OFDM; 318 break; 319 case AR5K_MODE_11B: 320 channels[count].hw_value = CHANNEL_B; 321 } 322 323 count++; 324 } 325 326 return count; 327 } 328 329 static void 330 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) 331 { 332 u8 i; 333 334 for (i = 0; i < AR5K_MAX_RATES; i++) 335 ah->rate_idx[b->band][i] = -1; 336 337 for (i = 0; i < b->n_bitrates; i++) { 338 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; 339 if (b->bitrates[i].hw_value_short) 340 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 341 } 342 } 343 344 static int 345 ath5k_setup_bands(struct ieee80211_hw *hw) 346 { 347 struct ath5k_hw *ah = hw->priv; 348 struct ieee80211_supported_band *sband; 349 int max_c, count_c = 0; 350 int i; 351 352 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS); 353 max_c = ARRAY_SIZE(ah->channels); 354 355 /* 2GHz band */ 356 sband = &ah->sbands[IEEE80211_BAND_2GHZ]; 357 sband->band = IEEE80211_BAND_2GHZ; 358 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0]; 359 360 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { 361 /* G mode */ 362 memcpy(sband->bitrates, &ath5k_rates[0], 363 sizeof(struct ieee80211_rate) * 12); 364 sband->n_bitrates = 12; 365 366 sband->channels = ah->channels; 367 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 368 AR5K_MODE_11G, max_c); 369 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 371 count_c = sband->n_channels; 372 max_c -= count_c; 373 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { 374 /* B mode */ 375 memcpy(sband->bitrates, &ath5k_rates[0], 376 sizeof(struct ieee80211_rate) * 4); 377 sband->n_bitrates = 4; 378 379 /* 5211 only supports B rates and uses 4bit rate codes 380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 381 * fix them up here: 382 */ 383 if (ah->ah_version == AR5K_AR5211) { 384 for (i = 0; i < 4; i++) { 385 sband->bitrates[i].hw_value = 386 sband->bitrates[i].hw_value & 0xF; 387 sband->bitrates[i].hw_value_short = 388 sband->bitrates[i].hw_value_short & 0xF; 389 } 390 } 391 392 sband->channels = ah->channels; 393 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 394 AR5K_MODE_11B, max_c); 395 396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 397 count_c = sband->n_channels; 398 max_c -= count_c; 399 } 400 ath5k_setup_rate_idx(ah, sband); 401 402 /* 5GHz band, A mode */ 403 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { 404 sband = &ah->sbands[IEEE80211_BAND_5GHZ]; 405 sband->band = IEEE80211_BAND_5GHZ; 406 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0]; 407 408 memcpy(sband->bitrates, &ath5k_rates[4], 409 sizeof(struct ieee80211_rate) * 8); 410 sband->n_bitrates = 8; 411 412 sband->channels = &ah->channels[count_c]; 413 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 414 AR5K_MODE_11A, max_c); 415 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 417 } 418 ath5k_setup_rate_idx(ah, sband); 419 420 ath5k_debug_dump_bands(ah); 421 422 return 0; 423 } 424 425 /* 426 * Set/change channels. We always reset the chip. 427 * To accomplish this we must first cleanup any pending DMA, 428 * then restart stuff after a la ath5k_init. 429 * 430 * Called with ah->lock. 431 */ 432 int 433 ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan) 434 { 435 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 436 "channel set, resetting (%u -> %u MHz)\n", 437 ah->curchan->center_freq, chan->center_freq); 438 439 /* 440 * To switch channels clear any pending DMA operations; 441 * wait long enough for the RX fifo to drain, reset the 442 * hardware at the new frequency, and then re-enable 443 * the relevant bits of the h/w. 444 */ 445 return ath5k_reset(ah, chan, true); 446 } 447 448 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 449 { 450 struct ath5k_vif_iter_data *iter_data = data; 451 int i; 452 struct ath5k_vif *avf = (void *)vif->drv_priv; 453 454 if (iter_data->hw_macaddr) 455 for (i = 0; i < ETH_ALEN; i++) 456 iter_data->mask[i] &= 457 ~(iter_data->hw_macaddr[i] ^ mac[i]); 458 459 if (!iter_data->found_active) { 460 iter_data->found_active = true; 461 memcpy(iter_data->active_mac, mac, ETH_ALEN); 462 } 463 464 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 465 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0) 466 iter_data->need_set_hw_addr = false; 467 468 if (!iter_data->any_assoc) { 469 if (avf->assoc) 470 iter_data->any_assoc = true; 471 } 472 473 /* Calculate combined mode - when APs are active, operate in AP mode. 474 * Otherwise use the mode of the new interface. This can currently 475 * only deal with combinations of APs and STAs. Only one ad-hoc 476 * interfaces is allowed. 477 */ 478 if (avf->opmode == NL80211_IFTYPE_AP) 479 iter_data->opmode = NL80211_IFTYPE_AP; 480 else { 481 if (avf->opmode == NL80211_IFTYPE_STATION) 482 iter_data->n_stas++; 483 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 484 iter_data->opmode = avf->opmode; 485 } 486 } 487 488 void 489 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, 490 struct ieee80211_vif *vif) 491 { 492 struct ath_common *common = ath5k_hw_common(ah); 493 struct ath5k_vif_iter_data iter_data; 494 u32 rfilt; 495 496 /* 497 * Use the hardware MAC address as reference, the hardware uses it 498 * together with the BSSID mask when matching addresses. 499 */ 500 iter_data.hw_macaddr = common->macaddr; 501 memset(&iter_data.mask, 0xff, ETH_ALEN); 502 iter_data.found_active = false; 503 iter_data.need_set_hw_addr = true; 504 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 505 iter_data.n_stas = 0; 506 507 if (vif) 508 ath5k_vif_iter(&iter_data, vif->addr, vif); 509 510 /* Get list of all active MAC addresses */ 511 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter, 512 &iter_data); 513 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); 514 515 ah->opmode = iter_data.opmode; 516 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) 517 /* Nothing active, default to station mode */ 518 ah->opmode = NL80211_IFTYPE_STATION; 519 520 ath5k_hw_set_opmode(ah, ah->opmode); 521 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 522 ah->opmode, ath_opmode_to_string(ah->opmode)); 523 524 if (iter_data.need_set_hw_addr && iter_data.found_active) 525 ath5k_hw_set_lladdr(ah, iter_data.active_mac); 526 527 if (ath5k_hw_hasbssidmask(ah)) 528 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); 529 530 /* Set up RX Filter */ 531 if (iter_data.n_stas > 1) { 532 /* If you have multiple STA interfaces connected to 533 * different APs, ARPs are not received (most of the time?) 534 * Enabling PROMISC appears to fix that problem. 535 */ 536 ah->filter_flags |= AR5K_RX_FILTER_PROM; 537 } 538 539 rfilt = ah->filter_flags; 540 ath5k_hw_set_rx_filter(ah, rfilt); 541 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 542 } 543 544 static inline int 545 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) 546 { 547 int rix; 548 549 /* return base rate on errors */ 550 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 551 "hw_rix out of bounds: %x\n", hw_rix)) 552 return 0; 553 554 rix = ah->rate_idx[ah->curchan->band][hw_rix]; 555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 556 rix = 0; 557 558 return rix; 559 } 560 561 /***************\ 562 * Buffers setup * 563 \***************/ 564 565 static 566 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) 567 { 568 struct ath_common *common = ath5k_hw_common(ah); 569 struct sk_buff *skb; 570 571 /* 572 * Allocate buffer with headroom_needed space for the 573 * fake physical layer header at the start. 574 */ 575 skb = ath_rxbuf_alloc(common, 576 common->rx_bufsize, 577 GFP_ATOMIC); 578 579 if (!skb) { 580 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", 581 common->rx_bufsize); 582 return NULL; 583 } 584 585 *skb_addr = dma_map_single(ah->dev, 586 skb->data, common->rx_bufsize, 587 DMA_FROM_DEVICE); 588 589 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { 590 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); 591 dev_kfree_skb(skb); 592 return NULL; 593 } 594 return skb; 595 } 596 597 static int 598 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 599 { 600 struct sk_buff *skb = bf->skb; 601 struct ath5k_desc *ds; 602 int ret; 603 604 if (!skb) { 605 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); 606 if (!skb) 607 return -ENOMEM; 608 bf->skb = skb; 609 } 610 611 /* 612 * Setup descriptors. For receive we always terminate 613 * the descriptor list with a self-linked entry so we'll 614 * not get overrun under high load (as can happen with a 615 * 5212 when ANI processing enables PHY error frames). 616 * 617 * To ensure the last descriptor is self-linked we create 618 * each descriptor as self-linked and add it to the end. As 619 * each additional descriptor is added the previous self-linked 620 * entry is "fixed" naturally. This should be safe even 621 * if DMA is happening. When processing RX interrupts we 622 * never remove/process the last, self-linked, entry on the 623 * descriptor list. This ensures the hardware always has 624 * someplace to write a new frame. 625 */ 626 ds = bf->desc; 627 ds->ds_link = bf->daddr; /* link to self */ 628 ds->ds_data = bf->skbaddr; 629 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 630 if (ret) { 631 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); 632 return ret; 633 } 634 635 if (ah->rxlink != NULL) 636 *ah->rxlink = bf->daddr; 637 ah->rxlink = &ds->ds_link; 638 return 0; 639 } 640 641 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 642 { 643 struct ieee80211_hdr *hdr; 644 enum ath5k_pkt_type htype; 645 __le16 fc; 646 647 hdr = (struct ieee80211_hdr *)skb->data; 648 fc = hdr->frame_control; 649 650 if (ieee80211_is_beacon(fc)) 651 htype = AR5K_PKT_TYPE_BEACON; 652 else if (ieee80211_is_probe_resp(fc)) 653 htype = AR5K_PKT_TYPE_PROBE_RESP; 654 else if (ieee80211_is_atim(fc)) 655 htype = AR5K_PKT_TYPE_ATIM; 656 else if (ieee80211_is_pspoll(fc)) 657 htype = AR5K_PKT_TYPE_PSPOLL; 658 else 659 htype = AR5K_PKT_TYPE_NORMAL; 660 661 return htype; 662 } 663 664 static int 665 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, 666 struct ath5k_txq *txq, int padsize) 667 { 668 struct ath5k_desc *ds = bf->desc; 669 struct sk_buff *skb = bf->skb; 670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 671 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 672 struct ieee80211_rate *rate; 673 unsigned int mrr_rate[3], mrr_tries[3]; 674 int i, ret; 675 u16 hw_rate; 676 u16 cts_rate = 0; 677 u16 duration = 0; 678 u8 rc_flags; 679 680 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 681 682 /* XXX endianness */ 683 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 684 DMA_TO_DEVICE); 685 686 rate = ieee80211_get_tx_rate(ah->hw, info); 687 if (!rate) { 688 ret = -EINVAL; 689 goto err_unmap; 690 } 691 692 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 693 flags |= AR5K_TXDESC_NOACK; 694 695 rc_flags = info->control.rates[0].flags; 696 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 697 rate->hw_value_short : rate->hw_value; 698 699 pktlen = skb->len; 700 701 /* FIXME: If we are in g mode and rate is a CCK rate 702 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 703 * from tx power (value is in dB units already) */ 704 if (info->control.hw_key) { 705 keyidx = info->control.hw_key->hw_key_idx; 706 pktlen += info->control.hw_key->icv_len; 707 } 708 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 709 flags |= AR5K_TXDESC_RTSENA; 710 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 711 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, 712 info->control.vif, pktlen, info)); 713 } 714 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 715 flags |= AR5K_TXDESC_CTSENA; 716 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 717 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, 718 info->control.vif, pktlen, info)); 719 } 720 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 721 ieee80211_get_hdrlen_from_skb(skb), padsize, 722 get_hw_packet_type(skb), 723 (ah->power_level * 2), 724 hw_rate, 725 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 726 cts_rate, duration); 727 if (ret) 728 goto err_unmap; 729 730 memset(mrr_rate, 0, sizeof(mrr_rate)); 731 memset(mrr_tries, 0, sizeof(mrr_tries)); 732 for (i = 0; i < 3; i++) { 733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i); 734 if (!rate) 735 break; 736 737 mrr_rate[i] = rate->hw_value; 738 mrr_tries[i] = info->control.rates[i + 1].count; 739 } 740 741 ath5k_hw_setup_mrr_tx_desc(ah, ds, 742 mrr_rate[0], mrr_tries[0], 743 mrr_rate[1], mrr_tries[1], 744 mrr_rate[2], mrr_tries[2]); 745 746 ds->ds_link = 0; 747 ds->ds_data = bf->skbaddr; 748 749 spin_lock_bh(&txq->lock); 750 list_add_tail(&bf->list, &txq->q); 751 txq->txq_len++; 752 if (txq->link == NULL) /* is this first packet? */ 753 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 754 else /* no, so only link it */ 755 *txq->link = bf->daddr; 756 757 txq->link = &ds->ds_link; 758 ath5k_hw_start_tx_dma(ah, txq->qnum); 759 mmiowb(); 760 spin_unlock_bh(&txq->lock); 761 762 return 0; 763 err_unmap: 764 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 765 return ret; 766 } 767 768 /*******************\ 769 * Descriptors setup * 770 \*******************/ 771 772 static int 773 ath5k_desc_alloc(struct ath5k_hw *ah) 774 { 775 struct ath5k_desc *ds; 776 struct ath5k_buf *bf; 777 dma_addr_t da; 778 unsigned int i; 779 int ret; 780 781 /* allocate descriptors */ 782 ah->desc_len = sizeof(struct ath5k_desc) * 783 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 784 785 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, 786 &ah->desc_daddr, GFP_KERNEL); 787 if (ah->desc == NULL) { 788 ATH5K_ERR(ah, "can't allocate descriptors\n"); 789 ret = -ENOMEM; 790 goto err; 791 } 792 ds = ah->desc; 793 da = ah->desc_daddr; 794 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 795 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); 796 797 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 798 sizeof(struct ath5k_buf), GFP_KERNEL); 799 if (bf == NULL) { 800 ATH5K_ERR(ah, "can't allocate bufptr\n"); 801 ret = -ENOMEM; 802 goto err_free; 803 } 804 ah->bufptr = bf; 805 806 INIT_LIST_HEAD(&ah->rxbuf); 807 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 808 bf->desc = ds; 809 bf->daddr = da; 810 list_add_tail(&bf->list, &ah->rxbuf); 811 } 812 813 INIT_LIST_HEAD(&ah->txbuf); 814 ah->txbuf_len = ATH_TXBUF; 815 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 816 bf->desc = ds; 817 bf->daddr = da; 818 list_add_tail(&bf->list, &ah->txbuf); 819 } 820 821 /* beacon buffers */ 822 INIT_LIST_HEAD(&ah->bcbuf); 823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 824 bf->desc = ds; 825 bf->daddr = da; 826 list_add_tail(&bf->list, &ah->bcbuf); 827 } 828 829 return 0; 830 err_free: 831 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 832 err: 833 ah->desc = NULL; 834 return ret; 835 } 836 837 void 838 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 839 { 840 BUG_ON(!bf); 841 if (!bf->skb) 842 return; 843 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, 844 DMA_TO_DEVICE); 845 dev_kfree_skb_any(bf->skb); 846 bf->skb = NULL; 847 bf->skbaddr = 0; 848 bf->desc->ds_data = 0; 849 } 850 851 void 852 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 853 { 854 struct ath_common *common = ath5k_hw_common(ah); 855 856 BUG_ON(!bf); 857 if (!bf->skb) 858 return; 859 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, 860 DMA_FROM_DEVICE); 861 dev_kfree_skb_any(bf->skb); 862 bf->skb = NULL; 863 bf->skbaddr = 0; 864 bf->desc->ds_data = 0; 865 } 866 867 static void 868 ath5k_desc_free(struct ath5k_hw *ah) 869 { 870 struct ath5k_buf *bf; 871 872 list_for_each_entry(bf, &ah->txbuf, list) 873 ath5k_txbuf_free_skb(ah, bf); 874 list_for_each_entry(bf, &ah->rxbuf, list) 875 ath5k_rxbuf_free_skb(ah, bf); 876 list_for_each_entry(bf, &ah->bcbuf, list) 877 ath5k_txbuf_free_skb(ah, bf); 878 879 /* Free memory associated with all descriptors */ 880 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 881 ah->desc = NULL; 882 ah->desc_daddr = 0; 883 884 kfree(ah->bufptr); 885 ah->bufptr = NULL; 886 } 887 888 889 /**************\ 890 * Queues setup * 891 \**************/ 892 893 static struct ath5k_txq * 894 ath5k_txq_setup(struct ath5k_hw *ah, 895 int qtype, int subtype) 896 { 897 struct ath5k_txq *txq; 898 struct ath5k_txq_info qi = { 899 .tqi_subtype = subtype, 900 /* XXX: default values not correct for B and XR channels, 901 * but who cares? */ 902 .tqi_aifs = AR5K_TUNE_AIFS, 903 .tqi_cw_min = AR5K_TUNE_CWMIN, 904 .tqi_cw_max = AR5K_TUNE_CWMAX 905 }; 906 int qnum; 907 908 /* 909 * Enable interrupts only for EOL and DESC conditions. 910 * We mark tx descriptors to receive a DESC interrupt 911 * when a tx queue gets deep; otherwise we wait for the 912 * EOL to reap descriptors. Note that this is done to 913 * reduce interrupt load and this only defers reaping 914 * descriptors, never transmitting frames. Aside from 915 * reducing interrupts this also permits more concurrency. 916 * The only potential downside is if the tx queue backs 917 * up in which case the top half of the kernel may backup 918 * due to a lack of tx descriptors. 919 */ 920 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 921 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 922 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 923 if (qnum < 0) { 924 /* 925 * NB: don't print a message, this happens 926 * normally on parts with too few tx queues 927 */ 928 return ERR_PTR(qnum); 929 } 930 if (qnum >= ARRAY_SIZE(ah->txqs)) { 931 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n", 932 qnum, ARRAY_SIZE(ah->txqs)); 933 ath5k_hw_release_tx_queue(ah, qnum); 934 return ERR_PTR(-EINVAL); 935 } 936 txq = &ah->txqs[qnum]; 937 if (!txq->setup) { 938 txq->qnum = qnum; 939 txq->link = NULL; 940 INIT_LIST_HEAD(&txq->q); 941 spin_lock_init(&txq->lock); 942 txq->setup = true; 943 txq->txq_len = 0; 944 txq->txq_max = ATH5K_TXQ_LEN_MAX; 945 txq->txq_poll_mark = false; 946 txq->txq_stuck = 0; 947 } 948 return &ah->txqs[qnum]; 949 } 950 951 static int 952 ath5k_beaconq_setup(struct ath5k_hw *ah) 953 { 954 struct ath5k_txq_info qi = { 955 /* XXX: default values not correct for B and XR channels, 956 * but who cares? */ 957 .tqi_aifs = AR5K_TUNE_AIFS, 958 .tqi_cw_min = AR5K_TUNE_CWMIN, 959 .tqi_cw_max = AR5K_TUNE_CWMAX, 960 /* NB: for dynamic turbo, don't enable any other interrupts */ 961 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 962 }; 963 964 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 965 } 966 967 static int 968 ath5k_beaconq_config(struct ath5k_hw *ah) 969 { 970 struct ath5k_txq_info qi; 971 int ret; 972 973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); 974 if (ret) 975 goto err; 976 977 if (ah->opmode == NL80211_IFTYPE_AP || 978 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 979 /* 980 * Always burst out beacon and CAB traffic 981 * (aifs = cwmin = cwmax = 0) 982 */ 983 qi.tqi_aifs = 0; 984 qi.tqi_cw_min = 0; 985 qi.tqi_cw_max = 0; 986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { 987 /* 988 * Adhoc mode; backoff between 0 and (2 * cw_min). 989 */ 990 qi.tqi_aifs = 0; 991 qi.tqi_cw_min = 0; 992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 993 } 994 995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 998 999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); 1000 if (ret) { 1001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " 1002 "hardware queue!\n", __func__); 1003 goto err; 1004 } 1005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ 1006 if (ret) 1007 goto err; 1008 1009 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1010 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1011 if (ret) 1012 goto err; 1013 1014 qi.tqi_ready_time = (ah->bintval * 80) / 100; 1015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1016 if (ret) 1017 goto err; 1018 1019 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1020 err: 1021 return ret; 1022 } 1023 1024 /** 1025 * ath5k_drain_tx_buffs - Empty tx buffers 1026 * 1027 * @ah The &struct ath5k_hw 1028 * 1029 * Empty tx buffers from all queues in preparation 1030 * of a reset or during shutdown. 1031 * 1032 * NB: this assumes output has been stopped and 1033 * we do not need to block ath5k_tx_tasklet 1034 */ 1035 static void 1036 ath5k_drain_tx_buffs(struct ath5k_hw *ah) 1037 { 1038 struct ath5k_txq *txq; 1039 struct ath5k_buf *bf, *bf0; 1040 int i; 1041 1042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 1043 if (ah->txqs[i].setup) { 1044 txq = &ah->txqs[i]; 1045 spin_lock_bh(&txq->lock); 1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1047 ath5k_debug_printtxbuf(ah, bf); 1048 1049 ath5k_txbuf_free_skb(ah, bf); 1050 1051 spin_lock_bh(&ah->txbuflock); 1052 list_move_tail(&bf->list, &ah->txbuf); 1053 ah->txbuf_len++; 1054 txq->txq_len--; 1055 spin_unlock_bh(&ah->txbuflock); 1056 } 1057 txq->link = NULL; 1058 txq->txq_poll_mark = false; 1059 spin_unlock_bh(&txq->lock); 1060 } 1061 } 1062 } 1063 1064 static void 1065 ath5k_txq_release(struct ath5k_hw *ah) 1066 { 1067 struct ath5k_txq *txq = ah->txqs; 1068 unsigned int i; 1069 1070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) 1071 if (txq->setup) { 1072 ath5k_hw_release_tx_queue(ah, txq->qnum); 1073 txq->setup = false; 1074 } 1075 } 1076 1077 1078 /*************\ 1079 * RX Handling * 1080 \*************/ 1081 1082 /* 1083 * Enable the receive h/w following a reset. 1084 */ 1085 static int 1086 ath5k_rx_start(struct ath5k_hw *ah) 1087 { 1088 struct ath_common *common = ath5k_hw_common(ah); 1089 struct ath5k_buf *bf; 1090 int ret; 1091 1092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1093 1094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1095 common->cachelsz, common->rx_bufsize); 1096 1097 spin_lock_bh(&ah->rxbuflock); 1098 ah->rxlink = NULL; 1099 list_for_each_entry(bf, &ah->rxbuf, list) { 1100 ret = ath5k_rxbuf_setup(ah, bf); 1101 if (ret != 0) { 1102 spin_unlock_bh(&ah->rxbuflock); 1103 goto err; 1104 } 1105 } 1106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1107 ath5k_hw_set_rxdp(ah, bf->daddr); 1108 spin_unlock_bh(&ah->rxbuflock); 1109 1110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ 1112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1113 1114 return 0; 1115 err: 1116 return ret; 1117 } 1118 1119 /* 1120 * Disable the receive logic on PCU (DRU) 1121 * In preparation for a shutdown. 1122 * 1123 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1124 * does. 1125 */ 1126 static void 1127 ath5k_rx_stop(struct ath5k_hw *ah) 1128 { 1129 1130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1132 1133 ath5k_debug_printrxbuffs(ah); 1134 } 1135 1136 static unsigned int 1137 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, 1138 struct ath5k_rx_status *rs) 1139 { 1140 struct ath_common *common = ath5k_hw_common(ah); 1141 struct ieee80211_hdr *hdr = (void *)skb->data; 1142 unsigned int keyix, hlen; 1143 1144 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1145 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1146 return RX_FLAG_DECRYPTED; 1147 1148 /* Apparently when a default key is used to decrypt the packet 1149 the hw does not set the index used to decrypt. In such cases 1150 get the index from the packet. */ 1151 hlen = ieee80211_hdrlen(hdr->frame_control); 1152 if (ieee80211_has_protected(hdr->frame_control) && 1153 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1154 skb->len >= hlen + 4) { 1155 keyix = skb->data[hlen + 3] >> 6; 1156 1157 if (test_bit(keyix, common->keymap)) 1158 return RX_FLAG_DECRYPTED; 1159 } 1160 1161 return 0; 1162 } 1163 1164 1165 static void 1166 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, 1167 struct ieee80211_rx_status *rxs) 1168 { 1169 struct ath_common *common = ath5k_hw_common(ah); 1170 u64 tsf, bc_tstamp; 1171 u32 hw_tu; 1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1173 1174 if (ieee80211_is_beacon(mgmt->frame_control) && 1175 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1176 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1177 /* 1178 * Received an IBSS beacon with the same BSSID. Hardware *must* 1179 * have updated the local TSF. We have to work around various 1180 * hardware bugs, though... 1181 */ 1182 tsf = ath5k_hw_get_tsf64(ah); 1183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1184 hw_tu = TSF_TO_TU(tsf); 1185 1186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1188 (unsigned long long)bc_tstamp, 1189 (unsigned long long)rxs->mactime, 1190 (unsigned long long)(rxs->mactime - bc_tstamp), 1191 (unsigned long long)tsf); 1192 1193 /* 1194 * Sometimes the HW will give us a wrong tstamp in the rx 1195 * status, causing the timestamp extension to go wrong. 1196 * (This seems to happen especially with beacon frames bigger 1197 * than 78 byte (incl. FCS)) 1198 * But we know that the receive timestamp must be later than the 1199 * timestamp of the beacon since HW must have synced to that. 1200 * 1201 * NOTE: here we assume mactime to be after the frame was 1202 * received, not like mac80211 which defines it at the start. 1203 */ 1204 if (bc_tstamp > rxs->mactime) { 1205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1206 "fixing mactime from %llx to %llx\n", 1207 (unsigned long long)rxs->mactime, 1208 (unsigned long long)tsf); 1209 rxs->mactime = tsf; 1210 } 1211 1212 /* 1213 * Local TSF might have moved higher than our beacon timers, 1214 * in that case we have to update them to continue sending 1215 * beacons. This also takes care of synchronizing beacon sending 1216 * times with other stations. 1217 */ 1218 if (hw_tu >= ah->nexttbtt) 1219 ath5k_beacon_update_timers(ah, bc_tstamp); 1220 1221 /* Check if the beacon timers are still correct, because a TSF 1222 * update might have created a window between them - for a 1223 * longer description see the comment of this function: */ 1224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { 1225 ath5k_beacon_update_timers(ah, bc_tstamp); 1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1227 "fixed beacon timers after beacon receive\n"); 1228 } 1229 } 1230 } 1231 1232 static void 1233 ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi) 1234 { 1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1236 struct ath_common *common = ath5k_hw_common(ah); 1237 1238 /* only beacons from our BSSID */ 1239 if (!ieee80211_is_beacon(mgmt->frame_control) || 1240 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) 1241 return; 1242 1243 ewma_add(&ah->ah_beacon_rssi_avg, rssi); 1244 1245 /* in IBSS mode we should keep RSSI statistics per neighbour */ 1246 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ 1247 } 1248 1249 /* 1250 * Compute padding position. skb must contain an IEEE 802.11 frame 1251 */ 1252 static int ath5k_common_padpos(struct sk_buff *skb) 1253 { 1254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1255 __le16 frame_control = hdr->frame_control; 1256 int padpos = 24; 1257 1258 if (ieee80211_has_a4(frame_control)) 1259 padpos += ETH_ALEN; 1260 1261 if (ieee80211_is_data_qos(frame_control)) 1262 padpos += IEEE80211_QOS_CTL_LEN; 1263 1264 return padpos; 1265 } 1266 1267 /* 1268 * This function expects an 802.11 frame and returns the number of 1269 * bytes added, or -1 if we don't have enough header room. 1270 */ 1271 static int ath5k_add_padding(struct sk_buff *skb) 1272 { 1273 int padpos = ath5k_common_padpos(skb); 1274 int padsize = padpos & 3; 1275 1276 if (padsize && skb->len > padpos) { 1277 1278 if (skb_headroom(skb) < padsize) 1279 return -1; 1280 1281 skb_push(skb, padsize); 1282 memmove(skb->data, skb->data + padsize, padpos); 1283 return padsize; 1284 } 1285 1286 return 0; 1287 } 1288 1289 /* 1290 * The MAC header is padded to have 32-bit boundary if the 1291 * packet payload is non-zero. The general calculation for 1292 * padsize would take into account odd header lengths: 1293 * padsize = 4 - (hdrlen & 3); however, since only 1294 * even-length headers are used, padding can only be 0 or 2 1295 * bytes and we can optimize this a bit. We must not try to 1296 * remove padding from short control frames that do not have a 1297 * payload. 1298 * 1299 * This function expects an 802.11 frame and returns the number of 1300 * bytes removed. 1301 */ 1302 static int ath5k_remove_padding(struct sk_buff *skb) 1303 { 1304 int padpos = ath5k_common_padpos(skb); 1305 int padsize = padpos & 3; 1306 1307 if (padsize && skb->len >= padpos + padsize) { 1308 memmove(skb->data + padsize, skb->data, padpos); 1309 skb_pull(skb, padsize); 1310 return padsize; 1311 } 1312 1313 return 0; 1314 } 1315 1316 static void 1317 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, 1318 struct ath5k_rx_status *rs) 1319 { 1320 struct ieee80211_rx_status *rxs; 1321 1322 ath5k_remove_padding(skb); 1323 1324 rxs = IEEE80211_SKB_RXCB(skb); 1325 1326 rxs->flag = 0; 1327 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1328 rxs->flag |= RX_FLAG_MMIC_ERROR; 1329 1330 /* 1331 * always extend the mac timestamp, since this information is 1332 * also needed for proper IBSS merging. 1333 * 1334 * XXX: it might be too late to do it here, since rs_tstamp is 1335 * 15bit only. that means TSF extension has to be done within 1336 * 32768usec (about 32ms). it might be necessary to move this to 1337 * the interrupt handler, like it is done in madwifi. 1338 * 1339 * Unfortunately we don't know when the hardware takes the rx 1340 * timestamp (beginning of phy frame, data frame, end of rx?). 1341 * The only thing we know is that it is hardware specific... 1342 * On AR5213 it seems the rx timestamp is at the end of the 1343 * frame, but I'm not sure. 1344 * 1345 * NOTE: mac80211 defines mactime at the beginning of the first 1346 * data symbol. Since we don't have any time references it's 1347 * impossible to comply to that. This affects IBSS merge only 1348 * right now, so it's not too bad... 1349 */ 1350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); 1351 rxs->flag |= RX_FLAG_MACTIME_MPDU; 1352 1353 rxs->freq = ah->curchan->center_freq; 1354 rxs->band = ah->curchan->band; 1355 1356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; 1357 1358 rxs->antenna = rs->rs_antenna; 1359 1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1361 ah->stats.antenna_rx[rs->rs_antenna]++; 1362 else 1363 ah->stats.antenna_rx[0]++; /* invalid */ 1364 1365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); 1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); 1367 1368 if (rxs->rate_idx >= 0 && rs->rs_rate == 1369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1370 rxs->flag |= RX_FLAG_SHORTPRE; 1371 1372 trace_ath5k_rx(ah, skb); 1373 1374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi); 1375 1376 /* check beacons in IBSS mode */ 1377 if (ah->opmode == NL80211_IFTYPE_ADHOC) 1378 ath5k_check_ibss_tsf(ah, skb, rxs); 1379 1380 ieee80211_rx(ah->hw, skb); 1381 } 1382 1383 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1384 * 1385 * Check if we want to further process this frame or not. Also update 1386 * statistics. Return true if we want this frame, false if not. 1387 */ 1388 static bool 1389 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) 1390 { 1391 ah->stats.rx_all_count++; 1392 ah->stats.rx_bytes_count += rs->rs_datalen; 1393 1394 if (unlikely(rs->rs_status)) { 1395 if (rs->rs_status & AR5K_RXERR_CRC) 1396 ah->stats.rxerr_crc++; 1397 if (rs->rs_status & AR5K_RXERR_FIFO) 1398 ah->stats.rxerr_fifo++; 1399 if (rs->rs_status & AR5K_RXERR_PHY) { 1400 ah->stats.rxerr_phy++; 1401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; 1403 return false; 1404 } 1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1406 /* 1407 * Decrypt error. If the error occurred 1408 * because there was no hardware key, then 1409 * let the frame through so the upper layers 1410 * can process it. This is necessary for 5210 1411 * parts which have no way to setup a ``clear'' 1412 * key cache entry. 1413 * 1414 * XXX do key cache faulting 1415 */ 1416 ah->stats.rxerr_decrypt++; 1417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1418 !(rs->rs_status & AR5K_RXERR_CRC)) 1419 return true; 1420 } 1421 if (rs->rs_status & AR5K_RXERR_MIC) { 1422 ah->stats.rxerr_mic++; 1423 return true; 1424 } 1425 1426 /* reject any frames with non-crypto errors */ 1427 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) 1428 return false; 1429 } 1430 1431 if (unlikely(rs->rs_more)) { 1432 ah->stats.rxerr_jumbo++; 1433 return false; 1434 } 1435 return true; 1436 } 1437 1438 static void 1439 ath5k_set_current_imask(struct ath5k_hw *ah) 1440 { 1441 enum ath5k_int imask; 1442 unsigned long flags; 1443 1444 spin_lock_irqsave(&ah->irqlock, flags); 1445 imask = ah->imask; 1446 if (ah->rx_pending) 1447 imask &= ~AR5K_INT_RX_ALL; 1448 if (ah->tx_pending) 1449 imask &= ~AR5K_INT_TX_ALL; 1450 ath5k_hw_set_imr(ah, imask); 1451 spin_unlock_irqrestore(&ah->irqlock, flags); 1452 } 1453 1454 static void 1455 ath5k_tasklet_rx(unsigned long data) 1456 { 1457 struct ath5k_rx_status rs = {}; 1458 struct sk_buff *skb, *next_skb; 1459 dma_addr_t next_skb_addr; 1460 struct ath5k_hw *ah = (void *)data; 1461 struct ath_common *common = ath5k_hw_common(ah); 1462 struct ath5k_buf *bf; 1463 struct ath5k_desc *ds; 1464 int ret; 1465 1466 spin_lock(&ah->rxbuflock); 1467 if (list_empty(&ah->rxbuf)) { 1468 ATH5K_WARN(ah, "empty rx buf pool\n"); 1469 goto unlock; 1470 } 1471 do { 1472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1473 BUG_ON(bf->skb == NULL); 1474 skb = bf->skb; 1475 ds = bf->desc; 1476 1477 /* bail if HW is still using self-linked descriptor */ 1478 if (ath5k_hw_get_rxdp(ah) == bf->daddr) 1479 break; 1480 1481 ret = ah->ah_proc_rx_desc(ah, ds, &rs); 1482 if (unlikely(ret == -EINPROGRESS)) 1483 break; 1484 else if (unlikely(ret)) { 1485 ATH5K_ERR(ah, "error in processing rx descriptor\n"); 1486 ah->stats.rxerr_proc++; 1487 break; 1488 } 1489 1490 if (ath5k_receive_frame_ok(ah, &rs)) { 1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); 1492 1493 /* 1494 * If we can't replace bf->skb with a new skb under 1495 * memory pressure, just skip this packet 1496 */ 1497 if (!next_skb) 1498 goto next; 1499 1500 dma_unmap_single(ah->dev, bf->skbaddr, 1501 common->rx_bufsize, 1502 DMA_FROM_DEVICE); 1503 1504 skb_put(skb, rs.rs_datalen); 1505 1506 ath5k_receive_frame(ah, skb, &rs); 1507 1508 bf->skb = next_skb; 1509 bf->skbaddr = next_skb_addr; 1510 } 1511 next: 1512 list_move_tail(&bf->list, &ah->rxbuf); 1513 } while (ath5k_rxbuf_setup(ah, bf) == 0); 1514 unlock: 1515 spin_unlock(&ah->rxbuflock); 1516 ah->rx_pending = false; 1517 ath5k_set_current_imask(ah); 1518 } 1519 1520 1521 /*************\ 1522 * TX Handling * 1523 \*************/ 1524 1525 void 1526 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1527 struct ath5k_txq *txq) 1528 { 1529 struct ath5k_hw *ah = hw->priv; 1530 struct ath5k_buf *bf; 1531 unsigned long flags; 1532 int padsize; 1533 1534 trace_ath5k_tx(ah, skb, txq); 1535 1536 /* 1537 * The hardware expects the header padded to 4 byte boundaries. 1538 * If this is not the case, we add the padding after the header. 1539 */ 1540 padsize = ath5k_add_padding(skb); 1541 if (padsize < 0) { 1542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" 1543 " headroom to pad"); 1544 goto drop_packet; 1545 } 1546 1547 if (txq->txq_len >= txq->txq_max && 1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1549 ieee80211_stop_queue(hw, txq->qnum); 1550 1551 spin_lock_irqsave(&ah->txbuflock, flags); 1552 if (list_empty(&ah->txbuf)) { 1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); 1554 spin_unlock_irqrestore(&ah->txbuflock, flags); 1555 ieee80211_stop_queues(hw); 1556 goto drop_packet; 1557 } 1558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); 1559 list_del(&bf->list); 1560 ah->txbuf_len--; 1561 if (list_empty(&ah->txbuf)) 1562 ieee80211_stop_queues(hw); 1563 spin_unlock_irqrestore(&ah->txbuflock, flags); 1564 1565 bf->skb = skb; 1566 1567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) { 1568 bf->skb = NULL; 1569 spin_lock_irqsave(&ah->txbuflock, flags); 1570 list_add_tail(&bf->list, &ah->txbuf); 1571 ah->txbuf_len++; 1572 spin_unlock_irqrestore(&ah->txbuflock, flags); 1573 goto drop_packet; 1574 } 1575 return; 1576 1577 drop_packet: 1578 dev_kfree_skb_any(skb); 1579 } 1580 1581 static void 1582 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, 1583 struct ath5k_txq *txq, struct ath5k_tx_status *ts) 1584 { 1585 struct ieee80211_tx_info *info; 1586 u8 tries[3]; 1587 int i; 1588 1589 ah->stats.tx_all_count++; 1590 ah->stats.tx_bytes_count += skb->len; 1591 info = IEEE80211_SKB_CB(skb); 1592 1593 tries[0] = info->status.rates[0].count; 1594 tries[1] = info->status.rates[1].count; 1595 tries[2] = info->status.rates[2].count; 1596 1597 ieee80211_tx_info_clear_status(info); 1598 1599 for (i = 0; i < ts->ts_final_idx; i++) { 1600 struct ieee80211_tx_rate *r = 1601 &info->status.rates[i]; 1602 1603 r->count = tries[i]; 1604 } 1605 1606 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1607 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1608 1609 if (unlikely(ts->ts_status)) { 1610 ah->stats.ack_fail++; 1611 if (ts->ts_status & AR5K_TXERR_FILT) { 1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1613 ah->stats.txerr_filt++; 1614 } 1615 if (ts->ts_status & AR5K_TXERR_XRETRY) 1616 ah->stats.txerr_retry++; 1617 if (ts->ts_status & AR5K_TXERR_FIFO) 1618 ah->stats.txerr_fifo++; 1619 } else { 1620 info->flags |= IEEE80211_TX_STAT_ACK; 1621 info->status.ack_signal = ts->ts_rssi; 1622 1623 /* count the successful attempt as well */ 1624 info->status.rates[ts->ts_final_idx].count++; 1625 } 1626 1627 /* 1628 * Remove MAC header padding before giving the frame 1629 * back to mac80211. 1630 */ 1631 ath5k_remove_padding(skb); 1632 1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1634 ah->stats.antenna_tx[ts->ts_antenna]++; 1635 else 1636 ah->stats.antenna_tx[0]++; /* invalid */ 1637 1638 trace_ath5k_tx_complete(ah, skb, txq, ts); 1639 ieee80211_tx_status(ah->hw, skb); 1640 } 1641 1642 static void 1643 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) 1644 { 1645 struct ath5k_tx_status ts = {}; 1646 struct ath5k_buf *bf, *bf0; 1647 struct ath5k_desc *ds; 1648 struct sk_buff *skb; 1649 int ret; 1650 1651 spin_lock(&txq->lock); 1652 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1653 1654 txq->txq_poll_mark = false; 1655 1656 /* skb might already have been processed last time. */ 1657 if (bf->skb != NULL) { 1658 ds = bf->desc; 1659 1660 ret = ah->ah_proc_tx_desc(ah, ds, &ts); 1661 if (unlikely(ret == -EINPROGRESS)) 1662 break; 1663 else if (unlikely(ret)) { 1664 ATH5K_ERR(ah, 1665 "error %d while processing " 1666 "queue %u\n", ret, txq->qnum); 1667 break; 1668 } 1669 1670 skb = bf->skb; 1671 bf->skb = NULL; 1672 1673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, 1674 DMA_TO_DEVICE); 1675 ath5k_tx_frame_completed(ah, skb, txq, &ts); 1676 } 1677 1678 /* 1679 * It's possible that the hardware can say the buffer is 1680 * completed when it hasn't yet loaded the ds_link from 1681 * host memory and moved on. 1682 * Always keep the last descriptor to avoid HW races... 1683 */ 1684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { 1685 spin_lock(&ah->txbuflock); 1686 list_move_tail(&bf->list, &ah->txbuf); 1687 ah->txbuf_len++; 1688 txq->txq_len--; 1689 spin_unlock(&ah->txbuflock); 1690 } 1691 } 1692 spin_unlock(&txq->lock); 1693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1694 ieee80211_wake_queue(ah->hw, txq->qnum); 1695 } 1696 1697 static void 1698 ath5k_tasklet_tx(unsigned long data) 1699 { 1700 int i; 1701 struct ath5k_hw *ah = (void *)data; 1702 1703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1704 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i))) 1705 ath5k_tx_processq(ah, &ah->txqs[i]); 1706 1707 ah->tx_pending = false; 1708 ath5k_set_current_imask(ah); 1709 } 1710 1711 1712 /*****************\ 1713 * Beacon handling * 1714 \*****************/ 1715 1716 /* 1717 * Setup the beacon frame for transmit. 1718 */ 1719 static int 1720 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 1721 { 1722 struct sk_buff *skb = bf->skb; 1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1724 struct ath5k_desc *ds; 1725 int ret = 0; 1726 u8 antenna; 1727 u32 flags; 1728 const int padsize = 0; 1729 1730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 1731 DMA_TO_DEVICE); 1732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1733 "skbaddr %llx\n", skb, skb->data, skb->len, 1734 (unsigned long long)bf->skbaddr); 1735 1736 if (dma_mapping_error(ah->dev, bf->skbaddr)) { 1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); 1738 dev_kfree_skb_any(skb); 1739 bf->skb = NULL; 1740 return -EIO; 1741 } 1742 1743 ds = bf->desc; 1744 antenna = ah->ah_tx_ant; 1745 1746 flags = AR5K_TXDESC_NOACK; 1747 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1748 ds->ds_link = bf->daddr; /* self-linked */ 1749 flags |= AR5K_TXDESC_VEOL; 1750 } else 1751 ds->ds_link = 0; 1752 1753 /* 1754 * If we use multiple antennas on AP and use 1755 * the Sectored AP scenario, switch antenna every 1756 * 4 beacons to make sure everybody hears our AP. 1757 * When a client tries to associate, hw will keep 1758 * track of the tx antenna to be used for this client 1759 * automatically, based on ACKed packets. 1760 * 1761 * Note: AP still listens and transmits RTS on the 1762 * default antenna which is supposed to be an omni. 1763 * 1764 * Note2: On sectored scenarios it's possible to have 1765 * multiple antennas (1 omni -- the default -- and 14 1766 * sectors), so if we choose to actually support this 1767 * mode, we need to allow the user to set how many antennas 1768 * we have and tweak the code below to send beacons 1769 * on all of them. 1770 */ 1771 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1772 antenna = ah->bsent & 4 ? 2 : 1; 1773 1774 1775 /* FIXME: If we are in g mode and rate is a CCK rate 1776 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1777 * from tx power (value is in dB units already) */ 1778 ds->ds_data = bf->skbaddr; 1779 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1780 ieee80211_get_hdrlen_from_skb(skb), padsize, 1781 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2), 1782 ieee80211_get_tx_rate(ah->hw, info)->hw_value, 1783 1, AR5K_TXKEYIX_INVALID, 1784 antenna, flags, 0, 0); 1785 if (ret) 1786 goto err_unmap; 1787 1788 return 0; 1789 err_unmap: 1790 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1791 return ret; 1792 } 1793 1794 /* 1795 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1796 * this is called only once at config_bss time, for AP we do it every 1797 * SWBA interrupt so that the TIM will reflect buffered frames. 1798 * 1799 * Called with the beacon lock. 1800 */ 1801 int 1802 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1803 { 1804 int ret; 1805 struct ath5k_hw *ah = hw->priv; 1806 struct ath5k_vif *avf = (void *)vif->drv_priv; 1807 struct sk_buff *skb; 1808 1809 if (WARN_ON(!vif)) { 1810 ret = -EINVAL; 1811 goto out; 1812 } 1813 1814 skb = ieee80211_beacon_get(hw, vif); 1815 1816 if (!skb) { 1817 ret = -ENOMEM; 1818 goto out; 1819 } 1820 1821 ath5k_txbuf_free_skb(ah, avf->bbuf); 1822 avf->bbuf->skb = skb; 1823 ret = ath5k_beacon_setup(ah, avf->bbuf); 1824 out: 1825 return ret; 1826 } 1827 1828 /* 1829 * Transmit a beacon frame at SWBA. Dynamic updates to the 1830 * frame contents are done as needed and the slot time is 1831 * also adjusted based on current state. 1832 * 1833 * This is called from software irq context (beacontq tasklets) 1834 * or user context from ath5k_beacon_config. 1835 */ 1836 static void 1837 ath5k_beacon_send(struct ath5k_hw *ah) 1838 { 1839 struct ieee80211_vif *vif; 1840 struct ath5k_vif *avf; 1841 struct ath5k_buf *bf; 1842 struct sk_buff *skb; 1843 int err; 1844 1845 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1846 1847 /* 1848 * Check if the previous beacon has gone out. If 1849 * not, don't don't try to post another: skip this 1850 * period and wait for the next. Missed beacons 1851 * indicate a problem and should not occur. If we 1852 * miss too many consecutive beacons reset the device. 1853 */ 1854 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { 1855 ah->bmisscount++; 1856 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1857 "missed %u consecutive beacons\n", ah->bmisscount); 1858 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ 1859 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1860 "stuck beacon time (%u missed)\n", 1861 ah->bmisscount); 1862 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 1863 "stuck beacon, resetting\n"); 1864 ieee80211_queue_work(ah->hw, &ah->reset_work); 1865 } 1866 return; 1867 } 1868 if (unlikely(ah->bmisscount != 0)) { 1869 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1870 "resume beacon xmit after %u misses\n", 1871 ah->bmisscount); 1872 ah->bmisscount = 0; 1873 } 1874 1875 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) || 1876 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1877 u64 tsf = ath5k_hw_get_tsf64(ah); 1878 u32 tsftu = TSF_TO_TU(tsf); 1879 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; 1880 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; 1881 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1882 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1883 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); 1884 } else /* only one interface */ 1885 vif = ah->bslot[0]; 1886 1887 if (!vif) 1888 return; 1889 1890 avf = (void *)vif->drv_priv; 1891 bf = avf->bbuf; 1892 1893 /* 1894 * Stop any current dma and put the new frame on the queue. 1895 * This should never fail since we check above that no frames 1896 * are still pending on the queue. 1897 */ 1898 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { 1899 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); 1900 /* NB: hw still stops DMA, so proceed */ 1901 } 1902 1903 /* refresh the beacon for AP or MESH mode */ 1904 if (ah->opmode == NL80211_IFTYPE_AP || 1905 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1906 err = ath5k_beacon_update(ah->hw, vif); 1907 if (err) 1908 return; 1909 } 1910 1911 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || 1912 ah->opmode == NL80211_IFTYPE_MONITOR)) { 1913 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); 1914 return; 1915 } 1916 1917 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); 1918 1919 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); 1920 ath5k_hw_start_tx_dma(ah, ah->bhalq); 1921 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1922 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); 1923 1924 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1925 while (skb) { 1926 ath5k_tx_queue(ah->hw, skb, ah->cabq); 1927 1928 if (ah->cabq->txq_len >= ah->cabq->txq_max) 1929 break; 1930 1931 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1932 } 1933 1934 ah->bsent++; 1935 } 1936 1937 /** 1938 * ath5k_beacon_update_timers - update beacon timers 1939 * 1940 * @ah: struct ath5k_hw pointer we are operating on 1941 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1942 * beacon timer update based on the current HW TSF. 1943 * 1944 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 1945 * of a received beacon or the current local hardware TSF and write it to the 1946 * beacon timer registers. 1947 * 1948 * This is called in a variety of situations, e.g. when a beacon is received, 1949 * when a TSF update has been detected, but also when an new IBSS is created or 1950 * when we otherwise know we have to update the timers, but we keep it in this 1951 * function to have it all together in one place. 1952 */ 1953 void 1954 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) 1955 { 1956 u32 nexttbtt, intval, hw_tu, bc_tu; 1957 u64 hw_tsf; 1958 1959 intval = ah->bintval & AR5K_BEACON_PERIOD; 1960 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) { 1961 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 1962 if (intval < 15) 1963 ATH5K_WARN(ah, "intval %u is too low, min 15\n", 1964 intval); 1965 } 1966 if (WARN_ON(!intval)) 1967 return; 1968 1969 /* beacon TSF converted to TU */ 1970 bc_tu = TSF_TO_TU(bc_tsf); 1971 1972 /* current TSF converted to TU */ 1973 hw_tsf = ath5k_hw_get_tsf64(ah); 1974 hw_tu = TSF_TO_TU(hw_tsf); 1975 1976 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) 1977 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 1978 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 1979 * configuration we need to make sure it is bigger than that. */ 1980 1981 if (bc_tsf == -1) { 1982 /* 1983 * no beacons received, called internally. 1984 * just need to refresh timers based on HW TSF. 1985 */ 1986 nexttbtt = roundup(hw_tu + FUDGE, intval); 1987 } else if (bc_tsf == 0) { 1988 /* 1989 * no beacon received, probably called by ath5k_reset_tsf(). 1990 * reset TSF to start with 0. 1991 */ 1992 nexttbtt = intval; 1993 intval |= AR5K_BEACON_RESET_TSF; 1994 } else if (bc_tsf > hw_tsf) { 1995 /* 1996 * beacon received, SW merge happened but HW TSF not yet updated. 1997 * not possible to reconfigure timers yet, but next time we 1998 * receive a beacon with the same BSSID, the hardware will 1999 * automatically update the TSF and then we need to reconfigure 2000 * the timers. 2001 */ 2002 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2003 "need to wait for HW TSF sync\n"); 2004 return; 2005 } else { 2006 /* 2007 * most important case for beacon synchronization between STA. 2008 * 2009 * beacon received and HW TSF has been already updated by HW. 2010 * update next TBTT based on the TSF of the beacon, but make 2011 * sure it is ahead of our local TSF timer. 2012 */ 2013 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2014 } 2015 #undef FUDGE 2016 2017 ah->nexttbtt = nexttbtt; 2018 2019 intval |= AR5K_BEACON_ENA; 2020 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2021 2022 /* 2023 * debugging output last in order to preserve the time critical aspect 2024 * of this function 2025 */ 2026 if (bc_tsf == -1) 2027 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2028 "reconfigured timers based on HW TSF\n"); 2029 else if (bc_tsf == 0) 2030 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2031 "reset HW TSF and timers\n"); 2032 else 2033 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2034 "updated timers based on beacon TSF\n"); 2035 2036 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2037 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2038 (unsigned long long) bc_tsf, 2039 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2040 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2041 intval & AR5K_BEACON_PERIOD, 2042 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2043 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2044 } 2045 2046 /** 2047 * ath5k_beacon_config - Configure the beacon queues and interrupts 2048 * 2049 * @ah: struct ath5k_hw pointer we are operating on 2050 * 2051 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2052 * interrupts to detect TSF updates only. 2053 */ 2054 void 2055 ath5k_beacon_config(struct ath5k_hw *ah) 2056 { 2057 unsigned long flags; 2058 2059 spin_lock_irqsave(&ah->block, flags); 2060 ah->bmisscount = 0; 2061 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2062 2063 if (ah->enable_beacon) { 2064 /* 2065 * In IBSS mode we use a self-linked tx descriptor and let the 2066 * hardware send the beacons automatically. We have to load it 2067 * only once here. 2068 * We use the SWBA interrupt only to keep track of the beacon 2069 * timers in order to detect automatic TSF updates. 2070 */ 2071 ath5k_beaconq_config(ah); 2072 2073 ah->imask |= AR5K_INT_SWBA; 2074 2075 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2076 if (ath5k_hw_hasveol(ah)) 2077 ath5k_beacon_send(ah); 2078 } else 2079 ath5k_beacon_update_timers(ah, -1); 2080 } else { 2081 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); 2082 } 2083 2084 ath5k_hw_set_imr(ah, ah->imask); 2085 mmiowb(); 2086 spin_unlock_irqrestore(&ah->block, flags); 2087 } 2088 2089 static void ath5k_tasklet_beacon(unsigned long data) 2090 { 2091 struct ath5k_hw *ah = (struct ath5k_hw *) data; 2092 2093 /* 2094 * Software beacon alert--time to send a beacon. 2095 * 2096 * In IBSS mode we use this interrupt just to 2097 * keep track of the next TBTT (target beacon 2098 * transmission time) in order to detect whether 2099 * automatic TSF updates happened. 2100 */ 2101 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2102 /* XXX: only if VEOL supported */ 2103 u64 tsf = ath5k_hw_get_tsf64(ah); 2104 ah->nexttbtt += ah->bintval; 2105 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2106 "SWBA nexttbtt: %x hw_tu: %x " 2107 "TSF: %llx\n", 2108 ah->nexttbtt, 2109 TSF_TO_TU(tsf), 2110 (unsigned long long) tsf); 2111 } else { 2112 spin_lock(&ah->block); 2113 ath5k_beacon_send(ah); 2114 spin_unlock(&ah->block); 2115 } 2116 } 2117 2118 2119 /********************\ 2120 * Interrupt handling * 2121 \********************/ 2122 2123 static void 2124 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2125 { 2126 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2127 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) { 2128 /* run ANI only when full calibration is not active */ 2129 ah->ah_cal_next_ani = jiffies + 2130 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2131 tasklet_schedule(&ah->ani_tasklet); 2132 2133 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2134 ah->ah_cal_next_full = jiffies + 2135 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2136 tasklet_schedule(&ah->calib); 2137 } 2138 /* we could use SWI to generate enough interrupts to meet our 2139 * calibration interval requirements, if necessary: 2140 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2141 } 2142 2143 static void 2144 ath5k_schedule_rx(struct ath5k_hw *ah) 2145 { 2146 ah->rx_pending = true; 2147 tasklet_schedule(&ah->rxtq); 2148 } 2149 2150 static void 2151 ath5k_schedule_tx(struct ath5k_hw *ah) 2152 { 2153 ah->tx_pending = true; 2154 tasklet_schedule(&ah->txtq); 2155 } 2156 2157 static irqreturn_t 2158 ath5k_intr(int irq, void *dev_id) 2159 { 2160 struct ath5k_hw *ah = dev_id; 2161 enum ath5k_int status; 2162 unsigned int counter = 1000; 2163 2164 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || 2165 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2166 !ath5k_hw_is_intr_pending(ah)))) 2167 return IRQ_NONE; 2168 2169 do { 2170 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2171 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2172 status, ah->imask); 2173 if (unlikely(status & AR5K_INT_FATAL)) { 2174 /* 2175 * Fatal errors are unrecoverable. 2176 * Typically these are caused by DMA errors. 2177 */ 2178 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2179 "fatal int, resetting\n"); 2180 ieee80211_queue_work(ah->hw, &ah->reset_work); 2181 } else if (unlikely(status & AR5K_INT_RXORN)) { 2182 /* 2183 * Receive buffers are full. Either the bus is busy or 2184 * the CPU is not fast enough to process all received 2185 * frames. 2186 * Older chipsets need a reset to come out of this 2187 * condition, but we treat it as RX for newer chips. 2188 * We don't know exactly which versions need a reset - 2189 * this guess is copied from the HAL. 2190 */ 2191 ah->stats.rxorn_intr++; 2192 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2193 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2194 "rx overrun, resetting\n"); 2195 ieee80211_queue_work(ah->hw, &ah->reset_work); 2196 } else 2197 ath5k_schedule_rx(ah); 2198 } else { 2199 if (status & AR5K_INT_SWBA) 2200 tasklet_hi_schedule(&ah->beacontq); 2201 2202 if (status & AR5K_INT_RXEOL) { 2203 /* 2204 * NB: the hardware should re-read the link when 2205 * RXE bit is written, but it doesn't work at 2206 * least on older hardware revs. 2207 */ 2208 ah->stats.rxeol_intr++; 2209 } 2210 if (status & AR5K_INT_TXURN) { 2211 /* bump tx trigger level */ 2212 ath5k_hw_update_tx_triglevel(ah, true); 2213 } 2214 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2215 ath5k_schedule_rx(ah); 2216 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2217 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2218 ath5k_schedule_tx(ah); 2219 if (status & AR5K_INT_BMISS) { 2220 /* TODO */ 2221 } 2222 if (status & AR5K_INT_MIB) { 2223 ah->stats.mib_intr++; 2224 ath5k_hw_update_mib_counters(ah); 2225 ath5k_ani_mib_intr(ah); 2226 } 2227 if (status & AR5K_INT_GPIO) 2228 tasklet_schedule(&ah->rf_kill.toggleq); 2229 2230 } 2231 2232 if (ath5k_get_bus_type(ah) == ATH_AHB) 2233 break; 2234 2235 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2236 2237 if (ah->rx_pending || ah->tx_pending) 2238 ath5k_set_current_imask(ah); 2239 2240 if (unlikely(!counter)) 2241 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); 2242 2243 ath5k_intr_calibration_poll(ah); 2244 2245 return IRQ_HANDLED; 2246 } 2247 2248 /* 2249 * Periodically recalibrate the PHY to account 2250 * for temperature/environment changes. 2251 */ 2252 static void 2253 ath5k_tasklet_calibrate(unsigned long data) 2254 { 2255 struct ath5k_hw *ah = (void *)data; 2256 2257 /* Only full calibration for now */ 2258 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2259 2260 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2261 ieee80211_frequency_to_channel(ah->curchan->center_freq), 2262 ah->curchan->hw_value); 2263 2264 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2265 /* 2266 * Rfgain is out of bounds, reset the chip 2267 * to load new gain values. 2268 */ 2269 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2270 ieee80211_queue_work(ah->hw, &ah->reset_work); 2271 } 2272 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) 2273 ATH5K_ERR(ah, "calibration of channel %u failed\n", 2274 ieee80211_frequency_to_channel( 2275 ah->curchan->center_freq)); 2276 2277 /* Noise floor calibration interrupts rx/tx path while I/Q calibration 2278 * doesn't. 2279 * TODO: We should stop TX here, so that it doesn't interfere. 2280 * Note that stopping the queues is not enough to stop TX! */ 2281 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) { 2282 ah->ah_cal_next_nf = jiffies + 2283 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF); 2284 ath5k_hw_update_noise_floor(ah); 2285 } 2286 2287 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2288 } 2289 2290 2291 static void 2292 ath5k_tasklet_ani(unsigned long data) 2293 { 2294 struct ath5k_hw *ah = (void *)data; 2295 2296 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2297 ath5k_ani_calibration(ah); 2298 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2299 } 2300 2301 2302 static void 2303 ath5k_tx_complete_poll_work(struct work_struct *work) 2304 { 2305 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2306 tx_complete_work.work); 2307 struct ath5k_txq *txq; 2308 int i; 2309 bool needreset = false; 2310 2311 mutex_lock(&ah->lock); 2312 2313 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 2314 if (ah->txqs[i].setup) { 2315 txq = &ah->txqs[i]; 2316 spin_lock_bh(&txq->lock); 2317 if (txq->txq_len > 1) { 2318 if (txq->txq_poll_mark) { 2319 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, 2320 "TX queue stuck %d\n", 2321 txq->qnum); 2322 needreset = true; 2323 txq->txq_stuck++; 2324 spin_unlock_bh(&txq->lock); 2325 break; 2326 } else { 2327 txq->txq_poll_mark = true; 2328 } 2329 } 2330 spin_unlock_bh(&txq->lock); 2331 } 2332 } 2333 2334 if (needreset) { 2335 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2336 "TX queues stuck, resetting\n"); 2337 ath5k_reset(ah, NULL, true); 2338 } 2339 2340 mutex_unlock(&ah->lock); 2341 2342 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2343 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2344 } 2345 2346 2347 /*************************\ 2348 * Initialization routines * 2349 \*************************/ 2350 2351 int __devinit 2352 ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) 2353 { 2354 struct ieee80211_hw *hw = ah->hw; 2355 struct ath_common *common; 2356 int ret; 2357 int csz; 2358 2359 /* Initialize driver private data */ 2360 SET_IEEE80211_DEV(hw, ah->dev); 2361 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2362 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2363 IEEE80211_HW_SIGNAL_DBM | 2364 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 2365 2366 hw->wiphy->interface_modes = 2367 BIT(NL80211_IFTYPE_AP) | 2368 BIT(NL80211_IFTYPE_STATION) | 2369 BIT(NL80211_IFTYPE_ADHOC) | 2370 BIT(NL80211_IFTYPE_MESH_POINT); 2371 2372 /* both antennas can be configured as RX or TX */ 2373 hw->wiphy->available_antennas_tx = 0x3; 2374 hw->wiphy->available_antennas_rx = 0x3; 2375 2376 hw->extra_tx_headroom = 2; 2377 hw->channel_change_time = 5000; 2378 2379 /* 2380 * Mark the device as detached to avoid processing 2381 * interrupts until setup is complete. 2382 */ 2383 __set_bit(ATH_STAT_INVALID, ah->status); 2384 2385 ah->opmode = NL80211_IFTYPE_STATION; 2386 ah->bintval = 1000; 2387 mutex_init(&ah->lock); 2388 spin_lock_init(&ah->rxbuflock); 2389 spin_lock_init(&ah->txbuflock); 2390 spin_lock_init(&ah->block); 2391 spin_lock_init(&ah->irqlock); 2392 2393 /* Setup interrupt handler */ 2394 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); 2395 if (ret) { 2396 ATH5K_ERR(ah, "request_irq failed\n"); 2397 goto err; 2398 } 2399 2400 common = ath5k_hw_common(ah); 2401 common->ops = &ath5k_common_ops; 2402 common->bus_ops = bus_ops; 2403 common->ah = ah; 2404 common->hw = hw; 2405 common->priv = ah; 2406 common->clockrate = 40; 2407 2408 /* 2409 * Cache line size is used to size and align various 2410 * structures used to communicate with the hardware. 2411 */ 2412 ath5k_read_cachesize(common, &csz); 2413 common->cachelsz = csz << 2; /* convert to bytes */ 2414 2415 spin_lock_init(&common->cc_lock); 2416 2417 /* Initialize device */ 2418 ret = ath5k_hw_init(ah); 2419 if (ret) 2420 goto err_irq; 2421 2422 /* set up multi-rate retry capabilities */ 2423 if (ah->ah_version == AR5K_AR5212) { 2424 hw->max_rates = 4; 2425 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2426 AR5K_INIT_RETRY_LONG); 2427 } 2428 2429 hw->vif_data_size = sizeof(struct ath5k_vif); 2430 2431 /* Finish private driver data initialization */ 2432 ret = ath5k_init(hw); 2433 if (ret) 2434 goto err_ah; 2435 2436 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2437 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), 2438 ah->ah_mac_srev, 2439 ah->ah_phy_revision); 2440 2441 if (!ah->ah_single_chip) { 2442 /* Single chip radio (!RF5111) */ 2443 if (ah->ah_radio_5ghz_revision && 2444 !ah->ah_radio_2ghz_revision) { 2445 /* No 5GHz support -> report 2GHz radio */ 2446 if (!test_bit(AR5K_MODE_11A, 2447 ah->ah_capabilities.cap_mode)) { 2448 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2449 ath5k_chip_name(AR5K_VERSION_RAD, 2450 ah->ah_radio_5ghz_revision), 2451 ah->ah_radio_5ghz_revision); 2452 /* No 2GHz support (5110 and some 2453 * 5GHz only cards) -> report 5GHz radio */ 2454 } else if (!test_bit(AR5K_MODE_11B, 2455 ah->ah_capabilities.cap_mode)) { 2456 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2457 ath5k_chip_name(AR5K_VERSION_RAD, 2458 ah->ah_radio_5ghz_revision), 2459 ah->ah_radio_5ghz_revision); 2460 /* Multiband radio */ 2461 } else { 2462 ATH5K_INFO(ah, "RF%s multiband radio found" 2463 " (0x%x)\n", 2464 ath5k_chip_name(AR5K_VERSION_RAD, 2465 ah->ah_radio_5ghz_revision), 2466 ah->ah_radio_5ghz_revision); 2467 } 2468 } 2469 /* Multi chip radio (RF5111 - RF2111) -> 2470 * report both 2GHz/5GHz radios */ 2471 else if (ah->ah_radio_5ghz_revision && 2472 ah->ah_radio_2ghz_revision) { 2473 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2474 ath5k_chip_name(AR5K_VERSION_RAD, 2475 ah->ah_radio_5ghz_revision), 2476 ah->ah_radio_5ghz_revision); 2477 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2478 ath5k_chip_name(AR5K_VERSION_RAD, 2479 ah->ah_radio_2ghz_revision), 2480 ah->ah_radio_2ghz_revision); 2481 } 2482 } 2483 2484 ath5k_debug_init_device(ah); 2485 2486 /* ready to process interrupts */ 2487 __clear_bit(ATH_STAT_INVALID, ah->status); 2488 2489 return 0; 2490 err_ah: 2491 ath5k_hw_deinit(ah); 2492 err_irq: 2493 free_irq(ah->irq, ah); 2494 err: 2495 return ret; 2496 } 2497 2498 static int 2499 ath5k_stop_locked(struct ath5k_hw *ah) 2500 { 2501 2502 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", 2503 test_bit(ATH_STAT_INVALID, ah->status)); 2504 2505 /* 2506 * Shutdown the hardware and driver: 2507 * stop output from above 2508 * disable interrupts 2509 * turn off timers 2510 * turn off the radio 2511 * clear transmit machinery 2512 * clear receive machinery 2513 * drain and release tx queues 2514 * reclaim beacon resources 2515 * power down hardware 2516 * 2517 * Note that some of this work is not possible if the 2518 * hardware is gone (invalid). 2519 */ 2520 ieee80211_stop_queues(ah->hw); 2521 2522 if (!test_bit(ATH_STAT_INVALID, ah->status)) { 2523 ath5k_led_off(ah); 2524 ath5k_hw_set_imr(ah, 0); 2525 synchronize_irq(ah->irq); 2526 ath5k_rx_stop(ah); 2527 ath5k_hw_dma_stop(ah); 2528 ath5k_drain_tx_buffs(ah); 2529 ath5k_hw_phy_disable(ah); 2530 } 2531 2532 return 0; 2533 } 2534 2535 int ath5k_start(struct ieee80211_hw *hw) 2536 { 2537 struct ath5k_hw *ah = hw->priv; 2538 struct ath_common *common = ath5k_hw_common(ah); 2539 int ret, i; 2540 2541 mutex_lock(&ah->lock); 2542 2543 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); 2544 2545 /* 2546 * Stop anything previously setup. This is safe 2547 * no matter this is the first time through or not. 2548 */ 2549 ath5k_stop_locked(ah); 2550 2551 /* 2552 * The basic interface to setting the hardware in a good 2553 * state is ``reset''. On return the hardware is known to 2554 * be powered up and with interrupts disabled. This must 2555 * be followed by initialization of the appropriate bits 2556 * and then setup of the interrupt mask. 2557 */ 2558 ah->curchan = ah->hw->conf.channel; 2559 ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2560 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2561 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; 2562 2563 ret = ath5k_reset(ah, NULL, false); 2564 if (ret) 2565 goto done; 2566 2567 ath5k_rfkill_hw_start(ah); 2568 2569 /* 2570 * Reset the key cache since some parts do not reset the 2571 * contents on initial power up or resume from suspend. 2572 */ 2573 for (i = 0; i < common->keymax; i++) 2574 ath_hw_keyreset(common, (u16) i); 2575 2576 /* Use higher rates for acks instead of base 2577 * rate */ 2578 ah->ah_ack_bitrate_high = true; 2579 2580 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) 2581 ah->bslot[i] = NULL; 2582 2583 ret = 0; 2584 done: 2585 mmiowb(); 2586 mutex_unlock(&ah->lock); 2587 2588 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2589 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2590 2591 return ret; 2592 } 2593 2594 static void ath5k_stop_tasklets(struct ath5k_hw *ah) 2595 { 2596 ah->rx_pending = false; 2597 ah->tx_pending = false; 2598 tasklet_kill(&ah->rxtq); 2599 tasklet_kill(&ah->txtq); 2600 tasklet_kill(&ah->calib); 2601 tasklet_kill(&ah->beacontq); 2602 tasklet_kill(&ah->ani_tasklet); 2603 } 2604 2605 /* 2606 * Stop the device, grabbing the top-level lock to protect 2607 * against concurrent entry through ath5k_init (which can happen 2608 * if another thread does a system call and the thread doing the 2609 * stop is preempted). 2610 */ 2611 void ath5k_stop(struct ieee80211_hw *hw) 2612 { 2613 struct ath5k_hw *ah = hw->priv; 2614 int ret; 2615 2616 mutex_lock(&ah->lock); 2617 ret = ath5k_stop_locked(ah); 2618 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { 2619 /* 2620 * Don't set the card in full sleep mode! 2621 * 2622 * a) When the device is in this state it must be carefully 2623 * woken up or references to registers in the PCI clock 2624 * domain may freeze the bus (and system). This varies 2625 * by chip and is mostly an issue with newer parts 2626 * (madwifi sources mentioned srev >= 0x78) that go to 2627 * sleep more quickly. 2628 * 2629 * b) On older chips full sleep results a weird behaviour 2630 * during wakeup. I tested various cards with srev < 0x78 2631 * and they don't wake up after module reload, a second 2632 * module reload is needed to bring the card up again. 2633 * 2634 * Until we figure out what's going on don't enable 2635 * full chip reset on any chip (this is what Legacy HAL 2636 * and Sam's HAL do anyway). Instead Perform a full reset 2637 * on the device (same as initial state after attach) and 2638 * leave it idle (keep MAC/BB on warm reset) */ 2639 ret = ath5k_hw_on_hold(ah); 2640 2641 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2642 "putting device to sleep\n"); 2643 } 2644 2645 mmiowb(); 2646 mutex_unlock(&ah->lock); 2647 2648 ath5k_stop_tasklets(ah); 2649 2650 cancel_delayed_work_sync(&ah->tx_complete_work); 2651 2652 ath5k_rfkill_hw_stop(ah); 2653 } 2654 2655 /* 2656 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2657 * and change to the given channel. 2658 * 2659 * This should be called with ah->lock. 2660 */ 2661 static int 2662 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 2663 bool skip_pcu) 2664 { 2665 struct ath_common *common = ath5k_hw_common(ah); 2666 int ret, ani_mode; 2667 bool fast; 2668 2669 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); 2670 2671 ath5k_hw_set_imr(ah, 0); 2672 synchronize_irq(ah->irq); 2673 ath5k_stop_tasklets(ah); 2674 2675 /* Save ani mode and disable ANI during 2676 * reset. If we don't we might get false 2677 * PHY error interrupts. */ 2678 ani_mode = ah->ani_state.ani_mode; 2679 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2680 2681 /* We are going to empty hw queues 2682 * so we should also free any remaining 2683 * tx buffers */ 2684 ath5k_drain_tx_buffs(ah); 2685 if (chan) 2686 ah->curchan = chan; 2687 2688 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2689 2690 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); 2691 if (ret) { 2692 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); 2693 goto err; 2694 } 2695 2696 ret = ath5k_rx_start(ah); 2697 if (ret) { 2698 ATH5K_ERR(ah, "can't start recv logic\n"); 2699 goto err; 2700 } 2701 2702 ath5k_ani_init(ah, ani_mode); 2703 2704 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100); 2705 ah->ah_cal_next_ani = jiffies; 2706 ah->ah_cal_next_nf = jiffies; 2707 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2708 2709 /* clear survey data and cycle counters */ 2710 memset(&ah->survey, 0, sizeof(ah->survey)); 2711 spin_lock_bh(&common->cc_lock); 2712 ath_hw_cycle_counters_update(common); 2713 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2714 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2715 spin_unlock_bh(&common->cc_lock); 2716 2717 /* 2718 * Change channels and update the h/w rate map if we're switching; 2719 * e.g. 11a to 11b/g. 2720 * 2721 * We may be doing a reset in response to an ioctl that changes the 2722 * channel so update any state that might change as a result. 2723 * 2724 * XXX needed? 2725 */ 2726 /* ath5k_chan_change(ah, c); */ 2727 2728 ath5k_beacon_config(ah); 2729 /* intrs are enabled by ath5k_beacon_config */ 2730 2731 ieee80211_wake_queues(ah->hw); 2732 2733 return 0; 2734 err: 2735 return ret; 2736 } 2737 2738 static void ath5k_reset_work(struct work_struct *work) 2739 { 2740 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2741 reset_work); 2742 2743 mutex_lock(&ah->lock); 2744 ath5k_reset(ah, NULL, true); 2745 mutex_unlock(&ah->lock); 2746 } 2747 2748 static int __devinit 2749 ath5k_init(struct ieee80211_hw *hw) 2750 { 2751 2752 struct ath5k_hw *ah = hw->priv; 2753 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2754 struct ath5k_txq *txq; 2755 u8 mac[ETH_ALEN] = {}; 2756 int ret; 2757 2758 2759 /* 2760 * Check if the MAC has multi-rate retry support. 2761 * We do this by trying to setup a fake extended 2762 * descriptor. MACs that don't have support will 2763 * return false w/o doing anything. MACs that do 2764 * support it will return true w/o doing anything. 2765 */ 2766 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 2767 2768 if (ret < 0) 2769 goto err; 2770 if (ret > 0) 2771 __set_bit(ATH_STAT_MRRETRY, ah->status); 2772 2773 /* 2774 * Collect the channel list. The 802.11 layer 2775 * is responsible for filtering this list based 2776 * on settings like the phy mode and regulatory 2777 * domain restrictions. 2778 */ 2779 ret = ath5k_setup_bands(hw); 2780 if (ret) { 2781 ATH5K_ERR(ah, "can't get channels\n"); 2782 goto err; 2783 } 2784 2785 /* 2786 * Allocate tx+rx descriptors and populate the lists. 2787 */ 2788 ret = ath5k_desc_alloc(ah); 2789 if (ret) { 2790 ATH5K_ERR(ah, "can't allocate descriptors\n"); 2791 goto err; 2792 } 2793 2794 /* 2795 * Allocate hardware transmit queues: one queue for 2796 * beacon frames and one data queue for each QoS 2797 * priority. Note that hw functions handle resetting 2798 * these queues at the needed time. 2799 */ 2800 ret = ath5k_beaconq_setup(ah); 2801 if (ret < 0) { 2802 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); 2803 goto err_desc; 2804 } 2805 ah->bhalq = ret; 2806 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); 2807 if (IS_ERR(ah->cabq)) { 2808 ATH5K_ERR(ah, "can't setup cab queue\n"); 2809 ret = PTR_ERR(ah->cabq); 2810 goto err_bhal; 2811 } 2812 2813 /* 5211 and 5212 usually support 10 queues but we better rely on the 2814 * capability information */ 2815 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2816 /* This order matches mac80211's queue priority, so we can 2817 * directly use the mac80211 queue number without any mapping */ 2818 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2819 if (IS_ERR(txq)) { 2820 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2821 ret = PTR_ERR(txq); 2822 goto err_queues; 2823 } 2824 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2825 if (IS_ERR(txq)) { 2826 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2827 ret = PTR_ERR(txq); 2828 goto err_queues; 2829 } 2830 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2831 if (IS_ERR(txq)) { 2832 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2833 ret = PTR_ERR(txq); 2834 goto err_queues; 2835 } 2836 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2837 if (IS_ERR(txq)) { 2838 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2839 ret = PTR_ERR(txq); 2840 goto err_queues; 2841 } 2842 hw->queues = 4; 2843 } else { 2844 /* older hardware (5210) can only support one data queue */ 2845 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2846 if (IS_ERR(txq)) { 2847 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2848 ret = PTR_ERR(txq); 2849 goto err_queues; 2850 } 2851 hw->queues = 1; 2852 } 2853 2854 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah); 2855 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah); 2856 tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah); 2857 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah); 2858 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah); 2859 2860 INIT_WORK(&ah->reset_work, ath5k_reset_work); 2861 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); 2862 2863 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 2864 if (ret) { 2865 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); 2866 goto err_queues; 2867 } 2868 2869 SET_IEEE80211_PERM_ADDR(hw, mac); 2870 memcpy(&ah->lladdr, mac, ETH_ALEN); 2871 /* All MAC address bits matter for ACKs */ 2872 ath5k_update_bssid_mask_and_opmode(ah, NULL); 2873 2874 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 2875 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 2876 if (ret) { 2877 ATH5K_ERR(ah, "can't initialize regulatory system\n"); 2878 goto err_queues; 2879 } 2880 2881 ret = ieee80211_register_hw(hw); 2882 if (ret) { 2883 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); 2884 goto err_queues; 2885 } 2886 2887 if (!ath_is_world_regd(regulatory)) 2888 regulatory_hint(hw->wiphy, regulatory->alpha2); 2889 2890 ath5k_init_leds(ah); 2891 2892 ath5k_sysfs_register(ah); 2893 2894 return 0; 2895 err_queues: 2896 ath5k_txq_release(ah); 2897 err_bhal: 2898 ath5k_hw_release_tx_queue(ah, ah->bhalq); 2899 err_desc: 2900 ath5k_desc_free(ah); 2901 err: 2902 return ret; 2903 } 2904 2905 void 2906 ath5k_deinit_softc(struct ath5k_hw *ah) 2907 { 2908 struct ieee80211_hw *hw = ah->hw; 2909 2910 /* 2911 * NB: the order of these is important: 2912 * o call the 802.11 layer before detaching ath5k_hw to 2913 * ensure callbacks into the driver to delete global 2914 * key cache entries can be handled 2915 * o reclaim the tx queue data structures after calling 2916 * the 802.11 layer as we'll get called back to reclaim 2917 * node state and potentially want to use them 2918 * o to cleanup the tx queues the hal is called, so detach 2919 * it last 2920 * XXX: ??? detach ath5k_hw ??? 2921 * Other than that, it's straightforward... 2922 */ 2923 ieee80211_unregister_hw(hw); 2924 ath5k_desc_free(ah); 2925 ath5k_txq_release(ah); 2926 ath5k_hw_release_tx_queue(ah, ah->bhalq); 2927 ath5k_unregister_leds(ah); 2928 2929 ath5k_sysfs_unregister(ah); 2930 /* 2931 * NB: can't reclaim these until after ieee80211_ifdetach 2932 * returns because we'll get called back to reclaim node 2933 * state and potentially want to use them. 2934 */ 2935 ath5k_hw_deinit(ah); 2936 free_irq(ah->irq, ah); 2937 } 2938 2939 bool 2940 ath5k_any_vif_assoc(struct ath5k_hw *ah) 2941 { 2942 struct ath5k_vif_iter_data iter_data; 2943 iter_data.hw_macaddr = NULL; 2944 iter_data.any_assoc = false; 2945 iter_data.need_set_hw_addr = false; 2946 iter_data.found_active = true; 2947 2948 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter, 2949 &iter_data); 2950 return iter_data.any_assoc; 2951 } 2952 2953 void 2954 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 2955 { 2956 struct ath5k_hw *ah = hw->priv; 2957 u32 rfilt; 2958 rfilt = ath5k_hw_get_rx_filter(ah); 2959 if (enable) 2960 rfilt |= AR5K_RX_FILTER_BEACON; 2961 else 2962 rfilt &= ~AR5K_RX_FILTER_BEACON; 2963 ath5k_hw_set_rx_filter(ah, rfilt); 2964 ah->filter_flags = rfilt; 2965 } 2966