xref: /linux/drivers/net/wireless/ath/ath5k/base.c (revision 6673e2e8e040e319e0505f31580b7f1dbb5862e4)
1 /*-
2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
4  * Copyright (c) 2006 Devicescape Software, Inc.
5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7  *
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer,
15  *    without modification.
16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18  *    redistribution must be conditioned upon including a substantially
19  *    similar Disclaimer requirement for further binary redistribution.
20  * 3. Neither the names of the above-listed copyright holders nor the names
21  *    of any contributors may be used to endorse or promote products derived
22  *    from this software without specific prior written permission.
23  *
24  * Alternatively, this software may be distributed under the terms of the
25  * GNU General Public License ("GPL") version 2 as published by the Free
26  * Software Foundation.
27  *
28  * NO WARRANTY
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39  * THE POSSIBILITY OF SUCH DAMAGES.
40  *
41  */
42 
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53 #include <linux/slab.h>
54 
55 #include <net/ieee80211_radiotap.h>
56 
57 #include <asm/unaligned.h>
58 
59 #include "base.h"
60 #include "reg.h"
61 #include "debug.h"
62 #include "ani.h"
63 
64 static int modparam_nohwcrypt;
65 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
66 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 
68 static int modparam_all_channels;
69 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
70 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71 
72 
73 /******************\
74 * Internal defines *
75 \******************/
76 
77 /* Module info */
78 MODULE_AUTHOR("Jiri Slaby");
79 MODULE_AUTHOR("Nick Kossifidis");
80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82 MODULE_LICENSE("Dual BSD/GPL");
83 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
84 
85 
86 /* Known PCI ids */
87 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
88 	{ PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 	{ PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 	{ PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 	{ PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 	{ PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 	{ PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
94 	{ PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
95 	{ PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 	{ PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 	{ PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 	{ PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 	{ PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 	{ PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 	{ PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 	{ PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 	{ PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 	{ PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 	{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
106 	{ 0 }
107 };
108 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109 
110 /* Known SREVs */
111 static const struct ath5k_srev_name srev_names[] = {
112 	{ "5210",	AR5K_VERSION_MAC,	AR5K_SREV_AR5210 },
113 	{ "5311",	AR5K_VERSION_MAC,	AR5K_SREV_AR5311 },
114 	{ "5311A",	AR5K_VERSION_MAC,	AR5K_SREV_AR5311A },
115 	{ "5311B",	AR5K_VERSION_MAC,	AR5K_SREV_AR5311B },
116 	{ "5211",	AR5K_VERSION_MAC,	AR5K_SREV_AR5211 },
117 	{ "5212",	AR5K_VERSION_MAC,	AR5K_SREV_AR5212 },
118 	{ "5213",	AR5K_VERSION_MAC,	AR5K_SREV_AR5213 },
119 	{ "5213A",	AR5K_VERSION_MAC,	AR5K_SREV_AR5213A },
120 	{ "2413",	AR5K_VERSION_MAC,	AR5K_SREV_AR2413 },
121 	{ "2414",	AR5K_VERSION_MAC,	AR5K_SREV_AR2414 },
122 	{ "5424",	AR5K_VERSION_MAC,	AR5K_SREV_AR5424 },
123 	{ "5413",	AR5K_VERSION_MAC,	AR5K_SREV_AR5413 },
124 	{ "5414",	AR5K_VERSION_MAC,	AR5K_SREV_AR5414 },
125 	{ "2415",	AR5K_VERSION_MAC,	AR5K_SREV_AR2415 },
126 	{ "5416",	AR5K_VERSION_MAC,	AR5K_SREV_AR5416 },
127 	{ "5418",	AR5K_VERSION_MAC,	AR5K_SREV_AR5418 },
128 	{ "2425",	AR5K_VERSION_MAC,	AR5K_SREV_AR2425 },
129 	{ "2417",	AR5K_VERSION_MAC,	AR5K_SREV_AR2417 },
130 	{ "xxxxx",	AR5K_VERSION_MAC,	AR5K_SREV_UNKNOWN },
131 	{ "5110",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5110 },
132 	{ "5111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5111 },
133 	{ "5111A",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5111A },
134 	{ "2111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2111 },
135 	{ "5112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112 },
136 	{ "5112A",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112A },
137 	{ "5112B",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112B },
138 	{ "2112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112 },
139 	{ "2112A",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112A },
140 	{ "2112B",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112B },
141 	{ "2413",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2413 },
142 	{ "5413",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5413 },
143 	{ "2316",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2316 },
144 	{ "2317",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2317 },
145 	{ "5424",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5424 },
146 	{ "5133",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5133 },
147 	{ "xxxxx",	AR5K_VERSION_RAD,	AR5K_SREV_UNKNOWN },
148 };
149 
150 static const struct ieee80211_rate ath5k_rates[] = {
151 	{ .bitrate = 10,
152 	  .hw_value = ATH5K_RATE_CODE_1M, },
153 	{ .bitrate = 20,
154 	  .hw_value = ATH5K_RATE_CODE_2M,
155 	  .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 	  .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 	{ .bitrate = 55,
158 	  .hw_value = ATH5K_RATE_CODE_5_5M,
159 	  .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 	  .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 	{ .bitrate = 110,
162 	  .hw_value = ATH5K_RATE_CODE_11M,
163 	  .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 	  .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 	{ .bitrate = 60,
166 	  .hw_value = ATH5K_RATE_CODE_6M,
167 	  .flags = 0 },
168 	{ .bitrate = 90,
169 	  .hw_value = ATH5K_RATE_CODE_9M,
170 	  .flags = 0 },
171 	{ .bitrate = 120,
172 	  .hw_value = ATH5K_RATE_CODE_12M,
173 	  .flags = 0 },
174 	{ .bitrate = 180,
175 	  .hw_value = ATH5K_RATE_CODE_18M,
176 	  .flags = 0 },
177 	{ .bitrate = 240,
178 	  .hw_value = ATH5K_RATE_CODE_24M,
179 	  .flags = 0 },
180 	{ .bitrate = 360,
181 	  .hw_value = ATH5K_RATE_CODE_36M,
182 	  .flags = 0 },
183 	{ .bitrate = 480,
184 	  .hw_value = ATH5K_RATE_CODE_48M,
185 	  .flags = 0 },
186 	{ .bitrate = 540,
187 	  .hw_value = ATH5K_RATE_CODE_54M,
188 	  .flags = 0 },
189 	/* XR missing */
190 };
191 
192 /*
193  * Prototypes - PCI stack related functions
194  */
195 static int __devinit	ath5k_pci_probe(struct pci_dev *pdev,
196 				const struct pci_device_id *id);
197 static void __devexit	ath5k_pci_remove(struct pci_dev *pdev);
198 #ifdef CONFIG_PM
199 static int		ath5k_pci_suspend(struct device *dev);
200 static int		ath5k_pci_resume(struct device *dev);
201 
202 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
203 #define ATH5K_PM_OPS	(&ath5k_pm_ops)
204 #else
205 #define ATH5K_PM_OPS	NULL
206 #endif /* CONFIG_PM */
207 
208 static struct pci_driver ath5k_pci_driver = {
209 	.name		= KBUILD_MODNAME,
210 	.id_table	= ath5k_pci_id_table,
211 	.probe		= ath5k_pci_probe,
212 	.remove		= __devexit_p(ath5k_pci_remove),
213 	.driver.pm	= ATH5K_PM_OPS,
214 };
215 
216 
217 
218 /*
219  * Prototypes - MAC 802.11 stack related functions
220  */
221 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
222 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 		struct ath5k_txq *txq);
224 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
225 static int ath5k_reset_wake(struct ath5k_softc *sc);
226 static int ath5k_start(struct ieee80211_hw *hw);
227 static void ath5k_stop(struct ieee80211_hw *hw);
228 static int ath5k_add_interface(struct ieee80211_hw *hw,
229 		struct ieee80211_vif *vif);
230 static void ath5k_remove_interface(struct ieee80211_hw *hw,
231 		struct ieee80211_vif *vif);
232 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
233 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
234 				   struct netdev_hw_addr_list *mc_list);
235 static void ath5k_configure_filter(struct ieee80211_hw *hw,
236 		unsigned int changed_flags,
237 		unsigned int *new_flags,
238 		u64 multicast);
239 static int ath5k_set_key(struct ieee80211_hw *hw,
240 		enum set_key_cmd cmd,
241 		struct ieee80211_vif *vif, struct ieee80211_sta *sta,
242 		struct ieee80211_key_conf *key);
243 static int ath5k_get_stats(struct ieee80211_hw *hw,
244 		struct ieee80211_low_level_stats *stats);
245 static int ath5k_get_survey(struct ieee80211_hw *hw,
246 		int idx, struct survey_info *survey);
247 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
248 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
249 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
250 static int ath5k_beacon_update(struct ieee80211_hw *hw,
251 		struct ieee80211_vif *vif);
252 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
253 		struct ieee80211_vif *vif,
254 		struct ieee80211_bss_conf *bss_conf,
255 		u32 changes);
256 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
257 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
258 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
259 		u8 coverage_class);
260 
261 static const struct ieee80211_ops ath5k_hw_ops = {
262 	.tx 		= ath5k_tx,
263 	.start 		= ath5k_start,
264 	.stop 		= ath5k_stop,
265 	.add_interface 	= ath5k_add_interface,
266 	.remove_interface = ath5k_remove_interface,
267 	.config 	= ath5k_config,
268 	.prepare_multicast = ath5k_prepare_multicast,
269 	.configure_filter = ath5k_configure_filter,
270 	.set_key 	= ath5k_set_key,
271 	.get_stats 	= ath5k_get_stats,
272 	.get_survey	= ath5k_get_survey,
273 	.conf_tx 	= NULL,
274 	.get_tsf 	= ath5k_get_tsf,
275 	.set_tsf 	= ath5k_set_tsf,
276 	.reset_tsf 	= ath5k_reset_tsf,
277 	.bss_info_changed = ath5k_bss_info_changed,
278 	.sw_scan_start	= ath5k_sw_scan_start,
279 	.sw_scan_complete = ath5k_sw_scan_complete,
280 	.set_coverage_class = ath5k_set_coverage_class,
281 };
282 
283 /*
284  * Prototypes - Internal functions
285  */
286 /* Attach detach */
287 static int 	ath5k_attach(struct pci_dev *pdev,
288 			struct ieee80211_hw *hw);
289 static void 	ath5k_detach(struct pci_dev *pdev,
290 			struct ieee80211_hw *hw);
291 /* Channel/mode setup */
292 static inline short ath5k_ieee2mhz(short chan);
293 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
294 				struct ieee80211_channel *channels,
295 				unsigned int mode,
296 				unsigned int max);
297 static int 	ath5k_setup_bands(struct ieee80211_hw *hw);
298 static int 	ath5k_chan_set(struct ath5k_softc *sc,
299 				struct ieee80211_channel *chan);
300 static void	ath5k_setcurmode(struct ath5k_softc *sc,
301 				unsigned int mode);
302 static void	ath5k_mode_setup(struct ath5k_softc *sc);
303 
304 /* Descriptor setup */
305 static int	ath5k_desc_alloc(struct ath5k_softc *sc,
306 				struct pci_dev *pdev);
307 static void	ath5k_desc_free(struct ath5k_softc *sc,
308 				struct pci_dev *pdev);
309 /* Buffers setup */
310 static int 	ath5k_rxbuf_setup(struct ath5k_softc *sc,
311 				struct ath5k_buf *bf);
312 static int 	ath5k_txbuf_setup(struct ath5k_softc *sc,
313 				struct ath5k_buf *bf,
314 				struct ath5k_txq *txq, int padsize);
315 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
316 				struct ath5k_buf *bf)
317 {
318 	BUG_ON(!bf);
319 	if (!bf->skb)
320 		return;
321 	pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
322 			PCI_DMA_TODEVICE);
323 	dev_kfree_skb_any(bf->skb);
324 	bf->skb = NULL;
325 }
326 
327 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
328 				struct ath5k_buf *bf)
329 {
330 	struct ath5k_hw *ah = sc->ah;
331 	struct ath_common *common = ath5k_hw_common(ah);
332 
333 	BUG_ON(!bf);
334 	if (!bf->skb)
335 		return;
336 	pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
337 			PCI_DMA_FROMDEVICE);
338 	dev_kfree_skb_any(bf->skb);
339 	bf->skb = NULL;
340 }
341 
342 
343 /* Queues setup */
344 static struct 	ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
345 				int qtype, int subtype);
346 static int 	ath5k_beaconq_setup(struct ath5k_hw *ah);
347 static int 	ath5k_beaconq_config(struct ath5k_softc *sc);
348 static void 	ath5k_txq_drainq(struct ath5k_softc *sc,
349 				struct ath5k_txq *txq);
350 static void 	ath5k_txq_cleanup(struct ath5k_softc *sc);
351 static void 	ath5k_txq_release(struct ath5k_softc *sc);
352 /* Rx handling */
353 static int 	ath5k_rx_start(struct ath5k_softc *sc);
354 static void 	ath5k_rx_stop(struct ath5k_softc *sc);
355 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
356 					struct ath5k_desc *ds,
357 					struct sk_buff *skb,
358 					struct ath5k_rx_status *rs);
359 static void 	ath5k_tasklet_rx(unsigned long data);
360 /* Tx handling */
361 static void 	ath5k_tx_processq(struct ath5k_softc *sc,
362 				struct ath5k_txq *txq);
363 static void 	ath5k_tasklet_tx(unsigned long data);
364 /* Beacon handling */
365 static int 	ath5k_beacon_setup(struct ath5k_softc *sc,
366 					struct ath5k_buf *bf);
367 static void 	ath5k_beacon_send(struct ath5k_softc *sc);
368 static void 	ath5k_beacon_config(struct ath5k_softc *sc);
369 static void	ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
370 static void	ath5k_tasklet_beacon(unsigned long data);
371 static void	ath5k_tasklet_ani(unsigned long data);
372 
373 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
374 {
375 	u64 tsf = ath5k_hw_get_tsf64(ah);
376 
377 	if ((tsf & 0x7fff) < rstamp)
378 		tsf -= 0x8000;
379 
380 	return (tsf & ~0x7fff) | rstamp;
381 }
382 
383 /* Interrupt handling */
384 static int 	ath5k_init(struct ath5k_softc *sc);
385 static int 	ath5k_stop_locked(struct ath5k_softc *sc);
386 static int 	ath5k_stop_hw(struct ath5k_softc *sc);
387 static irqreturn_t ath5k_intr(int irq, void *dev_id);
388 static void 	ath5k_tasklet_reset(unsigned long data);
389 
390 static void 	ath5k_tasklet_calibrate(unsigned long data);
391 
392 /*
393  * Module init/exit functions
394  */
395 static int __init
396 init_ath5k_pci(void)
397 {
398 	int ret;
399 
400 	ath5k_debug_init();
401 
402 	ret = pci_register_driver(&ath5k_pci_driver);
403 	if (ret) {
404 		printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
405 		return ret;
406 	}
407 
408 	return 0;
409 }
410 
411 static void __exit
412 exit_ath5k_pci(void)
413 {
414 	pci_unregister_driver(&ath5k_pci_driver);
415 
416 	ath5k_debug_finish();
417 }
418 
419 module_init(init_ath5k_pci);
420 module_exit(exit_ath5k_pci);
421 
422 
423 /********************\
424 * PCI Initialization *
425 \********************/
426 
427 static const char *
428 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
429 {
430 	const char *name = "xxxxx";
431 	unsigned int i;
432 
433 	for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
434 		if (srev_names[i].sr_type != type)
435 			continue;
436 
437 		if ((val & 0xf0) == srev_names[i].sr_val)
438 			name = srev_names[i].sr_name;
439 
440 		if ((val & 0xff) == srev_names[i].sr_val) {
441 			name = srev_names[i].sr_name;
442 			break;
443 		}
444 	}
445 
446 	return name;
447 }
448 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
449 {
450 	struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
451 	return ath5k_hw_reg_read(ah, reg_offset);
452 }
453 
454 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
455 {
456 	struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
457 	ath5k_hw_reg_write(ah, val, reg_offset);
458 }
459 
460 static const struct ath_ops ath5k_common_ops = {
461 	.read = ath5k_ioread32,
462 	.write = ath5k_iowrite32,
463 };
464 
465 static int __devinit
466 ath5k_pci_probe(struct pci_dev *pdev,
467 		const struct pci_device_id *id)
468 {
469 	void __iomem *mem;
470 	struct ath5k_softc *sc;
471 	struct ath_common *common;
472 	struct ieee80211_hw *hw;
473 	int ret;
474 	u8 csz;
475 
476 	ret = pci_enable_device(pdev);
477 	if (ret) {
478 		dev_err(&pdev->dev, "can't enable device\n");
479 		goto err;
480 	}
481 
482 	/* XXX 32-bit addressing only */
483 	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
484 	if (ret) {
485 		dev_err(&pdev->dev, "32-bit DMA not available\n");
486 		goto err_dis;
487 	}
488 
489 	/*
490 	 * Cache line size is used to size and align various
491 	 * structures used to communicate with the hardware.
492 	 */
493 	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
494 	if (csz == 0) {
495 		/*
496 		 * Linux 2.4.18 (at least) writes the cache line size
497 		 * register as a 16-bit wide register which is wrong.
498 		 * We must have this setup properly for rx buffer
499 		 * DMA to work so force a reasonable value here if it
500 		 * comes up zero.
501 		 */
502 		csz = L1_CACHE_BYTES >> 2;
503 		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
504 	}
505 	/*
506 	 * The default setting of latency timer yields poor results,
507 	 * set it to the value used by other systems.  It may be worth
508 	 * tweaking this setting more.
509 	 */
510 	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
511 
512 	/* Enable bus mastering */
513 	pci_set_master(pdev);
514 
515 	/*
516 	 * Disable the RETRY_TIMEOUT register (0x41) to keep
517 	 * PCI Tx retries from interfering with C3 CPU state.
518 	 */
519 	pci_write_config_byte(pdev, 0x41, 0);
520 
521 	ret = pci_request_region(pdev, 0, "ath5k");
522 	if (ret) {
523 		dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
524 		goto err_dis;
525 	}
526 
527 	mem = pci_iomap(pdev, 0, 0);
528 	if (!mem) {
529 		dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
530 		ret = -EIO;
531 		goto err_reg;
532 	}
533 
534 	/*
535 	 * Allocate hw (mac80211 main struct)
536 	 * and hw->priv (driver private data)
537 	 */
538 	hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
539 	if (hw == NULL) {
540 		dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
541 		ret = -ENOMEM;
542 		goto err_map;
543 	}
544 
545 	dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
546 
547 	/* Initialize driver private data */
548 	SET_IEEE80211_DEV(hw, &pdev->dev);
549 	hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
550 		    IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
551 		    IEEE80211_HW_SIGNAL_DBM;
552 
553 	hw->wiphy->interface_modes =
554 		BIT(NL80211_IFTYPE_AP) |
555 		BIT(NL80211_IFTYPE_STATION) |
556 		BIT(NL80211_IFTYPE_ADHOC) |
557 		BIT(NL80211_IFTYPE_MESH_POINT);
558 
559 	hw->extra_tx_headroom = 2;
560 	hw->channel_change_time = 5000;
561 	sc = hw->priv;
562 	sc->hw = hw;
563 	sc->pdev = pdev;
564 
565 	ath5k_debug_init_device(sc);
566 
567 	/*
568 	 * Mark the device as detached to avoid processing
569 	 * interrupts until setup is complete.
570 	 */
571 	__set_bit(ATH_STAT_INVALID, sc->status);
572 
573 	sc->iobase = mem; /* So we can unmap it on detach */
574 	sc->opmode = NL80211_IFTYPE_STATION;
575 	sc->bintval = 1000;
576 	mutex_init(&sc->lock);
577 	spin_lock_init(&sc->rxbuflock);
578 	spin_lock_init(&sc->txbuflock);
579 	spin_lock_init(&sc->block);
580 
581 	/* Set private data */
582 	pci_set_drvdata(pdev, sc);
583 
584 	/* Setup interrupt handler */
585 	ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
586 	if (ret) {
587 		ATH5K_ERR(sc, "request_irq failed\n");
588 		goto err_free;
589 	}
590 
591 	/*If we passed the test malloc a ath5k_hw struct*/
592 	sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
593 	if (!sc->ah) {
594 		ret = -ENOMEM;
595 		ATH5K_ERR(sc, "out of memory\n");
596 		goto err_irq;
597 	}
598 
599 	sc->ah->ah_sc = sc;
600 	sc->ah->ah_iobase = sc->iobase;
601 	common = ath5k_hw_common(sc->ah);
602 	common->ops = &ath5k_common_ops;
603 	common->ah = sc->ah;
604 	common->hw = hw;
605 	common->cachelsz = csz << 2; /* convert to bytes */
606 
607 	/* Initialize device */
608 	ret = ath5k_hw_attach(sc);
609 	if (ret) {
610 		goto err_free_ah;
611 	}
612 
613 	/* set up multi-rate retry capabilities */
614 	if (sc->ah->ah_version == AR5K_AR5212) {
615 		hw->max_rates = 4;
616 		hw->max_rate_tries = 11;
617 	}
618 
619 	/* Finish private driver data initialization */
620 	ret = ath5k_attach(pdev, hw);
621 	if (ret)
622 		goto err_ah;
623 
624 	ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
625 			ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
626 					sc->ah->ah_mac_srev,
627 					sc->ah->ah_phy_revision);
628 
629 	if (!sc->ah->ah_single_chip) {
630 		/* Single chip radio (!RF5111) */
631 		if (sc->ah->ah_radio_5ghz_revision &&
632 			!sc->ah->ah_radio_2ghz_revision) {
633 			/* No 5GHz support -> report 2GHz radio */
634 			if (!test_bit(AR5K_MODE_11A,
635 				sc->ah->ah_capabilities.cap_mode)) {
636 				ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
637 					ath5k_chip_name(AR5K_VERSION_RAD,
638 						sc->ah->ah_radio_5ghz_revision),
639 						sc->ah->ah_radio_5ghz_revision);
640 			/* No 2GHz support (5110 and some
641 			 * 5Ghz only cards) -> report 5Ghz radio */
642 			} else if (!test_bit(AR5K_MODE_11B,
643 				sc->ah->ah_capabilities.cap_mode)) {
644 				ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
645 					ath5k_chip_name(AR5K_VERSION_RAD,
646 						sc->ah->ah_radio_5ghz_revision),
647 						sc->ah->ah_radio_5ghz_revision);
648 			/* Multiband radio */
649 			} else {
650 				ATH5K_INFO(sc, "RF%s multiband radio found"
651 					" (0x%x)\n",
652 					ath5k_chip_name(AR5K_VERSION_RAD,
653 						sc->ah->ah_radio_5ghz_revision),
654 						sc->ah->ah_radio_5ghz_revision);
655 			}
656 		}
657 		/* Multi chip radio (RF5111 - RF2111) ->
658 		 * report both 2GHz/5GHz radios */
659 		else if (sc->ah->ah_radio_5ghz_revision &&
660 				sc->ah->ah_radio_2ghz_revision){
661 			ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
662 				ath5k_chip_name(AR5K_VERSION_RAD,
663 					sc->ah->ah_radio_5ghz_revision),
664 					sc->ah->ah_radio_5ghz_revision);
665 			ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
666 				ath5k_chip_name(AR5K_VERSION_RAD,
667 					sc->ah->ah_radio_2ghz_revision),
668 					sc->ah->ah_radio_2ghz_revision);
669 		}
670 	}
671 
672 
673 	/* ready to process interrupts */
674 	__clear_bit(ATH_STAT_INVALID, sc->status);
675 
676 	return 0;
677 err_ah:
678 	ath5k_hw_detach(sc->ah);
679 err_irq:
680 	free_irq(pdev->irq, sc);
681 err_free_ah:
682 	kfree(sc->ah);
683 err_free:
684 	ieee80211_free_hw(hw);
685 err_map:
686 	pci_iounmap(pdev, mem);
687 err_reg:
688 	pci_release_region(pdev, 0);
689 err_dis:
690 	pci_disable_device(pdev);
691 err:
692 	return ret;
693 }
694 
695 static void __devexit
696 ath5k_pci_remove(struct pci_dev *pdev)
697 {
698 	struct ath5k_softc *sc = pci_get_drvdata(pdev);
699 
700 	ath5k_debug_finish_device(sc);
701 	ath5k_detach(pdev, sc->hw);
702 	ath5k_hw_detach(sc->ah);
703 	kfree(sc->ah);
704 	free_irq(pdev->irq, sc);
705 	pci_iounmap(pdev, sc->iobase);
706 	pci_release_region(pdev, 0);
707 	pci_disable_device(pdev);
708 	ieee80211_free_hw(sc->hw);
709 }
710 
711 #ifdef CONFIG_PM
712 static int ath5k_pci_suspend(struct device *dev)
713 {
714 	struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
715 
716 	ath5k_led_off(sc);
717 	return 0;
718 }
719 
720 static int ath5k_pci_resume(struct device *dev)
721 {
722 	struct pci_dev *pdev = to_pci_dev(dev);
723 	struct ath5k_softc *sc = pci_get_drvdata(pdev);
724 
725 	/*
726 	 * Suspend/Resume resets the PCI configuration space, so we have to
727 	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
728 	 * PCI Tx retries from interfering with C3 CPU state
729 	 */
730 	pci_write_config_byte(pdev, 0x41, 0);
731 
732 	ath5k_led_enable(sc);
733 	return 0;
734 }
735 #endif /* CONFIG_PM */
736 
737 
738 /***********************\
739 * Driver Initialization *
740 \***********************/
741 
742 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
743 {
744 	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
745 	struct ath5k_softc *sc = hw->priv;
746 	struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
747 
748 	return ath_reg_notifier_apply(wiphy, request, regulatory);
749 }
750 
751 static int
752 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
753 {
754 	struct ath5k_softc *sc = hw->priv;
755 	struct ath5k_hw *ah = sc->ah;
756 	struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
757 	u8 mac[ETH_ALEN] = {};
758 	int ret;
759 
760 	ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
761 
762 	/*
763 	 * Check if the MAC has multi-rate retry support.
764 	 * We do this by trying to setup a fake extended
765 	 * descriptor.  MAC's that don't have support will
766 	 * return false w/o doing anything.  MAC's that do
767 	 * support it will return true w/o doing anything.
768 	 */
769 	ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
770 	if (ret < 0)
771 		goto err;
772 	if (ret > 0)
773 		__set_bit(ATH_STAT_MRRETRY, sc->status);
774 
775 	/*
776 	 * Collect the channel list.  The 802.11 layer
777 	 * is resposible for filtering this list based
778 	 * on settings like the phy mode and regulatory
779 	 * domain restrictions.
780 	 */
781 	ret = ath5k_setup_bands(hw);
782 	if (ret) {
783 		ATH5K_ERR(sc, "can't get channels\n");
784 		goto err;
785 	}
786 
787 	/* NB: setup here so ath5k_rate_update is happy */
788 	if (test_bit(AR5K_MODE_11A, ah->ah_modes))
789 		ath5k_setcurmode(sc, AR5K_MODE_11A);
790 	else
791 		ath5k_setcurmode(sc, AR5K_MODE_11B);
792 
793 	/*
794 	 * Allocate tx+rx descriptors and populate the lists.
795 	 */
796 	ret = ath5k_desc_alloc(sc, pdev);
797 	if (ret) {
798 		ATH5K_ERR(sc, "can't allocate descriptors\n");
799 		goto err;
800 	}
801 
802 	/*
803 	 * Allocate hardware transmit queues: one queue for
804 	 * beacon frames and one data queue for each QoS
805 	 * priority.  Note that hw functions handle reseting
806 	 * these queues at the needed time.
807 	 */
808 	ret = ath5k_beaconq_setup(ah);
809 	if (ret < 0) {
810 		ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
811 		goto err_desc;
812 	}
813 	sc->bhalq = ret;
814 	sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
815 	if (IS_ERR(sc->cabq)) {
816 		ATH5K_ERR(sc, "can't setup cab queue\n");
817 		ret = PTR_ERR(sc->cabq);
818 		goto err_bhal;
819 	}
820 
821 	sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
822 	if (IS_ERR(sc->txq)) {
823 		ATH5K_ERR(sc, "can't setup xmit queue\n");
824 		ret = PTR_ERR(sc->txq);
825 		goto err_queues;
826 	}
827 
828 	tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
829 	tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
830 	tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
831 	tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
832 	tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
833 	tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
834 
835 	ret = ath5k_eeprom_read_mac(ah, mac);
836 	if (ret) {
837 		ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
838 			sc->pdev->device);
839 		goto err_queues;
840 	}
841 
842 	SET_IEEE80211_PERM_ADDR(hw, mac);
843 	/* All MAC address bits matter for ACKs */
844 	memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
845 	ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
846 
847 	regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
848 	ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
849 	if (ret) {
850 		ATH5K_ERR(sc, "can't initialize regulatory system\n");
851 		goto err_queues;
852 	}
853 
854 	ret = ieee80211_register_hw(hw);
855 	if (ret) {
856 		ATH5K_ERR(sc, "can't register ieee80211 hw\n");
857 		goto err_queues;
858 	}
859 
860 	if (!ath_is_world_regd(regulatory))
861 		regulatory_hint(hw->wiphy, regulatory->alpha2);
862 
863 	ath5k_init_leds(sc);
864 
865 	return 0;
866 err_queues:
867 	ath5k_txq_release(sc);
868 err_bhal:
869 	ath5k_hw_release_tx_queue(ah, sc->bhalq);
870 err_desc:
871 	ath5k_desc_free(sc, pdev);
872 err:
873 	return ret;
874 }
875 
876 static void
877 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
878 {
879 	struct ath5k_softc *sc = hw->priv;
880 
881 	/*
882 	 * NB: the order of these is important:
883 	 * o call the 802.11 layer before detaching ath5k_hw to
884 	 *   insure callbacks into the driver to delete global
885 	 *   key cache entries can be handled
886 	 * o reclaim the tx queue data structures after calling
887 	 *   the 802.11 layer as we'll get called back to reclaim
888 	 *   node state and potentially want to use them
889 	 * o to cleanup the tx queues the hal is called, so detach
890 	 *   it last
891 	 * XXX: ??? detach ath5k_hw ???
892 	 * Other than that, it's straightforward...
893 	 */
894 	ieee80211_unregister_hw(hw);
895 	ath5k_desc_free(sc, pdev);
896 	ath5k_txq_release(sc);
897 	ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
898 	ath5k_unregister_leds(sc);
899 
900 	/*
901 	 * NB: can't reclaim these until after ieee80211_ifdetach
902 	 * returns because we'll get called back to reclaim node
903 	 * state and potentially want to use them.
904 	 */
905 }
906 
907 
908 
909 
910 /********************\
911 * Channel/mode setup *
912 \********************/
913 
914 /*
915  * Convert IEEE channel number to MHz frequency.
916  */
917 static inline short
918 ath5k_ieee2mhz(short chan)
919 {
920 	if (chan <= 14 || chan >= 27)
921 		return ieee80211chan2mhz(chan);
922 	else
923 		return 2212 + chan * 20;
924 }
925 
926 /*
927  * Returns true for the channel numbers used without all_channels modparam.
928  */
929 static bool ath5k_is_standard_channel(short chan)
930 {
931 	return ((chan <= 14) ||
932 		/* UNII 1,2 */
933 		((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
934 		/* midband */
935 		((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
936 		/* UNII-3 */
937 		((chan & 3) == 1 && chan >= 149 && chan <= 165));
938 }
939 
940 static unsigned int
941 ath5k_copy_channels(struct ath5k_hw *ah,
942 		struct ieee80211_channel *channels,
943 		unsigned int mode,
944 		unsigned int max)
945 {
946 	unsigned int i, count, size, chfreq, freq, ch;
947 
948 	if (!test_bit(mode, ah->ah_modes))
949 		return 0;
950 
951 	switch (mode) {
952 	case AR5K_MODE_11A:
953 	case AR5K_MODE_11A_TURBO:
954 		/* 1..220, but 2GHz frequencies are filtered by check_channel */
955 		size = 220 ;
956 		chfreq = CHANNEL_5GHZ;
957 		break;
958 	case AR5K_MODE_11B:
959 	case AR5K_MODE_11G:
960 	case AR5K_MODE_11G_TURBO:
961 		size = 26;
962 		chfreq = CHANNEL_2GHZ;
963 		break;
964 	default:
965 		ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
966 		return 0;
967 	}
968 
969 	for (i = 0, count = 0; i < size && max > 0; i++) {
970 		ch = i + 1 ;
971 		freq = ath5k_ieee2mhz(ch);
972 
973 		/* Check if channel is supported by the chipset */
974 		if (!ath5k_channel_ok(ah, freq, chfreq))
975 			continue;
976 
977 		if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
978 			continue;
979 
980 		/* Write channel info and increment counter */
981 		channels[count].center_freq = freq;
982 		channels[count].band = (chfreq == CHANNEL_2GHZ) ?
983 			IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
984 		switch (mode) {
985 		case AR5K_MODE_11A:
986 		case AR5K_MODE_11G:
987 			channels[count].hw_value = chfreq | CHANNEL_OFDM;
988 			break;
989 		case AR5K_MODE_11A_TURBO:
990 		case AR5K_MODE_11G_TURBO:
991 			channels[count].hw_value = chfreq |
992 				CHANNEL_OFDM | CHANNEL_TURBO;
993 			break;
994 		case AR5K_MODE_11B:
995 			channels[count].hw_value = CHANNEL_B;
996 		}
997 
998 		count++;
999 		max--;
1000 	}
1001 
1002 	return count;
1003 }
1004 
1005 static void
1006 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1007 {
1008 	u8 i;
1009 
1010 	for (i = 0; i < AR5K_MAX_RATES; i++)
1011 		sc->rate_idx[b->band][i] = -1;
1012 
1013 	for (i = 0; i < b->n_bitrates; i++) {
1014 		sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1015 		if (b->bitrates[i].hw_value_short)
1016 			sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1017 	}
1018 }
1019 
1020 static int
1021 ath5k_setup_bands(struct ieee80211_hw *hw)
1022 {
1023 	struct ath5k_softc *sc = hw->priv;
1024 	struct ath5k_hw *ah = sc->ah;
1025 	struct ieee80211_supported_band *sband;
1026 	int max_c, count_c = 0;
1027 	int i;
1028 
1029 	BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1030 	max_c = ARRAY_SIZE(sc->channels);
1031 
1032 	/* 2GHz band */
1033 	sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1034 	sband->band = IEEE80211_BAND_2GHZ;
1035 	sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1036 
1037 	if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1038 		/* G mode */
1039 		memcpy(sband->bitrates, &ath5k_rates[0],
1040 		       sizeof(struct ieee80211_rate) * 12);
1041 		sband->n_bitrates = 12;
1042 
1043 		sband->channels = sc->channels;
1044 		sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1045 					AR5K_MODE_11G, max_c);
1046 
1047 		hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1048 		count_c = sband->n_channels;
1049 		max_c -= count_c;
1050 	} else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1051 		/* B mode */
1052 		memcpy(sband->bitrates, &ath5k_rates[0],
1053 		       sizeof(struct ieee80211_rate) * 4);
1054 		sband->n_bitrates = 4;
1055 
1056 		/* 5211 only supports B rates and uses 4bit rate codes
1057 		 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1058 		 * fix them up here:
1059 		 */
1060 		if (ah->ah_version == AR5K_AR5211) {
1061 			for (i = 0; i < 4; i++) {
1062 				sband->bitrates[i].hw_value =
1063 					sband->bitrates[i].hw_value & 0xF;
1064 				sband->bitrates[i].hw_value_short =
1065 					sband->bitrates[i].hw_value_short & 0xF;
1066 			}
1067 		}
1068 
1069 		sband->channels = sc->channels;
1070 		sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1071 					AR5K_MODE_11B, max_c);
1072 
1073 		hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1074 		count_c = sband->n_channels;
1075 		max_c -= count_c;
1076 	}
1077 	ath5k_setup_rate_idx(sc, sband);
1078 
1079 	/* 5GHz band, A mode */
1080 	if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1081 		sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1082 		sband->band = IEEE80211_BAND_5GHZ;
1083 		sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1084 
1085 		memcpy(sband->bitrates, &ath5k_rates[4],
1086 		       sizeof(struct ieee80211_rate) * 8);
1087 		sband->n_bitrates = 8;
1088 
1089 		sband->channels = &sc->channels[count_c];
1090 		sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1091 					AR5K_MODE_11A, max_c);
1092 
1093 		hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1094 	}
1095 	ath5k_setup_rate_idx(sc, sband);
1096 
1097 	ath5k_debug_dump_bands(sc);
1098 
1099 	return 0;
1100 }
1101 
1102 /*
1103  * Set/change channels. We always reset the chip.
1104  * To accomplish this we must first cleanup any pending DMA,
1105  * then restart stuff after a la  ath5k_init.
1106  *
1107  * Called with sc->lock.
1108  */
1109 static int
1110 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1111 {
1112 	ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1113 		sc->curchan->center_freq, chan->center_freq);
1114 
1115 	/*
1116 	 * To switch channels clear any pending DMA operations;
1117 	 * wait long enough for the RX fifo to drain, reset the
1118 	 * hardware at the new frequency, and then re-enable
1119 	 * the relevant bits of the h/w.
1120 	 */
1121 	return ath5k_reset(sc, chan);
1122 }
1123 
1124 static void
1125 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1126 {
1127 	sc->curmode = mode;
1128 
1129 	if (mode == AR5K_MODE_11A) {
1130 		sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1131 	} else {
1132 		sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1133 	}
1134 }
1135 
1136 static void
1137 ath5k_mode_setup(struct ath5k_softc *sc)
1138 {
1139 	struct ath5k_hw *ah = sc->ah;
1140 	u32 rfilt;
1141 
1142 	/* configure rx filter */
1143 	rfilt = sc->filter_flags;
1144 	ath5k_hw_set_rx_filter(ah, rfilt);
1145 
1146 	if (ath5k_hw_hasbssidmask(ah))
1147 		ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1148 
1149 	/* configure operational mode */
1150 	ath5k_hw_set_opmode(ah, sc->opmode);
1151 
1152 	ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
1153 	ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1154 }
1155 
1156 static inline int
1157 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1158 {
1159 	int rix;
1160 
1161 	/* return base rate on errors */
1162 	if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1163 			"hw_rix out of bounds: %x\n", hw_rix))
1164 		return 0;
1165 
1166 	rix = sc->rate_idx[sc->curband->band][hw_rix];
1167 	if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1168 		rix = 0;
1169 
1170 	return rix;
1171 }
1172 
1173 /***************\
1174 * Buffers setup *
1175 \***************/
1176 
1177 static
1178 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1179 {
1180 	struct ath_common *common = ath5k_hw_common(sc->ah);
1181 	struct sk_buff *skb;
1182 
1183 	/*
1184 	 * Allocate buffer with headroom_needed space for the
1185 	 * fake physical layer header at the start.
1186 	 */
1187 	skb = ath_rxbuf_alloc(common,
1188 			      common->rx_bufsize,
1189 			      GFP_ATOMIC);
1190 
1191 	if (!skb) {
1192 		ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1193 				common->rx_bufsize);
1194 		return NULL;
1195 	}
1196 
1197 	*skb_addr = pci_map_single(sc->pdev,
1198 				   skb->data, common->rx_bufsize,
1199 				   PCI_DMA_FROMDEVICE);
1200 	if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1201 		ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1202 		dev_kfree_skb(skb);
1203 		return NULL;
1204 	}
1205 	return skb;
1206 }
1207 
1208 static int
1209 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1210 {
1211 	struct ath5k_hw *ah = sc->ah;
1212 	struct sk_buff *skb = bf->skb;
1213 	struct ath5k_desc *ds;
1214 	int ret;
1215 
1216 	if (!skb) {
1217 		skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1218 		if (!skb)
1219 			return -ENOMEM;
1220 		bf->skb = skb;
1221 	}
1222 
1223 	/*
1224 	 * Setup descriptors.  For receive we always terminate
1225 	 * the descriptor list with a self-linked entry so we'll
1226 	 * not get overrun under high load (as can happen with a
1227 	 * 5212 when ANI processing enables PHY error frames).
1228 	 *
1229 	 * To insure the last descriptor is self-linked we create
1230 	 * each descriptor as self-linked and add it to the end.  As
1231 	 * each additional descriptor is added the previous self-linked
1232 	 * entry is ``fixed'' naturally.  This should be safe even
1233 	 * if DMA is happening.  When processing RX interrupts we
1234 	 * never remove/process the last, self-linked, entry on the
1235 	 * descriptor list.  This insures the hardware always has
1236 	 * someplace to write a new frame.
1237 	 */
1238 	ds = bf->desc;
1239 	ds->ds_link = bf->daddr;	/* link to self */
1240 	ds->ds_data = bf->skbaddr;
1241 	ret = ah->ah_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
1242 	if (ret)
1243 		return ret;
1244 
1245 	if (sc->rxlink != NULL)
1246 		*sc->rxlink = bf->daddr;
1247 	sc->rxlink = &ds->ds_link;
1248 	return 0;
1249 }
1250 
1251 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1252 {
1253 	struct ieee80211_hdr *hdr;
1254 	enum ath5k_pkt_type htype;
1255 	__le16 fc;
1256 
1257 	hdr = (struct ieee80211_hdr *)skb->data;
1258 	fc = hdr->frame_control;
1259 
1260 	if (ieee80211_is_beacon(fc))
1261 		htype = AR5K_PKT_TYPE_BEACON;
1262 	else if (ieee80211_is_probe_resp(fc))
1263 		htype = AR5K_PKT_TYPE_PROBE_RESP;
1264 	else if (ieee80211_is_atim(fc))
1265 		htype = AR5K_PKT_TYPE_ATIM;
1266 	else if (ieee80211_is_pspoll(fc))
1267 		htype = AR5K_PKT_TYPE_PSPOLL;
1268 	else
1269 		htype = AR5K_PKT_TYPE_NORMAL;
1270 
1271 	return htype;
1272 }
1273 
1274 static int
1275 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1276 		  struct ath5k_txq *txq, int padsize)
1277 {
1278 	struct ath5k_hw *ah = sc->ah;
1279 	struct ath5k_desc *ds = bf->desc;
1280 	struct sk_buff *skb = bf->skb;
1281 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1282 	unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1283 	struct ieee80211_rate *rate;
1284 	unsigned int mrr_rate[3], mrr_tries[3];
1285 	int i, ret;
1286 	u16 hw_rate;
1287 	u16 cts_rate = 0;
1288 	u16 duration = 0;
1289 	u8 rc_flags;
1290 
1291 	flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1292 
1293 	/* XXX endianness */
1294 	bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1295 			PCI_DMA_TODEVICE);
1296 
1297 	rate = ieee80211_get_tx_rate(sc->hw, info);
1298 
1299 	if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1300 		flags |= AR5K_TXDESC_NOACK;
1301 
1302 	rc_flags = info->control.rates[0].flags;
1303 	hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1304 		rate->hw_value_short : rate->hw_value;
1305 
1306 	pktlen = skb->len;
1307 
1308 	/* FIXME: If we are in g mode and rate is a CCK rate
1309 	 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1310 	 * from tx power (value is in dB units already) */
1311 	if (info->control.hw_key) {
1312 		keyidx = info->control.hw_key->hw_key_idx;
1313 		pktlen += info->control.hw_key->icv_len;
1314 	}
1315 	if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1316 		flags |= AR5K_TXDESC_RTSENA;
1317 		cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1318 		duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1319 			sc->vif, pktlen, info));
1320 	}
1321 	if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1322 		flags |= AR5K_TXDESC_CTSENA;
1323 		cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1324 		duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1325 			sc->vif, pktlen, info));
1326 	}
1327 	ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1328 		ieee80211_get_hdrlen_from_skb(skb), padsize,
1329 		get_hw_packet_type(skb),
1330 		(sc->power_level * 2),
1331 		hw_rate,
1332 		info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1333 		cts_rate, duration);
1334 	if (ret)
1335 		goto err_unmap;
1336 
1337 	memset(mrr_rate, 0, sizeof(mrr_rate));
1338 	memset(mrr_tries, 0, sizeof(mrr_tries));
1339 	for (i = 0; i < 3; i++) {
1340 		rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1341 		if (!rate)
1342 			break;
1343 
1344 		mrr_rate[i] = rate->hw_value;
1345 		mrr_tries[i] = info->control.rates[i + 1].count;
1346 	}
1347 
1348 	ah->ah_setup_mrr_tx_desc(ah, ds,
1349 		mrr_rate[0], mrr_tries[0],
1350 		mrr_rate[1], mrr_tries[1],
1351 		mrr_rate[2], mrr_tries[2]);
1352 
1353 	ds->ds_link = 0;
1354 	ds->ds_data = bf->skbaddr;
1355 
1356 	spin_lock_bh(&txq->lock);
1357 	list_add_tail(&bf->list, &txq->q);
1358 	if (txq->link == NULL) /* is this first packet? */
1359 		ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1360 	else /* no, so only link it */
1361 		*txq->link = bf->daddr;
1362 
1363 	txq->link = &ds->ds_link;
1364 	ath5k_hw_start_tx_dma(ah, txq->qnum);
1365 	mmiowb();
1366 	spin_unlock_bh(&txq->lock);
1367 
1368 	return 0;
1369 err_unmap:
1370 	pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1371 	return ret;
1372 }
1373 
1374 /*******************\
1375 * Descriptors setup *
1376 \*******************/
1377 
1378 static int
1379 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1380 {
1381 	struct ath5k_desc *ds;
1382 	struct ath5k_buf *bf;
1383 	dma_addr_t da;
1384 	unsigned int i;
1385 	int ret;
1386 
1387 	/* allocate descriptors */
1388 	sc->desc_len = sizeof(struct ath5k_desc) *
1389 			(ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1390 	sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1391 	if (sc->desc == NULL) {
1392 		ATH5K_ERR(sc, "can't allocate descriptors\n");
1393 		ret = -ENOMEM;
1394 		goto err;
1395 	}
1396 	ds = sc->desc;
1397 	da = sc->desc_daddr;
1398 	ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1399 		ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1400 
1401 	bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1402 			sizeof(struct ath5k_buf), GFP_KERNEL);
1403 	if (bf == NULL) {
1404 		ATH5K_ERR(sc, "can't allocate bufptr\n");
1405 		ret = -ENOMEM;
1406 		goto err_free;
1407 	}
1408 	sc->bufptr = bf;
1409 
1410 	INIT_LIST_HEAD(&sc->rxbuf);
1411 	for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1412 		bf->desc = ds;
1413 		bf->daddr = da;
1414 		list_add_tail(&bf->list, &sc->rxbuf);
1415 	}
1416 
1417 	INIT_LIST_HEAD(&sc->txbuf);
1418 	sc->txbuf_len = ATH_TXBUF;
1419 	for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1420 			da += sizeof(*ds)) {
1421 		bf->desc = ds;
1422 		bf->daddr = da;
1423 		list_add_tail(&bf->list, &sc->txbuf);
1424 	}
1425 
1426 	/* beacon buffer */
1427 	bf->desc = ds;
1428 	bf->daddr = da;
1429 	sc->bbuf = bf;
1430 
1431 	return 0;
1432 err_free:
1433 	pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1434 err:
1435 	sc->desc = NULL;
1436 	return ret;
1437 }
1438 
1439 static void
1440 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1441 {
1442 	struct ath5k_buf *bf;
1443 
1444 	ath5k_txbuf_free(sc, sc->bbuf);
1445 	list_for_each_entry(bf, &sc->txbuf, list)
1446 		ath5k_txbuf_free(sc, bf);
1447 	list_for_each_entry(bf, &sc->rxbuf, list)
1448 		ath5k_rxbuf_free(sc, bf);
1449 
1450 	/* Free memory associated with all descriptors */
1451 	pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1452 
1453 	kfree(sc->bufptr);
1454 	sc->bufptr = NULL;
1455 }
1456 
1457 
1458 
1459 
1460 
1461 /**************\
1462 * Queues setup *
1463 \**************/
1464 
1465 static struct ath5k_txq *
1466 ath5k_txq_setup(struct ath5k_softc *sc,
1467 		int qtype, int subtype)
1468 {
1469 	struct ath5k_hw *ah = sc->ah;
1470 	struct ath5k_txq *txq;
1471 	struct ath5k_txq_info qi = {
1472 		.tqi_subtype = subtype,
1473 		.tqi_aifs = AR5K_TXQ_USEDEFAULT,
1474 		.tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1475 		.tqi_cw_max = AR5K_TXQ_USEDEFAULT
1476 	};
1477 	int qnum;
1478 
1479 	/*
1480 	 * Enable interrupts only for EOL and DESC conditions.
1481 	 * We mark tx descriptors to receive a DESC interrupt
1482 	 * when a tx queue gets deep; otherwise waiting for the
1483 	 * EOL to reap descriptors.  Note that this is done to
1484 	 * reduce interrupt load and this only defers reaping
1485 	 * descriptors, never transmitting frames.  Aside from
1486 	 * reducing interrupts this also permits more concurrency.
1487 	 * The only potential downside is if the tx queue backs
1488 	 * up in which case the top half of the kernel may backup
1489 	 * due to a lack of tx descriptors.
1490 	 */
1491 	qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1492 				AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1493 	qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1494 	if (qnum < 0) {
1495 		/*
1496 		 * NB: don't print a message, this happens
1497 		 * normally on parts with too few tx queues
1498 		 */
1499 		return ERR_PTR(qnum);
1500 	}
1501 	if (qnum >= ARRAY_SIZE(sc->txqs)) {
1502 		ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1503 			qnum, ARRAY_SIZE(sc->txqs));
1504 		ath5k_hw_release_tx_queue(ah, qnum);
1505 		return ERR_PTR(-EINVAL);
1506 	}
1507 	txq = &sc->txqs[qnum];
1508 	if (!txq->setup) {
1509 		txq->qnum = qnum;
1510 		txq->link = NULL;
1511 		INIT_LIST_HEAD(&txq->q);
1512 		spin_lock_init(&txq->lock);
1513 		txq->setup = true;
1514 	}
1515 	return &sc->txqs[qnum];
1516 }
1517 
1518 static int
1519 ath5k_beaconq_setup(struct ath5k_hw *ah)
1520 {
1521 	struct ath5k_txq_info qi = {
1522 		.tqi_aifs = AR5K_TXQ_USEDEFAULT,
1523 		.tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1524 		.tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1525 		/* NB: for dynamic turbo, don't enable any other interrupts */
1526 		.tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1527 	};
1528 
1529 	return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1530 }
1531 
1532 static int
1533 ath5k_beaconq_config(struct ath5k_softc *sc)
1534 {
1535 	struct ath5k_hw *ah = sc->ah;
1536 	struct ath5k_txq_info qi;
1537 	int ret;
1538 
1539 	ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1540 	if (ret)
1541 		goto err;
1542 
1543 	if (sc->opmode == NL80211_IFTYPE_AP ||
1544 		sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1545 		/*
1546 		 * Always burst out beacon and CAB traffic
1547 		 * (aifs = cwmin = cwmax = 0)
1548 		 */
1549 		qi.tqi_aifs = 0;
1550 		qi.tqi_cw_min = 0;
1551 		qi.tqi_cw_max = 0;
1552 	} else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1553 		/*
1554 		 * Adhoc mode; backoff between 0 and (2 * cw_min).
1555 		 */
1556 		qi.tqi_aifs = 0;
1557 		qi.tqi_cw_min = 0;
1558 		qi.tqi_cw_max = 2 * ah->ah_cw_min;
1559 	}
1560 
1561 	ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1562 		"beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1563 		qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1564 
1565 	ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1566 	if (ret) {
1567 		ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1568 			"hardware queue!\n", __func__);
1569 		goto err;
1570 	}
1571 	ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1572 	if (ret)
1573 		goto err;
1574 
1575 	/* reconfigure cabq with ready time to 80% of beacon_interval */
1576 	ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1577 	if (ret)
1578 		goto err;
1579 
1580 	qi.tqi_ready_time = (sc->bintval * 80) / 100;
1581 	ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1582 	if (ret)
1583 		goto err;
1584 
1585 	ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1586 err:
1587 	return ret;
1588 }
1589 
1590 static void
1591 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1592 {
1593 	struct ath5k_buf *bf, *bf0;
1594 
1595 	/*
1596 	 * NB: this assumes output has been stopped and
1597 	 *     we do not need to block ath5k_tx_tasklet
1598 	 */
1599 	spin_lock_bh(&txq->lock);
1600 	list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1601 		ath5k_debug_printtxbuf(sc, bf);
1602 
1603 		ath5k_txbuf_free(sc, bf);
1604 
1605 		spin_lock_bh(&sc->txbuflock);
1606 		list_move_tail(&bf->list, &sc->txbuf);
1607 		sc->txbuf_len++;
1608 		spin_unlock_bh(&sc->txbuflock);
1609 	}
1610 	txq->link = NULL;
1611 	spin_unlock_bh(&txq->lock);
1612 }
1613 
1614 /*
1615  * Drain the transmit queues and reclaim resources.
1616  */
1617 static void
1618 ath5k_txq_cleanup(struct ath5k_softc *sc)
1619 {
1620 	struct ath5k_hw *ah = sc->ah;
1621 	unsigned int i;
1622 
1623 	/* XXX return value */
1624 	if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1625 		/* don't touch the hardware if marked invalid */
1626 		ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1627 		ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1628 			ath5k_hw_get_txdp(ah, sc->bhalq));
1629 		for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1630 			if (sc->txqs[i].setup) {
1631 				ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1632 				ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1633 					"link %p\n",
1634 					sc->txqs[i].qnum,
1635 					ath5k_hw_get_txdp(ah,
1636 							sc->txqs[i].qnum),
1637 					sc->txqs[i].link);
1638 			}
1639 	}
1640 
1641 	for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1642 		if (sc->txqs[i].setup)
1643 			ath5k_txq_drainq(sc, &sc->txqs[i]);
1644 }
1645 
1646 static void
1647 ath5k_txq_release(struct ath5k_softc *sc)
1648 {
1649 	struct ath5k_txq *txq = sc->txqs;
1650 	unsigned int i;
1651 
1652 	for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1653 		if (txq->setup) {
1654 			ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1655 			txq->setup = false;
1656 		}
1657 }
1658 
1659 
1660 
1661 
1662 /*************\
1663 * RX Handling *
1664 \*************/
1665 
1666 /*
1667  * Enable the receive h/w following a reset.
1668  */
1669 static int
1670 ath5k_rx_start(struct ath5k_softc *sc)
1671 {
1672 	struct ath5k_hw *ah = sc->ah;
1673 	struct ath_common *common = ath5k_hw_common(ah);
1674 	struct ath5k_buf *bf;
1675 	int ret;
1676 
1677 	common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1678 
1679 	ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1680 		  common->cachelsz, common->rx_bufsize);
1681 
1682 	spin_lock_bh(&sc->rxbuflock);
1683 	sc->rxlink = NULL;
1684 	list_for_each_entry(bf, &sc->rxbuf, list) {
1685 		ret = ath5k_rxbuf_setup(sc, bf);
1686 		if (ret != 0) {
1687 			spin_unlock_bh(&sc->rxbuflock);
1688 			goto err;
1689 		}
1690 	}
1691 	bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1692 	ath5k_hw_set_rxdp(ah, bf->daddr);
1693 	spin_unlock_bh(&sc->rxbuflock);
1694 
1695 	ath5k_hw_start_rx_dma(ah);	/* enable recv descriptors */
1696 	ath5k_mode_setup(sc);		/* set filters, etc. */
1697 	ath5k_hw_start_rx_pcu(ah);	/* re-enable PCU/DMA engine */
1698 
1699 	return 0;
1700 err:
1701 	return ret;
1702 }
1703 
1704 /*
1705  * Disable the receive h/w in preparation for a reset.
1706  */
1707 static void
1708 ath5k_rx_stop(struct ath5k_softc *sc)
1709 {
1710 	struct ath5k_hw *ah = sc->ah;
1711 
1712 	ath5k_hw_stop_rx_pcu(ah);	/* disable PCU */
1713 	ath5k_hw_set_rx_filter(ah, 0);	/* clear recv filter */
1714 	ath5k_hw_stop_rx_dma(ah);	/* disable DMA engine */
1715 
1716 	ath5k_debug_printrxbuffs(sc, ah);
1717 
1718 	sc->rxlink = NULL;		/* just in case */
1719 }
1720 
1721 static unsigned int
1722 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1723 		struct sk_buff *skb, struct ath5k_rx_status *rs)
1724 {
1725 	struct ath5k_hw *ah = sc->ah;
1726 	struct ath_common *common = ath5k_hw_common(ah);
1727 	struct ieee80211_hdr *hdr = (void *)skb->data;
1728 	unsigned int keyix, hlen;
1729 
1730 	if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1731 			rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1732 		return RX_FLAG_DECRYPTED;
1733 
1734 	/* Apparently when a default key is used to decrypt the packet
1735 	   the hw does not set the index used to decrypt.  In such cases
1736 	   get the index from the packet. */
1737 	hlen = ieee80211_hdrlen(hdr->frame_control);
1738 	if (ieee80211_has_protected(hdr->frame_control) &&
1739 	    !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1740 	    skb->len >= hlen + 4) {
1741 		keyix = skb->data[hlen + 3] >> 6;
1742 
1743 		if (test_bit(keyix, common->keymap))
1744 			return RX_FLAG_DECRYPTED;
1745 	}
1746 
1747 	return 0;
1748 }
1749 
1750 
1751 static void
1752 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1753 		     struct ieee80211_rx_status *rxs)
1754 {
1755 	struct ath_common *common = ath5k_hw_common(sc->ah);
1756 	u64 tsf, bc_tstamp;
1757 	u32 hw_tu;
1758 	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1759 
1760 	if (ieee80211_is_beacon(mgmt->frame_control) &&
1761 	    le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1762 	    memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1763 		/*
1764 		 * Received an IBSS beacon with the same BSSID. Hardware *must*
1765 		 * have updated the local TSF. We have to work around various
1766 		 * hardware bugs, though...
1767 		 */
1768 		tsf = ath5k_hw_get_tsf64(sc->ah);
1769 		bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1770 		hw_tu = TSF_TO_TU(tsf);
1771 
1772 		ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1773 			"beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1774 			(unsigned long long)bc_tstamp,
1775 			(unsigned long long)rxs->mactime,
1776 			(unsigned long long)(rxs->mactime - bc_tstamp),
1777 			(unsigned long long)tsf);
1778 
1779 		/*
1780 		 * Sometimes the HW will give us a wrong tstamp in the rx
1781 		 * status, causing the timestamp extension to go wrong.
1782 		 * (This seems to happen especially with beacon frames bigger
1783 		 * than 78 byte (incl. FCS))
1784 		 * But we know that the receive timestamp must be later than the
1785 		 * timestamp of the beacon since HW must have synced to that.
1786 		 *
1787 		 * NOTE: here we assume mactime to be after the frame was
1788 		 * received, not like mac80211 which defines it at the start.
1789 		 */
1790 		if (bc_tstamp > rxs->mactime) {
1791 			ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1792 				"fixing mactime from %llx to %llx\n",
1793 				(unsigned long long)rxs->mactime,
1794 				(unsigned long long)tsf);
1795 			rxs->mactime = tsf;
1796 		}
1797 
1798 		/*
1799 		 * Local TSF might have moved higher than our beacon timers,
1800 		 * in that case we have to update them to continue sending
1801 		 * beacons. This also takes care of synchronizing beacon sending
1802 		 * times with other stations.
1803 		 */
1804 		if (hw_tu >= sc->nexttbtt)
1805 			ath5k_beacon_update_timers(sc, bc_tstamp);
1806 	}
1807 }
1808 
1809 static void
1810 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1811 {
1812 	struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1813 	struct ath5k_hw *ah = sc->ah;
1814 	struct ath_common *common = ath5k_hw_common(ah);
1815 
1816 	/* only beacons from our BSSID */
1817 	if (!ieee80211_is_beacon(mgmt->frame_control) ||
1818 	    memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1819 		return;
1820 
1821 	ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1822 						      rssi);
1823 
1824 	/* in IBSS mode we should keep RSSI statistics per neighbour */
1825 	/* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1826 }
1827 
1828 /*
1829  * Compute padding position. skb must contains an IEEE 802.11 frame
1830  */
1831 static int ath5k_common_padpos(struct sk_buff *skb)
1832 {
1833 	struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1834 	__le16 frame_control = hdr->frame_control;
1835 	int padpos = 24;
1836 
1837 	if (ieee80211_has_a4(frame_control)) {
1838 		padpos += ETH_ALEN;
1839 	}
1840 	if (ieee80211_is_data_qos(frame_control)) {
1841 		padpos += IEEE80211_QOS_CTL_LEN;
1842 	}
1843 
1844 	return padpos;
1845 }
1846 
1847 /*
1848  * This function expects a 802.11 frame and returns the number of
1849  * bytes added, or -1 if we don't have enought header room.
1850  */
1851 
1852 static int ath5k_add_padding(struct sk_buff *skb)
1853 {
1854 	int padpos = ath5k_common_padpos(skb);
1855 	int padsize = padpos & 3;
1856 
1857 	if (padsize && skb->len>padpos) {
1858 
1859 		if (skb_headroom(skb) < padsize)
1860 			return -1;
1861 
1862 		skb_push(skb, padsize);
1863 		memmove(skb->data, skb->data+padsize, padpos);
1864 		return padsize;
1865 	}
1866 
1867 	return 0;
1868 }
1869 
1870 /*
1871  * This function expects a 802.11 frame and returns the number of
1872  * bytes removed
1873  */
1874 
1875 static int ath5k_remove_padding(struct sk_buff *skb)
1876 {
1877 	int padpos = ath5k_common_padpos(skb);
1878 	int padsize = padpos & 3;
1879 
1880 	if (padsize && skb->len>=padpos+padsize) {
1881 		memmove(skb->data + padsize, skb->data, padpos);
1882 		skb_pull(skb, padsize);
1883 		return padsize;
1884 	}
1885 
1886 	return 0;
1887 }
1888 
1889 static void
1890 ath5k_tasklet_rx(unsigned long data)
1891 {
1892 	struct ieee80211_rx_status *rxs;
1893 	struct ath5k_rx_status rs = {};
1894 	struct sk_buff *skb, *next_skb;
1895 	dma_addr_t next_skb_addr;
1896 	struct ath5k_softc *sc = (void *)data;
1897 	struct ath5k_hw *ah = sc->ah;
1898 	struct ath_common *common = ath5k_hw_common(ah);
1899 	struct ath5k_buf *bf;
1900 	struct ath5k_desc *ds;
1901 	int ret;
1902 	int rx_flag;
1903 
1904 	spin_lock(&sc->rxbuflock);
1905 	if (list_empty(&sc->rxbuf)) {
1906 		ATH5K_WARN(sc, "empty rx buf pool\n");
1907 		goto unlock;
1908 	}
1909 	do {
1910 		rx_flag = 0;
1911 
1912 		bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1913 		BUG_ON(bf->skb == NULL);
1914 		skb = bf->skb;
1915 		ds = bf->desc;
1916 
1917 		/* bail if HW is still using self-linked descriptor */
1918 		if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1919 			break;
1920 
1921 		ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1922 		if (unlikely(ret == -EINPROGRESS))
1923 			break;
1924 		else if (unlikely(ret)) {
1925 			ATH5K_ERR(sc, "error in processing rx descriptor\n");
1926 			sc->stats.rxerr_proc++;
1927 			spin_unlock(&sc->rxbuflock);
1928 			return;
1929 		}
1930 
1931 		sc->stats.rx_all_count++;
1932 
1933 		if (unlikely(rs.rs_status)) {
1934 			if (rs.rs_status & AR5K_RXERR_CRC)
1935 				sc->stats.rxerr_crc++;
1936 			if (rs.rs_status & AR5K_RXERR_FIFO)
1937 				sc->stats.rxerr_fifo++;
1938 			if (rs.rs_status & AR5K_RXERR_PHY) {
1939 				sc->stats.rxerr_phy++;
1940 				if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
1941 					sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
1942 				goto next;
1943 			}
1944 			if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1945 				/*
1946 				 * Decrypt error.  If the error occurred
1947 				 * because there was no hardware key, then
1948 				 * let the frame through so the upper layers
1949 				 * can process it.  This is necessary for 5210
1950 				 * parts which have no way to setup a ``clear''
1951 				 * key cache entry.
1952 				 *
1953 				 * XXX do key cache faulting
1954 				 */
1955 				sc->stats.rxerr_decrypt++;
1956 				if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1957 				    !(rs.rs_status & AR5K_RXERR_CRC))
1958 					goto accept;
1959 			}
1960 			if (rs.rs_status & AR5K_RXERR_MIC) {
1961 				rx_flag |= RX_FLAG_MMIC_ERROR;
1962 				sc->stats.rxerr_mic++;
1963 				goto accept;
1964 			}
1965 
1966 			/* let crypto-error packets fall through in MNTR */
1967 			if ((rs.rs_status &
1968 				~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1969 					sc->opmode != NL80211_IFTYPE_MONITOR)
1970 				goto next;
1971 		}
1972 
1973 		if (unlikely(rs.rs_more)) {
1974 			sc->stats.rxerr_jumbo++;
1975 			goto next;
1976 
1977 		}
1978 accept:
1979 		next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1980 
1981 		/*
1982 		 * If we can't replace bf->skb with a new skb under memory
1983 		 * pressure, just skip this packet
1984 		 */
1985 		if (!next_skb)
1986 			goto next;
1987 
1988 		pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1989 				PCI_DMA_FROMDEVICE);
1990 		skb_put(skb, rs.rs_datalen);
1991 
1992 		/* The MAC header is padded to have 32-bit boundary if the
1993 		 * packet payload is non-zero. The general calculation for
1994 		 * padsize would take into account odd header lengths:
1995 		 * padsize = (4 - hdrlen % 4) % 4; However, since only
1996 		 * even-length headers are used, padding can only be 0 or 2
1997 		 * bytes and we can optimize this a bit. In addition, we must
1998 		 * not try to remove padding from short control frames that do
1999 		 * not have payload. */
2000 		ath5k_remove_padding(skb);
2001 
2002 		rxs = IEEE80211_SKB_RXCB(skb);
2003 
2004 		/*
2005 		 * always extend the mac timestamp, since this information is
2006 		 * also needed for proper IBSS merging.
2007 		 *
2008 		 * XXX: it might be too late to do it here, since rs_tstamp is
2009 		 * 15bit only. that means TSF extension has to be done within
2010 		 * 32768usec (about 32ms). it might be necessary to move this to
2011 		 * the interrupt handler, like it is done in madwifi.
2012 		 *
2013 		 * Unfortunately we don't know when the hardware takes the rx
2014 		 * timestamp (beginning of phy frame, data frame, end of rx?).
2015 		 * The only thing we know is that it is hardware specific...
2016 		 * On AR5213 it seems the rx timestamp is at the end of the
2017 		 * frame, but i'm not sure.
2018 		 *
2019 		 * NOTE: mac80211 defines mactime at the beginning of the first
2020 		 * data symbol. Since we don't have any time references it's
2021 		 * impossible to comply to that. This affects IBSS merge only
2022 		 * right now, so it's not too bad...
2023 		 */
2024 		rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2025 		rxs->flag = rx_flag | RX_FLAG_TSFT;
2026 
2027 		rxs->freq = sc->curchan->center_freq;
2028 		rxs->band = sc->curband->band;
2029 
2030 		rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi;
2031 
2032 		rxs->antenna = rs.rs_antenna;
2033 
2034 		if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2035 			sc->stats.antenna_rx[rs.rs_antenna]++;
2036 		else
2037 			sc->stats.antenna_rx[0]++; /* invalid */
2038 
2039 		rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2040 		rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
2041 
2042 		if (rxs->rate_idx >= 0 && rs.rs_rate ==
2043 		    sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2044 			rxs->flag |= RX_FLAG_SHORTPRE;
2045 
2046 		ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
2047 
2048 		ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
2049 
2050 		/* check beacons in IBSS mode */
2051 		if (sc->opmode == NL80211_IFTYPE_ADHOC)
2052 			ath5k_check_ibss_tsf(sc, skb, rxs);
2053 
2054 		ieee80211_rx(sc->hw, skb);
2055 
2056 		bf->skb = next_skb;
2057 		bf->skbaddr = next_skb_addr;
2058 next:
2059 		list_move_tail(&bf->list, &sc->rxbuf);
2060 	} while (ath5k_rxbuf_setup(sc, bf) == 0);
2061 unlock:
2062 	spin_unlock(&sc->rxbuflock);
2063 }
2064 
2065 
2066 
2067 
2068 /*************\
2069 * TX Handling *
2070 \*************/
2071 
2072 static void
2073 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2074 {
2075 	struct ath5k_tx_status ts = {};
2076 	struct ath5k_buf *bf, *bf0;
2077 	struct ath5k_desc *ds;
2078 	struct sk_buff *skb;
2079 	struct ieee80211_tx_info *info;
2080 	int i, ret;
2081 
2082 	spin_lock(&txq->lock);
2083 	list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2084 		ds = bf->desc;
2085 
2086 		/*
2087 		 * It's possible that the hardware can say the buffer is
2088 		 * completed when it hasn't yet loaded the ds_link from
2089 		 * host memory and moved on.  If there are more TX
2090 		 * descriptors in the queue, wait for TXDP to change
2091 		 * before processing this one.
2092 		 */
2093 		if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2094 		    !list_is_last(&bf->list, &txq->q))
2095 			break;
2096 
2097 		ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
2098 		if (unlikely(ret == -EINPROGRESS))
2099 			break;
2100 		else if (unlikely(ret)) {
2101 			ATH5K_ERR(sc, "error %d while processing queue %u\n",
2102 				ret, txq->qnum);
2103 			break;
2104 		}
2105 
2106 		sc->stats.tx_all_count++;
2107 		skb = bf->skb;
2108 		info = IEEE80211_SKB_CB(skb);
2109 		bf->skb = NULL;
2110 
2111 		pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2112 				PCI_DMA_TODEVICE);
2113 
2114 		ieee80211_tx_info_clear_status(info);
2115 		for (i = 0; i < 4; i++) {
2116 			struct ieee80211_tx_rate *r =
2117 				&info->status.rates[i];
2118 
2119 			if (ts.ts_rate[i]) {
2120 				r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2121 				r->count = ts.ts_retry[i];
2122 			} else {
2123 				r->idx = -1;
2124 				r->count = 0;
2125 			}
2126 		}
2127 
2128 		/* count the successful attempt as well */
2129 		info->status.rates[ts.ts_final_idx].count++;
2130 
2131 		if (unlikely(ts.ts_status)) {
2132 			sc->stats.ack_fail++;
2133 			if (ts.ts_status & AR5K_TXERR_FILT) {
2134 				info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2135 				sc->stats.txerr_filt++;
2136 			}
2137 			if (ts.ts_status & AR5K_TXERR_XRETRY)
2138 				sc->stats.txerr_retry++;
2139 			if (ts.ts_status & AR5K_TXERR_FIFO)
2140 				sc->stats.txerr_fifo++;
2141 		} else {
2142 			info->flags |= IEEE80211_TX_STAT_ACK;
2143 			info->status.ack_signal = ts.ts_rssi;
2144 		}
2145 
2146 		/*
2147 		 * Remove MAC header padding before giving the frame
2148 		 * back to mac80211.
2149 		 */
2150 		ath5k_remove_padding(skb);
2151 
2152 		if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2153 			sc->stats.antenna_tx[ts.ts_antenna]++;
2154 		else
2155 			sc->stats.antenna_tx[0]++; /* invalid */
2156 
2157 		ieee80211_tx_status(sc->hw, skb);
2158 
2159 		spin_lock(&sc->txbuflock);
2160 		list_move_tail(&bf->list, &sc->txbuf);
2161 		sc->txbuf_len++;
2162 		spin_unlock(&sc->txbuflock);
2163 	}
2164 	if (likely(list_empty(&txq->q)))
2165 		txq->link = NULL;
2166 	spin_unlock(&txq->lock);
2167 	if (sc->txbuf_len > ATH_TXBUF / 5)
2168 		ieee80211_wake_queues(sc->hw);
2169 }
2170 
2171 static void
2172 ath5k_tasklet_tx(unsigned long data)
2173 {
2174 	int i;
2175 	struct ath5k_softc *sc = (void *)data;
2176 
2177 	for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2178 		if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2179 			ath5k_tx_processq(sc, &sc->txqs[i]);
2180 }
2181 
2182 
2183 /*****************\
2184 * Beacon handling *
2185 \*****************/
2186 
2187 /*
2188  * Setup the beacon frame for transmit.
2189  */
2190 static int
2191 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2192 {
2193 	struct sk_buff *skb = bf->skb;
2194 	struct	ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2195 	struct ath5k_hw *ah = sc->ah;
2196 	struct ath5k_desc *ds;
2197 	int ret = 0;
2198 	u8 antenna;
2199 	u32 flags;
2200 	const int padsize = 0;
2201 
2202 	bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2203 			PCI_DMA_TODEVICE);
2204 	ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2205 			"skbaddr %llx\n", skb, skb->data, skb->len,
2206 			(unsigned long long)bf->skbaddr);
2207 	if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2208 		ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2209 		return -EIO;
2210 	}
2211 
2212 	ds = bf->desc;
2213 	antenna = ah->ah_tx_ant;
2214 
2215 	flags = AR5K_TXDESC_NOACK;
2216 	if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2217 		ds->ds_link = bf->daddr;	/* self-linked */
2218 		flags |= AR5K_TXDESC_VEOL;
2219 	} else
2220 		ds->ds_link = 0;
2221 
2222 	/*
2223 	 * If we use multiple antennas on AP and use
2224 	 * the Sectored AP scenario, switch antenna every
2225 	 * 4 beacons to make sure everybody hears our AP.
2226 	 * When a client tries to associate, hw will keep
2227 	 * track of the tx antenna to be used for this client
2228 	 * automaticaly, based on ACKed packets.
2229 	 *
2230 	 * Note: AP still listens and transmits RTS on the
2231 	 * default antenna which is supposed to be an omni.
2232 	 *
2233 	 * Note2: On sectored scenarios it's possible to have
2234 	 * multiple antennas (1omni -the default- and 14 sectors)
2235 	 * so if we choose to actually support this mode we need
2236 	 * to allow user to set how many antennas we have and tweak
2237 	 * the code below to send beacons on all of them.
2238 	 */
2239 	if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2240 		antenna = sc->bsent & 4 ? 2 : 1;
2241 
2242 
2243 	/* FIXME: If we are in g mode and rate is a CCK rate
2244 	 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2245 	 * from tx power (value is in dB units already) */
2246 	ds->ds_data = bf->skbaddr;
2247 	ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2248 			ieee80211_get_hdrlen_from_skb(skb), padsize,
2249 			AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2250 			ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2251 			1, AR5K_TXKEYIX_INVALID,
2252 			antenna, flags, 0, 0);
2253 	if (ret)
2254 		goto err_unmap;
2255 
2256 	return 0;
2257 err_unmap:
2258 	pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2259 	return ret;
2260 }
2261 
2262 /*
2263  * Transmit a beacon frame at SWBA.  Dynamic updates to the
2264  * frame contents are done as needed and the slot time is
2265  * also adjusted based on current state.
2266  *
2267  * This is called from software irq context (beacontq or restq
2268  * tasklets) or user context from ath5k_beacon_config.
2269  */
2270 static void
2271 ath5k_beacon_send(struct ath5k_softc *sc)
2272 {
2273 	struct ath5k_buf *bf = sc->bbuf;
2274 	struct ath5k_hw *ah = sc->ah;
2275 	struct sk_buff *skb;
2276 
2277 	ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2278 
2279 	if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2280 			sc->opmode == NL80211_IFTYPE_MONITOR)) {
2281 		ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2282 		return;
2283 	}
2284 	/*
2285 	 * Check if the previous beacon has gone out.  If
2286 	 * not don't don't try to post another, skip this
2287 	 * period and wait for the next.  Missed beacons
2288 	 * indicate a problem and should not occur.  If we
2289 	 * miss too many consecutive beacons reset the device.
2290 	 */
2291 	if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2292 		sc->bmisscount++;
2293 		ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2294 			"missed %u consecutive beacons\n", sc->bmisscount);
2295 		if (sc->bmisscount > 10) {	/* NB: 10 is a guess */
2296 			ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2297 				"stuck beacon time (%u missed)\n",
2298 				sc->bmisscount);
2299 			tasklet_schedule(&sc->restq);
2300 		}
2301 		return;
2302 	}
2303 	if (unlikely(sc->bmisscount != 0)) {
2304 		ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2305 			"resume beacon xmit after %u misses\n",
2306 			sc->bmisscount);
2307 		sc->bmisscount = 0;
2308 	}
2309 
2310 	/*
2311 	 * Stop any current dma and put the new frame on the queue.
2312 	 * This should never fail since we check above that no frames
2313 	 * are still pending on the queue.
2314 	 */
2315 	if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2316 		ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2317 		/* NB: hw still stops DMA, so proceed */
2318 	}
2319 
2320 	/* refresh the beacon for AP mode */
2321 	if (sc->opmode == NL80211_IFTYPE_AP)
2322 		ath5k_beacon_update(sc->hw, sc->vif);
2323 
2324 	ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2325 	ath5k_hw_start_tx_dma(ah, sc->bhalq);
2326 	ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2327 		sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2328 
2329 	skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2330 	while (skb) {
2331 		ath5k_tx_queue(sc->hw, skb, sc->cabq);
2332 		skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2333 	}
2334 
2335 	sc->bsent++;
2336 }
2337 
2338 
2339 /**
2340  * ath5k_beacon_update_timers - update beacon timers
2341  *
2342  * @sc: struct ath5k_softc pointer we are operating on
2343  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2344  *          beacon timer update based on the current HW TSF.
2345  *
2346  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2347  * of a received beacon or the current local hardware TSF and write it to the
2348  * beacon timer registers.
2349  *
2350  * This is called in a variety of situations, e.g. when a beacon is received,
2351  * when a TSF update has been detected, but also when an new IBSS is created or
2352  * when we otherwise know we have to update the timers, but we keep it in this
2353  * function to have it all together in one place.
2354  */
2355 static void
2356 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2357 {
2358 	struct ath5k_hw *ah = sc->ah;
2359 	u32 nexttbtt, intval, hw_tu, bc_tu;
2360 	u64 hw_tsf;
2361 
2362 	intval = sc->bintval & AR5K_BEACON_PERIOD;
2363 	if (WARN_ON(!intval))
2364 		return;
2365 
2366 	/* beacon TSF converted to TU */
2367 	bc_tu = TSF_TO_TU(bc_tsf);
2368 
2369 	/* current TSF converted to TU */
2370 	hw_tsf = ath5k_hw_get_tsf64(ah);
2371 	hw_tu = TSF_TO_TU(hw_tsf);
2372 
2373 #define FUDGE 3
2374 	/* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2375 	if (bc_tsf == -1) {
2376 		/*
2377 		 * no beacons received, called internally.
2378 		 * just need to refresh timers based on HW TSF.
2379 		 */
2380 		nexttbtt = roundup(hw_tu + FUDGE, intval);
2381 	} else if (bc_tsf == 0) {
2382 		/*
2383 		 * no beacon received, probably called by ath5k_reset_tsf().
2384 		 * reset TSF to start with 0.
2385 		 */
2386 		nexttbtt = intval;
2387 		intval |= AR5K_BEACON_RESET_TSF;
2388 	} else if (bc_tsf > hw_tsf) {
2389 		/*
2390 		 * beacon received, SW merge happend but HW TSF not yet updated.
2391 		 * not possible to reconfigure timers yet, but next time we
2392 		 * receive a beacon with the same BSSID, the hardware will
2393 		 * automatically update the TSF and then we need to reconfigure
2394 		 * the timers.
2395 		 */
2396 		ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2397 			"need to wait for HW TSF sync\n");
2398 		return;
2399 	} else {
2400 		/*
2401 		 * most important case for beacon synchronization between STA.
2402 		 *
2403 		 * beacon received and HW TSF has been already updated by HW.
2404 		 * update next TBTT based on the TSF of the beacon, but make
2405 		 * sure it is ahead of our local TSF timer.
2406 		 */
2407 		nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2408 	}
2409 #undef FUDGE
2410 
2411 	sc->nexttbtt = nexttbtt;
2412 
2413 	intval |= AR5K_BEACON_ENA;
2414 	ath5k_hw_init_beacon(ah, nexttbtt, intval);
2415 
2416 	/*
2417 	 * debugging output last in order to preserve the time critical aspect
2418 	 * of this function
2419 	 */
2420 	if (bc_tsf == -1)
2421 		ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2422 			"reconfigured timers based on HW TSF\n");
2423 	else if (bc_tsf == 0)
2424 		ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2425 			"reset HW TSF and timers\n");
2426 	else
2427 		ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2428 			"updated timers based on beacon TSF\n");
2429 
2430 	ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2431 			  "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2432 			  (unsigned long long) bc_tsf,
2433 			  (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2434 	ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2435 		intval & AR5K_BEACON_PERIOD,
2436 		intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2437 		intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2438 }
2439 
2440 
2441 /**
2442  * ath5k_beacon_config - Configure the beacon queues and interrupts
2443  *
2444  * @sc: struct ath5k_softc pointer we are operating on
2445  *
2446  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2447  * interrupts to detect TSF updates only.
2448  */
2449 static void
2450 ath5k_beacon_config(struct ath5k_softc *sc)
2451 {
2452 	struct ath5k_hw *ah = sc->ah;
2453 	unsigned long flags;
2454 
2455 	spin_lock_irqsave(&sc->block, flags);
2456 	sc->bmisscount = 0;
2457 	sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2458 
2459 	if (sc->enable_beacon) {
2460 		/*
2461 		 * In IBSS mode we use a self-linked tx descriptor and let the
2462 		 * hardware send the beacons automatically. We have to load it
2463 		 * only once here.
2464 		 * We use the SWBA interrupt only to keep track of the beacon
2465 		 * timers in order to detect automatic TSF updates.
2466 		 */
2467 		ath5k_beaconq_config(sc);
2468 
2469 		sc->imask |= AR5K_INT_SWBA;
2470 
2471 		if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2472 			if (ath5k_hw_hasveol(ah))
2473 				ath5k_beacon_send(sc);
2474 		} else
2475 			ath5k_beacon_update_timers(sc, -1);
2476 	} else {
2477 		ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2478 	}
2479 
2480 	ath5k_hw_set_imr(ah, sc->imask);
2481 	mmiowb();
2482 	spin_unlock_irqrestore(&sc->block, flags);
2483 }
2484 
2485 static void ath5k_tasklet_beacon(unsigned long data)
2486 {
2487 	struct ath5k_softc *sc = (struct ath5k_softc *) data;
2488 
2489 	/*
2490 	 * Software beacon alert--time to send a beacon.
2491 	 *
2492 	 * In IBSS mode we use this interrupt just to
2493 	 * keep track of the next TBTT (target beacon
2494 	 * transmission time) in order to detect wether
2495 	 * automatic TSF updates happened.
2496 	 */
2497 	if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2498 		/* XXX: only if VEOL suppported */
2499 		u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2500 		sc->nexttbtt += sc->bintval;
2501 		ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2502 				"SWBA nexttbtt: %x hw_tu: %x "
2503 				"TSF: %llx\n",
2504 				sc->nexttbtt,
2505 				TSF_TO_TU(tsf),
2506 				(unsigned long long) tsf);
2507 	} else {
2508 		spin_lock(&sc->block);
2509 		ath5k_beacon_send(sc);
2510 		spin_unlock(&sc->block);
2511 	}
2512 }
2513 
2514 
2515 /********************\
2516 * Interrupt handling *
2517 \********************/
2518 
2519 static int
2520 ath5k_init(struct ath5k_softc *sc)
2521 {
2522 	struct ath5k_hw *ah = sc->ah;
2523 	int ret, i;
2524 
2525 	mutex_lock(&sc->lock);
2526 
2527 	ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2528 
2529 	/*
2530 	 * Stop anything previously setup.  This is safe
2531 	 * no matter this is the first time through or not.
2532 	 */
2533 	ath5k_stop_locked(sc);
2534 
2535 	/*
2536 	 * The basic interface to setting the hardware in a good
2537 	 * state is ``reset''.  On return the hardware is known to
2538 	 * be powered up and with interrupts disabled.  This must
2539 	 * be followed by initialization of the appropriate bits
2540 	 * and then setup of the interrupt mask.
2541 	 */
2542 	sc->curchan = sc->hw->conf.channel;
2543 	sc->curband = &sc->sbands[sc->curchan->band];
2544 	sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2545 		AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2546 		AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2547 
2548 	ret = ath5k_reset(sc, NULL);
2549 	if (ret)
2550 		goto done;
2551 
2552 	ath5k_rfkill_hw_start(ah);
2553 
2554 	/*
2555 	 * Reset the key cache since some parts do not reset the
2556 	 * contents on initial power up or resume from suspend.
2557 	 */
2558 	for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2559 		ath5k_hw_reset_key(ah, i);
2560 
2561 	ath5k_hw_set_ack_bitrate_high(ah, true);
2562 	ret = 0;
2563 done:
2564 	mmiowb();
2565 	mutex_unlock(&sc->lock);
2566 	return ret;
2567 }
2568 
2569 static int
2570 ath5k_stop_locked(struct ath5k_softc *sc)
2571 {
2572 	struct ath5k_hw *ah = sc->ah;
2573 
2574 	ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2575 			test_bit(ATH_STAT_INVALID, sc->status));
2576 
2577 	/*
2578 	 * Shutdown the hardware and driver:
2579 	 *    stop output from above
2580 	 *    disable interrupts
2581 	 *    turn off timers
2582 	 *    turn off the radio
2583 	 *    clear transmit machinery
2584 	 *    clear receive machinery
2585 	 *    drain and release tx queues
2586 	 *    reclaim beacon resources
2587 	 *    power down hardware
2588 	 *
2589 	 * Note that some of this work is not possible if the
2590 	 * hardware is gone (invalid).
2591 	 */
2592 	ieee80211_stop_queues(sc->hw);
2593 
2594 	if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2595 		ath5k_led_off(sc);
2596 		ath5k_hw_set_imr(ah, 0);
2597 		synchronize_irq(sc->pdev->irq);
2598 	}
2599 	ath5k_txq_cleanup(sc);
2600 	if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2601 		ath5k_rx_stop(sc);
2602 		ath5k_hw_phy_disable(ah);
2603 	} else
2604 		sc->rxlink = NULL;
2605 
2606 	return 0;
2607 }
2608 
2609 /*
2610  * Stop the device, grabbing the top-level lock to protect
2611  * against concurrent entry through ath5k_init (which can happen
2612  * if another thread does a system call and the thread doing the
2613  * stop is preempted).
2614  */
2615 static int
2616 ath5k_stop_hw(struct ath5k_softc *sc)
2617 {
2618 	int ret;
2619 
2620 	mutex_lock(&sc->lock);
2621 	ret = ath5k_stop_locked(sc);
2622 	if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2623 		/*
2624 		 * Don't set the card in full sleep mode!
2625 		 *
2626 		 * a) When the device is in this state it must be carefully
2627 		 * woken up or references to registers in the PCI clock
2628 		 * domain may freeze the bus (and system).  This varies
2629 		 * by chip and is mostly an issue with newer parts
2630 		 * (madwifi sources mentioned srev >= 0x78) that go to
2631 		 * sleep more quickly.
2632 		 *
2633 		 * b) On older chips full sleep results a weird behaviour
2634 		 * during wakeup. I tested various cards with srev < 0x78
2635 		 * and they don't wake up after module reload, a second
2636 		 * module reload is needed to bring the card up again.
2637 		 *
2638 		 * Until we figure out what's going on don't enable
2639 		 * full chip reset on any chip (this is what Legacy HAL
2640 		 * and Sam's HAL do anyway). Instead Perform a full reset
2641 		 * on the device (same as initial state after attach) and
2642 		 * leave it idle (keep MAC/BB on warm reset) */
2643 		ret = ath5k_hw_on_hold(sc->ah);
2644 
2645 		ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2646 				"putting device to sleep\n");
2647 	}
2648 	ath5k_txbuf_free(sc, sc->bbuf);
2649 
2650 	mmiowb();
2651 	mutex_unlock(&sc->lock);
2652 
2653 	tasklet_kill(&sc->rxtq);
2654 	tasklet_kill(&sc->txtq);
2655 	tasklet_kill(&sc->restq);
2656 	tasklet_kill(&sc->calib);
2657 	tasklet_kill(&sc->beacontq);
2658 	tasklet_kill(&sc->ani_tasklet);
2659 
2660 	ath5k_rfkill_hw_stop(sc->ah);
2661 
2662 	return ret;
2663 }
2664 
2665 static void
2666 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2667 {
2668 	if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2669 	    !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2670 		/* run ANI only when full calibration is not active */
2671 		ah->ah_cal_next_ani = jiffies +
2672 			msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2673 		tasklet_schedule(&ah->ah_sc->ani_tasklet);
2674 
2675 	} else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2676 		ah->ah_cal_next_full = jiffies +
2677 			msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2678 		tasklet_schedule(&ah->ah_sc->calib);
2679 	}
2680 	/* we could use SWI to generate enough interrupts to meet our
2681 	 * calibration interval requirements, if necessary:
2682 	 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2683 }
2684 
2685 static irqreturn_t
2686 ath5k_intr(int irq, void *dev_id)
2687 {
2688 	struct ath5k_softc *sc = dev_id;
2689 	struct ath5k_hw *ah = sc->ah;
2690 	enum ath5k_int status;
2691 	unsigned int counter = 1000;
2692 
2693 	if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2694 				!ath5k_hw_is_intr_pending(ah)))
2695 		return IRQ_NONE;
2696 
2697 	do {
2698 		ath5k_hw_get_isr(ah, &status);		/* NB: clears IRQ too */
2699 		ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2700 				status, sc->imask);
2701 		if (unlikely(status & AR5K_INT_FATAL)) {
2702 			/*
2703 			 * Fatal errors are unrecoverable.
2704 			 * Typically these are caused by DMA errors.
2705 			 */
2706 			tasklet_schedule(&sc->restq);
2707 		} else if (unlikely(status & AR5K_INT_RXORN)) {
2708 			/*
2709 			 * Receive buffers are full. Either the bus is busy or
2710 			 * the CPU is not fast enough to process all received
2711 			 * frames.
2712 			 * Older chipsets need a reset to come out of this
2713 			 * condition, but we treat it as RX for newer chips.
2714 			 * We don't know exactly which versions need a reset -
2715 			 * this guess is copied from the HAL.
2716 			 */
2717 			sc->stats.rxorn_intr++;
2718 			if (ah->ah_mac_srev < AR5K_SREV_AR5212)
2719 				tasklet_schedule(&sc->restq);
2720 			else
2721 				tasklet_schedule(&sc->rxtq);
2722 		} else {
2723 			if (status & AR5K_INT_SWBA) {
2724 				tasklet_hi_schedule(&sc->beacontq);
2725 			}
2726 			if (status & AR5K_INT_RXEOL) {
2727 				/*
2728 				* NB: the hardware should re-read the link when
2729 				*     RXE bit is written, but it doesn't work at
2730 				*     least on older hardware revs.
2731 				*/
2732 				sc->rxlink = NULL;
2733 			}
2734 			if (status & AR5K_INT_TXURN) {
2735 				/* bump tx trigger level */
2736 				ath5k_hw_update_tx_triglevel(ah, true);
2737 			}
2738 			if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2739 				tasklet_schedule(&sc->rxtq);
2740 			if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2741 					| AR5K_INT_TXERR | AR5K_INT_TXEOL))
2742 				tasklet_schedule(&sc->txtq);
2743 			if (status & AR5K_INT_BMISS) {
2744 				/* TODO */
2745 			}
2746 			if (status & AR5K_INT_MIB) {
2747 				sc->stats.mib_intr++;
2748 				ath5k_hw_update_mib_counters(ah);
2749 				ath5k_ani_mib_intr(ah);
2750 			}
2751 			if (status & AR5K_INT_GPIO)
2752 				tasklet_schedule(&sc->rf_kill.toggleq);
2753 
2754 		}
2755 	} while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2756 
2757 	if (unlikely(!counter))
2758 		ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2759 
2760 	ath5k_intr_calibration_poll(ah);
2761 
2762 	return IRQ_HANDLED;
2763 }
2764 
2765 static void
2766 ath5k_tasklet_reset(unsigned long data)
2767 {
2768 	struct ath5k_softc *sc = (void *)data;
2769 
2770 	ath5k_reset_wake(sc);
2771 }
2772 
2773 /*
2774  * Periodically recalibrate the PHY to account
2775  * for temperature/environment changes.
2776  */
2777 static void
2778 ath5k_tasklet_calibrate(unsigned long data)
2779 {
2780 	struct ath5k_softc *sc = (void *)data;
2781 	struct ath5k_hw *ah = sc->ah;
2782 
2783 	/* Only full calibration for now */
2784 	ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2785 
2786 	ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2787 		ieee80211_frequency_to_channel(sc->curchan->center_freq),
2788 		sc->curchan->hw_value);
2789 
2790 	if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2791 		/*
2792 		 * Rfgain is out of bounds, reset the chip
2793 		 * to load new gain values.
2794 		 */
2795 		ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2796 		ath5k_reset(sc, sc->curchan);
2797 	}
2798 	if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2799 		ATH5K_ERR(sc, "calibration of channel %u failed\n",
2800 			ieee80211_frequency_to_channel(
2801 				sc->curchan->center_freq));
2802 
2803 	/* Noise floor calibration interrupts rx/tx path while I/Q calibration
2804 	 * doesn't. We stop the queues so that calibration doesn't interfere
2805 	 * with TX and don't run it as often */
2806 	if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2807 		ah->ah_cal_next_nf = jiffies +
2808 			msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2809 		ieee80211_stop_queues(sc->hw);
2810 		ath5k_hw_update_noise_floor(ah);
2811 		ieee80211_wake_queues(sc->hw);
2812 	}
2813 
2814 	ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2815 }
2816 
2817 
2818 static void
2819 ath5k_tasklet_ani(unsigned long data)
2820 {
2821 	struct ath5k_softc *sc = (void *)data;
2822 	struct ath5k_hw *ah = sc->ah;
2823 
2824 	ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2825 	ath5k_ani_calibration(ah);
2826 	ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2827 }
2828 
2829 
2830 /********************\
2831 * Mac80211 functions *
2832 \********************/
2833 
2834 static int
2835 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2836 {
2837 	struct ath5k_softc *sc = hw->priv;
2838 
2839 	return ath5k_tx_queue(hw, skb, sc->txq);
2840 }
2841 
2842 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2843 			  struct ath5k_txq *txq)
2844 {
2845 	struct ath5k_softc *sc = hw->priv;
2846 	struct ath5k_buf *bf;
2847 	unsigned long flags;
2848 	int padsize;
2849 
2850 	ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2851 
2852 	if (sc->opmode == NL80211_IFTYPE_MONITOR)
2853 		ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2854 
2855 	/*
2856 	 * the hardware expects the header padded to 4 byte boundaries
2857 	 * if this is not the case we add the padding after the header
2858 	 */
2859 	padsize = ath5k_add_padding(skb);
2860 	if (padsize < 0) {
2861 		ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2862 			  " headroom to pad");
2863 		goto drop_packet;
2864 	}
2865 
2866 	spin_lock_irqsave(&sc->txbuflock, flags);
2867 	if (list_empty(&sc->txbuf)) {
2868 		ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2869 		spin_unlock_irqrestore(&sc->txbuflock, flags);
2870 		ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2871 		goto drop_packet;
2872 	}
2873 	bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2874 	list_del(&bf->list);
2875 	sc->txbuf_len--;
2876 	if (list_empty(&sc->txbuf))
2877 		ieee80211_stop_queues(hw);
2878 	spin_unlock_irqrestore(&sc->txbuflock, flags);
2879 
2880 	bf->skb = skb;
2881 
2882 	if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
2883 		bf->skb = NULL;
2884 		spin_lock_irqsave(&sc->txbuflock, flags);
2885 		list_add_tail(&bf->list, &sc->txbuf);
2886 		sc->txbuf_len++;
2887 		spin_unlock_irqrestore(&sc->txbuflock, flags);
2888 		goto drop_packet;
2889 	}
2890 	return NETDEV_TX_OK;
2891 
2892 drop_packet:
2893 	dev_kfree_skb_any(skb);
2894 	return NETDEV_TX_OK;
2895 }
2896 
2897 /*
2898  * Reset the hardware.  If chan is not NULL, then also pause rx/tx
2899  * and change to the given channel.
2900  */
2901 static int
2902 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2903 {
2904 	struct ath5k_hw *ah = sc->ah;
2905 	int ret;
2906 
2907 	ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2908 
2909 	if (chan) {
2910 		ath5k_hw_set_imr(ah, 0);
2911 		ath5k_txq_cleanup(sc);
2912 		ath5k_rx_stop(sc);
2913 
2914 		sc->curchan = chan;
2915 		sc->curband = &sc->sbands[chan->band];
2916 	}
2917 	ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2918 	if (ret) {
2919 		ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2920 		goto err;
2921 	}
2922 
2923 	ret = ath5k_rx_start(sc);
2924 	if (ret) {
2925 		ATH5K_ERR(sc, "can't start recv logic\n");
2926 		goto err;
2927 	}
2928 
2929 	ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2930 
2931 	ah->ah_cal_next_full = jiffies;
2932 	ah->ah_cal_next_ani = jiffies;
2933 	ah->ah_cal_next_nf = jiffies;
2934 
2935 	/*
2936 	 * Change channels and update the h/w rate map if we're switching;
2937 	 * e.g. 11a to 11b/g.
2938 	 *
2939 	 * We may be doing a reset in response to an ioctl that changes the
2940 	 * channel so update any state that might change as a result.
2941 	 *
2942 	 * XXX needed?
2943 	 */
2944 /*	ath5k_chan_change(sc, c); */
2945 
2946 	ath5k_beacon_config(sc);
2947 	/* intrs are enabled by ath5k_beacon_config */
2948 
2949 	return 0;
2950 err:
2951 	return ret;
2952 }
2953 
2954 static int
2955 ath5k_reset_wake(struct ath5k_softc *sc)
2956 {
2957 	int ret;
2958 
2959 	ret = ath5k_reset(sc, sc->curchan);
2960 	if (!ret)
2961 		ieee80211_wake_queues(sc->hw);
2962 
2963 	return ret;
2964 }
2965 
2966 static int ath5k_start(struct ieee80211_hw *hw)
2967 {
2968 	return ath5k_init(hw->priv);
2969 }
2970 
2971 static void ath5k_stop(struct ieee80211_hw *hw)
2972 {
2973 	ath5k_stop_hw(hw->priv);
2974 }
2975 
2976 static int ath5k_add_interface(struct ieee80211_hw *hw,
2977 		struct ieee80211_vif *vif)
2978 {
2979 	struct ath5k_softc *sc = hw->priv;
2980 	int ret;
2981 
2982 	mutex_lock(&sc->lock);
2983 	if (sc->vif) {
2984 		ret = 0;
2985 		goto end;
2986 	}
2987 
2988 	sc->vif = vif;
2989 
2990 	switch (vif->type) {
2991 	case NL80211_IFTYPE_AP:
2992 	case NL80211_IFTYPE_STATION:
2993 	case NL80211_IFTYPE_ADHOC:
2994 	case NL80211_IFTYPE_MESH_POINT:
2995 	case NL80211_IFTYPE_MONITOR:
2996 		sc->opmode = vif->type;
2997 		break;
2998 	default:
2999 		ret = -EOPNOTSUPP;
3000 		goto end;
3001 	}
3002 
3003 	ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
3004 
3005 	ath5k_hw_set_lladdr(sc->ah, vif->addr);
3006 	ath5k_mode_setup(sc);
3007 
3008 	ret = 0;
3009 end:
3010 	mutex_unlock(&sc->lock);
3011 	return ret;
3012 }
3013 
3014 static void
3015 ath5k_remove_interface(struct ieee80211_hw *hw,
3016 			struct ieee80211_vif *vif)
3017 {
3018 	struct ath5k_softc *sc = hw->priv;
3019 	u8 mac[ETH_ALEN] = {};
3020 
3021 	mutex_lock(&sc->lock);
3022 	if (sc->vif != vif)
3023 		goto end;
3024 
3025 	ath5k_hw_set_lladdr(sc->ah, mac);
3026 	sc->vif = NULL;
3027 end:
3028 	mutex_unlock(&sc->lock);
3029 }
3030 
3031 /*
3032  * TODO: Phy disable/diversity etc
3033  */
3034 static int
3035 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3036 {
3037 	struct ath5k_softc *sc = hw->priv;
3038 	struct ath5k_hw *ah = sc->ah;
3039 	struct ieee80211_conf *conf = &hw->conf;
3040 	int ret = 0;
3041 
3042 	mutex_lock(&sc->lock);
3043 
3044 	if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3045 		ret = ath5k_chan_set(sc, conf->channel);
3046 		if (ret < 0)
3047 			goto unlock;
3048 	}
3049 
3050 	if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3051 	(sc->power_level != conf->power_level)) {
3052 		sc->power_level = conf->power_level;
3053 
3054 		/* Half dB steps */
3055 		ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3056 	}
3057 
3058 	/* TODO:
3059 	 * 1) Move this on config_interface and handle each case
3060 	 * separately eg. when we have only one STA vif, use
3061 	 * AR5K_ANTMODE_SINGLE_AP
3062 	 *
3063 	 * 2) Allow the user to change antenna mode eg. when only
3064 	 * one antenna is present
3065 	 *
3066 	 * 3) Allow the user to set default/tx antenna when possible
3067 	 *
3068 	 * 4) Default mode should handle 90% of the cases, together
3069 	 * with fixed a/b and single AP modes we should be able to
3070 	 * handle 99%. Sectored modes are extreme cases and i still
3071 	 * haven't found a usage for them. If we decide to support them,
3072 	 * then we must allow the user to set how many tx antennas we
3073 	 * have available
3074 	 */
3075 	ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3076 
3077 unlock:
3078 	mutex_unlock(&sc->lock);
3079 	return ret;
3080 }
3081 
3082 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3083 				   struct netdev_hw_addr_list *mc_list)
3084 {
3085 	u32 mfilt[2], val;
3086 	u8 pos;
3087 	struct netdev_hw_addr *ha;
3088 
3089 	mfilt[0] = 0;
3090 	mfilt[1] = 1;
3091 
3092 	netdev_hw_addr_list_for_each(ha, mc_list) {
3093 		/* calculate XOR of eight 6-bit values */
3094 		val = get_unaligned_le32(ha->addr + 0);
3095 		pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3096 		val = get_unaligned_le32(ha->addr + 3);
3097 		pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3098 		pos &= 0x3f;
3099 		mfilt[pos / 32] |= (1 << (pos % 32));
3100 		/* XXX: we might be able to just do this instead,
3101 		* but not sure, needs testing, if we do use this we'd
3102 		* neet to inform below to not reset the mcast */
3103 		/* ath5k_hw_set_mcast_filterindex(ah,
3104 		 *      ha->addr[5]); */
3105 	}
3106 
3107 	return ((u64)(mfilt[1]) << 32) | mfilt[0];
3108 }
3109 
3110 #define SUPPORTED_FIF_FLAGS \
3111 	FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
3112 	FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3113 	FIF_BCN_PRBRESP_PROMISC
3114 /*
3115  * o always accept unicast, broadcast, and multicast traffic
3116  * o multicast traffic for all BSSIDs will be enabled if mac80211
3117  *   says it should be
3118  * o maintain current state of phy ofdm or phy cck error reception.
3119  *   If the hardware detects any of these type of errors then
3120  *   ath5k_hw_get_rx_filter() will pass to us the respective
3121  *   hardware filters to be able to receive these type of frames.
3122  * o probe request frames are accepted only when operating in
3123  *   hostap, adhoc, or monitor modes
3124  * o enable promiscuous mode according to the interface state
3125  * o accept beacons:
3126  *   - when operating in adhoc mode so the 802.11 layer creates
3127  *     node table entries for peers,
3128  *   - when operating in station mode for collecting rssi data when
3129  *     the station is otherwise quiet, or
3130  *   - when scanning
3131  */
3132 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3133 		unsigned int changed_flags,
3134 		unsigned int *new_flags,
3135 		u64 multicast)
3136 {
3137 	struct ath5k_softc *sc = hw->priv;
3138 	struct ath5k_hw *ah = sc->ah;
3139 	u32 mfilt[2], rfilt;
3140 
3141 	mutex_lock(&sc->lock);
3142 
3143 	mfilt[0] = multicast;
3144 	mfilt[1] = multicast >> 32;
3145 
3146 	/* Only deal with supported flags */
3147 	changed_flags &= SUPPORTED_FIF_FLAGS;
3148 	*new_flags &= SUPPORTED_FIF_FLAGS;
3149 
3150 	/* If HW detects any phy or radar errors, leave those filters on.
3151 	 * Also, always enable Unicast, Broadcasts and Multicast
3152 	 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3153 	rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3154 		(AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3155 		AR5K_RX_FILTER_MCAST);
3156 
3157 	if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3158 		if (*new_flags & FIF_PROMISC_IN_BSS) {
3159 			rfilt |= AR5K_RX_FILTER_PROM;
3160 			__set_bit(ATH_STAT_PROMISC, sc->status);
3161 		} else {
3162 			__clear_bit(ATH_STAT_PROMISC, sc->status);
3163 		}
3164 	}
3165 
3166 	/* Note, AR5K_RX_FILTER_MCAST is already enabled */
3167 	if (*new_flags & FIF_ALLMULTI) {
3168 		mfilt[0] =  ~0;
3169 		mfilt[1] =  ~0;
3170 	}
3171 
3172 	/* This is the best we can do */
3173 	if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3174 		rfilt |= AR5K_RX_FILTER_PHYERR;
3175 
3176 	/* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3177 	* and probes for any BSSID, this needs testing */
3178 	if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3179 		rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3180 
3181 	/* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3182 	 * set we should only pass on control frames for this
3183 	 * station. This needs testing. I believe right now this
3184 	 * enables *all* control frames, which is OK.. but
3185 	 * but we should see if we can improve on granularity */
3186 	if (*new_flags & FIF_CONTROL)
3187 		rfilt |= AR5K_RX_FILTER_CONTROL;
3188 
3189 	/* Additional settings per mode -- this is per ath5k */
3190 
3191 	/* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3192 
3193 	switch (sc->opmode) {
3194 	case NL80211_IFTYPE_MESH_POINT:
3195 	case NL80211_IFTYPE_MONITOR:
3196 		rfilt |= AR5K_RX_FILTER_CONTROL |
3197 			 AR5K_RX_FILTER_BEACON |
3198 			 AR5K_RX_FILTER_PROBEREQ |
3199 			 AR5K_RX_FILTER_PROM;
3200 		break;
3201 	case NL80211_IFTYPE_AP:
3202 	case NL80211_IFTYPE_ADHOC:
3203 		rfilt |= AR5K_RX_FILTER_PROBEREQ |
3204 			 AR5K_RX_FILTER_BEACON;
3205 		break;
3206 	case NL80211_IFTYPE_STATION:
3207 		if (sc->assoc)
3208 			rfilt |= AR5K_RX_FILTER_BEACON;
3209 	default:
3210 		break;
3211 	}
3212 
3213 	/* Set filters */
3214 	ath5k_hw_set_rx_filter(ah, rfilt);
3215 
3216 	/* Set multicast bits */
3217 	ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3218 	/* Set the cached hw filter flags, this will alter actually
3219 	 * be set in HW */
3220 	sc->filter_flags = rfilt;
3221 
3222 	mutex_unlock(&sc->lock);
3223 }
3224 
3225 static int
3226 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3227 	      struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3228 	      struct ieee80211_key_conf *key)
3229 {
3230 	struct ath5k_softc *sc = hw->priv;
3231 	struct ath5k_hw *ah = sc->ah;
3232 	struct ath_common *common = ath5k_hw_common(ah);
3233 	int ret = 0;
3234 
3235 	if (modparam_nohwcrypt)
3236 		return -EOPNOTSUPP;
3237 
3238 	if (sc->opmode == NL80211_IFTYPE_AP)
3239 		return -EOPNOTSUPP;
3240 
3241 	switch (key->alg) {
3242 	case ALG_WEP:
3243 	case ALG_TKIP:
3244 		break;
3245 	case ALG_CCMP:
3246 		if (sc->ah->ah_aes_support)
3247 			break;
3248 
3249 		return -EOPNOTSUPP;
3250 	default:
3251 		WARN_ON(1);
3252 		return -EINVAL;
3253 	}
3254 
3255 	mutex_lock(&sc->lock);
3256 
3257 	switch (cmd) {
3258 	case SET_KEY:
3259 		ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3260 				       sta ? sta->addr : NULL);
3261 		if (ret) {
3262 			ATH5K_ERR(sc, "can't set the key\n");
3263 			goto unlock;
3264 		}
3265 		__set_bit(key->keyidx, common->keymap);
3266 		key->hw_key_idx = key->keyidx;
3267 		key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3268 			       IEEE80211_KEY_FLAG_GENERATE_MMIC);
3269 		break;
3270 	case DISABLE_KEY:
3271 		ath5k_hw_reset_key(sc->ah, key->keyidx);
3272 		__clear_bit(key->keyidx, common->keymap);
3273 		break;
3274 	default:
3275 		ret = -EINVAL;
3276 		goto unlock;
3277 	}
3278 
3279 unlock:
3280 	mmiowb();
3281 	mutex_unlock(&sc->lock);
3282 	return ret;
3283 }
3284 
3285 static int
3286 ath5k_get_stats(struct ieee80211_hw *hw,
3287 		struct ieee80211_low_level_stats *stats)
3288 {
3289 	struct ath5k_softc *sc = hw->priv;
3290 
3291 	/* Force update */
3292 	ath5k_hw_update_mib_counters(sc->ah);
3293 
3294 	stats->dot11ACKFailureCount = sc->stats.ack_fail;
3295 	stats->dot11RTSFailureCount = sc->stats.rts_fail;
3296 	stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3297 	stats->dot11FCSErrorCount = sc->stats.fcs_error;
3298 
3299 	return 0;
3300 }
3301 
3302 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3303 		struct survey_info *survey)
3304 {
3305 	struct ath5k_softc *sc = hw->priv;
3306 	struct ieee80211_conf *conf = &hw->conf;
3307 
3308 	 if (idx != 0)
3309 		return -ENOENT;
3310 
3311 	survey->channel = conf->channel;
3312 	survey->filled = SURVEY_INFO_NOISE_DBM;
3313 	survey->noise = sc->ah->ah_noise_floor;
3314 
3315 	return 0;
3316 }
3317 
3318 static u64
3319 ath5k_get_tsf(struct ieee80211_hw *hw)
3320 {
3321 	struct ath5k_softc *sc = hw->priv;
3322 
3323 	return ath5k_hw_get_tsf64(sc->ah);
3324 }
3325 
3326 static void
3327 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3328 {
3329 	struct ath5k_softc *sc = hw->priv;
3330 
3331 	ath5k_hw_set_tsf64(sc->ah, tsf);
3332 }
3333 
3334 static void
3335 ath5k_reset_tsf(struct ieee80211_hw *hw)
3336 {
3337 	struct ath5k_softc *sc = hw->priv;
3338 
3339 	/*
3340 	 * in IBSS mode we need to update the beacon timers too.
3341 	 * this will also reset the TSF if we call it with 0
3342 	 */
3343 	if (sc->opmode == NL80211_IFTYPE_ADHOC)
3344 		ath5k_beacon_update_timers(sc, 0);
3345 	else
3346 		ath5k_hw_reset_tsf(sc->ah);
3347 }
3348 
3349 /*
3350  * Updates the beacon that is sent by ath5k_beacon_send.  For adhoc,
3351  * this is called only once at config_bss time, for AP we do it every
3352  * SWBA interrupt so that the TIM will reflect buffered frames.
3353  *
3354  * Called with the beacon lock.
3355  */
3356 static int
3357 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3358 {
3359 	int ret;
3360 	struct ath5k_softc *sc = hw->priv;
3361 	struct sk_buff *skb;
3362 
3363 	if (WARN_ON(!vif)) {
3364 		ret = -EINVAL;
3365 		goto out;
3366 	}
3367 
3368 	skb = ieee80211_beacon_get(hw, vif);
3369 
3370 	if (!skb) {
3371 		ret = -ENOMEM;
3372 		goto out;
3373 	}
3374 
3375 	ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3376 
3377 	ath5k_txbuf_free(sc, sc->bbuf);
3378 	sc->bbuf->skb = skb;
3379 	ret = ath5k_beacon_setup(sc, sc->bbuf);
3380 	if (ret)
3381 		sc->bbuf->skb = NULL;
3382 out:
3383 	return ret;
3384 }
3385 
3386 static void
3387 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3388 {
3389 	struct ath5k_softc *sc = hw->priv;
3390 	struct ath5k_hw *ah = sc->ah;
3391 	u32 rfilt;
3392 	rfilt = ath5k_hw_get_rx_filter(ah);
3393 	if (enable)
3394 		rfilt |= AR5K_RX_FILTER_BEACON;
3395 	else
3396 		rfilt &= ~AR5K_RX_FILTER_BEACON;
3397 	ath5k_hw_set_rx_filter(ah, rfilt);
3398 	sc->filter_flags = rfilt;
3399 }
3400 
3401 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3402 				    struct ieee80211_vif *vif,
3403 				    struct ieee80211_bss_conf *bss_conf,
3404 				    u32 changes)
3405 {
3406 	struct ath5k_softc *sc = hw->priv;
3407 	struct ath5k_hw *ah = sc->ah;
3408 	struct ath_common *common = ath5k_hw_common(ah);
3409 	unsigned long flags;
3410 
3411 	mutex_lock(&sc->lock);
3412 	if (WARN_ON(sc->vif != vif))
3413 		goto unlock;
3414 
3415 	if (changes & BSS_CHANGED_BSSID) {
3416 		/* Cache for later use during resets */
3417 		memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3418 		common->curaid = 0;
3419 		ath5k_hw_set_associd(ah);
3420 		mmiowb();
3421 	}
3422 
3423 	if (changes & BSS_CHANGED_BEACON_INT)
3424 		sc->bintval = bss_conf->beacon_int;
3425 
3426 	if (changes & BSS_CHANGED_ASSOC) {
3427 		sc->assoc = bss_conf->assoc;
3428 		if (sc->opmode == NL80211_IFTYPE_STATION)
3429 			set_beacon_filter(hw, sc->assoc);
3430 		ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3431 			AR5K_LED_ASSOC : AR5K_LED_INIT);
3432 		if (bss_conf->assoc) {
3433 			ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3434 				  "Bss Info ASSOC %d, bssid: %pM\n",
3435 				  bss_conf->aid, common->curbssid);
3436 			common->curaid = bss_conf->aid;
3437 			ath5k_hw_set_associd(ah);
3438 			/* Once ANI is available you would start it here */
3439 		}
3440 	}
3441 
3442 	if (changes & BSS_CHANGED_BEACON) {
3443 		spin_lock_irqsave(&sc->block, flags);
3444 		ath5k_beacon_update(hw, vif);
3445 		spin_unlock_irqrestore(&sc->block, flags);
3446 	}
3447 
3448 	if (changes & BSS_CHANGED_BEACON_ENABLED)
3449 		sc->enable_beacon = bss_conf->enable_beacon;
3450 
3451 	if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3452 		       BSS_CHANGED_BEACON_INT))
3453 		ath5k_beacon_config(sc);
3454 
3455  unlock:
3456 	mutex_unlock(&sc->lock);
3457 }
3458 
3459 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3460 {
3461 	struct ath5k_softc *sc = hw->priv;
3462 	if (!sc->assoc)
3463 		ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3464 }
3465 
3466 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3467 {
3468 	struct ath5k_softc *sc = hw->priv;
3469 	ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3470 		AR5K_LED_ASSOC : AR5K_LED_INIT);
3471 }
3472 
3473 /**
3474  * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3475  *
3476  * @hw: struct ieee80211_hw pointer
3477  * @coverage_class: IEEE 802.11 coverage class number
3478  *
3479  * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3480  * coverage class. The values are persistent, they are restored after device
3481  * reset.
3482  */
3483 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3484 {
3485 	struct ath5k_softc *sc = hw->priv;
3486 
3487 	mutex_lock(&sc->lock);
3488 	ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3489 	mutex_unlock(&sc->lock);
3490 }
3491