1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/hardirq.h> 46 #include <linux/if.h> 47 #include <linux/io.h> 48 #include <linux/netdevice.h> 49 #include <linux/cache.h> 50 #include <linux/pci.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 #include <linux/slab.h> 54 55 #include <net/ieee80211_radiotap.h> 56 57 #include <asm/unaligned.h> 58 59 #include "base.h" 60 #include "reg.h" 61 #include "debug.h" 62 #include "ani.h" 63 64 static int modparam_nohwcrypt; 65 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 66 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 67 68 static int modparam_all_channels; 69 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 70 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 71 72 73 /******************\ 74 * Internal defines * 75 \******************/ 76 77 /* Module info */ 78 MODULE_AUTHOR("Jiri Slaby"); 79 MODULE_AUTHOR("Nick Kossifidis"); 80 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 81 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 82 MODULE_LICENSE("Dual BSD/GPL"); 83 MODULE_VERSION("0.6.0 (EXPERIMENTAL)"); 84 85 86 /* Known PCI ids */ 87 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = { 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ 97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ 98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ 99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ 100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ 101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ 102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 106 { 0 } 107 }; 108 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 109 110 /* Known SREVs */ 111 static const struct ath5k_srev_name srev_names[] = { 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 148 }; 149 150 static const struct ieee80211_rate ath5k_rates[] = { 151 { .bitrate = 10, 152 .hw_value = ATH5K_RATE_CODE_1M, }, 153 { .bitrate = 20, 154 .hw_value = ATH5K_RATE_CODE_2M, 155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 156 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 157 { .bitrate = 55, 158 .hw_value = ATH5K_RATE_CODE_5_5M, 159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 160 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 161 { .bitrate = 110, 162 .hw_value = ATH5K_RATE_CODE_11M, 163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 164 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 165 { .bitrate = 60, 166 .hw_value = ATH5K_RATE_CODE_6M, 167 .flags = 0 }, 168 { .bitrate = 90, 169 .hw_value = ATH5K_RATE_CODE_9M, 170 .flags = 0 }, 171 { .bitrate = 120, 172 .hw_value = ATH5K_RATE_CODE_12M, 173 .flags = 0 }, 174 { .bitrate = 180, 175 .hw_value = ATH5K_RATE_CODE_18M, 176 .flags = 0 }, 177 { .bitrate = 240, 178 .hw_value = ATH5K_RATE_CODE_24M, 179 .flags = 0 }, 180 { .bitrate = 360, 181 .hw_value = ATH5K_RATE_CODE_36M, 182 .flags = 0 }, 183 { .bitrate = 480, 184 .hw_value = ATH5K_RATE_CODE_48M, 185 .flags = 0 }, 186 { .bitrate = 540, 187 .hw_value = ATH5K_RATE_CODE_54M, 188 .flags = 0 }, 189 /* XR missing */ 190 }; 191 192 /* 193 * Prototypes - PCI stack related functions 194 */ 195 static int __devinit ath5k_pci_probe(struct pci_dev *pdev, 196 const struct pci_device_id *id); 197 static void __devexit ath5k_pci_remove(struct pci_dev *pdev); 198 #ifdef CONFIG_PM_SLEEP 199 static int ath5k_pci_suspend(struct device *dev); 200 static int ath5k_pci_resume(struct device *dev); 201 202 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 203 #define ATH5K_PM_OPS (&ath5k_pm_ops) 204 #else 205 #define ATH5K_PM_OPS NULL 206 #endif /* CONFIG_PM_SLEEP */ 207 208 static struct pci_driver ath5k_pci_driver = { 209 .name = KBUILD_MODNAME, 210 .id_table = ath5k_pci_id_table, 211 .probe = ath5k_pci_probe, 212 .remove = __devexit_p(ath5k_pci_remove), 213 .driver.pm = ATH5K_PM_OPS, 214 }; 215 216 217 218 /* 219 * Prototypes - MAC 802.11 stack related functions 220 */ 221 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb); 222 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 223 struct ath5k_txq *txq); 224 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan); 225 static int ath5k_start(struct ieee80211_hw *hw); 226 static void ath5k_stop(struct ieee80211_hw *hw); 227 static int ath5k_add_interface(struct ieee80211_hw *hw, 228 struct ieee80211_vif *vif); 229 static void ath5k_remove_interface(struct ieee80211_hw *hw, 230 struct ieee80211_vif *vif); 231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed); 232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 233 struct netdev_hw_addr_list *mc_list); 234 static void ath5k_configure_filter(struct ieee80211_hw *hw, 235 unsigned int changed_flags, 236 unsigned int *new_flags, 237 u64 multicast); 238 static int ath5k_set_key(struct ieee80211_hw *hw, 239 enum set_key_cmd cmd, 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 241 struct ieee80211_key_conf *key); 242 static int ath5k_get_stats(struct ieee80211_hw *hw, 243 struct ieee80211_low_level_stats *stats); 244 static int ath5k_get_survey(struct ieee80211_hw *hw, 245 int idx, struct survey_info *survey); 246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw); 247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf); 248 static void ath5k_reset_tsf(struct ieee80211_hw *hw); 249 static int ath5k_beacon_update(struct ieee80211_hw *hw, 250 struct ieee80211_vif *vif); 251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 252 struct ieee80211_vif *vif, 253 struct ieee80211_bss_conf *bss_conf, 254 u32 changes); 255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw); 256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw); 257 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, 258 u8 coverage_class); 259 260 static const struct ieee80211_ops ath5k_hw_ops = { 261 .tx = ath5k_tx, 262 .start = ath5k_start, 263 .stop = ath5k_stop, 264 .add_interface = ath5k_add_interface, 265 .remove_interface = ath5k_remove_interface, 266 .config = ath5k_config, 267 .prepare_multicast = ath5k_prepare_multicast, 268 .configure_filter = ath5k_configure_filter, 269 .set_key = ath5k_set_key, 270 .get_stats = ath5k_get_stats, 271 .get_survey = ath5k_get_survey, 272 .conf_tx = NULL, 273 .get_tsf = ath5k_get_tsf, 274 .set_tsf = ath5k_set_tsf, 275 .reset_tsf = ath5k_reset_tsf, 276 .bss_info_changed = ath5k_bss_info_changed, 277 .sw_scan_start = ath5k_sw_scan_start, 278 .sw_scan_complete = ath5k_sw_scan_complete, 279 .set_coverage_class = ath5k_set_coverage_class, 280 }; 281 282 /* 283 * Prototypes - Internal functions 284 */ 285 /* Attach detach */ 286 static int ath5k_attach(struct pci_dev *pdev, 287 struct ieee80211_hw *hw); 288 static void ath5k_detach(struct pci_dev *pdev, 289 struct ieee80211_hw *hw); 290 /* Channel/mode setup */ 291 static inline short ath5k_ieee2mhz(short chan); 292 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, 293 struct ieee80211_channel *channels, 294 unsigned int mode, 295 unsigned int max); 296 static int ath5k_setup_bands(struct ieee80211_hw *hw); 297 static int ath5k_chan_set(struct ath5k_softc *sc, 298 struct ieee80211_channel *chan); 299 static void ath5k_setcurmode(struct ath5k_softc *sc, 300 unsigned int mode); 301 static void ath5k_mode_setup(struct ath5k_softc *sc); 302 303 /* Descriptor setup */ 304 static int ath5k_desc_alloc(struct ath5k_softc *sc, 305 struct pci_dev *pdev); 306 static void ath5k_desc_free(struct ath5k_softc *sc, 307 struct pci_dev *pdev); 308 /* Buffers setup */ 309 static int ath5k_rxbuf_setup(struct ath5k_softc *sc, 310 struct ath5k_buf *bf); 311 static int ath5k_txbuf_setup(struct ath5k_softc *sc, 312 struct ath5k_buf *bf, 313 struct ath5k_txq *txq, int padsize); 314 static inline void ath5k_txbuf_free(struct ath5k_softc *sc, 315 struct ath5k_buf *bf) 316 { 317 BUG_ON(!bf); 318 if (!bf->skb) 319 return; 320 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, 321 PCI_DMA_TODEVICE); 322 dev_kfree_skb_any(bf->skb); 323 bf->skb = NULL; 324 } 325 326 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc, 327 struct ath5k_buf *bf) 328 { 329 struct ath5k_hw *ah = sc->ah; 330 struct ath_common *common = ath5k_hw_common(ah); 331 332 BUG_ON(!bf); 333 if (!bf->skb) 334 return; 335 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize, 336 PCI_DMA_FROMDEVICE); 337 dev_kfree_skb_any(bf->skb); 338 bf->skb = NULL; 339 } 340 341 342 /* Queues setup */ 343 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc, 344 int qtype, int subtype); 345 static int ath5k_beaconq_setup(struct ath5k_hw *ah); 346 static int ath5k_beaconq_config(struct ath5k_softc *sc); 347 static void ath5k_txq_drainq(struct ath5k_softc *sc, 348 struct ath5k_txq *txq); 349 static void ath5k_txq_cleanup(struct ath5k_softc *sc); 350 static void ath5k_txq_release(struct ath5k_softc *sc); 351 /* Rx handling */ 352 static int ath5k_rx_start(struct ath5k_softc *sc); 353 static void ath5k_rx_stop(struct ath5k_softc *sc); 354 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, 355 struct ath5k_desc *ds, 356 struct sk_buff *skb, 357 struct ath5k_rx_status *rs); 358 static void ath5k_tasklet_rx(unsigned long data); 359 /* Tx handling */ 360 static void ath5k_tx_processq(struct ath5k_softc *sc, 361 struct ath5k_txq *txq); 362 static void ath5k_tasklet_tx(unsigned long data); 363 /* Beacon handling */ 364 static int ath5k_beacon_setup(struct ath5k_softc *sc, 365 struct ath5k_buf *bf); 366 static void ath5k_beacon_send(struct ath5k_softc *sc); 367 static void ath5k_beacon_config(struct ath5k_softc *sc); 368 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 369 static void ath5k_tasklet_beacon(unsigned long data); 370 static void ath5k_tasklet_ani(unsigned long data); 371 372 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 373 { 374 u64 tsf = ath5k_hw_get_tsf64(ah); 375 376 if ((tsf & 0x7fff) < rstamp) 377 tsf -= 0x8000; 378 379 return (tsf & ~0x7fff) | rstamp; 380 } 381 382 /* Interrupt handling */ 383 static int ath5k_init(struct ath5k_softc *sc); 384 static int ath5k_stop_locked(struct ath5k_softc *sc); 385 static int ath5k_stop_hw(struct ath5k_softc *sc); 386 static irqreturn_t ath5k_intr(int irq, void *dev_id); 387 static void ath5k_tasklet_reset(unsigned long data); 388 389 static void ath5k_tasklet_calibrate(unsigned long data); 390 391 /* 392 * Module init/exit functions 393 */ 394 static int __init 395 init_ath5k_pci(void) 396 { 397 int ret; 398 399 ath5k_debug_init(); 400 401 ret = pci_register_driver(&ath5k_pci_driver); 402 if (ret) { 403 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 404 return ret; 405 } 406 407 return 0; 408 } 409 410 static void __exit 411 exit_ath5k_pci(void) 412 { 413 pci_unregister_driver(&ath5k_pci_driver); 414 415 ath5k_debug_finish(); 416 } 417 418 module_init(init_ath5k_pci); 419 module_exit(exit_ath5k_pci); 420 421 422 /********************\ 423 * PCI Initialization * 424 \********************/ 425 426 static const char * 427 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 428 { 429 const char *name = "xxxxx"; 430 unsigned int i; 431 432 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 433 if (srev_names[i].sr_type != type) 434 continue; 435 436 if ((val & 0xf0) == srev_names[i].sr_val) 437 name = srev_names[i].sr_name; 438 439 if ((val & 0xff) == srev_names[i].sr_val) { 440 name = srev_names[i].sr_name; 441 break; 442 } 443 } 444 445 return name; 446 } 447 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 448 { 449 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 450 return ath5k_hw_reg_read(ah, reg_offset); 451 } 452 453 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 454 { 455 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 456 ath5k_hw_reg_write(ah, val, reg_offset); 457 } 458 459 static const struct ath_ops ath5k_common_ops = { 460 .read = ath5k_ioread32, 461 .write = ath5k_iowrite32, 462 }; 463 464 static int __devinit 465 ath5k_pci_probe(struct pci_dev *pdev, 466 const struct pci_device_id *id) 467 { 468 void __iomem *mem; 469 struct ath5k_softc *sc; 470 struct ath_common *common; 471 struct ieee80211_hw *hw; 472 int ret; 473 u8 csz; 474 475 ret = pci_enable_device(pdev); 476 if (ret) { 477 dev_err(&pdev->dev, "can't enable device\n"); 478 goto err; 479 } 480 481 /* XXX 32-bit addressing only */ 482 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 483 if (ret) { 484 dev_err(&pdev->dev, "32-bit DMA not available\n"); 485 goto err_dis; 486 } 487 488 /* 489 * Cache line size is used to size and align various 490 * structures used to communicate with the hardware. 491 */ 492 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 493 if (csz == 0) { 494 /* 495 * Linux 2.4.18 (at least) writes the cache line size 496 * register as a 16-bit wide register which is wrong. 497 * We must have this setup properly for rx buffer 498 * DMA to work so force a reasonable value here if it 499 * comes up zero. 500 */ 501 csz = L1_CACHE_BYTES >> 2; 502 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 503 } 504 /* 505 * The default setting of latency timer yields poor results, 506 * set it to the value used by other systems. It may be worth 507 * tweaking this setting more. 508 */ 509 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 510 511 /* Enable bus mastering */ 512 pci_set_master(pdev); 513 514 /* 515 * Disable the RETRY_TIMEOUT register (0x41) to keep 516 * PCI Tx retries from interfering with C3 CPU state. 517 */ 518 pci_write_config_byte(pdev, 0x41, 0); 519 520 ret = pci_request_region(pdev, 0, "ath5k"); 521 if (ret) { 522 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 523 goto err_dis; 524 } 525 526 mem = pci_iomap(pdev, 0, 0); 527 if (!mem) { 528 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; 529 ret = -EIO; 530 goto err_reg; 531 } 532 533 /* 534 * Allocate hw (mac80211 main struct) 535 * and hw->priv (driver private data) 536 */ 537 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); 538 if (hw == NULL) { 539 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 540 ret = -ENOMEM; 541 goto err_map; 542 } 543 544 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 545 546 /* Initialize driver private data */ 547 SET_IEEE80211_DEV(hw, &pdev->dev); 548 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 549 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 550 IEEE80211_HW_SIGNAL_DBM; 551 552 hw->wiphy->interface_modes = 553 BIT(NL80211_IFTYPE_AP) | 554 BIT(NL80211_IFTYPE_STATION) | 555 BIT(NL80211_IFTYPE_ADHOC) | 556 BIT(NL80211_IFTYPE_MESH_POINT); 557 558 hw->extra_tx_headroom = 2; 559 hw->channel_change_time = 5000; 560 sc = hw->priv; 561 sc->hw = hw; 562 sc->pdev = pdev; 563 564 ath5k_debug_init_device(sc); 565 566 /* 567 * Mark the device as detached to avoid processing 568 * interrupts until setup is complete. 569 */ 570 __set_bit(ATH_STAT_INVALID, sc->status); 571 572 sc->iobase = mem; /* So we can unmap it on detach */ 573 sc->opmode = NL80211_IFTYPE_STATION; 574 sc->bintval = 1000; 575 mutex_init(&sc->lock); 576 spin_lock_init(&sc->rxbuflock); 577 spin_lock_init(&sc->txbuflock); 578 spin_lock_init(&sc->block); 579 580 /* Set private data */ 581 pci_set_drvdata(pdev, hw); 582 583 /* Setup interrupt handler */ 584 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 585 if (ret) { 586 ATH5K_ERR(sc, "request_irq failed\n"); 587 goto err_free; 588 } 589 590 /*If we passed the test malloc a ath5k_hw struct*/ 591 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); 592 if (!sc->ah) { 593 ret = -ENOMEM; 594 ATH5K_ERR(sc, "out of memory\n"); 595 goto err_irq; 596 } 597 598 sc->ah->ah_sc = sc; 599 sc->ah->ah_iobase = sc->iobase; 600 common = ath5k_hw_common(sc->ah); 601 common->ops = &ath5k_common_ops; 602 common->ah = sc->ah; 603 common->hw = hw; 604 common->cachelsz = csz << 2; /* convert to bytes */ 605 606 /* Initialize device */ 607 ret = ath5k_hw_attach(sc); 608 if (ret) { 609 goto err_free_ah; 610 } 611 612 /* set up multi-rate retry capabilities */ 613 if (sc->ah->ah_version == AR5K_AR5212) { 614 hw->max_rates = 4; 615 hw->max_rate_tries = 11; 616 } 617 618 /* Finish private driver data initialization */ 619 ret = ath5k_attach(pdev, hw); 620 if (ret) 621 goto err_ah; 622 623 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 624 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 625 sc->ah->ah_mac_srev, 626 sc->ah->ah_phy_revision); 627 628 if (!sc->ah->ah_single_chip) { 629 /* Single chip radio (!RF5111) */ 630 if (sc->ah->ah_radio_5ghz_revision && 631 !sc->ah->ah_radio_2ghz_revision) { 632 /* No 5GHz support -> report 2GHz radio */ 633 if (!test_bit(AR5K_MODE_11A, 634 sc->ah->ah_capabilities.cap_mode)) { 635 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 636 ath5k_chip_name(AR5K_VERSION_RAD, 637 sc->ah->ah_radio_5ghz_revision), 638 sc->ah->ah_radio_5ghz_revision); 639 /* No 2GHz support (5110 and some 640 * 5Ghz only cards) -> report 5Ghz radio */ 641 } else if (!test_bit(AR5K_MODE_11B, 642 sc->ah->ah_capabilities.cap_mode)) { 643 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 644 ath5k_chip_name(AR5K_VERSION_RAD, 645 sc->ah->ah_radio_5ghz_revision), 646 sc->ah->ah_radio_5ghz_revision); 647 /* Multiband radio */ 648 } else { 649 ATH5K_INFO(sc, "RF%s multiband radio found" 650 " (0x%x)\n", 651 ath5k_chip_name(AR5K_VERSION_RAD, 652 sc->ah->ah_radio_5ghz_revision), 653 sc->ah->ah_radio_5ghz_revision); 654 } 655 } 656 /* Multi chip radio (RF5111 - RF2111) -> 657 * report both 2GHz/5GHz radios */ 658 else if (sc->ah->ah_radio_5ghz_revision && 659 sc->ah->ah_radio_2ghz_revision){ 660 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 661 ath5k_chip_name(AR5K_VERSION_RAD, 662 sc->ah->ah_radio_5ghz_revision), 663 sc->ah->ah_radio_5ghz_revision); 664 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 665 ath5k_chip_name(AR5K_VERSION_RAD, 666 sc->ah->ah_radio_2ghz_revision), 667 sc->ah->ah_radio_2ghz_revision); 668 } 669 } 670 671 672 /* ready to process interrupts */ 673 __clear_bit(ATH_STAT_INVALID, sc->status); 674 675 return 0; 676 err_ah: 677 ath5k_hw_detach(sc->ah); 678 err_irq: 679 free_irq(pdev->irq, sc); 680 err_free_ah: 681 kfree(sc->ah); 682 err_free: 683 ieee80211_free_hw(hw); 684 err_map: 685 pci_iounmap(pdev, mem); 686 err_reg: 687 pci_release_region(pdev, 0); 688 err_dis: 689 pci_disable_device(pdev); 690 err: 691 return ret; 692 } 693 694 static void __devexit 695 ath5k_pci_remove(struct pci_dev *pdev) 696 { 697 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 698 struct ath5k_softc *sc = hw->priv; 699 700 ath5k_debug_finish_device(sc); 701 ath5k_detach(pdev, hw); 702 ath5k_hw_detach(sc->ah); 703 kfree(sc->ah); 704 free_irq(pdev->irq, sc); 705 pci_iounmap(pdev, sc->iobase); 706 pci_release_region(pdev, 0); 707 pci_disable_device(pdev); 708 ieee80211_free_hw(hw); 709 } 710 711 #ifdef CONFIG_PM_SLEEP 712 static int ath5k_pci_suspend(struct device *dev) 713 { 714 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev)); 715 struct ath5k_softc *sc = hw->priv; 716 717 ath5k_led_off(sc); 718 return 0; 719 } 720 721 static int ath5k_pci_resume(struct device *dev) 722 { 723 struct pci_dev *pdev = to_pci_dev(dev); 724 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 725 struct ath5k_softc *sc = hw->priv; 726 727 /* 728 * Suspend/Resume resets the PCI configuration space, so we have to 729 * re-disable the RETRY_TIMEOUT register (0x41) to keep 730 * PCI Tx retries from interfering with C3 CPU state 731 */ 732 pci_write_config_byte(pdev, 0x41, 0); 733 734 ath5k_led_enable(sc); 735 return 0; 736 } 737 #endif /* CONFIG_PM_SLEEP */ 738 739 740 /***********************\ 741 * Driver Initialization * 742 \***********************/ 743 744 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 745 { 746 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 747 struct ath5k_softc *sc = hw->priv; 748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 749 750 return ath_reg_notifier_apply(wiphy, request, regulatory); 751 } 752 753 static int 754 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) 755 { 756 struct ath5k_softc *sc = hw->priv; 757 struct ath5k_hw *ah = sc->ah; 758 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 759 u8 mac[ETH_ALEN] = {}; 760 int ret; 761 762 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device); 763 764 /* 765 * Check if the MAC has multi-rate retry support. 766 * We do this by trying to setup a fake extended 767 * descriptor. MAC's that don't have support will 768 * return false w/o doing anything. MAC's that do 769 * support it will return true w/o doing anything. 770 */ 771 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 772 if (ret < 0) 773 goto err; 774 if (ret > 0) 775 __set_bit(ATH_STAT_MRRETRY, sc->status); 776 777 /* 778 * Collect the channel list. The 802.11 layer 779 * is resposible for filtering this list based 780 * on settings like the phy mode and regulatory 781 * domain restrictions. 782 */ 783 ret = ath5k_setup_bands(hw); 784 if (ret) { 785 ATH5K_ERR(sc, "can't get channels\n"); 786 goto err; 787 } 788 789 /* NB: setup here so ath5k_rate_update is happy */ 790 if (test_bit(AR5K_MODE_11A, ah->ah_modes)) 791 ath5k_setcurmode(sc, AR5K_MODE_11A); 792 else 793 ath5k_setcurmode(sc, AR5K_MODE_11B); 794 795 /* 796 * Allocate tx+rx descriptors and populate the lists. 797 */ 798 ret = ath5k_desc_alloc(sc, pdev); 799 if (ret) { 800 ATH5K_ERR(sc, "can't allocate descriptors\n"); 801 goto err; 802 } 803 804 /* 805 * Allocate hardware transmit queues: one queue for 806 * beacon frames and one data queue for each QoS 807 * priority. Note that hw functions handle reseting 808 * these queues at the needed time. 809 */ 810 ret = ath5k_beaconq_setup(ah); 811 if (ret < 0) { 812 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 813 goto err_desc; 814 } 815 sc->bhalq = ret; 816 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 817 if (IS_ERR(sc->cabq)) { 818 ATH5K_ERR(sc, "can't setup cab queue\n"); 819 ret = PTR_ERR(sc->cabq); 820 goto err_bhal; 821 } 822 823 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 824 if (IS_ERR(sc->txq)) { 825 ATH5K_ERR(sc, "can't setup xmit queue\n"); 826 ret = PTR_ERR(sc->txq); 827 goto err_queues; 828 } 829 830 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 831 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 832 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc); 833 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 834 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 835 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); 836 837 ret = ath5k_eeprom_read_mac(ah, mac); 838 if (ret) { 839 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n", 840 sc->pdev->device); 841 goto err_queues; 842 } 843 844 SET_IEEE80211_PERM_ADDR(hw, mac); 845 /* All MAC address bits matter for ACKs */ 846 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); 847 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 848 849 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 850 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 851 if (ret) { 852 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 853 goto err_queues; 854 } 855 856 ret = ieee80211_register_hw(hw); 857 if (ret) { 858 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 859 goto err_queues; 860 } 861 862 if (!ath_is_world_regd(regulatory)) 863 regulatory_hint(hw->wiphy, regulatory->alpha2); 864 865 ath5k_init_leds(sc); 866 867 return 0; 868 err_queues: 869 ath5k_txq_release(sc); 870 err_bhal: 871 ath5k_hw_release_tx_queue(ah, sc->bhalq); 872 err_desc: 873 ath5k_desc_free(sc, pdev); 874 err: 875 return ret; 876 } 877 878 static void 879 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) 880 { 881 struct ath5k_softc *sc = hw->priv; 882 883 /* 884 * NB: the order of these is important: 885 * o call the 802.11 layer before detaching ath5k_hw to 886 * insure callbacks into the driver to delete global 887 * key cache entries can be handled 888 * o reclaim the tx queue data structures after calling 889 * the 802.11 layer as we'll get called back to reclaim 890 * node state and potentially want to use them 891 * o to cleanup the tx queues the hal is called, so detach 892 * it last 893 * XXX: ??? detach ath5k_hw ??? 894 * Other than that, it's straightforward... 895 */ 896 ieee80211_unregister_hw(hw); 897 ath5k_desc_free(sc, pdev); 898 ath5k_txq_release(sc); 899 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 900 ath5k_unregister_leds(sc); 901 902 /* 903 * NB: can't reclaim these until after ieee80211_ifdetach 904 * returns because we'll get called back to reclaim node 905 * state and potentially want to use them. 906 */ 907 } 908 909 910 911 912 /********************\ 913 * Channel/mode setup * 914 \********************/ 915 916 /* 917 * Convert IEEE channel number to MHz frequency. 918 */ 919 static inline short 920 ath5k_ieee2mhz(short chan) 921 { 922 if (chan <= 14 || chan >= 27) 923 return ieee80211chan2mhz(chan); 924 else 925 return 2212 + chan * 20; 926 } 927 928 /* 929 * Returns true for the channel numbers used without all_channels modparam. 930 */ 931 static bool ath5k_is_standard_channel(short chan) 932 { 933 return ((chan <= 14) || 934 /* UNII 1,2 */ 935 ((chan & 3) == 0 && chan >= 36 && chan <= 64) || 936 /* midband */ 937 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 938 /* UNII-3 */ 939 ((chan & 3) == 1 && chan >= 149 && chan <= 165)); 940 } 941 942 static unsigned int 943 ath5k_copy_channels(struct ath5k_hw *ah, 944 struct ieee80211_channel *channels, 945 unsigned int mode, 946 unsigned int max) 947 { 948 unsigned int i, count, size, chfreq, freq, ch; 949 950 if (!test_bit(mode, ah->ah_modes)) 951 return 0; 952 953 switch (mode) { 954 case AR5K_MODE_11A: 955 case AR5K_MODE_11A_TURBO: 956 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 957 size = 220 ; 958 chfreq = CHANNEL_5GHZ; 959 break; 960 case AR5K_MODE_11B: 961 case AR5K_MODE_11G: 962 case AR5K_MODE_11G_TURBO: 963 size = 26; 964 chfreq = CHANNEL_2GHZ; 965 break; 966 default: 967 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 968 return 0; 969 } 970 971 for (i = 0, count = 0; i < size && max > 0; i++) { 972 ch = i + 1 ; 973 freq = ath5k_ieee2mhz(ch); 974 975 /* Check if channel is supported by the chipset */ 976 if (!ath5k_channel_ok(ah, freq, chfreq)) 977 continue; 978 979 if (!modparam_all_channels && !ath5k_is_standard_channel(ch)) 980 continue; 981 982 /* Write channel info and increment counter */ 983 channels[count].center_freq = freq; 984 channels[count].band = (chfreq == CHANNEL_2GHZ) ? 985 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; 986 switch (mode) { 987 case AR5K_MODE_11A: 988 case AR5K_MODE_11G: 989 channels[count].hw_value = chfreq | CHANNEL_OFDM; 990 break; 991 case AR5K_MODE_11A_TURBO: 992 case AR5K_MODE_11G_TURBO: 993 channels[count].hw_value = chfreq | 994 CHANNEL_OFDM | CHANNEL_TURBO; 995 break; 996 case AR5K_MODE_11B: 997 channels[count].hw_value = CHANNEL_B; 998 } 999 1000 count++; 1001 max--; 1002 } 1003 1004 return count; 1005 } 1006 1007 static void 1008 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 1009 { 1010 u8 i; 1011 1012 for (i = 0; i < AR5K_MAX_RATES; i++) 1013 sc->rate_idx[b->band][i] = -1; 1014 1015 for (i = 0; i < b->n_bitrates; i++) { 1016 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 1017 if (b->bitrates[i].hw_value_short) 1018 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 1019 } 1020 } 1021 1022 static int 1023 ath5k_setup_bands(struct ieee80211_hw *hw) 1024 { 1025 struct ath5k_softc *sc = hw->priv; 1026 struct ath5k_hw *ah = sc->ah; 1027 struct ieee80211_supported_band *sband; 1028 int max_c, count_c = 0; 1029 int i; 1030 1031 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 1032 max_c = ARRAY_SIZE(sc->channels); 1033 1034 /* 2GHz band */ 1035 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1036 sband->band = IEEE80211_BAND_2GHZ; 1037 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 1038 1039 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 1040 /* G mode */ 1041 memcpy(sband->bitrates, &ath5k_rates[0], 1042 sizeof(struct ieee80211_rate) * 12); 1043 sband->n_bitrates = 12; 1044 1045 sband->channels = sc->channels; 1046 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1047 AR5K_MODE_11G, max_c); 1048 1049 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1050 count_c = sband->n_channels; 1051 max_c -= count_c; 1052 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 1053 /* B mode */ 1054 memcpy(sband->bitrates, &ath5k_rates[0], 1055 sizeof(struct ieee80211_rate) * 4); 1056 sband->n_bitrates = 4; 1057 1058 /* 5211 only supports B rates and uses 4bit rate codes 1059 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 1060 * fix them up here: 1061 */ 1062 if (ah->ah_version == AR5K_AR5211) { 1063 for (i = 0; i < 4; i++) { 1064 sband->bitrates[i].hw_value = 1065 sband->bitrates[i].hw_value & 0xF; 1066 sband->bitrates[i].hw_value_short = 1067 sband->bitrates[i].hw_value_short & 0xF; 1068 } 1069 } 1070 1071 sband->channels = sc->channels; 1072 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1073 AR5K_MODE_11B, max_c); 1074 1075 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1076 count_c = sband->n_channels; 1077 max_c -= count_c; 1078 } 1079 ath5k_setup_rate_idx(sc, sband); 1080 1081 /* 5GHz band, A mode */ 1082 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 1083 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1084 sband->band = IEEE80211_BAND_5GHZ; 1085 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 1086 1087 memcpy(sband->bitrates, &ath5k_rates[4], 1088 sizeof(struct ieee80211_rate) * 8); 1089 sband->n_bitrates = 8; 1090 1091 sband->channels = &sc->channels[count_c]; 1092 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1093 AR5K_MODE_11A, max_c); 1094 1095 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 1096 } 1097 ath5k_setup_rate_idx(sc, sband); 1098 1099 ath5k_debug_dump_bands(sc); 1100 1101 return 0; 1102 } 1103 1104 /* 1105 * Set/change channels. We always reset the chip. 1106 * To accomplish this we must first cleanup any pending DMA, 1107 * then restart stuff after a la ath5k_init. 1108 * 1109 * Called with sc->lock. 1110 */ 1111 static int 1112 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 1113 { 1114 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", 1115 sc->curchan->center_freq, chan->center_freq); 1116 1117 /* 1118 * To switch channels clear any pending DMA operations; 1119 * wait long enough for the RX fifo to drain, reset the 1120 * hardware at the new frequency, and then re-enable 1121 * the relevant bits of the h/w. 1122 */ 1123 return ath5k_reset(sc, chan); 1124 } 1125 1126 static void 1127 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) 1128 { 1129 sc->curmode = mode; 1130 1131 if (mode == AR5K_MODE_11A) { 1132 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1133 } else { 1134 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1135 } 1136 } 1137 1138 static void 1139 ath5k_mode_setup(struct ath5k_softc *sc) 1140 { 1141 struct ath5k_hw *ah = sc->ah; 1142 u32 rfilt; 1143 1144 /* configure rx filter */ 1145 rfilt = sc->filter_flags; 1146 ath5k_hw_set_rx_filter(ah, rfilt); 1147 1148 if (ath5k_hw_hasbssidmask(ah)) 1149 ath5k_hw_set_bssid_mask(ah, sc->bssidmask); 1150 1151 /* configure operational mode */ 1152 ath5k_hw_set_opmode(ah, sc->opmode); 1153 1154 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode); 1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 1156 } 1157 1158 static inline int 1159 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 1160 { 1161 int rix; 1162 1163 /* return base rate on errors */ 1164 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 1165 "hw_rix out of bounds: %x\n", hw_rix)) 1166 return 0; 1167 1168 rix = sc->rate_idx[sc->curband->band][hw_rix]; 1169 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 1170 rix = 0; 1171 1172 return rix; 1173 } 1174 1175 /***************\ 1176 * Buffers setup * 1177 \***************/ 1178 1179 static 1180 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 1181 { 1182 struct ath_common *common = ath5k_hw_common(sc->ah); 1183 struct sk_buff *skb; 1184 1185 /* 1186 * Allocate buffer with headroom_needed space for the 1187 * fake physical layer header at the start. 1188 */ 1189 skb = ath_rxbuf_alloc(common, 1190 common->rx_bufsize, 1191 GFP_ATOMIC); 1192 1193 if (!skb) { 1194 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 1195 common->rx_bufsize); 1196 return NULL; 1197 } 1198 1199 *skb_addr = pci_map_single(sc->pdev, 1200 skb->data, common->rx_bufsize, 1201 PCI_DMA_FROMDEVICE); 1202 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) { 1203 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 1204 dev_kfree_skb(skb); 1205 return NULL; 1206 } 1207 return skb; 1208 } 1209 1210 static int 1211 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1212 { 1213 struct ath5k_hw *ah = sc->ah; 1214 struct sk_buff *skb = bf->skb; 1215 struct ath5k_desc *ds; 1216 int ret; 1217 1218 if (!skb) { 1219 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 1220 if (!skb) 1221 return -ENOMEM; 1222 bf->skb = skb; 1223 } 1224 1225 /* 1226 * Setup descriptors. For receive we always terminate 1227 * the descriptor list with a self-linked entry so we'll 1228 * not get overrun under high load (as can happen with a 1229 * 5212 when ANI processing enables PHY error frames). 1230 * 1231 * To insure the last descriptor is self-linked we create 1232 * each descriptor as self-linked and add it to the end. As 1233 * each additional descriptor is added the previous self-linked 1234 * entry is ``fixed'' naturally. This should be safe even 1235 * if DMA is happening. When processing RX interrupts we 1236 * never remove/process the last, self-linked, entry on the 1237 * descriptor list. This insures the hardware always has 1238 * someplace to write a new frame. 1239 */ 1240 ds = bf->desc; 1241 ds->ds_link = bf->daddr; /* link to self */ 1242 ds->ds_data = bf->skbaddr; 1243 ret = ah->ah_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 1244 if (ret) 1245 return ret; 1246 1247 if (sc->rxlink != NULL) 1248 *sc->rxlink = bf->daddr; 1249 sc->rxlink = &ds->ds_link; 1250 return 0; 1251 } 1252 1253 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1254 { 1255 struct ieee80211_hdr *hdr; 1256 enum ath5k_pkt_type htype; 1257 __le16 fc; 1258 1259 hdr = (struct ieee80211_hdr *)skb->data; 1260 fc = hdr->frame_control; 1261 1262 if (ieee80211_is_beacon(fc)) 1263 htype = AR5K_PKT_TYPE_BEACON; 1264 else if (ieee80211_is_probe_resp(fc)) 1265 htype = AR5K_PKT_TYPE_PROBE_RESP; 1266 else if (ieee80211_is_atim(fc)) 1267 htype = AR5K_PKT_TYPE_ATIM; 1268 else if (ieee80211_is_pspoll(fc)) 1269 htype = AR5K_PKT_TYPE_PSPOLL; 1270 else 1271 htype = AR5K_PKT_TYPE_NORMAL; 1272 1273 return htype; 1274 } 1275 1276 static int 1277 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1278 struct ath5k_txq *txq, int padsize) 1279 { 1280 struct ath5k_hw *ah = sc->ah; 1281 struct ath5k_desc *ds = bf->desc; 1282 struct sk_buff *skb = bf->skb; 1283 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1284 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 1285 struct ieee80211_rate *rate; 1286 unsigned int mrr_rate[3], mrr_tries[3]; 1287 int i, ret; 1288 u16 hw_rate; 1289 u16 cts_rate = 0; 1290 u16 duration = 0; 1291 u8 rc_flags; 1292 1293 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 1294 1295 /* XXX endianness */ 1296 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 1297 PCI_DMA_TODEVICE); 1298 1299 rate = ieee80211_get_tx_rate(sc->hw, info); 1300 1301 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1302 flags |= AR5K_TXDESC_NOACK; 1303 1304 rc_flags = info->control.rates[0].flags; 1305 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 1306 rate->hw_value_short : rate->hw_value; 1307 1308 pktlen = skb->len; 1309 1310 /* FIXME: If we are in g mode and rate is a CCK rate 1311 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1312 * from tx power (value is in dB units already) */ 1313 if (info->control.hw_key) { 1314 keyidx = info->control.hw_key->hw_key_idx; 1315 pktlen += info->control.hw_key->icv_len; 1316 } 1317 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1318 flags |= AR5K_TXDESC_RTSENA; 1319 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1320 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 1321 sc->vif, pktlen, info)); 1322 } 1323 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1324 flags |= AR5K_TXDESC_CTSENA; 1325 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1326 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 1327 sc->vif, pktlen, info)); 1328 } 1329 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 1330 ieee80211_get_hdrlen_from_skb(skb), padsize, 1331 get_hw_packet_type(skb), 1332 (sc->power_level * 2), 1333 hw_rate, 1334 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 1335 cts_rate, duration); 1336 if (ret) 1337 goto err_unmap; 1338 1339 memset(mrr_rate, 0, sizeof(mrr_rate)); 1340 memset(mrr_tries, 0, sizeof(mrr_tries)); 1341 for (i = 0; i < 3; i++) { 1342 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 1343 if (!rate) 1344 break; 1345 1346 mrr_rate[i] = rate->hw_value; 1347 mrr_tries[i] = info->control.rates[i + 1].count; 1348 } 1349 1350 ah->ah_setup_mrr_tx_desc(ah, ds, 1351 mrr_rate[0], mrr_tries[0], 1352 mrr_rate[1], mrr_tries[1], 1353 mrr_rate[2], mrr_tries[2]); 1354 1355 ds->ds_link = 0; 1356 ds->ds_data = bf->skbaddr; 1357 1358 spin_lock_bh(&txq->lock); 1359 list_add_tail(&bf->list, &txq->q); 1360 if (txq->link == NULL) /* is this first packet? */ 1361 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 1362 else /* no, so only link it */ 1363 *txq->link = bf->daddr; 1364 1365 txq->link = &ds->ds_link; 1366 ath5k_hw_start_tx_dma(ah, txq->qnum); 1367 mmiowb(); 1368 spin_unlock_bh(&txq->lock); 1369 1370 return 0; 1371 err_unmap: 1372 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 1373 return ret; 1374 } 1375 1376 /*******************\ 1377 * Descriptors setup * 1378 \*******************/ 1379 1380 static int 1381 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev) 1382 { 1383 struct ath5k_desc *ds; 1384 struct ath5k_buf *bf; 1385 dma_addr_t da; 1386 unsigned int i; 1387 int ret; 1388 1389 /* allocate descriptors */ 1390 sc->desc_len = sizeof(struct ath5k_desc) * 1391 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 1392 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); 1393 if (sc->desc == NULL) { 1394 ATH5K_ERR(sc, "can't allocate descriptors\n"); 1395 ret = -ENOMEM; 1396 goto err; 1397 } 1398 ds = sc->desc; 1399 da = sc->desc_daddr; 1400 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 1401 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 1402 1403 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 1404 sizeof(struct ath5k_buf), GFP_KERNEL); 1405 if (bf == NULL) { 1406 ATH5K_ERR(sc, "can't allocate bufptr\n"); 1407 ret = -ENOMEM; 1408 goto err_free; 1409 } 1410 sc->bufptr = bf; 1411 1412 INIT_LIST_HEAD(&sc->rxbuf); 1413 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 1414 bf->desc = ds; 1415 bf->daddr = da; 1416 list_add_tail(&bf->list, &sc->rxbuf); 1417 } 1418 1419 INIT_LIST_HEAD(&sc->txbuf); 1420 sc->txbuf_len = ATH_TXBUF; 1421 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 1422 da += sizeof(*ds)) { 1423 bf->desc = ds; 1424 bf->daddr = da; 1425 list_add_tail(&bf->list, &sc->txbuf); 1426 } 1427 1428 /* beacon buffer */ 1429 bf->desc = ds; 1430 bf->daddr = da; 1431 sc->bbuf = bf; 1432 1433 return 0; 1434 err_free: 1435 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1436 err: 1437 sc->desc = NULL; 1438 return ret; 1439 } 1440 1441 static void 1442 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) 1443 { 1444 struct ath5k_buf *bf; 1445 1446 ath5k_txbuf_free(sc, sc->bbuf); 1447 list_for_each_entry(bf, &sc->txbuf, list) 1448 ath5k_txbuf_free(sc, bf); 1449 list_for_each_entry(bf, &sc->rxbuf, list) 1450 ath5k_rxbuf_free(sc, bf); 1451 1452 /* Free memory associated with all descriptors */ 1453 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1454 1455 kfree(sc->bufptr); 1456 sc->bufptr = NULL; 1457 } 1458 1459 1460 1461 1462 1463 /**************\ 1464 * Queues setup * 1465 \**************/ 1466 1467 static struct ath5k_txq * 1468 ath5k_txq_setup(struct ath5k_softc *sc, 1469 int qtype, int subtype) 1470 { 1471 struct ath5k_hw *ah = sc->ah; 1472 struct ath5k_txq *txq; 1473 struct ath5k_txq_info qi = { 1474 .tqi_subtype = subtype, 1475 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1476 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1477 .tqi_cw_max = AR5K_TXQ_USEDEFAULT 1478 }; 1479 int qnum; 1480 1481 /* 1482 * Enable interrupts only for EOL and DESC conditions. 1483 * We mark tx descriptors to receive a DESC interrupt 1484 * when a tx queue gets deep; otherwise waiting for the 1485 * EOL to reap descriptors. Note that this is done to 1486 * reduce interrupt load and this only defers reaping 1487 * descriptors, never transmitting frames. Aside from 1488 * reducing interrupts this also permits more concurrency. 1489 * The only potential downside is if the tx queue backs 1490 * up in which case the top half of the kernel may backup 1491 * due to a lack of tx descriptors. 1492 */ 1493 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 1494 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1495 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1496 if (qnum < 0) { 1497 /* 1498 * NB: don't print a message, this happens 1499 * normally on parts with too few tx queues 1500 */ 1501 return ERR_PTR(qnum); 1502 } 1503 if (qnum >= ARRAY_SIZE(sc->txqs)) { 1504 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 1505 qnum, ARRAY_SIZE(sc->txqs)); 1506 ath5k_hw_release_tx_queue(ah, qnum); 1507 return ERR_PTR(-EINVAL); 1508 } 1509 txq = &sc->txqs[qnum]; 1510 if (!txq->setup) { 1511 txq->qnum = qnum; 1512 txq->link = NULL; 1513 INIT_LIST_HEAD(&txq->q); 1514 spin_lock_init(&txq->lock); 1515 txq->setup = true; 1516 } 1517 return &sc->txqs[qnum]; 1518 } 1519 1520 static int 1521 ath5k_beaconq_setup(struct ath5k_hw *ah) 1522 { 1523 struct ath5k_txq_info qi = { 1524 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1525 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1526 .tqi_cw_max = AR5K_TXQ_USEDEFAULT, 1527 /* NB: for dynamic turbo, don't enable any other interrupts */ 1528 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1529 }; 1530 1531 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1532 } 1533 1534 static int 1535 ath5k_beaconq_config(struct ath5k_softc *sc) 1536 { 1537 struct ath5k_hw *ah = sc->ah; 1538 struct ath5k_txq_info qi; 1539 int ret; 1540 1541 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 1542 if (ret) 1543 goto err; 1544 1545 if (sc->opmode == NL80211_IFTYPE_AP || 1546 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1547 /* 1548 * Always burst out beacon and CAB traffic 1549 * (aifs = cwmin = cwmax = 0) 1550 */ 1551 qi.tqi_aifs = 0; 1552 qi.tqi_cw_min = 0; 1553 qi.tqi_cw_max = 0; 1554 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 1555 /* 1556 * Adhoc mode; backoff between 0 and (2 * cw_min). 1557 */ 1558 qi.tqi_aifs = 0; 1559 qi.tqi_cw_min = 0; 1560 qi.tqi_cw_max = 2 * ah->ah_cw_min; 1561 } 1562 1563 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1564 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1565 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1566 1567 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1568 if (ret) { 1569 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1570 "hardware queue!\n", __func__); 1571 goto err; 1572 } 1573 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ 1574 if (ret) 1575 goto err; 1576 1577 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1578 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1579 if (ret) 1580 goto err; 1581 1582 qi.tqi_ready_time = (sc->bintval * 80) / 100; 1583 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1584 if (ret) 1585 goto err; 1586 1587 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1588 err: 1589 return ret; 1590 } 1591 1592 static void 1593 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1594 { 1595 struct ath5k_buf *bf, *bf0; 1596 1597 /* 1598 * NB: this assumes output has been stopped and 1599 * we do not need to block ath5k_tx_tasklet 1600 */ 1601 spin_lock_bh(&txq->lock); 1602 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1603 ath5k_debug_printtxbuf(sc, bf); 1604 1605 ath5k_txbuf_free(sc, bf); 1606 1607 spin_lock_bh(&sc->txbuflock); 1608 list_move_tail(&bf->list, &sc->txbuf); 1609 sc->txbuf_len++; 1610 spin_unlock_bh(&sc->txbuflock); 1611 } 1612 txq->link = NULL; 1613 spin_unlock_bh(&txq->lock); 1614 } 1615 1616 /* 1617 * Drain the transmit queues and reclaim resources. 1618 */ 1619 static void 1620 ath5k_txq_cleanup(struct ath5k_softc *sc) 1621 { 1622 struct ath5k_hw *ah = sc->ah; 1623 unsigned int i; 1624 1625 /* XXX return value */ 1626 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) { 1627 /* don't touch the hardware if marked invalid */ 1628 ath5k_hw_stop_tx_dma(ah, sc->bhalq); 1629 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", 1630 ath5k_hw_get_txdp(ah, sc->bhalq)); 1631 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1632 if (sc->txqs[i].setup) { 1633 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); 1634 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " 1635 "link %p\n", 1636 sc->txqs[i].qnum, 1637 ath5k_hw_get_txdp(ah, 1638 sc->txqs[i].qnum), 1639 sc->txqs[i].link); 1640 } 1641 } 1642 1643 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1644 if (sc->txqs[i].setup) 1645 ath5k_txq_drainq(sc, &sc->txqs[i]); 1646 } 1647 1648 static void 1649 ath5k_txq_release(struct ath5k_softc *sc) 1650 { 1651 struct ath5k_txq *txq = sc->txqs; 1652 unsigned int i; 1653 1654 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1655 if (txq->setup) { 1656 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1657 txq->setup = false; 1658 } 1659 } 1660 1661 1662 1663 1664 /*************\ 1665 * RX Handling * 1666 \*************/ 1667 1668 /* 1669 * Enable the receive h/w following a reset. 1670 */ 1671 static int 1672 ath5k_rx_start(struct ath5k_softc *sc) 1673 { 1674 struct ath5k_hw *ah = sc->ah; 1675 struct ath_common *common = ath5k_hw_common(ah); 1676 struct ath5k_buf *bf; 1677 int ret; 1678 1679 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz); 1680 1681 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1682 common->cachelsz, common->rx_bufsize); 1683 1684 spin_lock_bh(&sc->rxbuflock); 1685 sc->rxlink = NULL; 1686 list_for_each_entry(bf, &sc->rxbuf, list) { 1687 ret = ath5k_rxbuf_setup(sc, bf); 1688 if (ret != 0) { 1689 spin_unlock_bh(&sc->rxbuflock); 1690 goto err; 1691 } 1692 } 1693 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1694 ath5k_hw_set_rxdp(ah, bf->daddr); 1695 spin_unlock_bh(&sc->rxbuflock); 1696 1697 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1698 ath5k_mode_setup(sc); /* set filters, etc. */ 1699 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1700 1701 return 0; 1702 err: 1703 return ret; 1704 } 1705 1706 /* 1707 * Disable the receive h/w in preparation for a reset. 1708 */ 1709 static void 1710 ath5k_rx_stop(struct ath5k_softc *sc) 1711 { 1712 struct ath5k_hw *ah = sc->ah; 1713 1714 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1715 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1716 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ 1717 1718 ath5k_debug_printrxbuffs(sc, ah); 1719 1720 sc->rxlink = NULL; /* just in case */ 1721 } 1722 1723 static unsigned int 1724 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, 1725 struct sk_buff *skb, struct ath5k_rx_status *rs) 1726 { 1727 struct ath5k_hw *ah = sc->ah; 1728 struct ath_common *common = ath5k_hw_common(ah); 1729 struct ieee80211_hdr *hdr = (void *)skb->data; 1730 unsigned int keyix, hlen; 1731 1732 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1733 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1734 return RX_FLAG_DECRYPTED; 1735 1736 /* Apparently when a default key is used to decrypt the packet 1737 the hw does not set the index used to decrypt. In such cases 1738 get the index from the packet. */ 1739 hlen = ieee80211_hdrlen(hdr->frame_control); 1740 if (ieee80211_has_protected(hdr->frame_control) && 1741 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1742 skb->len >= hlen + 4) { 1743 keyix = skb->data[hlen + 3] >> 6; 1744 1745 if (test_bit(keyix, common->keymap)) 1746 return RX_FLAG_DECRYPTED; 1747 } 1748 1749 return 0; 1750 } 1751 1752 1753 static void 1754 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1755 struct ieee80211_rx_status *rxs) 1756 { 1757 struct ath_common *common = ath5k_hw_common(sc->ah); 1758 u64 tsf, bc_tstamp; 1759 u32 hw_tu; 1760 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1761 1762 if (ieee80211_is_beacon(mgmt->frame_control) && 1763 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1764 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1765 /* 1766 * Received an IBSS beacon with the same BSSID. Hardware *must* 1767 * have updated the local TSF. We have to work around various 1768 * hardware bugs, though... 1769 */ 1770 tsf = ath5k_hw_get_tsf64(sc->ah); 1771 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1772 hw_tu = TSF_TO_TU(tsf); 1773 1774 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1775 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1776 (unsigned long long)bc_tstamp, 1777 (unsigned long long)rxs->mactime, 1778 (unsigned long long)(rxs->mactime - bc_tstamp), 1779 (unsigned long long)tsf); 1780 1781 /* 1782 * Sometimes the HW will give us a wrong tstamp in the rx 1783 * status, causing the timestamp extension to go wrong. 1784 * (This seems to happen especially with beacon frames bigger 1785 * than 78 byte (incl. FCS)) 1786 * But we know that the receive timestamp must be later than the 1787 * timestamp of the beacon since HW must have synced to that. 1788 * 1789 * NOTE: here we assume mactime to be after the frame was 1790 * received, not like mac80211 which defines it at the start. 1791 */ 1792 if (bc_tstamp > rxs->mactime) { 1793 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1794 "fixing mactime from %llx to %llx\n", 1795 (unsigned long long)rxs->mactime, 1796 (unsigned long long)tsf); 1797 rxs->mactime = tsf; 1798 } 1799 1800 /* 1801 * Local TSF might have moved higher than our beacon timers, 1802 * in that case we have to update them to continue sending 1803 * beacons. This also takes care of synchronizing beacon sending 1804 * times with other stations. 1805 */ 1806 if (hw_tu >= sc->nexttbtt) 1807 ath5k_beacon_update_timers(sc, bc_tstamp); 1808 } 1809 } 1810 1811 static void 1812 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) 1813 { 1814 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1815 struct ath5k_hw *ah = sc->ah; 1816 struct ath_common *common = ath5k_hw_common(ah); 1817 1818 /* only beacons from our BSSID */ 1819 if (!ieee80211_is_beacon(mgmt->frame_control) || 1820 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) 1821 return; 1822 1823 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg, 1824 rssi); 1825 1826 /* in IBSS mode we should keep RSSI statistics per neighbour */ 1827 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ 1828 } 1829 1830 /* 1831 * Compute padding position. skb must contains an IEEE 802.11 frame 1832 */ 1833 static int ath5k_common_padpos(struct sk_buff *skb) 1834 { 1835 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 1836 __le16 frame_control = hdr->frame_control; 1837 int padpos = 24; 1838 1839 if (ieee80211_has_a4(frame_control)) { 1840 padpos += ETH_ALEN; 1841 } 1842 if (ieee80211_is_data_qos(frame_control)) { 1843 padpos += IEEE80211_QOS_CTL_LEN; 1844 } 1845 1846 return padpos; 1847 } 1848 1849 /* 1850 * This function expects a 802.11 frame and returns the number of 1851 * bytes added, or -1 if we don't have enought header room. 1852 */ 1853 1854 static int ath5k_add_padding(struct sk_buff *skb) 1855 { 1856 int padpos = ath5k_common_padpos(skb); 1857 int padsize = padpos & 3; 1858 1859 if (padsize && skb->len>padpos) { 1860 1861 if (skb_headroom(skb) < padsize) 1862 return -1; 1863 1864 skb_push(skb, padsize); 1865 memmove(skb->data, skb->data+padsize, padpos); 1866 return padsize; 1867 } 1868 1869 return 0; 1870 } 1871 1872 /* 1873 * This function expects a 802.11 frame and returns the number of 1874 * bytes removed 1875 */ 1876 1877 static int ath5k_remove_padding(struct sk_buff *skb) 1878 { 1879 int padpos = ath5k_common_padpos(skb); 1880 int padsize = padpos & 3; 1881 1882 if (padsize && skb->len>=padpos+padsize) { 1883 memmove(skb->data + padsize, skb->data, padpos); 1884 skb_pull(skb, padsize); 1885 return padsize; 1886 } 1887 1888 return 0; 1889 } 1890 1891 static void 1892 ath5k_tasklet_rx(unsigned long data) 1893 { 1894 struct ieee80211_rx_status *rxs; 1895 struct ath5k_rx_status rs = {}; 1896 struct sk_buff *skb, *next_skb; 1897 dma_addr_t next_skb_addr; 1898 struct ath5k_softc *sc = (void *)data; 1899 struct ath5k_hw *ah = sc->ah; 1900 struct ath_common *common = ath5k_hw_common(ah); 1901 struct ath5k_buf *bf; 1902 struct ath5k_desc *ds; 1903 int ret; 1904 int rx_flag; 1905 1906 spin_lock(&sc->rxbuflock); 1907 if (list_empty(&sc->rxbuf)) { 1908 ATH5K_WARN(sc, "empty rx buf pool\n"); 1909 goto unlock; 1910 } 1911 do { 1912 rx_flag = 0; 1913 1914 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1915 BUG_ON(bf->skb == NULL); 1916 skb = bf->skb; 1917 ds = bf->desc; 1918 1919 /* bail if HW is still using self-linked descriptor */ 1920 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1921 break; 1922 1923 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1924 if (unlikely(ret == -EINPROGRESS)) 1925 break; 1926 else if (unlikely(ret)) { 1927 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1928 sc->stats.rxerr_proc++; 1929 spin_unlock(&sc->rxbuflock); 1930 return; 1931 } 1932 1933 sc->stats.rx_all_count++; 1934 1935 if (unlikely(rs.rs_status)) { 1936 if (rs.rs_status & AR5K_RXERR_CRC) 1937 sc->stats.rxerr_crc++; 1938 if (rs.rs_status & AR5K_RXERR_FIFO) 1939 sc->stats.rxerr_fifo++; 1940 if (rs.rs_status & AR5K_RXERR_PHY) { 1941 sc->stats.rxerr_phy++; 1942 if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32) 1943 sc->stats.rxerr_phy_code[rs.rs_phyerr]++; 1944 goto next; 1945 } 1946 if (rs.rs_status & AR5K_RXERR_DECRYPT) { 1947 /* 1948 * Decrypt error. If the error occurred 1949 * because there was no hardware key, then 1950 * let the frame through so the upper layers 1951 * can process it. This is necessary for 5210 1952 * parts which have no way to setup a ``clear'' 1953 * key cache entry. 1954 * 1955 * XXX do key cache faulting 1956 */ 1957 sc->stats.rxerr_decrypt++; 1958 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && 1959 !(rs.rs_status & AR5K_RXERR_CRC)) 1960 goto accept; 1961 } 1962 if (rs.rs_status & AR5K_RXERR_MIC) { 1963 rx_flag |= RX_FLAG_MMIC_ERROR; 1964 sc->stats.rxerr_mic++; 1965 goto accept; 1966 } 1967 1968 /* let crypto-error packets fall through in MNTR */ 1969 if ((rs.rs_status & 1970 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || 1971 sc->opmode != NL80211_IFTYPE_MONITOR) 1972 goto next; 1973 } 1974 1975 if (unlikely(rs.rs_more)) { 1976 sc->stats.rxerr_jumbo++; 1977 goto next; 1978 1979 } 1980 accept: 1981 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1982 1983 /* 1984 * If we can't replace bf->skb with a new skb under memory 1985 * pressure, just skip this packet 1986 */ 1987 if (!next_skb) 1988 goto next; 1989 1990 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize, 1991 PCI_DMA_FROMDEVICE); 1992 skb_put(skb, rs.rs_datalen); 1993 1994 /* The MAC header is padded to have 32-bit boundary if the 1995 * packet payload is non-zero. The general calculation for 1996 * padsize would take into account odd header lengths: 1997 * padsize = (4 - hdrlen % 4) % 4; However, since only 1998 * even-length headers are used, padding can only be 0 or 2 1999 * bytes and we can optimize this a bit. In addition, we must 2000 * not try to remove padding from short control frames that do 2001 * not have payload. */ 2002 ath5k_remove_padding(skb); 2003 2004 rxs = IEEE80211_SKB_RXCB(skb); 2005 2006 /* 2007 * always extend the mac timestamp, since this information is 2008 * also needed for proper IBSS merging. 2009 * 2010 * XXX: it might be too late to do it here, since rs_tstamp is 2011 * 15bit only. that means TSF extension has to be done within 2012 * 32768usec (about 32ms). it might be necessary to move this to 2013 * the interrupt handler, like it is done in madwifi. 2014 * 2015 * Unfortunately we don't know when the hardware takes the rx 2016 * timestamp (beginning of phy frame, data frame, end of rx?). 2017 * The only thing we know is that it is hardware specific... 2018 * On AR5213 it seems the rx timestamp is at the end of the 2019 * frame, but i'm not sure. 2020 * 2021 * NOTE: mac80211 defines mactime at the beginning of the first 2022 * data symbol. Since we don't have any time references it's 2023 * impossible to comply to that. This affects IBSS merge only 2024 * right now, so it's not too bad... 2025 */ 2026 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp); 2027 rxs->flag = rx_flag | RX_FLAG_TSFT; 2028 2029 rxs->freq = sc->curchan->center_freq; 2030 rxs->band = sc->curband->band; 2031 2032 rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi; 2033 2034 rxs->antenna = rs.rs_antenna; 2035 2036 if (rs.rs_antenna > 0 && rs.rs_antenna < 5) 2037 sc->stats.antenna_rx[rs.rs_antenna]++; 2038 else 2039 sc->stats.antenna_rx[0]++; /* invalid */ 2040 2041 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); 2042 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs); 2043 2044 if (rxs->rate_idx >= 0 && rs.rs_rate == 2045 sc->curband->bitrates[rxs->rate_idx].hw_value_short) 2046 rxs->flag |= RX_FLAG_SHORTPRE; 2047 2048 ath5k_debug_dump_skb(sc, skb, "RX ", 0); 2049 2050 ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi); 2051 2052 /* check beacons in IBSS mode */ 2053 if (sc->opmode == NL80211_IFTYPE_ADHOC) 2054 ath5k_check_ibss_tsf(sc, skb, rxs); 2055 2056 ieee80211_rx(sc->hw, skb); 2057 2058 bf->skb = next_skb; 2059 bf->skbaddr = next_skb_addr; 2060 next: 2061 list_move_tail(&bf->list, &sc->rxbuf); 2062 } while (ath5k_rxbuf_setup(sc, bf) == 0); 2063 unlock: 2064 spin_unlock(&sc->rxbuflock); 2065 } 2066 2067 2068 2069 2070 /*************\ 2071 * TX Handling * 2072 \*************/ 2073 2074 static void 2075 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 2076 { 2077 struct ath5k_tx_status ts = {}; 2078 struct ath5k_buf *bf, *bf0; 2079 struct ath5k_desc *ds; 2080 struct sk_buff *skb; 2081 struct ieee80211_tx_info *info; 2082 int i, ret; 2083 2084 spin_lock(&txq->lock); 2085 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 2086 ds = bf->desc; 2087 2088 /* 2089 * It's possible that the hardware can say the buffer is 2090 * completed when it hasn't yet loaded the ds_link from 2091 * host memory and moved on. If there are more TX 2092 * descriptors in the queue, wait for TXDP to change 2093 * before processing this one. 2094 */ 2095 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr && 2096 !list_is_last(&bf->list, &txq->q)) 2097 break; 2098 2099 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 2100 if (unlikely(ret == -EINPROGRESS)) 2101 break; 2102 else if (unlikely(ret)) { 2103 ATH5K_ERR(sc, "error %d while processing queue %u\n", 2104 ret, txq->qnum); 2105 break; 2106 } 2107 2108 sc->stats.tx_all_count++; 2109 skb = bf->skb; 2110 info = IEEE80211_SKB_CB(skb); 2111 bf->skb = NULL; 2112 2113 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, 2114 PCI_DMA_TODEVICE); 2115 2116 ieee80211_tx_info_clear_status(info); 2117 for (i = 0; i < 4; i++) { 2118 struct ieee80211_tx_rate *r = 2119 &info->status.rates[i]; 2120 2121 if (ts.ts_rate[i]) { 2122 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]); 2123 r->count = ts.ts_retry[i]; 2124 } else { 2125 r->idx = -1; 2126 r->count = 0; 2127 } 2128 } 2129 2130 /* count the successful attempt as well */ 2131 info->status.rates[ts.ts_final_idx].count++; 2132 2133 if (unlikely(ts.ts_status)) { 2134 sc->stats.ack_fail++; 2135 if (ts.ts_status & AR5K_TXERR_FILT) { 2136 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2137 sc->stats.txerr_filt++; 2138 } 2139 if (ts.ts_status & AR5K_TXERR_XRETRY) 2140 sc->stats.txerr_retry++; 2141 if (ts.ts_status & AR5K_TXERR_FIFO) 2142 sc->stats.txerr_fifo++; 2143 } else { 2144 info->flags |= IEEE80211_TX_STAT_ACK; 2145 info->status.ack_signal = ts.ts_rssi; 2146 } 2147 2148 /* 2149 * Remove MAC header padding before giving the frame 2150 * back to mac80211. 2151 */ 2152 ath5k_remove_padding(skb); 2153 2154 if (ts.ts_antenna > 0 && ts.ts_antenna < 5) 2155 sc->stats.antenna_tx[ts.ts_antenna]++; 2156 else 2157 sc->stats.antenna_tx[0]++; /* invalid */ 2158 2159 ieee80211_tx_status(sc->hw, skb); 2160 2161 spin_lock(&sc->txbuflock); 2162 list_move_tail(&bf->list, &sc->txbuf); 2163 sc->txbuf_len++; 2164 spin_unlock(&sc->txbuflock); 2165 } 2166 if (likely(list_empty(&txq->q))) 2167 txq->link = NULL; 2168 spin_unlock(&txq->lock); 2169 if (sc->txbuf_len > ATH_TXBUF / 5) 2170 ieee80211_wake_queues(sc->hw); 2171 } 2172 2173 static void 2174 ath5k_tasklet_tx(unsigned long data) 2175 { 2176 int i; 2177 struct ath5k_softc *sc = (void *)data; 2178 2179 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 2180 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 2181 ath5k_tx_processq(sc, &sc->txqs[i]); 2182 } 2183 2184 2185 /*****************\ 2186 * Beacon handling * 2187 \*****************/ 2188 2189 /* 2190 * Setup the beacon frame for transmit. 2191 */ 2192 static int 2193 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 2194 { 2195 struct sk_buff *skb = bf->skb; 2196 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2197 struct ath5k_hw *ah = sc->ah; 2198 struct ath5k_desc *ds; 2199 int ret = 0; 2200 u8 antenna; 2201 u32 flags; 2202 const int padsize = 0; 2203 2204 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 2205 PCI_DMA_TODEVICE); 2206 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 2207 "skbaddr %llx\n", skb, skb->data, skb->len, 2208 (unsigned long long)bf->skbaddr); 2209 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) { 2210 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 2211 return -EIO; 2212 } 2213 2214 ds = bf->desc; 2215 antenna = ah->ah_tx_ant; 2216 2217 flags = AR5K_TXDESC_NOACK; 2218 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 2219 ds->ds_link = bf->daddr; /* self-linked */ 2220 flags |= AR5K_TXDESC_VEOL; 2221 } else 2222 ds->ds_link = 0; 2223 2224 /* 2225 * If we use multiple antennas on AP and use 2226 * the Sectored AP scenario, switch antenna every 2227 * 4 beacons to make sure everybody hears our AP. 2228 * When a client tries to associate, hw will keep 2229 * track of the tx antenna to be used for this client 2230 * automaticaly, based on ACKed packets. 2231 * 2232 * Note: AP still listens and transmits RTS on the 2233 * default antenna which is supposed to be an omni. 2234 * 2235 * Note2: On sectored scenarios it's possible to have 2236 * multiple antennas (1omni -the default- and 14 sectors) 2237 * so if we choose to actually support this mode we need 2238 * to allow user to set how many antennas we have and tweak 2239 * the code below to send beacons on all of them. 2240 */ 2241 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 2242 antenna = sc->bsent & 4 ? 2 : 1; 2243 2244 2245 /* FIXME: If we are in g mode and rate is a CCK rate 2246 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 2247 * from tx power (value is in dB units already) */ 2248 ds->ds_data = bf->skbaddr; 2249 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 2250 ieee80211_get_hdrlen_from_skb(skb), padsize, 2251 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 2252 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 2253 1, AR5K_TXKEYIX_INVALID, 2254 antenna, flags, 0, 0); 2255 if (ret) 2256 goto err_unmap; 2257 2258 return 0; 2259 err_unmap: 2260 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 2261 return ret; 2262 } 2263 2264 /* 2265 * Transmit a beacon frame at SWBA. Dynamic updates to the 2266 * frame contents are done as needed and the slot time is 2267 * also adjusted based on current state. 2268 * 2269 * This is called from software irq context (beacontq or restq 2270 * tasklets) or user context from ath5k_beacon_config. 2271 */ 2272 static void 2273 ath5k_beacon_send(struct ath5k_softc *sc) 2274 { 2275 struct ath5k_buf *bf = sc->bbuf; 2276 struct ath5k_hw *ah = sc->ah; 2277 struct sk_buff *skb; 2278 2279 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 2280 2281 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 2282 sc->opmode == NL80211_IFTYPE_MONITOR)) { 2283 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 2284 return; 2285 } 2286 /* 2287 * Check if the previous beacon has gone out. If 2288 * not don't don't try to post another, skip this 2289 * period and wait for the next. Missed beacons 2290 * indicate a problem and should not occur. If we 2291 * miss too many consecutive beacons reset the device. 2292 */ 2293 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 2294 sc->bmisscount++; 2295 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2296 "missed %u consecutive beacons\n", sc->bmisscount); 2297 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 2298 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2299 "stuck beacon time (%u missed)\n", 2300 sc->bmisscount); 2301 tasklet_schedule(&sc->restq); 2302 } 2303 return; 2304 } 2305 if (unlikely(sc->bmisscount != 0)) { 2306 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2307 "resume beacon xmit after %u misses\n", 2308 sc->bmisscount); 2309 sc->bmisscount = 0; 2310 } 2311 2312 /* 2313 * Stop any current dma and put the new frame on the queue. 2314 * This should never fail since we check above that no frames 2315 * are still pending on the queue. 2316 */ 2317 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { 2318 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 2319 /* NB: hw still stops DMA, so proceed */ 2320 } 2321 2322 /* refresh the beacon for AP mode */ 2323 if (sc->opmode == NL80211_IFTYPE_AP) 2324 ath5k_beacon_update(sc->hw, sc->vif); 2325 2326 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 2327 ath5k_hw_start_tx_dma(ah, sc->bhalq); 2328 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 2329 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 2330 2331 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2332 while (skb) { 2333 ath5k_tx_queue(sc->hw, skb, sc->cabq); 2334 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2335 } 2336 2337 sc->bsent++; 2338 } 2339 2340 2341 /** 2342 * ath5k_beacon_update_timers - update beacon timers 2343 * 2344 * @sc: struct ath5k_softc pointer we are operating on 2345 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2346 * beacon timer update based on the current HW TSF. 2347 * 2348 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2349 * of a received beacon or the current local hardware TSF and write it to the 2350 * beacon timer registers. 2351 * 2352 * This is called in a variety of situations, e.g. when a beacon is received, 2353 * when a TSF update has been detected, but also when an new IBSS is created or 2354 * when we otherwise know we have to update the timers, but we keep it in this 2355 * function to have it all together in one place. 2356 */ 2357 static void 2358 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 2359 { 2360 struct ath5k_hw *ah = sc->ah; 2361 u32 nexttbtt, intval, hw_tu, bc_tu; 2362 u64 hw_tsf; 2363 2364 intval = sc->bintval & AR5K_BEACON_PERIOD; 2365 if (WARN_ON(!intval)) 2366 return; 2367 2368 /* beacon TSF converted to TU */ 2369 bc_tu = TSF_TO_TU(bc_tsf); 2370 2371 /* current TSF converted to TU */ 2372 hw_tsf = ath5k_hw_get_tsf64(ah); 2373 hw_tu = TSF_TO_TU(hw_tsf); 2374 2375 #define FUDGE 3 2376 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */ 2377 if (bc_tsf == -1) { 2378 /* 2379 * no beacons received, called internally. 2380 * just need to refresh timers based on HW TSF. 2381 */ 2382 nexttbtt = roundup(hw_tu + FUDGE, intval); 2383 } else if (bc_tsf == 0) { 2384 /* 2385 * no beacon received, probably called by ath5k_reset_tsf(). 2386 * reset TSF to start with 0. 2387 */ 2388 nexttbtt = intval; 2389 intval |= AR5K_BEACON_RESET_TSF; 2390 } else if (bc_tsf > hw_tsf) { 2391 /* 2392 * beacon received, SW merge happend but HW TSF not yet updated. 2393 * not possible to reconfigure timers yet, but next time we 2394 * receive a beacon with the same BSSID, the hardware will 2395 * automatically update the TSF and then we need to reconfigure 2396 * the timers. 2397 */ 2398 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2399 "need to wait for HW TSF sync\n"); 2400 return; 2401 } else { 2402 /* 2403 * most important case for beacon synchronization between STA. 2404 * 2405 * beacon received and HW TSF has been already updated by HW. 2406 * update next TBTT based on the TSF of the beacon, but make 2407 * sure it is ahead of our local TSF timer. 2408 */ 2409 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2410 } 2411 #undef FUDGE 2412 2413 sc->nexttbtt = nexttbtt; 2414 2415 intval |= AR5K_BEACON_ENA; 2416 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2417 2418 /* 2419 * debugging output last in order to preserve the time critical aspect 2420 * of this function 2421 */ 2422 if (bc_tsf == -1) 2423 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2424 "reconfigured timers based on HW TSF\n"); 2425 else if (bc_tsf == 0) 2426 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2427 "reset HW TSF and timers\n"); 2428 else 2429 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2430 "updated timers based on beacon TSF\n"); 2431 2432 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2433 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2434 (unsigned long long) bc_tsf, 2435 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2436 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2437 intval & AR5K_BEACON_PERIOD, 2438 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2439 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2440 } 2441 2442 2443 /** 2444 * ath5k_beacon_config - Configure the beacon queues and interrupts 2445 * 2446 * @sc: struct ath5k_softc pointer we are operating on 2447 * 2448 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2449 * interrupts to detect TSF updates only. 2450 */ 2451 static void 2452 ath5k_beacon_config(struct ath5k_softc *sc) 2453 { 2454 struct ath5k_hw *ah = sc->ah; 2455 unsigned long flags; 2456 2457 spin_lock_irqsave(&sc->block, flags); 2458 sc->bmisscount = 0; 2459 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2460 2461 if (sc->enable_beacon) { 2462 /* 2463 * In IBSS mode we use a self-linked tx descriptor and let the 2464 * hardware send the beacons automatically. We have to load it 2465 * only once here. 2466 * We use the SWBA interrupt only to keep track of the beacon 2467 * timers in order to detect automatic TSF updates. 2468 */ 2469 ath5k_beaconq_config(sc); 2470 2471 sc->imask |= AR5K_INT_SWBA; 2472 2473 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2474 if (ath5k_hw_hasveol(ah)) 2475 ath5k_beacon_send(sc); 2476 } else 2477 ath5k_beacon_update_timers(sc, -1); 2478 } else { 2479 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq); 2480 } 2481 2482 ath5k_hw_set_imr(ah, sc->imask); 2483 mmiowb(); 2484 spin_unlock_irqrestore(&sc->block, flags); 2485 } 2486 2487 static void ath5k_tasklet_beacon(unsigned long data) 2488 { 2489 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2490 2491 /* 2492 * Software beacon alert--time to send a beacon. 2493 * 2494 * In IBSS mode we use this interrupt just to 2495 * keep track of the next TBTT (target beacon 2496 * transmission time) in order to detect wether 2497 * automatic TSF updates happened. 2498 */ 2499 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2500 /* XXX: only if VEOL suppported */ 2501 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2502 sc->nexttbtt += sc->bintval; 2503 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2504 "SWBA nexttbtt: %x hw_tu: %x " 2505 "TSF: %llx\n", 2506 sc->nexttbtt, 2507 TSF_TO_TU(tsf), 2508 (unsigned long long) tsf); 2509 } else { 2510 spin_lock(&sc->block); 2511 ath5k_beacon_send(sc); 2512 spin_unlock(&sc->block); 2513 } 2514 } 2515 2516 2517 /********************\ 2518 * Interrupt handling * 2519 \********************/ 2520 2521 static int 2522 ath5k_init(struct ath5k_softc *sc) 2523 { 2524 struct ath5k_hw *ah = sc->ah; 2525 int ret, i; 2526 2527 mutex_lock(&sc->lock); 2528 2529 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2530 2531 /* 2532 * Stop anything previously setup. This is safe 2533 * no matter this is the first time through or not. 2534 */ 2535 ath5k_stop_locked(sc); 2536 2537 /* 2538 * The basic interface to setting the hardware in a good 2539 * state is ``reset''. On return the hardware is known to 2540 * be powered up and with interrupts disabled. This must 2541 * be followed by initialization of the appropriate bits 2542 * and then setup of the interrupt mask. 2543 */ 2544 sc->curchan = sc->hw->conf.channel; 2545 sc->curband = &sc->sbands[sc->curchan->band]; 2546 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2547 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2548 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; 2549 2550 ret = ath5k_reset(sc, NULL); 2551 if (ret) 2552 goto done; 2553 2554 ath5k_rfkill_hw_start(ah); 2555 2556 /* 2557 * Reset the key cache since some parts do not reset the 2558 * contents on initial power up or resume from suspend. 2559 */ 2560 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) 2561 ath5k_hw_reset_key(ah, i); 2562 2563 ath5k_hw_set_ack_bitrate_high(ah, true); 2564 ret = 0; 2565 done: 2566 mmiowb(); 2567 mutex_unlock(&sc->lock); 2568 return ret; 2569 } 2570 2571 static int 2572 ath5k_stop_locked(struct ath5k_softc *sc) 2573 { 2574 struct ath5k_hw *ah = sc->ah; 2575 2576 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2577 test_bit(ATH_STAT_INVALID, sc->status)); 2578 2579 /* 2580 * Shutdown the hardware and driver: 2581 * stop output from above 2582 * disable interrupts 2583 * turn off timers 2584 * turn off the radio 2585 * clear transmit machinery 2586 * clear receive machinery 2587 * drain and release tx queues 2588 * reclaim beacon resources 2589 * power down hardware 2590 * 2591 * Note that some of this work is not possible if the 2592 * hardware is gone (invalid). 2593 */ 2594 ieee80211_stop_queues(sc->hw); 2595 2596 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2597 ath5k_led_off(sc); 2598 ath5k_hw_set_imr(ah, 0); 2599 synchronize_irq(sc->pdev->irq); 2600 } 2601 ath5k_txq_cleanup(sc); 2602 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2603 ath5k_rx_stop(sc); 2604 ath5k_hw_phy_disable(ah); 2605 } else 2606 sc->rxlink = NULL; 2607 2608 return 0; 2609 } 2610 2611 /* 2612 * Stop the device, grabbing the top-level lock to protect 2613 * against concurrent entry through ath5k_init (which can happen 2614 * if another thread does a system call and the thread doing the 2615 * stop is preempted). 2616 */ 2617 static int 2618 ath5k_stop_hw(struct ath5k_softc *sc) 2619 { 2620 int ret; 2621 2622 mutex_lock(&sc->lock); 2623 ret = ath5k_stop_locked(sc); 2624 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2625 /* 2626 * Don't set the card in full sleep mode! 2627 * 2628 * a) When the device is in this state it must be carefully 2629 * woken up or references to registers in the PCI clock 2630 * domain may freeze the bus (and system). This varies 2631 * by chip and is mostly an issue with newer parts 2632 * (madwifi sources mentioned srev >= 0x78) that go to 2633 * sleep more quickly. 2634 * 2635 * b) On older chips full sleep results a weird behaviour 2636 * during wakeup. I tested various cards with srev < 0x78 2637 * and they don't wake up after module reload, a second 2638 * module reload is needed to bring the card up again. 2639 * 2640 * Until we figure out what's going on don't enable 2641 * full chip reset on any chip (this is what Legacy HAL 2642 * and Sam's HAL do anyway). Instead Perform a full reset 2643 * on the device (same as initial state after attach) and 2644 * leave it idle (keep MAC/BB on warm reset) */ 2645 ret = ath5k_hw_on_hold(sc->ah); 2646 2647 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2648 "putting device to sleep\n"); 2649 } 2650 ath5k_txbuf_free(sc, sc->bbuf); 2651 2652 mmiowb(); 2653 mutex_unlock(&sc->lock); 2654 2655 tasklet_kill(&sc->rxtq); 2656 tasklet_kill(&sc->txtq); 2657 tasklet_kill(&sc->restq); 2658 tasklet_kill(&sc->calib); 2659 tasklet_kill(&sc->beacontq); 2660 tasklet_kill(&sc->ani_tasklet); 2661 2662 ath5k_rfkill_hw_stop(sc->ah); 2663 2664 return ret; 2665 } 2666 2667 static void 2668 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2669 { 2670 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2671 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) { 2672 /* run ANI only when full calibration is not active */ 2673 ah->ah_cal_next_ani = jiffies + 2674 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2675 tasklet_schedule(&ah->ah_sc->ani_tasklet); 2676 2677 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2678 ah->ah_cal_next_full = jiffies + 2679 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2680 tasklet_schedule(&ah->ah_sc->calib); 2681 } 2682 /* we could use SWI to generate enough interrupts to meet our 2683 * calibration interval requirements, if necessary: 2684 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2685 } 2686 2687 static irqreturn_t 2688 ath5k_intr(int irq, void *dev_id) 2689 { 2690 struct ath5k_softc *sc = dev_id; 2691 struct ath5k_hw *ah = sc->ah; 2692 enum ath5k_int status; 2693 unsigned int counter = 1000; 2694 2695 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2696 !ath5k_hw_is_intr_pending(ah))) 2697 return IRQ_NONE; 2698 2699 do { 2700 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2701 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2702 status, sc->imask); 2703 if (unlikely(status & AR5K_INT_FATAL)) { 2704 /* 2705 * Fatal errors are unrecoverable. 2706 * Typically these are caused by DMA errors. 2707 */ 2708 tasklet_schedule(&sc->restq); 2709 } else if (unlikely(status & AR5K_INT_RXORN)) { 2710 /* 2711 * Receive buffers are full. Either the bus is busy or 2712 * the CPU is not fast enough to process all received 2713 * frames. 2714 * Older chipsets need a reset to come out of this 2715 * condition, but we treat it as RX for newer chips. 2716 * We don't know exactly which versions need a reset - 2717 * this guess is copied from the HAL. 2718 */ 2719 sc->stats.rxorn_intr++; 2720 if (ah->ah_mac_srev < AR5K_SREV_AR5212) 2721 tasklet_schedule(&sc->restq); 2722 else 2723 tasklet_schedule(&sc->rxtq); 2724 } else { 2725 if (status & AR5K_INT_SWBA) { 2726 tasklet_hi_schedule(&sc->beacontq); 2727 } 2728 if (status & AR5K_INT_RXEOL) { 2729 /* 2730 * NB: the hardware should re-read the link when 2731 * RXE bit is written, but it doesn't work at 2732 * least on older hardware revs. 2733 */ 2734 sc->rxlink = NULL; 2735 } 2736 if (status & AR5K_INT_TXURN) { 2737 /* bump tx trigger level */ 2738 ath5k_hw_update_tx_triglevel(ah, true); 2739 } 2740 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2741 tasklet_schedule(&sc->rxtq); 2742 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2743 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2744 tasklet_schedule(&sc->txtq); 2745 if (status & AR5K_INT_BMISS) { 2746 /* TODO */ 2747 } 2748 if (status & AR5K_INT_MIB) { 2749 sc->stats.mib_intr++; 2750 ath5k_hw_update_mib_counters(ah); 2751 ath5k_ani_mib_intr(ah); 2752 } 2753 if (status & AR5K_INT_GPIO) 2754 tasklet_schedule(&sc->rf_kill.toggleq); 2755 2756 } 2757 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2758 2759 if (unlikely(!counter)) 2760 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2761 2762 ath5k_intr_calibration_poll(ah); 2763 2764 return IRQ_HANDLED; 2765 } 2766 2767 static void 2768 ath5k_tasklet_reset(unsigned long data) 2769 { 2770 struct ath5k_softc *sc = (void *)data; 2771 2772 ath5k_reset(sc, sc->curchan); 2773 } 2774 2775 /* 2776 * Periodically recalibrate the PHY to account 2777 * for temperature/environment changes. 2778 */ 2779 static void 2780 ath5k_tasklet_calibrate(unsigned long data) 2781 { 2782 struct ath5k_softc *sc = (void *)data; 2783 struct ath5k_hw *ah = sc->ah; 2784 2785 /* Only full calibration for now */ 2786 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2787 2788 /* Stop queues so that calibration 2789 * doesn't interfere with tx */ 2790 ieee80211_stop_queues(sc->hw); 2791 2792 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2793 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2794 sc->curchan->hw_value); 2795 2796 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2797 /* 2798 * Rfgain is out of bounds, reset the chip 2799 * to load new gain values. 2800 */ 2801 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2802 ath5k_reset(sc, sc->curchan); 2803 } 2804 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2805 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2806 ieee80211_frequency_to_channel( 2807 sc->curchan->center_freq)); 2808 2809 /* Wake queues */ 2810 ieee80211_wake_queues(sc->hw); 2811 2812 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2813 } 2814 2815 2816 static void 2817 ath5k_tasklet_ani(unsigned long data) 2818 { 2819 struct ath5k_softc *sc = (void *)data; 2820 struct ath5k_hw *ah = sc->ah; 2821 2822 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2823 ath5k_ani_calibration(ah); 2824 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2825 } 2826 2827 2828 /********************\ 2829 * Mac80211 functions * 2830 \********************/ 2831 2832 static int 2833 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2834 { 2835 struct ath5k_softc *sc = hw->priv; 2836 2837 return ath5k_tx_queue(hw, skb, sc->txq); 2838 } 2839 2840 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 2841 struct ath5k_txq *txq) 2842 { 2843 struct ath5k_softc *sc = hw->priv; 2844 struct ath5k_buf *bf; 2845 unsigned long flags; 2846 int padsize; 2847 2848 ath5k_debug_dump_skb(sc, skb, "TX ", 1); 2849 2850 if (sc->opmode == NL80211_IFTYPE_MONITOR) 2851 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n"); 2852 2853 /* 2854 * the hardware expects the header padded to 4 byte boundaries 2855 * if this is not the case we add the padding after the header 2856 */ 2857 padsize = ath5k_add_padding(skb); 2858 if (padsize < 0) { 2859 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" 2860 " headroom to pad"); 2861 goto drop_packet; 2862 } 2863 2864 spin_lock_irqsave(&sc->txbuflock, flags); 2865 if (list_empty(&sc->txbuf)) { 2866 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 2867 spin_unlock_irqrestore(&sc->txbuflock, flags); 2868 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 2869 goto drop_packet; 2870 } 2871 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 2872 list_del(&bf->list); 2873 sc->txbuf_len--; 2874 if (list_empty(&sc->txbuf)) 2875 ieee80211_stop_queues(hw); 2876 spin_unlock_irqrestore(&sc->txbuflock, flags); 2877 2878 bf->skb = skb; 2879 2880 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { 2881 bf->skb = NULL; 2882 spin_lock_irqsave(&sc->txbuflock, flags); 2883 list_add_tail(&bf->list, &sc->txbuf); 2884 sc->txbuf_len++; 2885 spin_unlock_irqrestore(&sc->txbuflock, flags); 2886 goto drop_packet; 2887 } 2888 return NETDEV_TX_OK; 2889 2890 drop_packet: 2891 dev_kfree_skb_any(skb); 2892 return NETDEV_TX_OK; 2893 } 2894 2895 /* 2896 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2897 * and change to the given channel. 2898 */ 2899 static int 2900 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan) 2901 { 2902 struct ath5k_hw *ah = sc->ah; 2903 int ret; 2904 2905 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2906 2907 if (chan) { 2908 ath5k_hw_set_imr(ah, 0); 2909 ath5k_txq_cleanup(sc); 2910 ath5k_rx_stop(sc); 2911 2912 sc->curchan = chan; 2913 sc->curband = &sc->sbands[chan->band]; 2914 } 2915 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL); 2916 if (ret) { 2917 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2918 goto err; 2919 } 2920 2921 ret = ath5k_rx_start(sc); 2922 if (ret) { 2923 ATH5K_ERR(sc, "can't start recv logic\n"); 2924 goto err; 2925 } 2926 2927 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode); 2928 2929 /* 2930 * Change channels and update the h/w rate map if we're switching; 2931 * e.g. 11a to 11b/g. 2932 * 2933 * We may be doing a reset in response to an ioctl that changes the 2934 * channel so update any state that might change as a result. 2935 * 2936 * XXX needed? 2937 */ 2938 /* ath5k_chan_change(sc, c); */ 2939 2940 ath5k_beacon_config(sc); 2941 /* intrs are enabled by ath5k_beacon_config */ 2942 2943 ieee80211_wake_queues(sc->hw); 2944 2945 return 0; 2946 err: 2947 return ret; 2948 } 2949 2950 static int ath5k_start(struct ieee80211_hw *hw) 2951 { 2952 return ath5k_init(hw->priv); 2953 } 2954 2955 static void ath5k_stop(struct ieee80211_hw *hw) 2956 { 2957 ath5k_stop_hw(hw->priv); 2958 } 2959 2960 static int ath5k_add_interface(struct ieee80211_hw *hw, 2961 struct ieee80211_vif *vif) 2962 { 2963 struct ath5k_softc *sc = hw->priv; 2964 int ret; 2965 2966 mutex_lock(&sc->lock); 2967 if (sc->vif) { 2968 ret = 0; 2969 goto end; 2970 } 2971 2972 sc->vif = vif; 2973 2974 switch (vif->type) { 2975 case NL80211_IFTYPE_AP: 2976 case NL80211_IFTYPE_STATION: 2977 case NL80211_IFTYPE_ADHOC: 2978 case NL80211_IFTYPE_MESH_POINT: 2979 case NL80211_IFTYPE_MONITOR: 2980 sc->opmode = vif->type; 2981 break; 2982 default: 2983 ret = -EOPNOTSUPP; 2984 goto end; 2985 } 2986 2987 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode); 2988 2989 ath5k_hw_set_lladdr(sc->ah, vif->addr); 2990 ath5k_mode_setup(sc); 2991 2992 ret = 0; 2993 end: 2994 mutex_unlock(&sc->lock); 2995 return ret; 2996 } 2997 2998 static void 2999 ath5k_remove_interface(struct ieee80211_hw *hw, 3000 struct ieee80211_vif *vif) 3001 { 3002 struct ath5k_softc *sc = hw->priv; 3003 u8 mac[ETH_ALEN] = {}; 3004 3005 mutex_lock(&sc->lock); 3006 if (sc->vif != vif) 3007 goto end; 3008 3009 ath5k_hw_set_lladdr(sc->ah, mac); 3010 sc->vif = NULL; 3011 end: 3012 mutex_unlock(&sc->lock); 3013 } 3014 3015 /* 3016 * TODO: Phy disable/diversity etc 3017 */ 3018 static int 3019 ath5k_config(struct ieee80211_hw *hw, u32 changed) 3020 { 3021 struct ath5k_softc *sc = hw->priv; 3022 struct ath5k_hw *ah = sc->ah; 3023 struct ieee80211_conf *conf = &hw->conf; 3024 int ret = 0; 3025 3026 mutex_lock(&sc->lock); 3027 3028 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 3029 ret = ath5k_chan_set(sc, conf->channel); 3030 if (ret < 0) 3031 goto unlock; 3032 } 3033 3034 if ((changed & IEEE80211_CONF_CHANGE_POWER) && 3035 (sc->power_level != conf->power_level)) { 3036 sc->power_level = conf->power_level; 3037 3038 /* Half dB steps */ 3039 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2)); 3040 } 3041 3042 /* TODO: 3043 * 1) Move this on config_interface and handle each case 3044 * separately eg. when we have only one STA vif, use 3045 * AR5K_ANTMODE_SINGLE_AP 3046 * 3047 * 2) Allow the user to change antenna mode eg. when only 3048 * one antenna is present 3049 * 3050 * 3) Allow the user to set default/tx antenna when possible 3051 * 3052 * 4) Default mode should handle 90% of the cases, together 3053 * with fixed a/b and single AP modes we should be able to 3054 * handle 99%. Sectored modes are extreme cases and i still 3055 * haven't found a usage for them. If we decide to support them, 3056 * then we must allow the user to set how many tx antennas we 3057 * have available 3058 */ 3059 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3060 3061 unlock: 3062 mutex_unlock(&sc->lock); 3063 return ret; 3064 } 3065 3066 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 3067 struct netdev_hw_addr_list *mc_list) 3068 { 3069 u32 mfilt[2], val; 3070 u8 pos; 3071 struct netdev_hw_addr *ha; 3072 3073 mfilt[0] = 0; 3074 mfilt[1] = 1; 3075 3076 netdev_hw_addr_list_for_each(ha, mc_list) { 3077 /* calculate XOR of eight 6-bit values */ 3078 val = get_unaligned_le32(ha->addr + 0); 3079 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 3080 val = get_unaligned_le32(ha->addr + 3); 3081 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 3082 pos &= 0x3f; 3083 mfilt[pos / 32] |= (1 << (pos % 32)); 3084 /* XXX: we might be able to just do this instead, 3085 * but not sure, needs testing, if we do use this we'd 3086 * neet to inform below to not reset the mcast */ 3087 /* ath5k_hw_set_mcast_filterindex(ah, 3088 * ha->addr[5]); */ 3089 } 3090 3091 return ((u64)(mfilt[1]) << 32) | mfilt[0]; 3092 } 3093 3094 #define SUPPORTED_FIF_FLAGS \ 3095 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ 3096 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ 3097 FIF_BCN_PRBRESP_PROMISC 3098 /* 3099 * o always accept unicast, broadcast, and multicast traffic 3100 * o multicast traffic for all BSSIDs will be enabled if mac80211 3101 * says it should be 3102 * o maintain current state of phy ofdm or phy cck error reception. 3103 * If the hardware detects any of these type of errors then 3104 * ath5k_hw_get_rx_filter() will pass to us the respective 3105 * hardware filters to be able to receive these type of frames. 3106 * o probe request frames are accepted only when operating in 3107 * hostap, adhoc, or monitor modes 3108 * o enable promiscuous mode according to the interface state 3109 * o accept beacons: 3110 * - when operating in adhoc mode so the 802.11 layer creates 3111 * node table entries for peers, 3112 * - when operating in station mode for collecting rssi data when 3113 * the station is otherwise quiet, or 3114 * - when scanning 3115 */ 3116 static void ath5k_configure_filter(struct ieee80211_hw *hw, 3117 unsigned int changed_flags, 3118 unsigned int *new_flags, 3119 u64 multicast) 3120 { 3121 struct ath5k_softc *sc = hw->priv; 3122 struct ath5k_hw *ah = sc->ah; 3123 u32 mfilt[2], rfilt; 3124 3125 mutex_lock(&sc->lock); 3126 3127 mfilt[0] = multicast; 3128 mfilt[1] = multicast >> 32; 3129 3130 /* Only deal with supported flags */ 3131 changed_flags &= SUPPORTED_FIF_FLAGS; 3132 *new_flags &= SUPPORTED_FIF_FLAGS; 3133 3134 /* If HW detects any phy or radar errors, leave those filters on. 3135 * Also, always enable Unicast, Broadcasts and Multicast 3136 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */ 3137 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) | 3138 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | 3139 AR5K_RX_FILTER_MCAST); 3140 3141 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { 3142 if (*new_flags & FIF_PROMISC_IN_BSS) { 3143 __set_bit(ATH_STAT_PROMISC, sc->status); 3144 } else { 3145 __clear_bit(ATH_STAT_PROMISC, sc->status); 3146 } 3147 } 3148 3149 if (test_bit(ATH_STAT_PROMISC, sc->status)) 3150 rfilt |= AR5K_RX_FILTER_PROM; 3151 3152 /* Note, AR5K_RX_FILTER_MCAST is already enabled */ 3153 if (*new_flags & FIF_ALLMULTI) { 3154 mfilt[0] = ~0; 3155 mfilt[1] = ~0; 3156 } 3157 3158 /* This is the best we can do */ 3159 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)) 3160 rfilt |= AR5K_RX_FILTER_PHYERR; 3161 3162 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons 3163 * and probes for any BSSID, this needs testing */ 3164 if (*new_flags & FIF_BCN_PRBRESP_PROMISC) 3165 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ; 3166 3167 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not 3168 * set we should only pass on control frames for this 3169 * station. This needs testing. I believe right now this 3170 * enables *all* control frames, which is OK.. but 3171 * but we should see if we can improve on granularity */ 3172 if (*new_flags & FIF_CONTROL) 3173 rfilt |= AR5K_RX_FILTER_CONTROL; 3174 3175 /* Additional settings per mode -- this is per ath5k */ 3176 3177 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ 3178 3179 switch (sc->opmode) { 3180 case NL80211_IFTYPE_MESH_POINT: 3181 case NL80211_IFTYPE_MONITOR: 3182 rfilt |= AR5K_RX_FILTER_CONTROL | 3183 AR5K_RX_FILTER_BEACON | 3184 AR5K_RX_FILTER_PROBEREQ | 3185 AR5K_RX_FILTER_PROM; 3186 break; 3187 case NL80211_IFTYPE_AP: 3188 case NL80211_IFTYPE_ADHOC: 3189 rfilt |= AR5K_RX_FILTER_PROBEREQ | 3190 AR5K_RX_FILTER_BEACON; 3191 break; 3192 case NL80211_IFTYPE_STATION: 3193 if (sc->assoc) 3194 rfilt |= AR5K_RX_FILTER_BEACON; 3195 default: 3196 break; 3197 } 3198 3199 /* Set filters */ 3200 ath5k_hw_set_rx_filter(ah, rfilt); 3201 3202 /* Set multicast bits */ 3203 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); 3204 /* Set the cached hw filter flags, this will alter actually 3205 * be set in HW */ 3206 sc->filter_flags = rfilt; 3207 3208 mutex_unlock(&sc->lock); 3209 } 3210 3211 static int 3212 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3213 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3214 struct ieee80211_key_conf *key) 3215 { 3216 struct ath5k_softc *sc = hw->priv; 3217 struct ath5k_hw *ah = sc->ah; 3218 struct ath_common *common = ath5k_hw_common(ah); 3219 int ret = 0; 3220 3221 if (modparam_nohwcrypt) 3222 return -EOPNOTSUPP; 3223 3224 if (sc->opmode == NL80211_IFTYPE_AP) 3225 return -EOPNOTSUPP; 3226 3227 switch (key->alg) { 3228 case ALG_WEP: 3229 case ALG_TKIP: 3230 break; 3231 case ALG_CCMP: 3232 if (sc->ah->ah_aes_support) 3233 break; 3234 3235 return -EOPNOTSUPP; 3236 default: 3237 WARN_ON(1); 3238 return -EINVAL; 3239 } 3240 3241 mutex_lock(&sc->lock); 3242 3243 switch (cmd) { 3244 case SET_KEY: 3245 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, 3246 sta ? sta->addr : NULL); 3247 if (ret) { 3248 ATH5K_ERR(sc, "can't set the key\n"); 3249 goto unlock; 3250 } 3251 __set_bit(key->keyidx, common->keymap); 3252 key->hw_key_idx = key->keyidx; 3253 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV | 3254 IEEE80211_KEY_FLAG_GENERATE_MMIC); 3255 break; 3256 case DISABLE_KEY: 3257 ath5k_hw_reset_key(sc->ah, key->keyidx); 3258 __clear_bit(key->keyidx, common->keymap); 3259 break; 3260 default: 3261 ret = -EINVAL; 3262 goto unlock; 3263 } 3264 3265 unlock: 3266 mmiowb(); 3267 mutex_unlock(&sc->lock); 3268 return ret; 3269 } 3270 3271 static int 3272 ath5k_get_stats(struct ieee80211_hw *hw, 3273 struct ieee80211_low_level_stats *stats) 3274 { 3275 struct ath5k_softc *sc = hw->priv; 3276 3277 /* Force update */ 3278 ath5k_hw_update_mib_counters(sc->ah); 3279 3280 stats->dot11ACKFailureCount = sc->stats.ack_fail; 3281 stats->dot11RTSFailureCount = sc->stats.rts_fail; 3282 stats->dot11RTSSuccessCount = sc->stats.rts_ok; 3283 stats->dot11FCSErrorCount = sc->stats.fcs_error; 3284 3285 return 0; 3286 } 3287 3288 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx, 3289 struct survey_info *survey) 3290 { 3291 struct ath5k_softc *sc = hw->priv; 3292 struct ieee80211_conf *conf = &hw->conf; 3293 3294 if (idx != 0) 3295 return -ENOENT; 3296 3297 survey->channel = conf->channel; 3298 survey->filled = SURVEY_INFO_NOISE_DBM; 3299 survey->noise = sc->ah->ah_noise_floor; 3300 3301 return 0; 3302 } 3303 3304 static u64 3305 ath5k_get_tsf(struct ieee80211_hw *hw) 3306 { 3307 struct ath5k_softc *sc = hw->priv; 3308 3309 return ath5k_hw_get_tsf64(sc->ah); 3310 } 3311 3312 static void 3313 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3314 { 3315 struct ath5k_softc *sc = hw->priv; 3316 3317 ath5k_hw_set_tsf64(sc->ah, tsf); 3318 } 3319 3320 static void 3321 ath5k_reset_tsf(struct ieee80211_hw *hw) 3322 { 3323 struct ath5k_softc *sc = hw->priv; 3324 3325 /* 3326 * in IBSS mode we need to update the beacon timers too. 3327 * this will also reset the TSF if we call it with 0 3328 */ 3329 if (sc->opmode == NL80211_IFTYPE_ADHOC) 3330 ath5k_beacon_update_timers(sc, 0); 3331 else 3332 ath5k_hw_reset_tsf(sc->ah); 3333 } 3334 3335 /* 3336 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 3337 * this is called only once at config_bss time, for AP we do it every 3338 * SWBA interrupt so that the TIM will reflect buffered frames. 3339 * 3340 * Called with the beacon lock. 3341 */ 3342 static int 3343 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 3344 { 3345 int ret; 3346 struct ath5k_softc *sc = hw->priv; 3347 struct sk_buff *skb; 3348 3349 if (WARN_ON(!vif)) { 3350 ret = -EINVAL; 3351 goto out; 3352 } 3353 3354 skb = ieee80211_beacon_get(hw, vif); 3355 3356 if (!skb) { 3357 ret = -ENOMEM; 3358 goto out; 3359 } 3360 3361 ath5k_debug_dump_skb(sc, skb, "BC ", 1); 3362 3363 ath5k_txbuf_free(sc, sc->bbuf); 3364 sc->bbuf->skb = skb; 3365 ret = ath5k_beacon_setup(sc, sc->bbuf); 3366 if (ret) 3367 sc->bbuf->skb = NULL; 3368 out: 3369 return ret; 3370 } 3371 3372 static void 3373 set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3374 { 3375 struct ath5k_softc *sc = hw->priv; 3376 struct ath5k_hw *ah = sc->ah; 3377 u32 rfilt; 3378 rfilt = ath5k_hw_get_rx_filter(ah); 3379 if (enable) 3380 rfilt |= AR5K_RX_FILTER_BEACON; 3381 else 3382 rfilt &= ~AR5K_RX_FILTER_BEACON; 3383 ath5k_hw_set_rx_filter(ah, rfilt); 3384 sc->filter_flags = rfilt; 3385 } 3386 3387 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 3388 struct ieee80211_vif *vif, 3389 struct ieee80211_bss_conf *bss_conf, 3390 u32 changes) 3391 { 3392 struct ath5k_softc *sc = hw->priv; 3393 struct ath5k_hw *ah = sc->ah; 3394 struct ath_common *common = ath5k_hw_common(ah); 3395 unsigned long flags; 3396 3397 mutex_lock(&sc->lock); 3398 if (WARN_ON(sc->vif != vif)) 3399 goto unlock; 3400 3401 if (changes & BSS_CHANGED_BSSID) { 3402 /* Cache for later use during resets */ 3403 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 3404 common->curaid = 0; 3405 ath5k_hw_set_associd(ah); 3406 mmiowb(); 3407 } 3408 3409 if (changes & BSS_CHANGED_BEACON_INT) 3410 sc->bintval = bss_conf->beacon_int; 3411 3412 if (changes & BSS_CHANGED_ASSOC) { 3413 sc->assoc = bss_conf->assoc; 3414 if (sc->opmode == NL80211_IFTYPE_STATION) 3415 set_beacon_filter(hw, sc->assoc); 3416 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3417 AR5K_LED_ASSOC : AR5K_LED_INIT); 3418 if (bss_conf->assoc) { 3419 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, 3420 "Bss Info ASSOC %d, bssid: %pM\n", 3421 bss_conf->aid, common->curbssid); 3422 common->curaid = bss_conf->aid; 3423 ath5k_hw_set_associd(ah); 3424 /* Once ANI is available you would start it here */ 3425 } 3426 } 3427 3428 if (changes & BSS_CHANGED_BEACON) { 3429 spin_lock_irqsave(&sc->block, flags); 3430 ath5k_beacon_update(hw, vif); 3431 spin_unlock_irqrestore(&sc->block, flags); 3432 } 3433 3434 if (changes & BSS_CHANGED_BEACON_ENABLED) 3435 sc->enable_beacon = bss_conf->enable_beacon; 3436 3437 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | 3438 BSS_CHANGED_BEACON_INT)) 3439 ath5k_beacon_config(sc); 3440 3441 unlock: 3442 mutex_unlock(&sc->lock); 3443 } 3444 3445 static void ath5k_sw_scan_start(struct ieee80211_hw *hw) 3446 { 3447 struct ath5k_softc *sc = hw->priv; 3448 if (!sc->assoc) 3449 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN); 3450 } 3451 3452 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw) 3453 { 3454 struct ath5k_softc *sc = hw->priv; 3455 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3456 AR5K_LED_ASSOC : AR5K_LED_INIT); 3457 } 3458 3459 /** 3460 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class 3461 * 3462 * @hw: struct ieee80211_hw pointer 3463 * @coverage_class: IEEE 802.11 coverage class number 3464 * 3465 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given 3466 * coverage class. The values are persistent, they are restored after device 3467 * reset. 3468 */ 3469 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 3470 { 3471 struct ath5k_softc *sc = hw->priv; 3472 3473 mutex_lock(&sc->lock); 3474 ath5k_hw_set_coverage_class(sc->ah, coverage_class); 3475 mutex_unlock(&sc->lock); 3476 } 3477