1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/hardirq.h> 46 #include <linux/if.h> 47 #include <linux/io.h> 48 #include <linux/netdevice.h> 49 #include <linux/cache.h> 50 #include <linux/ethtool.h> 51 #include <linux/uaccess.h> 52 #include <linux/slab.h> 53 #include <linux/etherdevice.h> 54 55 #include <net/ieee80211_radiotap.h> 56 57 #include <asm/unaligned.h> 58 59 #include "base.h" 60 #include "reg.h" 61 #include "debug.h" 62 #include "ani.h" 63 64 #define CREATE_TRACE_POINTS 65 #include "trace.h" 66 67 int ath5k_modparam_nohwcrypt; 68 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 69 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 70 71 static int modparam_all_channels; 72 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 73 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 74 75 /* Module info */ 76 MODULE_AUTHOR("Jiri Slaby"); 77 MODULE_AUTHOR("Nick Kossifidis"); 78 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 79 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 80 MODULE_LICENSE("Dual BSD/GPL"); 81 82 static int ath5k_init(struct ieee80211_hw *hw); 83 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 84 bool skip_pcu); 85 int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 86 void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 87 88 /* Known SREVs */ 89 static const struct ath5k_srev_name srev_names[] = { 90 #ifdef CONFIG_ATHEROS_AR231X 91 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 92 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 93 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 94 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 95 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 96 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 97 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 98 #else 99 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 100 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 101 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 102 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 103 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 104 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 105 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 106 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 107 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 108 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 109 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 110 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 111 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 112 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 113 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 114 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 115 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 116 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 117 #endif 118 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 119 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 120 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 121 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 122 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 123 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 124 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 125 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 128 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 129 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 130 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 131 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 133 #ifdef CONFIG_ATHEROS_AR231X 134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 136 #endif 137 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 138 }; 139 140 static const struct ieee80211_rate ath5k_rates[] = { 141 { .bitrate = 10, 142 .hw_value = ATH5K_RATE_CODE_1M, }, 143 { .bitrate = 20, 144 .hw_value = ATH5K_RATE_CODE_2M, 145 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 146 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 147 { .bitrate = 55, 148 .hw_value = ATH5K_RATE_CODE_5_5M, 149 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 150 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 151 { .bitrate = 110, 152 .hw_value = ATH5K_RATE_CODE_11M, 153 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 154 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 155 { .bitrate = 60, 156 .hw_value = ATH5K_RATE_CODE_6M, 157 .flags = 0 }, 158 { .bitrate = 90, 159 .hw_value = ATH5K_RATE_CODE_9M, 160 .flags = 0 }, 161 { .bitrate = 120, 162 .hw_value = ATH5K_RATE_CODE_12M, 163 .flags = 0 }, 164 { .bitrate = 180, 165 .hw_value = ATH5K_RATE_CODE_18M, 166 .flags = 0 }, 167 { .bitrate = 240, 168 .hw_value = ATH5K_RATE_CODE_24M, 169 .flags = 0 }, 170 { .bitrate = 360, 171 .hw_value = ATH5K_RATE_CODE_36M, 172 .flags = 0 }, 173 { .bitrate = 480, 174 .hw_value = ATH5K_RATE_CODE_48M, 175 .flags = 0 }, 176 { .bitrate = 540, 177 .hw_value = ATH5K_RATE_CODE_54M, 178 .flags = 0 }, 179 /* XR missing */ 180 }; 181 182 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 183 { 184 u64 tsf = ath5k_hw_get_tsf64(ah); 185 186 if ((tsf & 0x7fff) < rstamp) 187 tsf -= 0x8000; 188 189 return (tsf & ~0x7fff) | rstamp; 190 } 191 192 const char * 193 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 194 { 195 const char *name = "xxxxx"; 196 unsigned int i; 197 198 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 199 if (srev_names[i].sr_type != type) 200 continue; 201 202 if ((val & 0xf0) == srev_names[i].sr_val) 203 name = srev_names[i].sr_name; 204 205 if ((val & 0xff) == srev_names[i].sr_val) { 206 name = srev_names[i].sr_name; 207 break; 208 } 209 } 210 211 return name; 212 } 213 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 214 { 215 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 216 return ath5k_hw_reg_read(ah, reg_offset); 217 } 218 219 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 220 { 221 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 222 ath5k_hw_reg_write(ah, val, reg_offset); 223 } 224 225 static const struct ath_ops ath5k_common_ops = { 226 .read = ath5k_ioread32, 227 .write = ath5k_iowrite32, 228 }; 229 230 /***********************\ 231 * Driver Initialization * 232 \***********************/ 233 234 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 235 { 236 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 237 struct ath5k_softc *sc = hw->priv; 238 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 239 240 return ath_reg_notifier_apply(wiphy, request, regulatory); 241 } 242 243 /********************\ 244 * Channel/mode setup * 245 \********************/ 246 247 /* 248 * Returns true for the channel numbers used without all_channels modparam. 249 */ 250 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 251 { 252 if (band == IEEE80211_BAND_2GHZ && chan <= 14) 253 return true; 254 255 return /* UNII 1,2 */ 256 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 257 /* midband */ 258 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 259 /* UNII-3 */ 260 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 261 /* 802.11j 5.030-5.080 GHz (20MHz) */ 262 (chan == 8 || chan == 12 || chan == 16) || 263 /* 802.11j 4.9GHz (20MHz) */ 264 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 265 } 266 267 static unsigned int 268 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 269 unsigned int mode, unsigned int max) 270 { 271 unsigned int count, size, chfreq, freq, ch; 272 enum ieee80211_band band; 273 274 switch (mode) { 275 case AR5K_MODE_11A: 276 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 277 size = 220; 278 chfreq = CHANNEL_5GHZ; 279 band = IEEE80211_BAND_5GHZ; 280 break; 281 case AR5K_MODE_11B: 282 case AR5K_MODE_11G: 283 size = 26; 284 chfreq = CHANNEL_2GHZ; 285 band = IEEE80211_BAND_2GHZ; 286 break; 287 default: 288 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 289 return 0; 290 } 291 292 count = 0; 293 for (ch = 1; ch <= size && count < max; ch++) { 294 freq = ieee80211_channel_to_frequency(ch, band); 295 296 if (freq == 0) /* mapping failed - not a standard channel */ 297 continue; 298 299 /* Check if channel is supported by the chipset */ 300 if (!ath5k_channel_ok(ah, freq, chfreq)) 301 continue; 302 303 if (!modparam_all_channels && 304 !ath5k_is_standard_channel(ch, band)) 305 continue; 306 307 /* Write channel info and increment counter */ 308 channels[count].center_freq = freq; 309 channels[count].band = band; 310 switch (mode) { 311 case AR5K_MODE_11A: 312 case AR5K_MODE_11G: 313 channels[count].hw_value = chfreq | CHANNEL_OFDM; 314 break; 315 case AR5K_MODE_11B: 316 channels[count].hw_value = CHANNEL_B; 317 } 318 319 count++; 320 } 321 322 return count; 323 } 324 325 static void 326 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 327 { 328 u8 i; 329 330 for (i = 0; i < AR5K_MAX_RATES; i++) 331 sc->rate_idx[b->band][i] = -1; 332 333 for (i = 0; i < b->n_bitrates; i++) { 334 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 335 if (b->bitrates[i].hw_value_short) 336 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 337 } 338 } 339 340 static int 341 ath5k_setup_bands(struct ieee80211_hw *hw) 342 { 343 struct ath5k_softc *sc = hw->priv; 344 struct ath5k_hw *ah = sc->ah; 345 struct ieee80211_supported_band *sband; 346 int max_c, count_c = 0; 347 int i; 348 349 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 350 max_c = ARRAY_SIZE(sc->channels); 351 352 /* 2GHz band */ 353 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 354 sband->band = IEEE80211_BAND_2GHZ; 355 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 356 357 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 358 /* G mode */ 359 memcpy(sband->bitrates, &ath5k_rates[0], 360 sizeof(struct ieee80211_rate) * 12); 361 sband->n_bitrates = 12; 362 363 sband->channels = sc->channels; 364 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 365 AR5K_MODE_11G, max_c); 366 367 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 368 count_c = sband->n_channels; 369 max_c -= count_c; 370 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 371 /* B mode */ 372 memcpy(sband->bitrates, &ath5k_rates[0], 373 sizeof(struct ieee80211_rate) * 4); 374 sband->n_bitrates = 4; 375 376 /* 5211 only supports B rates and uses 4bit rate codes 377 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 378 * fix them up here: 379 */ 380 if (ah->ah_version == AR5K_AR5211) { 381 for (i = 0; i < 4; i++) { 382 sband->bitrates[i].hw_value = 383 sband->bitrates[i].hw_value & 0xF; 384 sband->bitrates[i].hw_value_short = 385 sband->bitrates[i].hw_value_short & 0xF; 386 } 387 } 388 389 sband->channels = sc->channels; 390 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 391 AR5K_MODE_11B, max_c); 392 393 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 394 count_c = sband->n_channels; 395 max_c -= count_c; 396 } 397 ath5k_setup_rate_idx(sc, sband); 398 399 /* 5GHz band, A mode */ 400 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 401 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 402 sband->band = IEEE80211_BAND_5GHZ; 403 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 404 405 memcpy(sband->bitrates, &ath5k_rates[4], 406 sizeof(struct ieee80211_rate) * 8); 407 sband->n_bitrates = 8; 408 409 sband->channels = &sc->channels[count_c]; 410 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 411 AR5K_MODE_11A, max_c); 412 413 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 414 } 415 ath5k_setup_rate_idx(sc, sband); 416 417 ath5k_debug_dump_bands(sc); 418 419 return 0; 420 } 421 422 /* 423 * Set/change channels. We always reset the chip. 424 * To accomplish this we must first cleanup any pending DMA, 425 * then restart stuff after a la ath5k_init. 426 * 427 * Called with sc->lock. 428 */ 429 int 430 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 431 { 432 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 433 "channel set, resetting (%u -> %u MHz)\n", 434 sc->curchan->center_freq, chan->center_freq); 435 436 /* 437 * To switch channels clear any pending DMA operations; 438 * wait long enough for the RX fifo to drain, reset the 439 * hardware at the new frequency, and then re-enable 440 * the relevant bits of the h/w. 441 */ 442 return ath5k_reset(sc, chan, true); 443 } 444 445 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 446 { 447 struct ath5k_vif_iter_data *iter_data = data; 448 int i; 449 struct ath5k_vif *avf = (void *)vif->drv_priv; 450 451 if (iter_data->hw_macaddr) 452 for (i = 0; i < ETH_ALEN; i++) 453 iter_data->mask[i] &= 454 ~(iter_data->hw_macaddr[i] ^ mac[i]); 455 456 if (!iter_data->found_active) { 457 iter_data->found_active = true; 458 memcpy(iter_data->active_mac, mac, ETH_ALEN); 459 } 460 461 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 462 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0) 463 iter_data->need_set_hw_addr = false; 464 465 if (!iter_data->any_assoc) { 466 if (avf->assoc) 467 iter_data->any_assoc = true; 468 } 469 470 /* Calculate combined mode - when APs are active, operate in AP mode. 471 * Otherwise use the mode of the new interface. This can currently 472 * only deal with combinations of APs and STAs. Only one ad-hoc 473 * interfaces is allowed. 474 */ 475 if (avf->opmode == NL80211_IFTYPE_AP) 476 iter_data->opmode = NL80211_IFTYPE_AP; 477 else { 478 if (avf->opmode == NL80211_IFTYPE_STATION) 479 iter_data->n_stas++; 480 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 481 iter_data->opmode = avf->opmode; 482 } 483 } 484 485 void 486 ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 487 struct ieee80211_vif *vif) 488 { 489 struct ath_common *common = ath5k_hw_common(sc->ah); 490 struct ath5k_vif_iter_data iter_data; 491 u32 rfilt; 492 493 /* 494 * Use the hardware MAC address as reference, the hardware uses it 495 * together with the BSSID mask when matching addresses. 496 */ 497 iter_data.hw_macaddr = common->macaddr; 498 memset(&iter_data.mask, 0xff, ETH_ALEN); 499 iter_data.found_active = false; 500 iter_data.need_set_hw_addr = true; 501 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 502 iter_data.n_stas = 0; 503 504 if (vif) 505 ath5k_vif_iter(&iter_data, vif->addr, vif); 506 507 /* Get list of all active MAC addresses */ 508 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 509 &iter_data); 510 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN); 511 512 sc->opmode = iter_data.opmode; 513 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED) 514 /* Nothing active, default to station mode */ 515 sc->opmode = NL80211_IFTYPE_STATION; 516 517 ath5k_hw_set_opmode(sc->ah, sc->opmode); 518 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 519 sc->opmode, ath_opmode_to_string(sc->opmode)); 520 521 if (iter_data.need_set_hw_addr && iter_data.found_active) 522 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac); 523 524 if (ath5k_hw_hasbssidmask(sc->ah)) 525 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 526 527 /* Set up RX Filter */ 528 if (iter_data.n_stas > 1) { 529 /* If you have multiple STA interfaces connected to 530 * different APs, ARPs are not received (most of the time?) 531 * Enabling PROMISC appears to fix that probem. 532 */ 533 sc->filter_flags |= AR5K_RX_FILTER_PROM; 534 } 535 536 rfilt = sc->filter_flags; 537 ath5k_hw_set_rx_filter(sc->ah, rfilt); 538 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 539 } 540 541 static inline int 542 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 543 { 544 int rix; 545 546 /* return base rate on errors */ 547 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 548 "hw_rix out of bounds: %x\n", hw_rix)) 549 return 0; 550 551 rix = sc->rate_idx[sc->curchan->band][hw_rix]; 552 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 553 rix = 0; 554 555 return rix; 556 } 557 558 /***************\ 559 * Buffers setup * 560 \***************/ 561 562 static 563 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 564 { 565 struct ath_common *common = ath5k_hw_common(sc->ah); 566 struct sk_buff *skb; 567 568 /* 569 * Allocate buffer with headroom_needed space for the 570 * fake physical layer header at the start. 571 */ 572 skb = ath_rxbuf_alloc(common, 573 common->rx_bufsize, 574 GFP_ATOMIC); 575 576 if (!skb) { 577 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 578 common->rx_bufsize); 579 return NULL; 580 } 581 582 *skb_addr = dma_map_single(sc->dev, 583 skb->data, common->rx_bufsize, 584 DMA_FROM_DEVICE); 585 586 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) { 587 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 588 dev_kfree_skb(skb); 589 return NULL; 590 } 591 return skb; 592 } 593 594 static int 595 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 596 { 597 struct ath5k_hw *ah = sc->ah; 598 struct sk_buff *skb = bf->skb; 599 struct ath5k_desc *ds; 600 int ret; 601 602 if (!skb) { 603 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 604 if (!skb) 605 return -ENOMEM; 606 bf->skb = skb; 607 } 608 609 /* 610 * Setup descriptors. For receive we always terminate 611 * the descriptor list with a self-linked entry so we'll 612 * not get overrun under high load (as can happen with a 613 * 5212 when ANI processing enables PHY error frames). 614 * 615 * To ensure the last descriptor is self-linked we create 616 * each descriptor as self-linked and add it to the end. As 617 * each additional descriptor is added the previous self-linked 618 * entry is "fixed" naturally. This should be safe even 619 * if DMA is happening. When processing RX interrupts we 620 * never remove/process the last, self-linked, entry on the 621 * descriptor list. This ensures the hardware always has 622 * someplace to write a new frame. 623 */ 624 ds = bf->desc; 625 ds->ds_link = bf->daddr; /* link to self */ 626 ds->ds_data = bf->skbaddr; 627 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 628 if (ret) { 629 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__); 630 return ret; 631 } 632 633 if (sc->rxlink != NULL) 634 *sc->rxlink = bf->daddr; 635 sc->rxlink = &ds->ds_link; 636 return 0; 637 } 638 639 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 640 { 641 struct ieee80211_hdr *hdr; 642 enum ath5k_pkt_type htype; 643 __le16 fc; 644 645 hdr = (struct ieee80211_hdr *)skb->data; 646 fc = hdr->frame_control; 647 648 if (ieee80211_is_beacon(fc)) 649 htype = AR5K_PKT_TYPE_BEACON; 650 else if (ieee80211_is_probe_resp(fc)) 651 htype = AR5K_PKT_TYPE_PROBE_RESP; 652 else if (ieee80211_is_atim(fc)) 653 htype = AR5K_PKT_TYPE_ATIM; 654 else if (ieee80211_is_pspoll(fc)) 655 htype = AR5K_PKT_TYPE_PSPOLL; 656 else 657 htype = AR5K_PKT_TYPE_NORMAL; 658 659 return htype; 660 } 661 662 static int 663 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 664 struct ath5k_txq *txq, int padsize) 665 { 666 struct ath5k_hw *ah = sc->ah; 667 struct ath5k_desc *ds = bf->desc; 668 struct sk_buff *skb = bf->skb; 669 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 670 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 671 struct ieee80211_rate *rate; 672 unsigned int mrr_rate[3], mrr_tries[3]; 673 int i, ret; 674 u16 hw_rate; 675 u16 cts_rate = 0; 676 u16 duration = 0; 677 u8 rc_flags; 678 679 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 680 681 /* XXX endianness */ 682 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 683 DMA_TO_DEVICE); 684 685 rate = ieee80211_get_tx_rate(sc->hw, info); 686 if (!rate) { 687 ret = -EINVAL; 688 goto err_unmap; 689 } 690 691 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 692 flags |= AR5K_TXDESC_NOACK; 693 694 rc_flags = info->control.rates[0].flags; 695 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 696 rate->hw_value_short : rate->hw_value; 697 698 pktlen = skb->len; 699 700 /* FIXME: If we are in g mode and rate is a CCK rate 701 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 702 * from tx power (value is in dB units already) */ 703 if (info->control.hw_key) { 704 keyidx = info->control.hw_key->hw_key_idx; 705 pktlen += info->control.hw_key->icv_len; 706 } 707 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 708 flags |= AR5K_TXDESC_RTSENA; 709 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 710 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 711 info->control.vif, pktlen, info)); 712 } 713 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 714 flags |= AR5K_TXDESC_CTSENA; 715 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 716 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 717 info->control.vif, pktlen, info)); 718 } 719 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 720 ieee80211_get_hdrlen_from_skb(skb), padsize, 721 get_hw_packet_type(skb), 722 (sc->power_level * 2), 723 hw_rate, 724 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 725 cts_rate, duration); 726 if (ret) 727 goto err_unmap; 728 729 memset(mrr_rate, 0, sizeof(mrr_rate)); 730 memset(mrr_tries, 0, sizeof(mrr_tries)); 731 for (i = 0; i < 3; i++) { 732 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 733 if (!rate) 734 break; 735 736 mrr_rate[i] = rate->hw_value; 737 mrr_tries[i] = info->control.rates[i + 1].count; 738 } 739 740 ath5k_hw_setup_mrr_tx_desc(ah, ds, 741 mrr_rate[0], mrr_tries[0], 742 mrr_rate[1], mrr_tries[1], 743 mrr_rate[2], mrr_tries[2]); 744 745 ds->ds_link = 0; 746 ds->ds_data = bf->skbaddr; 747 748 spin_lock_bh(&txq->lock); 749 list_add_tail(&bf->list, &txq->q); 750 txq->txq_len++; 751 if (txq->link == NULL) /* is this first packet? */ 752 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 753 else /* no, so only link it */ 754 *txq->link = bf->daddr; 755 756 txq->link = &ds->ds_link; 757 ath5k_hw_start_tx_dma(ah, txq->qnum); 758 mmiowb(); 759 spin_unlock_bh(&txq->lock); 760 761 return 0; 762 err_unmap: 763 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 764 return ret; 765 } 766 767 /*******************\ 768 * Descriptors setup * 769 \*******************/ 770 771 static int 772 ath5k_desc_alloc(struct ath5k_softc *sc) 773 { 774 struct ath5k_desc *ds; 775 struct ath5k_buf *bf; 776 dma_addr_t da; 777 unsigned int i; 778 int ret; 779 780 /* allocate descriptors */ 781 sc->desc_len = sizeof(struct ath5k_desc) * 782 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 783 784 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len, 785 &sc->desc_daddr, GFP_KERNEL); 786 if (sc->desc == NULL) { 787 ATH5K_ERR(sc, "can't allocate descriptors\n"); 788 ret = -ENOMEM; 789 goto err; 790 } 791 ds = sc->desc; 792 da = sc->desc_daddr; 793 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 794 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 795 796 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 797 sizeof(struct ath5k_buf), GFP_KERNEL); 798 if (bf == NULL) { 799 ATH5K_ERR(sc, "can't allocate bufptr\n"); 800 ret = -ENOMEM; 801 goto err_free; 802 } 803 sc->bufptr = bf; 804 805 INIT_LIST_HEAD(&sc->rxbuf); 806 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 807 bf->desc = ds; 808 bf->daddr = da; 809 list_add_tail(&bf->list, &sc->rxbuf); 810 } 811 812 INIT_LIST_HEAD(&sc->txbuf); 813 sc->txbuf_len = ATH_TXBUF; 814 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 815 da += sizeof(*ds)) { 816 bf->desc = ds; 817 bf->daddr = da; 818 list_add_tail(&bf->list, &sc->txbuf); 819 } 820 821 /* beacon buffers */ 822 INIT_LIST_HEAD(&sc->bcbuf); 823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 824 bf->desc = ds; 825 bf->daddr = da; 826 list_add_tail(&bf->list, &sc->bcbuf); 827 } 828 829 return 0; 830 err_free: 831 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 832 err: 833 sc->desc = NULL; 834 return ret; 835 } 836 837 void 838 ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 839 { 840 BUG_ON(!bf); 841 if (!bf->skb) 842 return; 843 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len, 844 DMA_TO_DEVICE); 845 dev_kfree_skb_any(bf->skb); 846 bf->skb = NULL; 847 bf->skbaddr = 0; 848 bf->desc->ds_data = 0; 849 } 850 851 void 852 ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 853 { 854 struct ath5k_hw *ah = sc->ah; 855 struct ath_common *common = ath5k_hw_common(ah); 856 857 BUG_ON(!bf); 858 if (!bf->skb) 859 return; 860 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize, 861 DMA_FROM_DEVICE); 862 dev_kfree_skb_any(bf->skb); 863 bf->skb = NULL; 864 bf->skbaddr = 0; 865 bf->desc->ds_data = 0; 866 } 867 868 static void 869 ath5k_desc_free(struct ath5k_softc *sc) 870 { 871 struct ath5k_buf *bf; 872 873 list_for_each_entry(bf, &sc->txbuf, list) 874 ath5k_txbuf_free_skb(sc, bf); 875 list_for_each_entry(bf, &sc->rxbuf, list) 876 ath5k_rxbuf_free_skb(sc, bf); 877 list_for_each_entry(bf, &sc->bcbuf, list) 878 ath5k_txbuf_free_skb(sc, bf); 879 880 /* Free memory associated with all descriptors */ 881 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 882 sc->desc = NULL; 883 sc->desc_daddr = 0; 884 885 kfree(sc->bufptr); 886 sc->bufptr = NULL; 887 } 888 889 890 /**************\ 891 * Queues setup * 892 \**************/ 893 894 static struct ath5k_txq * 895 ath5k_txq_setup(struct ath5k_softc *sc, 896 int qtype, int subtype) 897 { 898 struct ath5k_hw *ah = sc->ah; 899 struct ath5k_txq *txq; 900 struct ath5k_txq_info qi = { 901 .tqi_subtype = subtype, 902 /* XXX: default values not correct for B and XR channels, 903 * but who cares? */ 904 .tqi_aifs = AR5K_TUNE_AIFS, 905 .tqi_cw_min = AR5K_TUNE_CWMIN, 906 .tqi_cw_max = AR5K_TUNE_CWMAX 907 }; 908 int qnum; 909 910 /* 911 * Enable interrupts only for EOL and DESC conditions. 912 * We mark tx descriptors to receive a DESC interrupt 913 * when a tx queue gets deep; otherwise we wait for the 914 * EOL to reap descriptors. Note that this is done to 915 * reduce interrupt load and this only defers reaping 916 * descriptors, never transmitting frames. Aside from 917 * reducing interrupts this also permits more concurrency. 918 * The only potential downside is if the tx queue backs 919 * up in which case the top half of the kernel may backup 920 * due to a lack of tx descriptors. 921 */ 922 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 923 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 924 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 925 if (qnum < 0) { 926 /* 927 * NB: don't print a message, this happens 928 * normally on parts with too few tx queues 929 */ 930 return ERR_PTR(qnum); 931 } 932 if (qnum >= ARRAY_SIZE(sc->txqs)) { 933 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 934 qnum, ARRAY_SIZE(sc->txqs)); 935 ath5k_hw_release_tx_queue(ah, qnum); 936 return ERR_PTR(-EINVAL); 937 } 938 txq = &sc->txqs[qnum]; 939 if (!txq->setup) { 940 txq->qnum = qnum; 941 txq->link = NULL; 942 INIT_LIST_HEAD(&txq->q); 943 spin_lock_init(&txq->lock); 944 txq->setup = true; 945 txq->txq_len = 0; 946 txq->txq_max = ATH5K_TXQ_LEN_MAX; 947 txq->txq_poll_mark = false; 948 txq->txq_stuck = 0; 949 } 950 return &sc->txqs[qnum]; 951 } 952 953 static int 954 ath5k_beaconq_setup(struct ath5k_hw *ah) 955 { 956 struct ath5k_txq_info qi = { 957 /* XXX: default values not correct for B and XR channels, 958 * but who cares? */ 959 .tqi_aifs = AR5K_TUNE_AIFS, 960 .tqi_cw_min = AR5K_TUNE_CWMIN, 961 .tqi_cw_max = AR5K_TUNE_CWMAX, 962 /* NB: for dynamic turbo, don't enable any other interrupts */ 963 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 964 }; 965 966 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 967 } 968 969 static int 970 ath5k_beaconq_config(struct ath5k_softc *sc) 971 { 972 struct ath5k_hw *ah = sc->ah; 973 struct ath5k_txq_info qi; 974 int ret; 975 976 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 977 if (ret) 978 goto err; 979 980 if (sc->opmode == NL80211_IFTYPE_AP || 981 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 982 /* 983 * Always burst out beacon and CAB traffic 984 * (aifs = cwmin = cwmax = 0) 985 */ 986 qi.tqi_aifs = 0; 987 qi.tqi_cw_min = 0; 988 qi.tqi_cw_max = 0; 989 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 990 /* 991 * Adhoc mode; backoff between 0 and (2 * cw_min). 992 */ 993 qi.tqi_aifs = 0; 994 qi.tqi_cw_min = 0; 995 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 996 } 997 998 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 999 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1000 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1001 1002 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1003 if (ret) { 1004 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1005 "hardware queue!\n", __func__); 1006 goto err; 1007 } 1008 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ 1009 if (ret) 1010 goto err; 1011 1012 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1013 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1014 if (ret) 1015 goto err; 1016 1017 qi.tqi_ready_time = (sc->bintval * 80) / 100; 1018 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1019 if (ret) 1020 goto err; 1021 1022 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1023 err: 1024 return ret; 1025 } 1026 1027 /** 1028 * ath5k_drain_tx_buffs - Empty tx buffers 1029 * 1030 * @sc The &struct ath5k_softc 1031 * 1032 * Empty tx buffers from all queues in preparation 1033 * of a reset or during shutdown. 1034 * 1035 * NB: this assumes output has been stopped and 1036 * we do not need to block ath5k_tx_tasklet 1037 */ 1038 static void 1039 ath5k_drain_tx_buffs(struct ath5k_softc *sc) 1040 { 1041 struct ath5k_txq *txq; 1042 struct ath5k_buf *bf, *bf0; 1043 int i; 1044 1045 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 1046 if (sc->txqs[i].setup) { 1047 txq = &sc->txqs[i]; 1048 spin_lock_bh(&txq->lock); 1049 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1050 ath5k_debug_printtxbuf(sc, bf); 1051 1052 ath5k_txbuf_free_skb(sc, bf); 1053 1054 spin_lock_bh(&sc->txbuflock); 1055 list_move_tail(&bf->list, &sc->txbuf); 1056 sc->txbuf_len++; 1057 txq->txq_len--; 1058 spin_unlock_bh(&sc->txbuflock); 1059 } 1060 txq->link = NULL; 1061 txq->txq_poll_mark = false; 1062 spin_unlock_bh(&txq->lock); 1063 } 1064 } 1065 } 1066 1067 static void 1068 ath5k_txq_release(struct ath5k_softc *sc) 1069 { 1070 struct ath5k_txq *txq = sc->txqs; 1071 unsigned int i; 1072 1073 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1074 if (txq->setup) { 1075 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1076 txq->setup = false; 1077 } 1078 } 1079 1080 1081 /*************\ 1082 * RX Handling * 1083 \*************/ 1084 1085 /* 1086 * Enable the receive h/w following a reset. 1087 */ 1088 static int 1089 ath5k_rx_start(struct ath5k_softc *sc) 1090 { 1091 struct ath5k_hw *ah = sc->ah; 1092 struct ath_common *common = ath5k_hw_common(ah); 1093 struct ath5k_buf *bf; 1094 int ret; 1095 1096 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1097 1098 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1099 common->cachelsz, common->rx_bufsize); 1100 1101 spin_lock_bh(&sc->rxbuflock); 1102 sc->rxlink = NULL; 1103 list_for_each_entry(bf, &sc->rxbuf, list) { 1104 ret = ath5k_rxbuf_setup(sc, bf); 1105 if (ret != 0) { 1106 spin_unlock_bh(&sc->rxbuflock); 1107 goto err; 1108 } 1109 } 1110 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1111 ath5k_hw_set_rxdp(ah, bf->daddr); 1112 spin_unlock_bh(&sc->rxbuflock); 1113 1114 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1115 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */ 1116 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1117 1118 return 0; 1119 err: 1120 return ret; 1121 } 1122 1123 /* 1124 * Disable the receive logic on PCU (DRU) 1125 * In preparation for a shutdown. 1126 * 1127 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1128 * does. 1129 */ 1130 static void 1131 ath5k_rx_stop(struct ath5k_softc *sc) 1132 { 1133 struct ath5k_hw *ah = sc->ah; 1134 1135 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1136 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1137 1138 ath5k_debug_printrxbuffs(sc, ah); 1139 } 1140 1141 static unsigned int 1142 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb, 1143 struct ath5k_rx_status *rs) 1144 { 1145 struct ath5k_hw *ah = sc->ah; 1146 struct ath_common *common = ath5k_hw_common(ah); 1147 struct ieee80211_hdr *hdr = (void *)skb->data; 1148 unsigned int keyix, hlen; 1149 1150 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1151 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1152 return RX_FLAG_DECRYPTED; 1153 1154 /* Apparently when a default key is used to decrypt the packet 1155 the hw does not set the index used to decrypt. In such cases 1156 get the index from the packet. */ 1157 hlen = ieee80211_hdrlen(hdr->frame_control); 1158 if (ieee80211_has_protected(hdr->frame_control) && 1159 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1160 skb->len >= hlen + 4) { 1161 keyix = skb->data[hlen + 3] >> 6; 1162 1163 if (test_bit(keyix, common->keymap)) 1164 return RX_FLAG_DECRYPTED; 1165 } 1166 1167 return 0; 1168 } 1169 1170 1171 static void 1172 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1173 struct ieee80211_rx_status *rxs) 1174 { 1175 struct ath_common *common = ath5k_hw_common(sc->ah); 1176 u64 tsf, bc_tstamp; 1177 u32 hw_tu; 1178 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1179 1180 if (ieee80211_is_beacon(mgmt->frame_control) && 1181 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1182 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1183 /* 1184 * Received an IBSS beacon with the same BSSID. Hardware *must* 1185 * have updated the local TSF. We have to work around various 1186 * hardware bugs, though... 1187 */ 1188 tsf = ath5k_hw_get_tsf64(sc->ah); 1189 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1190 hw_tu = TSF_TO_TU(tsf); 1191 1192 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1193 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1194 (unsigned long long)bc_tstamp, 1195 (unsigned long long)rxs->mactime, 1196 (unsigned long long)(rxs->mactime - bc_tstamp), 1197 (unsigned long long)tsf); 1198 1199 /* 1200 * Sometimes the HW will give us a wrong tstamp in the rx 1201 * status, causing the timestamp extension to go wrong. 1202 * (This seems to happen especially with beacon frames bigger 1203 * than 78 byte (incl. FCS)) 1204 * But we know that the receive timestamp must be later than the 1205 * timestamp of the beacon since HW must have synced to that. 1206 * 1207 * NOTE: here we assume mactime to be after the frame was 1208 * received, not like mac80211 which defines it at the start. 1209 */ 1210 if (bc_tstamp > rxs->mactime) { 1211 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1212 "fixing mactime from %llx to %llx\n", 1213 (unsigned long long)rxs->mactime, 1214 (unsigned long long)tsf); 1215 rxs->mactime = tsf; 1216 } 1217 1218 /* 1219 * Local TSF might have moved higher than our beacon timers, 1220 * in that case we have to update them to continue sending 1221 * beacons. This also takes care of synchronizing beacon sending 1222 * times with other stations. 1223 */ 1224 if (hw_tu >= sc->nexttbtt) 1225 ath5k_beacon_update_timers(sc, bc_tstamp); 1226 1227 /* Check if the beacon timers are still correct, because a TSF 1228 * update might have created a window between them - for a 1229 * longer description see the comment of this function: */ 1230 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) { 1231 ath5k_beacon_update_timers(sc, bc_tstamp); 1232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1233 "fixed beacon timers after beacon receive\n"); 1234 } 1235 } 1236 } 1237 1238 static void 1239 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) 1240 { 1241 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1242 struct ath5k_hw *ah = sc->ah; 1243 struct ath_common *common = ath5k_hw_common(ah); 1244 1245 /* only beacons from our BSSID */ 1246 if (!ieee80211_is_beacon(mgmt->frame_control) || 1247 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) 1248 return; 1249 1250 ewma_add(&ah->ah_beacon_rssi_avg, rssi); 1251 1252 /* in IBSS mode we should keep RSSI statistics per neighbour */ 1253 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ 1254 } 1255 1256 /* 1257 * Compute padding position. skb must contain an IEEE 802.11 frame 1258 */ 1259 static int ath5k_common_padpos(struct sk_buff *skb) 1260 { 1261 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 1262 __le16 frame_control = hdr->frame_control; 1263 int padpos = 24; 1264 1265 if (ieee80211_has_a4(frame_control)) { 1266 padpos += ETH_ALEN; 1267 } 1268 if (ieee80211_is_data_qos(frame_control)) { 1269 padpos += IEEE80211_QOS_CTL_LEN; 1270 } 1271 1272 return padpos; 1273 } 1274 1275 /* 1276 * This function expects an 802.11 frame and returns the number of 1277 * bytes added, or -1 if we don't have enough header room. 1278 */ 1279 static int ath5k_add_padding(struct sk_buff *skb) 1280 { 1281 int padpos = ath5k_common_padpos(skb); 1282 int padsize = padpos & 3; 1283 1284 if (padsize && skb->len>padpos) { 1285 1286 if (skb_headroom(skb) < padsize) 1287 return -1; 1288 1289 skb_push(skb, padsize); 1290 memmove(skb->data, skb->data+padsize, padpos); 1291 return padsize; 1292 } 1293 1294 return 0; 1295 } 1296 1297 /* 1298 * The MAC header is padded to have 32-bit boundary if the 1299 * packet payload is non-zero. The general calculation for 1300 * padsize would take into account odd header lengths: 1301 * padsize = 4 - (hdrlen & 3); however, since only 1302 * even-length headers are used, padding can only be 0 or 2 1303 * bytes and we can optimize this a bit. We must not try to 1304 * remove padding from short control frames that do not have a 1305 * payload. 1306 * 1307 * This function expects an 802.11 frame and returns the number of 1308 * bytes removed. 1309 */ 1310 static int ath5k_remove_padding(struct sk_buff *skb) 1311 { 1312 int padpos = ath5k_common_padpos(skb); 1313 int padsize = padpos & 3; 1314 1315 if (padsize && skb->len>=padpos+padsize) { 1316 memmove(skb->data + padsize, skb->data, padpos); 1317 skb_pull(skb, padsize); 1318 return padsize; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static void 1325 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb, 1326 struct ath5k_rx_status *rs) 1327 { 1328 struct ieee80211_rx_status *rxs; 1329 1330 ath5k_remove_padding(skb); 1331 1332 rxs = IEEE80211_SKB_RXCB(skb); 1333 1334 rxs->flag = 0; 1335 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1336 rxs->flag |= RX_FLAG_MMIC_ERROR; 1337 1338 /* 1339 * always extend the mac timestamp, since this information is 1340 * also needed for proper IBSS merging. 1341 * 1342 * XXX: it might be too late to do it here, since rs_tstamp is 1343 * 15bit only. that means TSF extension has to be done within 1344 * 32768usec (about 32ms). it might be necessary to move this to 1345 * the interrupt handler, like it is done in madwifi. 1346 * 1347 * Unfortunately we don't know when the hardware takes the rx 1348 * timestamp (beginning of phy frame, data frame, end of rx?). 1349 * The only thing we know is that it is hardware specific... 1350 * On AR5213 it seems the rx timestamp is at the end of the 1351 * frame, but i'm not sure. 1352 * 1353 * NOTE: mac80211 defines mactime at the beginning of the first 1354 * data symbol. Since we don't have any time references it's 1355 * impossible to comply to that. This affects IBSS merge only 1356 * right now, so it's not too bad... 1357 */ 1358 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp); 1359 rxs->flag |= RX_FLAG_MACTIME_MPDU; 1360 1361 rxs->freq = sc->curchan->center_freq; 1362 rxs->band = sc->curchan->band; 1363 1364 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi; 1365 1366 rxs->antenna = rs->rs_antenna; 1367 1368 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1369 sc->stats.antenna_rx[rs->rs_antenna]++; 1370 else 1371 sc->stats.antenna_rx[0]++; /* invalid */ 1372 1373 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate); 1374 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs); 1375 1376 if (rxs->rate_idx >= 0 && rs->rs_rate == 1377 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1378 rxs->flag |= RX_FLAG_SHORTPRE; 1379 1380 trace_ath5k_rx(sc, skb); 1381 1382 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi); 1383 1384 /* check beacons in IBSS mode */ 1385 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1386 ath5k_check_ibss_tsf(sc, skb, rxs); 1387 1388 ieee80211_rx(sc->hw, skb); 1389 } 1390 1391 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1392 * 1393 * Check if we want to further process this frame or not. Also update 1394 * statistics. Return true if we want this frame, false if not. 1395 */ 1396 static bool 1397 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) 1398 { 1399 sc->stats.rx_all_count++; 1400 sc->stats.rx_bytes_count += rs->rs_datalen; 1401 1402 if (unlikely(rs->rs_status)) { 1403 if (rs->rs_status & AR5K_RXERR_CRC) 1404 sc->stats.rxerr_crc++; 1405 if (rs->rs_status & AR5K_RXERR_FIFO) 1406 sc->stats.rxerr_fifo++; 1407 if (rs->rs_status & AR5K_RXERR_PHY) { 1408 sc->stats.rxerr_phy++; 1409 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1410 sc->stats.rxerr_phy_code[rs->rs_phyerr]++; 1411 return false; 1412 } 1413 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1414 /* 1415 * Decrypt error. If the error occurred 1416 * because there was no hardware key, then 1417 * let the frame through so the upper layers 1418 * can process it. This is necessary for 5210 1419 * parts which have no way to setup a ``clear'' 1420 * key cache entry. 1421 * 1422 * XXX do key cache faulting 1423 */ 1424 sc->stats.rxerr_decrypt++; 1425 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1426 !(rs->rs_status & AR5K_RXERR_CRC)) 1427 return true; 1428 } 1429 if (rs->rs_status & AR5K_RXERR_MIC) { 1430 sc->stats.rxerr_mic++; 1431 return true; 1432 } 1433 1434 /* reject any frames with non-crypto errors */ 1435 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) 1436 return false; 1437 } 1438 1439 if (unlikely(rs->rs_more)) { 1440 sc->stats.rxerr_jumbo++; 1441 return false; 1442 } 1443 return true; 1444 } 1445 1446 static void 1447 ath5k_set_current_imask(struct ath5k_softc *sc) 1448 { 1449 enum ath5k_int imask = sc->imask; 1450 unsigned long flags; 1451 1452 spin_lock_irqsave(&sc->irqlock, flags); 1453 if (sc->rx_pending) 1454 imask &= ~AR5K_INT_RX_ALL; 1455 if (sc->tx_pending) 1456 imask &= ~AR5K_INT_TX_ALL; 1457 ath5k_hw_set_imr(sc->ah, imask); 1458 spin_unlock_irqrestore(&sc->irqlock, flags); 1459 } 1460 1461 static void 1462 ath5k_tasklet_rx(unsigned long data) 1463 { 1464 struct ath5k_rx_status rs = {}; 1465 struct sk_buff *skb, *next_skb; 1466 dma_addr_t next_skb_addr; 1467 struct ath5k_softc *sc = (void *)data; 1468 struct ath5k_hw *ah = sc->ah; 1469 struct ath_common *common = ath5k_hw_common(ah); 1470 struct ath5k_buf *bf; 1471 struct ath5k_desc *ds; 1472 int ret; 1473 1474 spin_lock(&sc->rxbuflock); 1475 if (list_empty(&sc->rxbuf)) { 1476 ATH5K_WARN(sc, "empty rx buf pool\n"); 1477 goto unlock; 1478 } 1479 do { 1480 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1481 BUG_ON(bf->skb == NULL); 1482 skb = bf->skb; 1483 ds = bf->desc; 1484 1485 /* bail if HW is still using self-linked descriptor */ 1486 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1487 break; 1488 1489 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1490 if (unlikely(ret == -EINPROGRESS)) 1491 break; 1492 else if (unlikely(ret)) { 1493 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1494 sc->stats.rxerr_proc++; 1495 break; 1496 } 1497 1498 if (ath5k_receive_frame_ok(sc, &rs)) { 1499 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1500 1501 /* 1502 * If we can't replace bf->skb with a new skb under 1503 * memory pressure, just skip this packet 1504 */ 1505 if (!next_skb) 1506 goto next; 1507 1508 dma_unmap_single(sc->dev, bf->skbaddr, 1509 common->rx_bufsize, 1510 DMA_FROM_DEVICE); 1511 1512 skb_put(skb, rs.rs_datalen); 1513 1514 ath5k_receive_frame(sc, skb, &rs); 1515 1516 bf->skb = next_skb; 1517 bf->skbaddr = next_skb_addr; 1518 } 1519 next: 1520 list_move_tail(&bf->list, &sc->rxbuf); 1521 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1522 unlock: 1523 spin_unlock(&sc->rxbuflock); 1524 sc->rx_pending = false; 1525 ath5k_set_current_imask(sc); 1526 } 1527 1528 1529 /*************\ 1530 * TX Handling * 1531 \*************/ 1532 1533 void 1534 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1535 struct ath5k_txq *txq) 1536 { 1537 struct ath5k_softc *sc = hw->priv; 1538 struct ath5k_buf *bf; 1539 unsigned long flags; 1540 int padsize; 1541 1542 trace_ath5k_tx(sc, skb, txq); 1543 1544 /* 1545 * The hardware expects the header padded to 4 byte boundaries. 1546 * If this is not the case, we add the padding after the header. 1547 */ 1548 padsize = ath5k_add_padding(skb); 1549 if (padsize < 0) { 1550 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" 1551 " headroom to pad"); 1552 goto drop_packet; 1553 } 1554 1555 if (txq->txq_len >= txq->txq_max) 1556 ieee80211_stop_queue(hw, txq->qnum); 1557 1558 spin_lock_irqsave(&sc->txbuflock, flags); 1559 if (list_empty(&sc->txbuf)) { 1560 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 1561 spin_unlock_irqrestore(&sc->txbuflock, flags); 1562 ieee80211_stop_queues(hw); 1563 goto drop_packet; 1564 } 1565 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 1566 list_del(&bf->list); 1567 sc->txbuf_len--; 1568 if (list_empty(&sc->txbuf)) 1569 ieee80211_stop_queues(hw); 1570 spin_unlock_irqrestore(&sc->txbuflock, flags); 1571 1572 bf->skb = skb; 1573 1574 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { 1575 bf->skb = NULL; 1576 spin_lock_irqsave(&sc->txbuflock, flags); 1577 list_add_tail(&bf->list, &sc->txbuf); 1578 sc->txbuf_len++; 1579 spin_unlock_irqrestore(&sc->txbuflock, flags); 1580 goto drop_packet; 1581 } 1582 return; 1583 1584 drop_packet: 1585 dev_kfree_skb_any(skb); 1586 } 1587 1588 static void 1589 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, 1590 struct ath5k_txq *txq, struct ath5k_tx_status *ts) 1591 { 1592 struct ieee80211_tx_info *info; 1593 u8 tries[3]; 1594 int i; 1595 1596 sc->stats.tx_all_count++; 1597 sc->stats.tx_bytes_count += skb->len; 1598 info = IEEE80211_SKB_CB(skb); 1599 1600 tries[0] = info->status.rates[0].count; 1601 tries[1] = info->status.rates[1].count; 1602 tries[2] = info->status.rates[2].count; 1603 1604 ieee80211_tx_info_clear_status(info); 1605 1606 for (i = 0; i < ts->ts_final_idx; i++) { 1607 struct ieee80211_tx_rate *r = 1608 &info->status.rates[i]; 1609 1610 r->count = tries[i]; 1611 } 1612 1613 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1614 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1615 1616 if (unlikely(ts->ts_status)) { 1617 sc->stats.ack_fail++; 1618 if (ts->ts_status & AR5K_TXERR_FILT) { 1619 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1620 sc->stats.txerr_filt++; 1621 } 1622 if (ts->ts_status & AR5K_TXERR_XRETRY) 1623 sc->stats.txerr_retry++; 1624 if (ts->ts_status & AR5K_TXERR_FIFO) 1625 sc->stats.txerr_fifo++; 1626 } else { 1627 info->flags |= IEEE80211_TX_STAT_ACK; 1628 info->status.ack_signal = ts->ts_rssi; 1629 1630 /* count the successful attempt as well */ 1631 info->status.rates[ts->ts_final_idx].count++; 1632 } 1633 1634 /* 1635 * Remove MAC header padding before giving the frame 1636 * back to mac80211. 1637 */ 1638 ath5k_remove_padding(skb); 1639 1640 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1641 sc->stats.antenna_tx[ts->ts_antenna]++; 1642 else 1643 sc->stats.antenna_tx[0]++; /* invalid */ 1644 1645 trace_ath5k_tx_complete(sc, skb, txq, ts); 1646 ieee80211_tx_status(sc->hw, skb); 1647 } 1648 1649 static void 1650 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1651 { 1652 struct ath5k_tx_status ts = {}; 1653 struct ath5k_buf *bf, *bf0; 1654 struct ath5k_desc *ds; 1655 struct sk_buff *skb; 1656 int ret; 1657 1658 spin_lock(&txq->lock); 1659 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1660 1661 txq->txq_poll_mark = false; 1662 1663 /* skb might already have been processed last time. */ 1664 if (bf->skb != NULL) { 1665 ds = bf->desc; 1666 1667 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1668 if (unlikely(ret == -EINPROGRESS)) 1669 break; 1670 else if (unlikely(ret)) { 1671 ATH5K_ERR(sc, 1672 "error %d while processing " 1673 "queue %u\n", ret, txq->qnum); 1674 break; 1675 } 1676 1677 skb = bf->skb; 1678 bf->skb = NULL; 1679 1680 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, 1681 DMA_TO_DEVICE); 1682 ath5k_tx_frame_completed(sc, skb, txq, &ts); 1683 } 1684 1685 /* 1686 * It's possible that the hardware can say the buffer is 1687 * completed when it hasn't yet loaded the ds_link from 1688 * host memory and moved on. 1689 * Always keep the last descriptor to avoid HW races... 1690 */ 1691 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) { 1692 spin_lock(&sc->txbuflock); 1693 list_move_tail(&bf->list, &sc->txbuf); 1694 sc->txbuf_len++; 1695 txq->txq_len--; 1696 spin_unlock(&sc->txbuflock); 1697 } 1698 } 1699 spin_unlock(&txq->lock); 1700 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1701 ieee80211_wake_queue(sc->hw, txq->qnum); 1702 } 1703 1704 static void 1705 ath5k_tasklet_tx(unsigned long data) 1706 { 1707 int i; 1708 struct ath5k_softc *sc = (void *)data; 1709 1710 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 1711 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 1712 ath5k_tx_processq(sc, &sc->txqs[i]); 1713 1714 sc->tx_pending = false; 1715 ath5k_set_current_imask(sc); 1716 } 1717 1718 1719 /*****************\ 1720 * Beacon handling * 1721 \*****************/ 1722 1723 /* 1724 * Setup the beacon frame for transmit. 1725 */ 1726 static int 1727 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1728 { 1729 struct sk_buff *skb = bf->skb; 1730 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1731 struct ath5k_hw *ah = sc->ah; 1732 struct ath5k_desc *ds; 1733 int ret = 0; 1734 u8 antenna; 1735 u32 flags; 1736 const int padsize = 0; 1737 1738 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 1739 DMA_TO_DEVICE); 1740 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1741 "skbaddr %llx\n", skb, skb->data, skb->len, 1742 (unsigned long long)bf->skbaddr); 1743 1744 if (dma_mapping_error(sc->dev, bf->skbaddr)) { 1745 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 1746 return -EIO; 1747 } 1748 1749 ds = bf->desc; 1750 antenna = ah->ah_tx_ant; 1751 1752 flags = AR5K_TXDESC_NOACK; 1753 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1754 ds->ds_link = bf->daddr; /* self-linked */ 1755 flags |= AR5K_TXDESC_VEOL; 1756 } else 1757 ds->ds_link = 0; 1758 1759 /* 1760 * If we use multiple antennas on AP and use 1761 * the Sectored AP scenario, switch antenna every 1762 * 4 beacons to make sure everybody hears our AP. 1763 * When a client tries to associate, hw will keep 1764 * track of the tx antenna to be used for this client 1765 * automaticaly, based on ACKed packets. 1766 * 1767 * Note: AP still listens and transmits RTS on the 1768 * default antenna which is supposed to be an omni. 1769 * 1770 * Note2: On sectored scenarios it's possible to have 1771 * multiple antennas (1 omni -- the default -- and 14 1772 * sectors), so if we choose to actually support this 1773 * mode, we need to allow the user to set how many antennas 1774 * we have and tweak the code below to send beacons 1775 * on all of them. 1776 */ 1777 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1778 antenna = sc->bsent & 4 ? 2 : 1; 1779 1780 1781 /* FIXME: If we are in g mode and rate is a CCK rate 1782 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1783 * from tx power (value is in dB units already) */ 1784 ds->ds_data = bf->skbaddr; 1785 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1786 ieee80211_get_hdrlen_from_skb(skb), padsize, 1787 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 1788 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 1789 1, AR5K_TXKEYIX_INVALID, 1790 antenna, flags, 0, 0); 1791 if (ret) 1792 goto err_unmap; 1793 1794 return 0; 1795 err_unmap: 1796 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1797 return ret; 1798 } 1799 1800 /* 1801 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1802 * this is called only once at config_bss time, for AP we do it every 1803 * SWBA interrupt so that the TIM will reflect buffered frames. 1804 * 1805 * Called with the beacon lock. 1806 */ 1807 int 1808 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1809 { 1810 int ret; 1811 struct ath5k_softc *sc = hw->priv; 1812 struct ath5k_vif *avf = (void *)vif->drv_priv; 1813 struct sk_buff *skb; 1814 1815 if (WARN_ON(!vif)) { 1816 ret = -EINVAL; 1817 goto out; 1818 } 1819 1820 skb = ieee80211_beacon_get(hw, vif); 1821 1822 if (!skb) { 1823 ret = -ENOMEM; 1824 goto out; 1825 } 1826 1827 ath5k_txbuf_free_skb(sc, avf->bbuf); 1828 avf->bbuf->skb = skb; 1829 ret = ath5k_beacon_setup(sc, avf->bbuf); 1830 if (ret) 1831 avf->bbuf->skb = NULL; 1832 out: 1833 return ret; 1834 } 1835 1836 /* 1837 * Transmit a beacon frame at SWBA. Dynamic updates to the 1838 * frame contents are done as needed and the slot time is 1839 * also adjusted based on current state. 1840 * 1841 * This is called from software irq context (beacontq tasklets) 1842 * or user context from ath5k_beacon_config. 1843 */ 1844 static void 1845 ath5k_beacon_send(struct ath5k_softc *sc) 1846 { 1847 struct ath5k_hw *ah = sc->ah; 1848 struct ieee80211_vif *vif; 1849 struct ath5k_vif *avf; 1850 struct ath5k_buf *bf; 1851 struct sk_buff *skb; 1852 1853 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1854 1855 /* 1856 * Check if the previous beacon has gone out. If 1857 * not, don't don't try to post another: skip this 1858 * period and wait for the next. Missed beacons 1859 * indicate a problem and should not occur. If we 1860 * miss too many consecutive beacons reset the device. 1861 */ 1862 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 1863 sc->bmisscount++; 1864 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1865 "missed %u consecutive beacons\n", sc->bmisscount); 1866 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 1867 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1868 "stuck beacon time (%u missed)\n", 1869 sc->bmisscount); 1870 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 1871 "stuck beacon, resetting\n"); 1872 ieee80211_queue_work(sc->hw, &sc->reset_work); 1873 } 1874 return; 1875 } 1876 if (unlikely(sc->bmisscount != 0)) { 1877 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1878 "resume beacon xmit after %u misses\n", 1879 sc->bmisscount); 1880 sc->bmisscount = 0; 1881 } 1882 1883 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) || 1884 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1885 u64 tsf = ath5k_hw_get_tsf64(ah); 1886 u32 tsftu = TSF_TO_TU(tsf); 1887 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; 1888 vif = sc->bslot[(slot + 1) % ATH_BCBUF]; 1889 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1890 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1891 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif); 1892 } else /* only one interface */ 1893 vif = sc->bslot[0]; 1894 1895 if (!vif) 1896 return; 1897 1898 avf = (void *)vif->drv_priv; 1899 bf = avf->bbuf; 1900 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 1901 sc->opmode == NL80211_IFTYPE_MONITOR)) { 1902 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 1903 return; 1904 } 1905 1906 /* 1907 * Stop any current dma and put the new frame on the queue. 1908 * This should never fail since we check above that no frames 1909 * are still pending on the queue. 1910 */ 1911 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) { 1912 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 1913 /* NB: hw still stops DMA, so proceed */ 1914 } 1915 1916 /* refresh the beacon for AP or MESH mode */ 1917 if (sc->opmode == NL80211_IFTYPE_AP || 1918 sc->opmode == NL80211_IFTYPE_MESH_POINT) 1919 ath5k_beacon_update(sc->hw, vif); 1920 1921 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]); 1922 1923 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 1924 ath5k_hw_start_tx_dma(ah, sc->bhalq); 1925 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1926 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 1927 1928 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1929 while (skb) { 1930 ath5k_tx_queue(sc->hw, skb, sc->cabq); 1931 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1932 } 1933 1934 sc->bsent++; 1935 } 1936 1937 /** 1938 * ath5k_beacon_update_timers - update beacon timers 1939 * 1940 * @sc: struct ath5k_softc pointer we are operating on 1941 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1942 * beacon timer update based on the current HW TSF. 1943 * 1944 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 1945 * of a received beacon or the current local hardware TSF and write it to the 1946 * beacon timer registers. 1947 * 1948 * This is called in a variety of situations, e.g. when a beacon is received, 1949 * when a TSF update has been detected, but also when an new IBSS is created or 1950 * when we otherwise know we have to update the timers, but we keep it in this 1951 * function to have it all together in one place. 1952 */ 1953 void 1954 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 1955 { 1956 struct ath5k_hw *ah = sc->ah; 1957 u32 nexttbtt, intval, hw_tu, bc_tu; 1958 u64 hw_tsf; 1959 1960 intval = sc->bintval & AR5K_BEACON_PERIOD; 1961 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { 1962 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 1963 if (intval < 15) 1964 ATH5K_WARN(sc, "intval %u is too low, min 15\n", 1965 intval); 1966 } 1967 if (WARN_ON(!intval)) 1968 return; 1969 1970 /* beacon TSF converted to TU */ 1971 bc_tu = TSF_TO_TU(bc_tsf); 1972 1973 /* current TSF converted to TU */ 1974 hw_tsf = ath5k_hw_get_tsf64(ah); 1975 hw_tu = TSF_TO_TU(hw_tsf); 1976 1977 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3 1978 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 1979 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 1980 * configuration we need to make sure it is bigger than that. */ 1981 1982 if (bc_tsf == -1) { 1983 /* 1984 * no beacons received, called internally. 1985 * just need to refresh timers based on HW TSF. 1986 */ 1987 nexttbtt = roundup(hw_tu + FUDGE, intval); 1988 } else if (bc_tsf == 0) { 1989 /* 1990 * no beacon received, probably called by ath5k_reset_tsf(). 1991 * reset TSF to start with 0. 1992 */ 1993 nexttbtt = intval; 1994 intval |= AR5K_BEACON_RESET_TSF; 1995 } else if (bc_tsf > hw_tsf) { 1996 /* 1997 * beacon received, SW merge happened but HW TSF not yet updated. 1998 * not possible to reconfigure timers yet, but next time we 1999 * receive a beacon with the same BSSID, the hardware will 2000 * automatically update the TSF and then we need to reconfigure 2001 * the timers. 2002 */ 2003 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2004 "need to wait for HW TSF sync\n"); 2005 return; 2006 } else { 2007 /* 2008 * most important case for beacon synchronization between STA. 2009 * 2010 * beacon received and HW TSF has been already updated by HW. 2011 * update next TBTT based on the TSF of the beacon, but make 2012 * sure it is ahead of our local TSF timer. 2013 */ 2014 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2015 } 2016 #undef FUDGE 2017 2018 sc->nexttbtt = nexttbtt; 2019 2020 intval |= AR5K_BEACON_ENA; 2021 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2022 2023 /* 2024 * debugging output last in order to preserve the time critical aspect 2025 * of this function 2026 */ 2027 if (bc_tsf == -1) 2028 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2029 "reconfigured timers based on HW TSF\n"); 2030 else if (bc_tsf == 0) 2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2032 "reset HW TSF and timers\n"); 2033 else 2034 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2035 "updated timers based on beacon TSF\n"); 2036 2037 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2038 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2039 (unsigned long long) bc_tsf, 2040 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2041 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2042 intval & AR5K_BEACON_PERIOD, 2043 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2044 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2045 } 2046 2047 /** 2048 * ath5k_beacon_config - Configure the beacon queues and interrupts 2049 * 2050 * @sc: struct ath5k_softc pointer we are operating on 2051 * 2052 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2053 * interrupts to detect TSF updates only. 2054 */ 2055 void 2056 ath5k_beacon_config(struct ath5k_softc *sc) 2057 { 2058 struct ath5k_hw *ah = sc->ah; 2059 unsigned long flags; 2060 2061 spin_lock_irqsave(&sc->block, flags); 2062 sc->bmisscount = 0; 2063 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2064 2065 if (sc->enable_beacon) { 2066 /* 2067 * In IBSS mode we use a self-linked tx descriptor and let the 2068 * hardware send the beacons automatically. We have to load it 2069 * only once here. 2070 * We use the SWBA interrupt only to keep track of the beacon 2071 * timers in order to detect automatic TSF updates. 2072 */ 2073 ath5k_beaconq_config(sc); 2074 2075 sc->imask |= AR5K_INT_SWBA; 2076 2077 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2078 if (ath5k_hw_hasveol(ah)) 2079 ath5k_beacon_send(sc); 2080 } else 2081 ath5k_beacon_update_timers(sc, -1); 2082 } else { 2083 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq); 2084 } 2085 2086 ath5k_hw_set_imr(ah, sc->imask); 2087 mmiowb(); 2088 spin_unlock_irqrestore(&sc->block, flags); 2089 } 2090 2091 static void ath5k_tasklet_beacon(unsigned long data) 2092 { 2093 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2094 2095 /* 2096 * Software beacon alert--time to send a beacon. 2097 * 2098 * In IBSS mode we use this interrupt just to 2099 * keep track of the next TBTT (target beacon 2100 * transmission time) in order to detect wether 2101 * automatic TSF updates happened. 2102 */ 2103 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2104 /* XXX: only if VEOL suppported */ 2105 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2106 sc->nexttbtt += sc->bintval; 2107 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2108 "SWBA nexttbtt: %x hw_tu: %x " 2109 "TSF: %llx\n", 2110 sc->nexttbtt, 2111 TSF_TO_TU(tsf), 2112 (unsigned long long) tsf); 2113 } else { 2114 spin_lock(&sc->block); 2115 ath5k_beacon_send(sc); 2116 spin_unlock(&sc->block); 2117 } 2118 } 2119 2120 2121 /********************\ 2122 * Interrupt handling * 2123 \********************/ 2124 2125 static void 2126 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2127 { 2128 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2129 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) { 2130 /* run ANI only when full calibration is not active */ 2131 ah->ah_cal_next_ani = jiffies + 2132 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2133 tasklet_schedule(&ah->ah_sc->ani_tasklet); 2134 2135 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2136 ah->ah_cal_next_full = jiffies + 2137 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2138 tasklet_schedule(&ah->ah_sc->calib); 2139 } 2140 /* we could use SWI to generate enough interrupts to meet our 2141 * calibration interval requirements, if necessary: 2142 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2143 } 2144 2145 static void 2146 ath5k_schedule_rx(struct ath5k_softc *sc) 2147 { 2148 sc->rx_pending = true; 2149 tasklet_schedule(&sc->rxtq); 2150 } 2151 2152 static void 2153 ath5k_schedule_tx(struct ath5k_softc *sc) 2154 { 2155 sc->tx_pending = true; 2156 tasklet_schedule(&sc->txtq); 2157 } 2158 2159 irqreturn_t 2160 ath5k_intr(int irq, void *dev_id) 2161 { 2162 struct ath5k_softc *sc = dev_id; 2163 struct ath5k_hw *ah = sc->ah; 2164 enum ath5k_int status; 2165 unsigned int counter = 1000; 2166 2167 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2168 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2169 !ath5k_hw_is_intr_pending(ah)))) 2170 return IRQ_NONE; 2171 2172 do { 2173 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2174 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2175 status, sc->imask); 2176 if (unlikely(status & AR5K_INT_FATAL)) { 2177 /* 2178 * Fatal errors are unrecoverable. 2179 * Typically these are caused by DMA errors. 2180 */ 2181 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2182 "fatal int, resetting\n"); 2183 ieee80211_queue_work(sc->hw, &sc->reset_work); 2184 } else if (unlikely(status & AR5K_INT_RXORN)) { 2185 /* 2186 * Receive buffers are full. Either the bus is busy or 2187 * the CPU is not fast enough to process all received 2188 * frames. 2189 * Older chipsets need a reset to come out of this 2190 * condition, but we treat it as RX for newer chips. 2191 * We don't know exactly which versions need a reset - 2192 * this guess is copied from the HAL. 2193 */ 2194 sc->stats.rxorn_intr++; 2195 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2196 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2197 "rx overrun, resetting\n"); 2198 ieee80211_queue_work(sc->hw, &sc->reset_work); 2199 } 2200 else 2201 ath5k_schedule_rx(sc); 2202 } else { 2203 if (status & AR5K_INT_SWBA) { 2204 tasklet_hi_schedule(&sc->beacontq); 2205 } 2206 if (status & AR5K_INT_RXEOL) { 2207 /* 2208 * NB: the hardware should re-read the link when 2209 * RXE bit is written, but it doesn't work at 2210 * least on older hardware revs. 2211 */ 2212 sc->stats.rxeol_intr++; 2213 } 2214 if (status & AR5K_INT_TXURN) { 2215 /* bump tx trigger level */ 2216 ath5k_hw_update_tx_triglevel(ah, true); 2217 } 2218 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2219 ath5k_schedule_rx(sc); 2220 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2221 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2222 ath5k_schedule_tx(sc); 2223 if (status & AR5K_INT_BMISS) { 2224 /* TODO */ 2225 } 2226 if (status & AR5K_INT_MIB) { 2227 sc->stats.mib_intr++; 2228 ath5k_hw_update_mib_counters(ah); 2229 ath5k_ani_mib_intr(ah); 2230 } 2231 if (status & AR5K_INT_GPIO) 2232 tasklet_schedule(&sc->rf_kill.toggleq); 2233 2234 } 2235 2236 if (ath5k_get_bus_type(ah) == ATH_AHB) 2237 break; 2238 2239 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2240 2241 if (sc->rx_pending || sc->tx_pending) 2242 ath5k_set_current_imask(sc); 2243 2244 if (unlikely(!counter)) 2245 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2246 2247 ath5k_intr_calibration_poll(ah); 2248 2249 return IRQ_HANDLED; 2250 } 2251 2252 /* 2253 * Periodically recalibrate the PHY to account 2254 * for temperature/environment changes. 2255 */ 2256 static void 2257 ath5k_tasklet_calibrate(unsigned long data) 2258 { 2259 struct ath5k_softc *sc = (void *)data; 2260 struct ath5k_hw *ah = sc->ah; 2261 2262 /* Only full calibration for now */ 2263 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2264 2265 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2266 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2267 sc->curchan->hw_value); 2268 2269 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2270 /* 2271 * Rfgain is out of bounds, reset the chip 2272 * to load new gain values. 2273 */ 2274 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2275 ieee80211_queue_work(sc->hw, &sc->reset_work); 2276 } 2277 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2278 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2279 ieee80211_frequency_to_channel( 2280 sc->curchan->center_freq)); 2281 2282 /* Noise floor calibration interrupts rx/tx path while I/Q calibration 2283 * doesn't. 2284 * TODO: We should stop TX here, so that it doesn't interfere. 2285 * Note that stopping the queues is not enough to stop TX! */ 2286 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) { 2287 ah->ah_cal_next_nf = jiffies + 2288 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF); 2289 ath5k_hw_update_noise_floor(ah); 2290 } 2291 2292 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2293 } 2294 2295 2296 static void 2297 ath5k_tasklet_ani(unsigned long data) 2298 { 2299 struct ath5k_softc *sc = (void *)data; 2300 struct ath5k_hw *ah = sc->ah; 2301 2302 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2303 ath5k_ani_calibration(ah); 2304 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2305 } 2306 2307 2308 static void 2309 ath5k_tx_complete_poll_work(struct work_struct *work) 2310 { 2311 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2312 tx_complete_work.work); 2313 struct ath5k_txq *txq; 2314 int i; 2315 bool needreset = false; 2316 2317 mutex_lock(&sc->lock); 2318 2319 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 2320 if (sc->txqs[i].setup) { 2321 txq = &sc->txqs[i]; 2322 spin_lock_bh(&txq->lock); 2323 if (txq->txq_len > 1) { 2324 if (txq->txq_poll_mark) { 2325 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, 2326 "TX queue stuck %d\n", 2327 txq->qnum); 2328 needreset = true; 2329 txq->txq_stuck++; 2330 spin_unlock_bh(&txq->lock); 2331 break; 2332 } else { 2333 txq->txq_poll_mark = true; 2334 } 2335 } 2336 spin_unlock_bh(&txq->lock); 2337 } 2338 } 2339 2340 if (needreset) { 2341 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2342 "TX queues stuck, resetting\n"); 2343 ath5k_reset(sc, NULL, true); 2344 } 2345 2346 mutex_unlock(&sc->lock); 2347 2348 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2349 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2350 } 2351 2352 2353 /*************************\ 2354 * Initialization routines * 2355 \*************************/ 2356 2357 int 2358 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) 2359 { 2360 struct ieee80211_hw *hw = sc->hw; 2361 struct ath_common *common; 2362 int ret; 2363 int csz; 2364 2365 /* Initialize driver private data */ 2366 SET_IEEE80211_DEV(hw, sc->dev); 2367 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2368 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2369 IEEE80211_HW_SIGNAL_DBM | 2370 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 2371 2372 hw->wiphy->interface_modes = 2373 BIT(NL80211_IFTYPE_AP) | 2374 BIT(NL80211_IFTYPE_STATION) | 2375 BIT(NL80211_IFTYPE_ADHOC) | 2376 BIT(NL80211_IFTYPE_MESH_POINT); 2377 2378 /* both antennas can be configured as RX or TX */ 2379 hw->wiphy->available_antennas_tx = 0x3; 2380 hw->wiphy->available_antennas_rx = 0x3; 2381 2382 hw->extra_tx_headroom = 2; 2383 hw->channel_change_time = 5000; 2384 2385 /* 2386 * Mark the device as detached to avoid processing 2387 * interrupts until setup is complete. 2388 */ 2389 __set_bit(ATH_STAT_INVALID, sc->status); 2390 2391 sc->opmode = NL80211_IFTYPE_STATION; 2392 sc->bintval = 1000; 2393 mutex_init(&sc->lock); 2394 spin_lock_init(&sc->rxbuflock); 2395 spin_lock_init(&sc->txbuflock); 2396 spin_lock_init(&sc->block); 2397 spin_lock_init(&sc->irqlock); 2398 2399 /* Setup interrupt handler */ 2400 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 2401 if (ret) { 2402 ATH5K_ERR(sc, "request_irq failed\n"); 2403 goto err; 2404 } 2405 2406 /* If we passed the test, malloc an ath5k_hw struct */ 2407 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); 2408 if (!sc->ah) { 2409 ret = -ENOMEM; 2410 ATH5K_ERR(sc, "out of memory\n"); 2411 goto err_irq; 2412 } 2413 2414 sc->ah->ah_sc = sc; 2415 sc->ah->ah_iobase = sc->iobase; 2416 common = ath5k_hw_common(sc->ah); 2417 common->ops = &ath5k_common_ops; 2418 common->bus_ops = bus_ops; 2419 common->ah = sc->ah; 2420 common->hw = hw; 2421 common->priv = sc; 2422 2423 /* 2424 * Cache line size is used to size and align various 2425 * structures used to communicate with the hardware. 2426 */ 2427 ath5k_read_cachesize(common, &csz); 2428 common->cachelsz = csz << 2; /* convert to bytes */ 2429 2430 spin_lock_init(&common->cc_lock); 2431 2432 /* Initialize device */ 2433 ret = ath5k_hw_init(sc); 2434 if (ret) 2435 goto err_free_ah; 2436 2437 /* set up multi-rate retry capabilities */ 2438 if (sc->ah->ah_version == AR5K_AR5212) { 2439 hw->max_rates = 4; 2440 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2441 AR5K_INIT_RETRY_LONG); 2442 } 2443 2444 hw->vif_data_size = sizeof(struct ath5k_vif); 2445 2446 /* Finish private driver data initialization */ 2447 ret = ath5k_init(hw); 2448 if (ret) 2449 goto err_ah; 2450 2451 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2452 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 2453 sc->ah->ah_mac_srev, 2454 sc->ah->ah_phy_revision); 2455 2456 if (!sc->ah->ah_single_chip) { 2457 /* Single chip radio (!RF5111) */ 2458 if (sc->ah->ah_radio_5ghz_revision && 2459 !sc->ah->ah_radio_2ghz_revision) { 2460 /* No 5GHz support -> report 2GHz radio */ 2461 if (!test_bit(AR5K_MODE_11A, 2462 sc->ah->ah_capabilities.cap_mode)) { 2463 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2464 ath5k_chip_name(AR5K_VERSION_RAD, 2465 sc->ah->ah_radio_5ghz_revision), 2466 sc->ah->ah_radio_5ghz_revision); 2467 /* No 2GHz support (5110 and some 2468 * 5Ghz only cards) -> report 5Ghz radio */ 2469 } else if (!test_bit(AR5K_MODE_11B, 2470 sc->ah->ah_capabilities.cap_mode)) { 2471 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2472 ath5k_chip_name(AR5K_VERSION_RAD, 2473 sc->ah->ah_radio_5ghz_revision), 2474 sc->ah->ah_radio_5ghz_revision); 2475 /* Multiband radio */ 2476 } else { 2477 ATH5K_INFO(sc, "RF%s multiband radio found" 2478 " (0x%x)\n", 2479 ath5k_chip_name(AR5K_VERSION_RAD, 2480 sc->ah->ah_radio_5ghz_revision), 2481 sc->ah->ah_radio_5ghz_revision); 2482 } 2483 } 2484 /* Multi chip radio (RF5111 - RF2111) -> 2485 * report both 2GHz/5GHz radios */ 2486 else if (sc->ah->ah_radio_5ghz_revision && 2487 sc->ah->ah_radio_2ghz_revision){ 2488 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2489 ath5k_chip_name(AR5K_VERSION_RAD, 2490 sc->ah->ah_radio_5ghz_revision), 2491 sc->ah->ah_radio_5ghz_revision); 2492 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2493 ath5k_chip_name(AR5K_VERSION_RAD, 2494 sc->ah->ah_radio_2ghz_revision), 2495 sc->ah->ah_radio_2ghz_revision); 2496 } 2497 } 2498 2499 ath5k_debug_init_device(sc); 2500 2501 /* ready to process interrupts */ 2502 __clear_bit(ATH_STAT_INVALID, sc->status); 2503 2504 return 0; 2505 err_ah: 2506 ath5k_hw_deinit(sc->ah); 2507 err_free_ah: 2508 kfree(sc->ah); 2509 err_irq: 2510 free_irq(sc->irq, sc); 2511 err: 2512 return ret; 2513 } 2514 2515 static int 2516 ath5k_stop_locked(struct ath5k_softc *sc) 2517 { 2518 struct ath5k_hw *ah = sc->ah; 2519 2520 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2521 test_bit(ATH_STAT_INVALID, sc->status)); 2522 2523 /* 2524 * Shutdown the hardware and driver: 2525 * stop output from above 2526 * disable interrupts 2527 * turn off timers 2528 * turn off the radio 2529 * clear transmit machinery 2530 * clear receive machinery 2531 * drain and release tx queues 2532 * reclaim beacon resources 2533 * power down hardware 2534 * 2535 * Note that some of this work is not possible if the 2536 * hardware is gone (invalid). 2537 */ 2538 ieee80211_stop_queues(sc->hw); 2539 2540 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2541 ath5k_led_off(sc); 2542 ath5k_hw_set_imr(ah, 0); 2543 synchronize_irq(sc->irq); 2544 ath5k_rx_stop(sc); 2545 ath5k_hw_dma_stop(ah); 2546 ath5k_drain_tx_buffs(sc); 2547 ath5k_hw_phy_disable(ah); 2548 } 2549 2550 return 0; 2551 } 2552 2553 int 2554 ath5k_init_hw(struct ath5k_softc *sc) 2555 { 2556 struct ath5k_hw *ah = sc->ah; 2557 struct ath_common *common = ath5k_hw_common(ah); 2558 int ret, i; 2559 2560 mutex_lock(&sc->lock); 2561 2562 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2563 2564 /* 2565 * Stop anything previously setup. This is safe 2566 * no matter this is the first time through or not. 2567 */ 2568 ath5k_stop_locked(sc); 2569 2570 /* 2571 * The basic interface to setting the hardware in a good 2572 * state is ``reset''. On return the hardware is known to 2573 * be powered up and with interrupts disabled. This must 2574 * be followed by initialization of the appropriate bits 2575 * and then setup of the interrupt mask. 2576 */ 2577 sc->curchan = sc->hw->conf.channel; 2578 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2579 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2580 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; 2581 2582 ret = ath5k_reset(sc, NULL, false); 2583 if (ret) 2584 goto done; 2585 2586 ath5k_rfkill_hw_start(ah); 2587 2588 /* 2589 * Reset the key cache since some parts do not reset the 2590 * contents on initial power up or resume from suspend. 2591 */ 2592 for (i = 0; i < common->keymax; i++) 2593 ath_hw_keyreset(common, (u16) i); 2594 2595 /* Use higher rates for acks instead of base 2596 * rate */ 2597 ah->ah_ack_bitrate_high = true; 2598 2599 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++) 2600 sc->bslot[i] = NULL; 2601 2602 ret = 0; 2603 done: 2604 mmiowb(); 2605 mutex_unlock(&sc->lock); 2606 2607 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2608 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2609 2610 return ret; 2611 } 2612 2613 static void stop_tasklets(struct ath5k_softc *sc) 2614 { 2615 sc->rx_pending = false; 2616 sc->tx_pending = false; 2617 tasklet_kill(&sc->rxtq); 2618 tasklet_kill(&sc->txtq); 2619 tasklet_kill(&sc->calib); 2620 tasklet_kill(&sc->beacontq); 2621 tasklet_kill(&sc->ani_tasklet); 2622 } 2623 2624 /* 2625 * Stop the device, grabbing the top-level lock to protect 2626 * against concurrent entry through ath5k_init (which can happen 2627 * if another thread does a system call and the thread doing the 2628 * stop is preempted). 2629 */ 2630 int 2631 ath5k_stop_hw(struct ath5k_softc *sc) 2632 { 2633 int ret; 2634 2635 mutex_lock(&sc->lock); 2636 ret = ath5k_stop_locked(sc); 2637 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2638 /* 2639 * Don't set the card in full sleep mode! 2640 * 2641 * a) When the device is in this state it must be carefully 2642 * woken up or references to registers in the PCI clock 2643 * domain may freeze the bus (and system). This varies 2644 * by chip and is mostly an issue with newer parts 2645 * (madwifi sources mentioned srev >= 0x78) that go to 2646 * sleep more quickly. 2647 * 2648 * b) On older chips full sleep results a weird behaviour 2649 * during wakeup. I tested various cards with srev < 0x78 2650 * and they don't wake up after module reload, a second 2651 * module reload is needed to bring the card up again. 2652 * 2653 * Until we figure out what's going on don't enable 2654 * full chip reset on any chip (this is what Legacy HAL 2655 * and Sam's HAL do anyway). Instead Perform a full reset 2656 * on the device (same as initial state after attach) and 2657 * leave it idle (keep MAC/BB on warm reset) */ 2658 ret = ath5k_hw_on_hold(sc->ah); 2659 2660 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2661 "putting device to sleep\n"); 2662 } 2663 2664 mmiowb(); 2665 mutex_unlock(&sc->lock); 2666 2667 stop_tasklets(sc); 2668 2669 cancel_delayed_work_sync(&sc->tx_complete_work); 2670 2671 ath5k_rfkill_hw_stop(sc->ah); 2672 2673 return ret; 2674 } 2675 2676 /* 2677 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2678 * and change to the given channel. 2679 * 2680 * This should be called with sc->lock. 2681 */ 2682 static int 2683 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 2684 bool skip_pcu) 2685 { 2686 struct ath5k_hw *ah = sc->ah; 2687 struct ath_common *common = ath5k_hw_common(ah); 2688 int ret, ani_mode; 2689 2690 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2691 2692 ath5k_hw_set_imr(ah, 0); 2693 synchronize_irq(sc->irq); 2694 stop_tasklets(sc); 2695 2696 /* Save ani mode and disable ANI during 2697 * reset. If we don't we might get false 2698 * PHY error interrupts. */ 2699 ani_mode = ah->ah_sc->ani_state.ani_mode; 2700 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2701 2702 /* We are going to empty hw queues 2703 * so we should also free any remaining 2704 * tx buffers */ 2705 ath5k_drain_tx_buffs(sc); 2706 if (chan) 2707 sc->curchan = chan; 2708 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL, 2709 skip_pcu); 2710 if (ret) { 2711 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2712 goto err; 2713 } 2714 2715 ret = ath5k_rx_start(sc); 2716 if (ret) { 2717 ATH5K_ERR(sc, "can't start recv logic\n"); 2718 goto err; 2719 } 2720 2721 ath5k_ani_init(ah, ani_mode); 2722 2723 ah->ah_cal_next_full = jiffies; 2724 ah->ah_cal_next_ani = jiffies; 2725 ah->ah_cal_next_nf = jiffies; 2726 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2727 2728 /* clear survey data and cycle counters */ 2729 memset(&sc->survey, 0, sizeof(sc->survey)); 2730 spin_lock_bh(&common->cc_lock); 2731 ath_hw_cycle_counters_update(common); 2732 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2733 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2734 spin_unlock_bh(&common->cc_lock); 2735 2736 /* 2737 * Change channels and update the h/w rate map if we're switching; 2738 * e.g. 11a to 11b/g. 2739 * 2740 * We may be doing a reset in response to an ioctl that changes the 2741 * channel so update any state that might change as a result. 2742 * 2743 * XXX needed? 2744 */ 2745 /* ath5k_chan_change(sc, c); */ 2746 2747 ath5k_beacon_config(sc); 2748 /* intrs are enabled by ath5k_beacon_config */ 2749 2750 ieee80211_wake_queues(sc->hw); 2751 2752 return 0; 2753 err: 2754 return ret; 2755 } 2756 2757 static void ath5k_reset_work(struct work_struct *work) 2758 { 2759 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2760 reset_work); 2761 2762 mutex_lock(&sc->lock); 2763 ath5k_reset(sc, NULL, true); 2764 mutex_unlock(&sc->lock); 2765 } 2766 2767 static int 2768 ath5k_init(struct ieee80211_hw *hw) 2769 { 2770 2771 struct ath5k_softc *sc = hw->priv; 2772 struct ath5k_hw *ah = sc->ah; 2773 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2774 struct ath5k_txq *txq; 2775 u8 mac[ETH_ALEN] = {}; 2776 int ret; 2777 2778 2779 /* 2780 * Check if the MAC has multi-rate retry support. 2781 * We do this by trying to setup a fake extended 2782 * descriptor. MACs that don't have support will 2783 * return false w/o doing anything. MACs that do 2784 * support it will return true w/o doing anything. 2785 */ 2786 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 2787 2788 if (ret < 0) 2789 goto err; 2790 if (ret > 0) 2791 __set_bit(ATH_STAT_MRRETRY, sc->status); 2792 2793 /* 2794 * Collect the channel list. The 802.11 layer 2795 * is resposible for filtering this list based 2796 * on settings like the phy mode and regulatory 2797 * domain restrictions. 2798 */ 2799 ret = ath5k_setup_bands(hw); 2800 if (ret) { 2801 ATH5K_ERR(sc, "can't get channels\n"); 2802 goto err; 2803 } 2804 2805 /* 2806 * Allocate tx+rx descriptors and populate the lists. 2807 */ 2808 ret = ath5k_desc_alloc(sc); 2809 if (ret) { 2810 ATH5K_ERR(sc, "can't allocate descriptors\n"); 2811 goto err; 2812 } 2813 2814 /* 2815 * Allocate hardware transmit queues: one queue for 2816 * beacon frames and one data queue for each QoS 2817 * priority. Note that hw functions handle resetting 2818 * these queues at the needed time. 2819 */ 2820 ret = ath5k_beaconq_setup(ah); 2821 if (ret < 0) { 2822 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 2823 goto err_desc; 2824 } 2825 sc->bhalq = ret; 2826 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 2827 if (IS_ERR(sc->cabq)) { 2828 ATH5K_ERR(sc, "can't setup cab queue\n"); 2829 ret = PTR_ERR(sc->cabq); 2830 goto err_bhal; 2831 } 2832 2833 /* 5211 and 5212 usually support 10 queues but we better rely on the 2834 * capability information */ 2835 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2836 /* This order matches mac80211's queue priority, so we can 2837 * directly use the mac80211 queue number without any mapping */ 2838 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2839 if (IS_ERR(txq)) { 2840 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2841 ret = PTR_ERR(txq); 2842 goto err_queues; 2843 } 2844 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2845 if (IS_ERR(txq)) { 2846 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2847 ret = PTR_ERR(txq); 2848 goto err_queues; 2849 } 2850 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2851 if (IS_ERR(txq)) { 2852 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2853 ret = PTR_ERR(txq); 2854 goto err_queues; 2855 } 2856 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2857 if (IS_ERR(txq)) { 2858 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2859 ret = PTR_ERR(txq); 2860 goto err_queues; 2861 } 2862 hw->queues = 4; 2863 } else { 2864 /* older hardware (5210) can only support one data queue */ 2865 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2866 if (IS_ERR(txq)) { 2867 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2868 ret = PTR_ERR(txq); 2869 goto err_queues; 2870 } 2871 hw->queues = 1; 2872 } 2873 2874 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 2875 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 2876 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 2877 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 2878 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); 2879 2880 INIT_WORK(&sc->reset_work, ath5k_reset_work); 2881 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work); 2882 2883 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 2884 if (ret) { 2885 ATH5K_ERR(sc, "unable to read address from EEPROM\n"); 2886 goto err_queues; 2887 } 2888 2889 SET_IEEE80211_PERM_ADDR(hw, mac); 2890 memcpy(&sc->lladdr, mac, ETH_ALEN); 2891 /* All MAC address bits matter for ACKs */ 2892 ath5k_update_bssid_mask_and_opmode(sc, NULL); 2893 2894 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 2895 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 2896 if (ret) { 2897 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 2898 goto err_queues; 2899 } 2900 2901 ret = ieee80211_register_hw(hw); 2902 if (ret) { 2903 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 2904 goto err_queues; 2905 } 2906 2907 if (!ath_is_world_regd(regulatory)) 2908 regulatory_hint(hw->wiphy, regulatory->alpha2); 2909 2910 ath5k_init_leds(sc); 2911 2912 ath5k_sysfs_register(sc); 2913 2914 return 0; 2915 err_queues: 2916 ath5k_txq_release(sc); 2917 err_bhal: 2918 ath5k_hw_release_tx_queue(ah, sc->bhalq); 2919 err_desc: 2920 ath5k_desc_free(sc); 2921 err: 2922 return ret; 2923 } 2924 2925 void 2926 ath5k_deinit_softc(struct ath5k_softc *sc) 2927 { 2928 struct ieee80211_hw *hw = sc->hw; 2929 2930 /* 2931 * NB: the order of these is important: 2932 * o call the 802.11 layer before detaching ath5k_hw to 2933 * ensure callbacks into the driver to delete global 2934 * key cache entries can be handled 2935 * o reclaim the tx queue data structures after calling 2936 * the 802.11 layer as we'll get called back to reclaim 2937 * node state and potentially want to use them 2938 * o to cleanup the tx queues the hal is called, so detach 2939 * it last 2940 * XXX: ??? detach ath5k_hw ??? 2941 * Other than that, it's straightforward... 2942 */ 2943 ieee80211_unregister_hw(hw); 2944 ath5k_desc_free(sc); 2945 ath5k_txq_release(sc); 2946 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 2947 ath5k_unregister_leds(sc); 2948 2949 ath5k_sysfs_unregister(sc); 2950 /* 2951 * NB: can't reclaim these until after ieee80211_ifdetach 2952 * returns because we'll get called back to reclaim node 2953 * state and potentially want to use them. 2954 */ 2955 ath5k_hw_deinit(sc->ah); 2956 free_irq(sc->irq, sc); 2957 } 2958 2959 bool 2960 ath_any_vif_assoc(struct ath5k_softc *sc) 2961 { 2962 struct ath5k_vif_iter_data iter_data; 2963 iter_data.hw_macaddr = NULL; 2964 iter_data.any_assoc = false; 2965 iter_data.need_set_hw_addr = false; 2966 iter_data.found_active = true; 2967 2968 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 2969 &iter_data); 2970 return iter_data.any_assoc; 2971 } 2972 2973 void 2974 set_beacon_filter(struct ieee80211_hw *hw, bool enable) 2975 { 2976 struct ath5k_softc *sc = hw->priv; 2977 struct ath5k_hw *ah = sc->ah; 2978 u32 rfilt; 2979 rfilt = ath5k_hw_get_rx_filter(ah); 2980 if (enable) 2981 rfilt |= AR5K_RX_FILTER_BEACON; 2982 else 2983 rfilt &= ~AR5K_RX_FILTER_BEACON; 2984 ath5k_hw_set_rx_filter(ah, rfilt); 2985 sc->filter_flags = rfilt; 2986 } 2987