1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 /*************************************\ 20 * Attach/Detach Functions and helpers * 21 \*************************************/ 22 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include "ath5k.h" 26 #include "reg.h" 27 #include "debug.h" 28 #include "base.h" 29 30 /** 31 * ath5k_hw_post - Power On Self Test helper function 32 * 33 * @ah: The &struct ath5k_hw 34 */ 35 static int ath5k_hw_post(struct ath5k_hw *ah) 36 { 37 38 static const u32 static_pattern[4] = { 39 0x55555555, 0xaaaaaaaa, 40 0x66666666, 0x99999999 41 }; 42 static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) }; 43 int i, c; 44 u16 cur_reg; 45 u32 var_pattern; 46 u32 init_val; 47 u32 cur_val; 48 49 for (c = 0; c < 2; c++) { 50 51 cur_reg = regs[c]; 52 53 /* Save previous value */ 54 init_val = ath5k_hw_reg_read(ah, cur_reg); 55 56 for (i = 0; i < 256; i++) { 57 var_pattern = i << 16 | i; 58 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 59 cur_val = ath5k_hw_reg_read(ah, cur_reg); 60 61 if (cur_val != var_pattern) { 62 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); 63 return -EAGAIN; 64 } 65 66 /* Found on ndiswrapper dumps */ 67 var_pattern = 0x0039080f; 68 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 69 } 70 71 for (i = 0; i < 4; i++) { 72 var_pattern = static_pattern[i]; 73 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 74 cur_val = ath5k_hw_reg_read(ah, cur_reg); 75 76 if (cur_val != var_pattern) { 77 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); 78 return -EAGAIN; 79 } 80 81 /* Found on ndiswrapper dumps */ 82 var_pattern = 0x003b080f; 83 ath5k_hw_reg_write(ah, var_pattern, cur_reg); 84 } 85 86 /* Restore previous value */ 87 ath5k_hw_reg_write(ah, init_val, cur_reg); 88 89 } 90 91 return 0; 92 93 } 94 95 /** 96 * ath5k_hw_attach - Check if hw is supported and init the needed structs 97 * 98 * @sc: The &struct ath5k_softc we got from the driver's attach function 99 * 100 * Check if the device is supported, perform a POST and initialize the needed 101 * structs. Returns -ENOMEM if we don't have memory for the needed structs, 102 * -ENODEV if the device is not supported or prints an error msg if something 103 * else went wrong. 104 */ 105 int ath5k_hw_attach(struct ath5k_softc *sc) 106 { 107 struct ath5k_hw *ah = sc->ah; 108 struct ath_common *common = ath5k_hw_common(ah); 109 struct pci_dev *pdev = sc->pdev; 110 struct ath5k_eeprom_info *ee; 111 int ret; 112 u32 srev; 113 114 /* 115 * HW information 116 */ 117 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; 118 ah->ah_turbo = false; 119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 120 ah->ah_imr = 0; 121 ah->ah_atim_window = 0; 122 ah->ah_aifs = AR5K_TUNE_AIFS; 123 ah->ah_cw_min = AR5K_TUNE_CWMIN; 124 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 125 ah->ah_software_retry = false; 126 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT; 127 ah->ah_noise_floor = -95; /* until first NF calibration is run */ 128 sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO; 129 130 /* 131 * Find the mac version 132 */ 133 srev = ath5k_hw_reg_read(ah, AR5K_SREV); 134 if (srev < AR5K_SREV_AR5311) 135 ah->ah_version = AR5K_AR5210; 136 else if (srev < AR5K_SREV_AR5212) 137 ah->ah_version = AR5K_AR5211; 138 else 139 ah->ah_version = AR5K_AR5212; 140 141 /*Fill the ath5k_hw struct with the needed functions*/ 142 ret = ath5k_hw_init_desc_functions(ah); 143 if (ret) 144 goto err_free; 145 146 /* Bring device out of sleep and reset it's units */ 147 ret = ath5k_hw_nic_wakeup(ah, 0, true); 148 if (ret) 149 goto err_free; 150 151 /* Get MAC, PHY and RADIO revisions */ 152 ah->ah_mac_srev = srev; 153 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); 154 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) & 155 0xffffffff; 156 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, 157 CHANNEL_5GHZ); 158 ah->ah_phy = AR5K_PHY(0); 159 160 /* Try to identify radio chip based on it's srev */ 161 switch (ah->ah_radio_5ghz_revision & 0xf0) { 162 case AR5K_SREV_RAD_5111: 163 ah->ah_radio = AR5K_RF5111; 164 ah->ah_single_chip = false; 165 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 166 CHANNEL_2GHZ); 167 break; 168 case AR5K_SREV_RAD_5112: 169 case AR5K_SREV_RAD_2112: 170 ah->ah_radio = AR5K_RF5112; 171 ah->ah_single_chip = false; 172 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 173 CHANNEL_2GHZ); 174 break; 175 case AR5K_SREV_RAD_2413: 176 ah->ah_radio = AR5K_RF2413; 177 ah->ah_single_chip = true; 178 break; 179 case AR5K_SREV_RAD_5413: 180 ah->ah_radio = AR5K_RF5413; 181 ah->ah_single_chip = true; 182 break; 183 case AR5K_SREV_RAD_2316: 184 ah->ah_radio = AR5K_RF2316; 185 ah->ah_single_chip = true; 186 break; 187 case AR5K_SREV_RAD_2317: 188 ah->ah_radio = AR5K_RF2317; 189 ah->ah_single_chip = true; 190 break; 191 case AR5K_SREV_RAD_5424: 192 if (ah->ah_mac_version == AR5K_SREV_AR2425 || 193 ah->ah_mac_version == AR5K_SREV_AR2417){ 194 ah->ah_radio = AR5K_RF2425; 195 ah->ah_single_chip = true; 196 } else { 197 ah->ah_radio = AR5K_RF5413; 198 ah->ah_single_chip = true; 199 } 200 break; 201 default: 202 /* Identify radio based on mac/phy srev */ 203 if (ah->ah_version == AR5K_AR5210) { 204 ah->ah_radio = AR5K_RF5110; 205 ah->ah_single_chip = false; 206 } else if (ah->ah_version == AR5K_AR5211) { 207 ah->ah_radio = AR5K_RF5111; 208 ah->ah_single_chip = false; 209 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 210 CHANNEL_2GHZ); 211 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) || 212 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) || 213 ah->ah_phy_revision == AR5K_SREV_PHY_2425) { 214 ah->ah_radio = AR5K_RF2425; 215 ah->ah_single_chip = true; 216 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; 217 } else if (srev == AR5K_SREV_AR5213A && 218 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) { 219 ah->ah_radio = AR5K_RF5112; 220 ah->ah_single_chip = false; 221 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B; 222 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) { 223 ah->ah_radio = AR5K_RF2316; 224 ah->ah_single_chip = true; 225 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; 226 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || 227 ah->ah_phy_revision == AR5K_SREV_PHY_5413) { 228 ah->ah_radio = AR5K_RF5413; 229 ah->ah_single_chip = true; 230 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; 231 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || 232 ah->ah_phy_revision == AR5K_SREV_PHY_2413) { 233 ah->ah_radio = AR5K_RF2413; 234 ah->ah_single_chip = true; 235 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; 236 } else { 237 ATH5K_ERR(sc, "Couldn't identify radio revision.\n"); 238 ret = -ENODEV; 239 goto err_free; 240 } 241 } 242 243 244 /* Return on unsuported chips (unsupported eeprom etc) */ 245 if ((srev >= AR5K_SREV_AR5416) && 246 (srev < AR5K_SREV_AR2425)) { 247 ATH5K_ERR(sc, "Device not yet supported.\n"); 248 ret = -ENODEV; 249 goto err_free; 250 } 251 252 /* 253 * POST 254 */ 255 ret = ath5k_hw_post(ah); 256 if (ret) 257 goto err_free; 258 259 /* Enable pci core retry fix on Hainan (5213A) and later chips */ 260 if (srev >= AR5K_SREV_AR5213A) 261 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX); 262 263 /* 264 * Get card capabilities, calibration values etc 265 * TODO: EEPROM work 266 */ 267 ret = ath5k_eeprom_init(ah); 268 if (ret) { 269 ATH5K_ERR(sc, "unable to init EEPROM\n"); 270 goto err_free; 271 } 272 273 ee = &ah->ah_capabilities.cap_eeprom; 274 275 /* 276 * Write PCI-E power save settings 277 */ 278 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) { 279 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES); 280 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES); 281 282 /* Shut off RX when elecidle is asserted */ 283 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES); 284 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES); 285 286 /* If serdes programing is enabled, increase PCI-E 287 * tx power for systems with long trace from host 288 * to minicard connector. */ 289 if (ee->ee_serdes) 290 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES); 291 else 292 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES); 293 294 /* Shut off PLL and CLKREQ active in L1 */ 295 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES); 296 297 /* Preserve other settings */ 298 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES); 299 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES); 300 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES); 301 302 /* Reset SERDES to load new settings */ 303 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET); 304 mdelay(1); 305 } 306 307 /* Get misc capabilities */ 308 ret = ath5k_hw_set_capabilities(ah); 309 if (ret) { 310 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n", 311 sc->pdev->device); 312 goto err_free; 313 } 314 315 /* Crypto settings */ 316 ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 && 317 (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 && 318 !AR5K_EEPROM_AES_DIS(ee->ee_misc5)); 319 320 if (srev >= AR5K_SREV_AR2414) { 321 ah->ah_combined_mic = true; 322 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE, 323 AR5K_MISC_MODE_COMBINED_MIC); 324 } 325 326 /* MAC address is cleared until add_interface */ 327 ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){}); 328 329 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ 330 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN); 331 ath5k_hw_set_associd(ah); 332 ath5k_hw_set_opmode(ah, sc->opmode); 333 334 ath5k_hw_rfgain_opt_init(ah); 335 336 ath5k_hw_init_nfcal_hist(ah); 337 338 /* turn on HW LEDs */ 339 ath5k_hw_set_ledstate(ah, AR5K_LED_INIT); 340 341 return 0; 342 err_free: 343 kfree(ah); 344 return ret; 345 } 346 347 /** 348 * ath5k_hw_detach - Free the ath5k_hw struct 349 * 350 * @ah: The &struct ath5k_hw 351 */ 352 void ath5k_hw_detach(struct ath5k_hw *ah) 353 { 354 ATH5K_TRACE(ah->ah_sc); 355 356 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status); 357 358 if (ah->ah_rf_banks != NULL) 359 kfree(ah->ah_rf_banks); 360 361 ath5k_eeprom_detach(ah); 362 363 /* assume interrupts are down */ 364 } 365